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+:102F620020686168A2680C3401E08B5C8354013AEA +:042F7200FBD57047D4 +:04000005080023A527 +:00000001FF Index: ecs_cellMon/Bootloader/SES/Output/Debug/Exe/bootloader.map =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Debug/Exe/bootloader.map (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Debug/Exe/bootloader.map (revision 3) @@ -0,0 +1,658 @@ +*********************************************************************************************** +*** *** +*** LINK INFORMATION *** +*** *** +*********************************************************************************************** + +Linker version: + + SEGGER ARM Linker 4.10.1 compiled Jun 4 2021 19:08:05 + Copyright (c) 2017-2021 SEGGER Microcontroller GmbH www.segger.com + + +*********************************************************************************************** +*** *** +*** MODULE SUMMARY *** +*** *** +*********************************************************************************************** + +Memory use by input file: + + Object File RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + SEGGER_THUMB_Startup.o 20 + SEGGER_crtinit_v6m_little.o 38 + STM32G07x_Vectors.o 260 + STM32G0xx_Startup.o 6 + aes.o 2 350 767 184 + main.o 4 902 1 308 9 + system_stm32g0xx.o 292 64 4 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (7 objects) 7 868 2 139 4 193 + --------------------------------------------- ---------- ---------- ---------- ---------- + libc_v6m_t_le_eabi_small.a 2 042 59 1 160 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (1 archives) 2 042 59 1 160 + --------------------------------------------- ---------- ---------- ---------- ---------- + Linker created (shared data, fills, blocks): 36 4 096 + ============================================= ========== ========== ========== ========== + Total: 9 910 2 234 4 5 449 + ============================================= ========== ========== ========== ========== + +Memory use by archive: + + Archive member RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) 432 20 1 160 + __SEGGER_RTL_vfprintf_int.o (libc_v6m_t_le_eabi_small.a) + 1 180 39 + intasmops_arm.o (libc_v6m_t_le_eabi_small.a) 40 + prinops.o (libc_v6m_t_le_eabi_small.a) 222 + prinops_scanops_rtt.o (libc_v6m_t_le_eabi_small.a) + 86 + strasmops_arm.o (libc_v6m_t_le_eabi_small.a) 62 + strops.o (libc_v6m_t_le_eabi_small.a) 20 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (7 members from 1 archives) 2 042 59 1 160 + Objects (7 files) 7 868 2 139 4 193 + Linker created (shared data, fills, blocks): 36 4 096 + ============================================= ========== ========== ========== ========== + Total: 9 910 2 234 4 5 449 + ============================================= ========== ========== ========== ========== + +Detailed memory use by linker: + + Description RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + Initialization table 36 + Memory for block 'stack' 4 096 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (linker created): 36 4 096 + --------------------------------------------- ---------- ---------- ---------- ---------- + Objects (7 files) 7 868 2 139 4 193 + Archives (1 files) 2 042 59 1 160 + ============================================= ========== ========== ========== ========== + Total: 9 910 2 234 4 5 449 + ============================================= ========== ========== ========== ========== + + +*********************************************************************************************** +*** *** +*** SECTION DETAIL *** +*** *** +*********************************************************************************************** + +Sections by address: + + Range Symbol or [section] Name Size Al Init Ac Object File + ----------------- ------------------------- ---------- -- ---- -- ----------- + 08000000-080000bf _vectors 192 512 + Code RX STM32G07x_Vectors.o + 080000c0-080000cf FW_VERSION 16 16 Cnst RO main.o + 080000d0-080000df SystemInit 16 4 Code RX system_stm32g0xx.o + 080000e0-080001f3 SystemCoreClockUpdate 276 4 Code RX system_stm32g0xx.o + 080001f4-08000233 AHBPrescTable 64 4 Cnst RO system_stm32g0xx.o + 08000234-08000e03 main 3 024 4 Code RX main.o + 08000e04-080010ab Init 680 4 Code RX main.o + 080010ac-080011eb WaitForByte 320 4 Code RX main.o + 080011ec-0800130b JumpToApplication 288 4 Code RX main.o + 0800130c-08001393 Transmit 136 4 Code RX main.o + 08001394-080013bf FLASH_Program_DoubleWord 44 4 Code RX main.o + 080013c0-080013e3 Delay 36 4 Code RX main.o + 080013e4-08001433 TurnErrorLEDOn 80 4 Code RX main.o + 08001434-08001443 SysTick_Handler 16 4 Code RX main.o + 08001444-0800148f SysTick_Config 76 4 Code RX main.o + 08001490-08001513 __NVIC_SetPriority 132 4 Code RX main.o + 08001514-08001547 AES128_ECB_decrypt 52 4 Code RX aes.o + 08001548-0800167b KeyExpansion 308 4 Code RX aes.o + 0800167c-08001693 getSBoxValue 24 4 Code RX aes.o + 08001694-080016fb AddRoundKey 104 4 Code RX aes.o + 080016fc-0800176b InvShiftRows 112 4 Code RX aes.o + 0800176c-080017d7 InvSubBytes 108 4 Code RX aes.o + 080017d8-08001d8f InvMixColumns 1 464 4 Code RX aes.o + 08001d90-08001da7 getSBoxInvert 24 4 Code RX aes.o + 08001da8-08001def printf_rtt 72 4 Code RX prinops_scanops_rtt.o (libc_v6m_t_le_eabi_small.a) + 08001df0-08001e4f _DoInit 96 4 Code RX SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 08001e50-08001ebb SEGGER_RTT_WriteNoLock 108 4 Code RX SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 08001ebc-08001ef3 SEGGER_RTT_Write 56 4 Code RX SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 08001ef4-0800238f __SEGGER_RTL_vfprintf_int 1 180 4 Code RX __SEGGER_RTL_vfprintf_int.o (libc_v6m_t_le_eabi_small.a) + 08002390-080023a3 _start 20 4 Code RX SEGGER_THUMB_Startup.o + 080023a4-080023a9 reset_handler 6 2 Code RX STM32G0xx_Startup.o + 080023aa-080023ab SVC_Handler 2 2 Code RX STM32G07x_Vectors.o + 080023ac-080023ad PendSV_Handler 2 2 Code RX STM32G07x_Vectors.o + 080023ae-080023af WWDG_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023b0-080023b1 PVD_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023b2-080023b3 RTC_STAMP_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023b4-080023b5 FLASH_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023b6-080023b7 RCC_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023b8-080023b9 EXTI0_1_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023ba-080023bb EXTI2_3_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023bc-080023bd EXTI4_15_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023be-080023bf UCPD1_UCPD2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023c0-080023c1 DMA_Channel1_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023c2-080023c3 DMA_Channel2_3_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023c4-080023c5 DMA_Channel4_5_6_7_IRQHandler + 2 2 Code RX STM32G07x_Vectors.o + 080023c6-080023c7 ADC_COMP_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023c8-080023c9 TIM1_BRK_UP_TRG_COMP_IRQHandler + 2 2 Code RX STM32G07x_Vectors.o + 080023ca-080023cb TIM1_CC_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023cc-080023cd TIM2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023ce-080023cf TIM3_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023d0-080023d1 TIM6_DAC_LPTIM1_IRQHandler + 2 2 Code RX STM32G07x_Vectors.o + 080023d2-080023d3 TIM7_LPTIM2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023d4-080023d5 TIM14_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023d6-080023d7 TIM15_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023d8-080023d9 TIM16_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023da-080023db TIM17_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023dc-080023dd I2C1_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023de-080023df I2C2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023e0-080023e1 SPI1_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023e2-080023e3 SPI2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023e4-080023e5 USART1_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023e6-080023e7 USART2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023e8-080023e9 USART3_USART4_LPUART1_IRQHandler + 2 2 Code RX STM32G07x_Vectors.o + 080023ea-080023eb CEC_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023ec-080023ed AES_RNG_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 080023ee-080023fb NMI_Handler 14 2 Code RX main.o + 080023fc-08002429 BlockCopy 46 2 Code RX aes.o + 0800242a-0800247b InvCipher 82 2 Code RX aes.o + 0800247c-08002495 xtime 26 2 Code RX aes.o + 08002496-080024a3 strcpy 14 2 Code RX strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 080024a4-080024b1 strlen 14 2 Code RX strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 080024b2-080024bf memcpy 14 2 Code RX strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 080024c0-080024cd __SEGGER_RTL_stdout_write 14 2 Code RX prinops_scanops_rtt.o (libc_v6m_t_le_eabi_small.a) + 080024ce-080024e3 _GetAvailWriteSpace 22 2 Code RX SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 080024e4-0800251d _WriteNoCheck 58 2 Code RX SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 0800251e-080025a3 __SEGGER_RTL_putc 134 2 Code RX prinops.o (libc_v6m_t_le_eabi_small.a) + 080025a4-080025bd __SEGGER_RTL_print_padding + 26 2 Code RX prinops.o (libc_v6m_t_le_eabi_small.a) + 080025be-080025d3 __SEGGER_RTL_pre_padding 22 2 Code RX prinops.o (libc_v6m_t_le_eabi_small.a) + 080025d4-080025e7 TransmitACK 20 2 Code RX main.o + 080025e8-080025fb TransmitNACK 20 2 Code RX main.o + 080025fc-0800260b HardFault_Handler 16 2 Code RX main.o + 0800260c-08002633 __aeabi_uidiv 40 2 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 08002634-08002647 __aeabi_memclr 20 2 Code RX strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 08002648-0800265b strnlen 20 2 Code RX strops.o (libc_v6m_t_le_eabi_small.a) + 0800265c-080026b7 _WriteBlocking 92 2 Code RX SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 080026b8-080026d3 __SEGGER_RTL_prin_flush 28 2 Code RX prinops.o (libc_v6m_t_le_eabi_small.a) + 080026d4-080026df __SEGGER_RTL_init_prin 12 2 Code RX prinops.o (libc_v6m_t_le_eabi_small.a) + 080026e0-080026f2 [.rodata..L.str.6] 19 1 Cnst RO main.o + 080026f3-08002709 [.rodata..L.str.7] 23 1 Cnst RO main.o + 0800270a-0800271c [.rodata..L.str.13] 19 1 Cnst RO main.o + 0800271d-08002733 [.rodata..L.str.16] 23 1 Cnst RO main.o + 08002734-0800275e [.rodata..L.str.17] 43 1 Cnst RO main.o + 0800275f-08002779 [.rodata..L.str.26] 27 1 Cnst RO main.o + 0800277a-080027b4 [.rodata..L.str.27] 59 1 Cnst RO main.o + 080027b5-080027cf [.rodata..L.str.29] 27 1 Cnst RO main.o + 080027d0-080027ee [.rodata..L.str.30] 31 1 Cnst RO main.o + 080027ef-080027fd [.rodata..L.str.46] 15 1 Cnst RO main.o + 080027fe-080028fc Rcon 255 1 Cnst RO aes.o + 080028fd-08002903 [.rodata.libc..L.str.2] 7 1 Cnst RO SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 08002904-0800290a [.rodata.libc..L.str] 7 1 Cnst RO __SEGGER_RTL_vfprintf_int.o (libc_v6m_t_le_eabi_small.a) + 0800290b-08002928 [.rodata..L.str.10] 30 1 Cnst RO main.o + 08002929-08002946 [.rodata..L.str.11] 30 1 Cnst RO main.o + 08002947-0800295c [.rodata..L.str.12] 22 1 Cnst RO main.o + 0800295d-0800295e [.rodata..L.str.15] 2 1 Cnst RO main.o + 0800295f-0800297c [.rodata..L.str.19] 30 1 Cnst RO main.o + 0800297d-08002996 [.rodata..L.str.20] 26 1 Cnst RO main.o + 08002997-080029b0 [.rodata..L.str.23] 26 1 Cnst RO main.o + 080029b1-080029d6 [.rodata..L.str.24] 38 1 Cnst RO main.o + 080029d7-08002a18 [.rodata..L.str.28] 66 1 Cnst RO main.o + 08002a19-08002a26 [.rodata..L.str.34] 14 1 Cnst RO main.o + 08002a27-08002a3c [.rodata..L.str.35] 22 1 Cnst RO main.o + 08002a3d-08002a5a [.rodata..L.str.38] 30 1 Cnst RO main.o + 08002a5b-08002a70 [.rodata..L.str.39] 22 1 Cnst RO main.o + 08002a71-08002a9a [.rodata..L.str.45] 42 1 Cnst RO main.o + 08002a9b-08002ac3 [.rodata..L.str.2] 41 1 Cnst RO main.o + 08002ac4-08002aec [.rodata..L.str.18] 41 1 Cnst RO main.o + 08002aed-08002b09 [.rodata..L.str.21] 29 1 Cnst RO main.o + 08002b0a-08002b1e [.rodata..L.str.31] 21 1 Cnst RO main.o + 08002b1f-08002b27 [.rodata..L.str.32] 9 1 Cnst RO main.o + 08002b28-08002b2c [.rodata..L.str.36] 5 1 Cnst RO main.o + 08002b2d-08002b31 [.rodata..L.str.37] 5 1 Cnst RO main.o + 08002b32-08002b4e [.rodata..L.str.41] 29 1 Cnst RO main.o + 08002b4f-08002b53 [.rodata..L.str.42] 5 1 Cnst RO main.o + 08002b54-08002b68 [.rodata..L.str.44] 21 1 Cnst RO main.o + 08002b69-08002b71 [.rodata.libc..L.str] 9 1 Cnst RO SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 08002b72-08002b73 ( UNUSED .=.+2 ) 2 - ---- - - + 08002b74-08002b77 [.init_array] 4 4 ---- -- STM32G0xx_Startup.o + 08002b78-08002b87 AES_KEY 16 1 Cnst RO main.o + 08002b88-08002bbb [.rodata..L.str] 52 1 Cnst RO main.o + 08002bbc-08002bc3 [.rodata..L.str.1] 8 1 Cnst RO main.o + 08002bc4-08002bcb [.rodata..L.str.3] 8 1 Cnst RO main.o + 08002bcc-08002bdf [.rodata..L.str.4] 20 1 Cnst RO main.o + 08002be0-08002c13 [.rodata..L.str.5] 52 1 Cnst RO main.o + 08002c14-08002c27 [.rodata..L.str.8] 20 1 Cnst RO main.o + 08002c28-08002c43 [.rodata..L.str.9] 28 1 Cnst RO main.o + 08002c44-08002c47 [.rodata..L.str.14] 4 1 Cnst RO main.o + 08002c48-08002c6f [.rodata..L.str.22] 40 1 Cnst RO main.o + 08002c70-08002c97 [.rodata..L.str.25] 40 1 Cnst RO main.o + 08002c98-08002cab [.rodata..L.str.33] 20 1 Cnst RO main.o + 08002cac-08002cc7 [.rodata..L.str.40] 28 1 Cnst RO main.o + 08002cc8-08002cdf [.rodata..L.str.43] 24 1 Cnst RO main.o + 08002ce0-08002cff [.rodata..L.str.47] 32 1 Cnst RO main.o + 08002d00-08002d07 [.rodata..L.str.48] 8 1 Cnst RO main.o + 08002d08-08002e07 sbox 256 1 Cnst RO aes.o + 08002e08-08002f07 rsbox 256 1 Cnst RO aes.o + 08002f08-08002f0b [.rodata.libc..L.str.1] 4 1 Cnst RO SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 08002f0c-08002f1b __SEGGER_RTL_hex_uc 16 1 Cnst RO __SEGGER_RTL_vfprintf_int.o (libc_v6m_t_le_eabi_small.a) + 08002f1c-08002f2b __SEGGER_RTL_hex_lc 16 1 Cnst RO __SEGGER_RTL_vfprintf_int.o (libc_v6m_t_le_eabi_small.a) + 08002f2c-08002f4b __SEGGER_init_table__ 32 4 Cnst RO [ Linker created ] + 08002f4c-08002f4f __SEGGER_init_data__ 4 4 Cnst RO [ Linker created ] + 08002f50-08002f61 __SEGGER_init_zero 18 2 Code RX SEGGER_crtinit_v6m_little.o + 08002f62-08002f75 __SEGGER_init_copy 20 2 Code RX SEGGER_crtinit_v6m_little.o + 08002f76-1fffffff ( UNUSED .=.+402641034 ) 402 641 034 + - ---- - - + 20000000-20000003 SystemCoreClock 4 4 Init RW system_stm32g0xx.o + 20000004-2000007b _SEGGER_RTT 120 4 Zero ZI SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 2000007c-2000007f state 4 4 Zero ZI aes.o + 20000080-20000083 msCounter 4 4 Zero ZI main.o + 20000084-20000087 Key 4 4 Zero ZI aes.o + 20000088-20000487 _acUpBuffer 1 024 1 Zero ZI SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 20000488-20000537 RoundKey 176 1 Zero ZI aes.o + 20000538-20000547 _acDownBuffer 16 1 Zero ZI SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 20000548-2000054c u 5 1 Zero ZI main.o + 2000054d-20006fff ( UNUSED .=.+27315 ) 27 315 - ---- - - + 20007000-20007fff [.bss.block.stack] 4 096 8 None ZI [ Linker created ] + + +*********************************************************************************************** +*** *** +*** SYMBOL LIST *** +*** *** +*********************************************************************************************** + +Function symbols by name and then by address: + + Symbol name Address Size Align Type Bd Object File + ------------------------- ---------- ---------- ----- ---- -- ----------- + ADC_COMP_IRQHandler 0x080023C7 2 Code Wk STM32G07x_Vectors.o + AES128_ECB_decrypt 0x08001515 52 4 Code Gb aes.o + AES_RNG_IRQHandler 0x080023ED 2 Code Wk STM32G07x_Vectors.o + AddRoundKey 0x08001695 104 4 Code Lc aes.o + BlockCopy 0x080023FD 46 2 Code Lc aes.o + CEC_IRQHandler 0x080023EB 2 Code Wk STM32G07x_Vectors.o + DMA_Channel1_IRQHandler 0x080023C1 2 Code Wk STM32G07x_Vectors.o + DMA_Channel2_3_IRQHandler 0x080023C3 2 Code Wk STM32G07x_Vectors.o + DMA_Channel4_5_6_7_IRQHandler + 0x080023C5 2 Code Wk STM32G07x_Vectors.o + Delay 0x080013C1 36 4 Code Gb main.o + EXTI0_1_IRQHandler 0x080023B9 2 Code Wk STM32G07x_Vectors.o + EXTI2_3_IRQHandler 0x080023BB 2 Code Wk STM32G07x_Vectors.o + EXTI4_15_IRQHandler 0x080023BD 2 Code Wk STM32G07x_Vectors.o + FLASH_IRQHandler 0x080023B5 2 Code Wk STM32G07x_Vectors.o + FLASH_Program_DoubleWord 0x08001395 44 4 Code Gb main.o + HardFault_Handler 0x080025FD 16 2 Code Gb main.o + I2C1_IRQHandler 0x080023DD 2 Code Wk STM32G07x_Vectors.o + I2C2_IRQHandler 0x080023DF 2 Code Wk STM32G07x_Vectors.o + Init 0x08000E05 680 4 Code Gb main.o + InvCipher 0x0800242B 82 2 Code Lc aes.o + InvMixColumns 0x080017D9 1 464 4 Code Lc aes.o + InvShiftRows 0x080016FD 112 4 Code Lc aes.o + InvSubBytes 0x0800176D 108 4 Code Lc aes.o + JumpToApplication 0x080011ED 288 4 Code Gb main.o + KeyExpansion 0x08001549 308 4 Code Lc aes.o + NMI_Handler 0x080023EF 14 2 Code Gb main.o + PVD_IRQHandler 0x080023B1 2 Code Wk STM32G07x_Vectors.o + PendSV_Handler 0x080023AD 2 Code Wk STM32G07x_Vectors.o + RCC_IRQHandler 0x080023B7 2 Code Wk STM32G07x_Vectors.o + RTC_STAMP_IRQHandler 0x080023B3 2 Code Wk STM32G07x_Vectors.o + Reset_Handler 0x080023A5 2 Code Gb STM32G0xx_Startup.o + SEGGER_RTT_Write 0x08001EBD 56 4 Code Gb SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + SEGGER_RTT_WriteNoLock 0x08001E51 108 4 Code Gb SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + SPI1_IRQHandler 0x080023E1 2 Code Wk STM32G07x_Vectors.o + SPI2_IRQHandler 0x080023E3 2 Code Wk STM32G07x_Vectors.o + SVC_Handler 0x080023AB 2 Code Wk STM32G07x_Vectors.o + SysTick_Config 0x08001445 76 4 Code Lc main.o + SysTick_Handler 0x08001435 16 4 Code Gb main.o + SystemCoreClockUpdate 0x080000E1 276 4 Code Gb system_stm32g0xx.o + SystemInit 0x080000D1 16 4 Code Gb system_stm32g0xx.o + TIM14_IRQHandler 0x080023D5 2 Code Wk STM32G07x_Vectors.o + TIM15_IRQHandler 0x080023D7 2 Code Wk STM32G07x_Vectors.o + TIM16_IRQHandler 0x080023D9 2 Code Wk STM32G07x_Vectors.o + TIM17_IRQHandler 0x080023DB 2 Code Wk STM32G07x_Vectors.o + TIM1_BRK_UP_TRG_COMP_IRQHandler + 0x080023C9 2 Code Wk STM32G07x_Vectors.o + TIM1_CC_IRQHandler 0x080023CB 2 Code Wk STM32G07x_Vectors.o + TIM2_IRQHandler 0x080023CD 2 Code Wk STM32G07x_Vectors.o + TIM3_IRQHandler 0x080023CF 2 Code Wk STM32G07x_Vectors.o + TIM6_DAC_LPTIM1_IRQHandler + 0x080023D1 2 Code Wk STM32G07x_Vectors.o + TIM7_LPTIM2_IRQHandler 0x080023D3 2 Code Wk STM32G07x_Vectors.o + Transmit 0x0800130D 136 4 Code Gb main.o + TransmitACK 0x080025D5 20 2 Code Gb main.o + TransmitNACK 0x080025E9 20 2 Code Gb main.o + TurnErrorLEDOn 0x080013E5 80 4 Code Gb main.o + UCPD1_UCPD2_IRQHandler 0x080023BF 2 Code Wk STM32G07x_Vectors.o + USART1_IRQHandler 0x080023E5 2 Code Wk STM32G07x_Vectors.o + USART2_IRQHandler 0x080023E7 2 Code Wk STM32G07x_Vectors.o + USART3_USART4_LPUART1_IRQHandler + 0x080023E9 2 Code Wk STM32G07x_Vectors.o + WWDG_IRQHandler 0x080023AF 2 Code Wk STM32G07x_Vectors.o + WaitForByte 0x080010AD 320 4 Code Gb main.o + _DoInit 0x08001DF1 96 4 Code Lc SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + _GetAvailWriteSpace 0x080024CF 22 2 Code Lc SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + _WriteBlocking 0x0800265D 92 2 Code Lc SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + _WriteNoCheck 0x080024E5 58 2 Code Lc SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + __NVIC_SetPriority 0x08001491 132 4 Code Lc main.o + __SEGGER_RTL_init_prin 0x080026D5 12 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_pre_padding 0x080025BF 22 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_prin_flush 0x080026B9 28 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_print_padding + 0x080025A5 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_putc 0x0800251F 134 2 Code Gb prinops.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_stdout_write 0x080024C1 14 2 Code Lc prinops_scanops_rtt.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_vfprintf 0x08001EF5 1 180 4 Code Gb __SEGGER_RTL_vfprintf_int.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_RTL_vfprintf_int 0x08001EF5 1 180 4 Code Gb __SEGGER_RTL_vfprintf_int.o (libc_v6m_t_le_eabi_small.a) + __SEGGER_init_copy 0x08002F63 20 2 Code Wk SEGGER_crtinit_v6m_little.o + __SEGGER_init_done 0x0800239B 4 Code Gb SEGGER_THUMB_Startup.o + __SEGGER_init_zero 0x08002F51 18 2 Code Wk SEGGER_crtinit_v6m_little.o + __aeabi_memclr 0x08002635 20 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memclr4 0x08002635 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memclr8 0x08002635 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memcpy 0x080024B3 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memcpy4 0x080024B3 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memcpy8 0x080024B3 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memset 0x08002637 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memset4 0x08002637 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memset8 0x08002637 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_uidiv 0x0800260D 40 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + _start 0x08002391 4 Code Gb SEGGER_THUMB_Startup.o + exit 0x0800239F 4 Code Gb SEGGER_THUMB_Startup.o + getSBoxInvert 0x08001D91 24 4 Code Lc aes.o + getSBoxValue 0x0800167D 24 4 Code Lc aes.o + main 0x08000235 3 024 4 Code Gb main.o + memcpy 0x080024B3 14 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + memset 0x0800263D 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + printf 0x08001DA9 72 4 Code Gb prinops_scanops_rtt.o (libc_v6m_t_le_eabi_small.a) + printf_rtt 0x08001DA9 72 4 Code Gb prinops_scanops_rtt.o (libc_v6m_t_le_eabi_small.a) + reset_handler 0x080023A5 2 Code Gb STM32G0xx_Startup.o + strcpy 0x08002497 14 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + strlen 0x080024A5 14 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + strnlen 0x08002649 20 2 Code Wk strops.o (libc_v6m_t_le_eabi_small.a) + xtime 0x0800247D 26 2 Code Lc aes.o + +Function symbols by address and then by name: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x080000D1 SystemInit 16 4 Code Gb system_stm32g0xx.o + 0x080000E1 SystemCoreClockUpdate 276 4 Code Gb system_stm32g0xx.o + 0x08000235 main 3 024 4 Code Gb main.o + 0x08000E05 Init 680 4 Code Gb main.o + 0x080010AD WaitForByte 320 4 Code Gb main.o + 0x080011ED JumpToApplication 288 4 Code Gb main.o + 0x0800130D Transmit 136 4 Code Gb main.o + 0x08001395 FLASH_Program_DoubleWord 44 4 Code Gb main.o + 0x080013C1 Delay 36 4 Code Gb main.o + 0x080013E5 TurnErrorLEDOn 80 4 Code Gb main.o + 0x08001435 SysTick_Handler 16 4 Code Gb main.o + 0x08001445 SysTick_Config 76 4 Code Lc main.o + 0x08001491 __NVIC_SetPriority 132 4 Code Lc main.o + 0x08001515 AES128_ECB_decrypt 52 4 Code Gb aes.o + 0x08001549 KeyExpansion 308 4 Code Lc aes.o + 0x0800167D getSBoxValue 24 4 Code Lc aes.o + 0x08001695 AddRoundKey 104 4 Code Lc aes.o + 0x080016FD InvShiftRows 112 4 Code Lc aes.o + 0x0800176D InvSubBytes 108 4 Code Lc aes.o + 0x080017D9 InvMixColumns 1 464 4 Code Lc aes.o + 0x08001D91 getSBoxInvert 24 4 Code Lc aes.o + 0x08001DA9 printf 72 4 Code Gb prinops_scanops_rtt.o (libc_v6m_t_le_eabi_small.a) + 0x08001DA9 printf_rtt 72 4 Code Gb prinops_scanops_rtt.o (libc_v6m_t_le_eabi_small.a) + 0x08001DF1 _DoInit 96 4 Code Lc SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 0x08001E51 SEGGER_RTT_WriteNoLock 108 4 Code Gb SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 0x08001EBD SEGGER_RTT_Write 56 4 Code Gb SEGGER_RTT.o (libc_v6m_t_le_eabi_small.a) + 0x08001EF5 __SEGGER_RTL_vfprintf 1 180 4 Code Gb __SEGGER_RTL_vfprintf_int.o (libc_v6m_t_le_eabi_small.a) + 0x08001EF5 __SEGGER_RTL_vfprintf_int 1 180 4 Code Gb __SEGGER_RTL_vfprintf_int.o (libc_v6m_t_le_eabi_small.a) + 0x08002391 _start 4 Code Gb SEGGER_THUMB_Startup.o + 0x0800239B __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + 0x0800239F exit 4 Code Gb SEGGER_THUMB_Startup.o + 0x080023A5 Reset_Handler 2 Code Gb STM32G0xx_Startup.o + 0x080023A5 reset_handler 2 Code Gb STM32G0xx_Startup.o + 0x080023AB SVC_Handler 2 Code Wk STM32G07x_Vectors.o + 0x080023AD PendSV_Handler 2 Code Wk STM32G07x_Vectors.o + 0x080023AF WWDG_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x080023B1 PVD_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x080023B3 RTC_STAMP_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x080023B5 FLASH_IRQHandler 2 Code Wk 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__FLASH1_segment_end__ ---- Gb [ Linker created ] + 0x08003000 __FLASH_segment_end__ ---- Gb [ Linker created ] + 0x20000000 __RAM1_segment_start__ ---- Gb [ Linker created ] + 0x20000000 __RAM1_segment_used_start__ + ---- Gb [ Linker created ] + 0x20000000 __RAM_segment_start__ ---- Gb [ Linker created ] + 0x20000000 __RAM_segment_used_start__ + ---- Gb [ Linker created ] + 0x20008000 __RAM1_segment_end__ ---- Gb [ Linker created ] + 0x20008000 __RAM1_segment_used_end__ ---- Gb [ Linker created ] + 0x20008000 __RAM_segment_end__ ---- Gb [ Linker created ] + 0x20008000 __RAM_segment_used_end__ ---- Gb [ Linker created ] + 0x20008000 __stack_end__ ---- Gb [ Linker created ] + + +*********************************************************************************************** +*** *** +*** LINK SUMMARY *** +*** *** +*********************************************************************************************** + +Memory breakdown: + + 9 910 bytes read-only code + 2 234 bytes read-only data + 5 453 bytes read-write data + +Region summary: + + Name Range Size Used Unused Alignment Loss + ---------- ----------------- ---------- ------------------ ------------------ ------------------ + FLASH 08000000-08002fff 12 288 12 148 98.86% 140 1.14% 0 0.00% + RAM 20000000-20007fff 32 768 5 453 16.64% 27 315 83.36% 0 0.00% + +Link complete: 0 errors, 0 warnings, 0 remarks Index: ecs_cellMon/Bootloader/SES/Output/Debug/Obj/SEGGER_THUMB_Startup.d =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Debug/Obj/SEGGER_THUMB_Startup.d (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Debug/Obj/SEGGER_THUMB_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/SEGGER_THUMB_Startup.o: \ + D\:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\SEGGER_THUMB_Startup.s Index: ecs_cellMon/Bootloader/SES/Output/Debug/Obj/STM32G07x_Vectors.d =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Debug/Obj/STM32G07x_Vectors.d (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Debug/Obj/STM32G07x_Vectors.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/STM32G07x_Vectors.o: \ + D\:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\Source\STM32G07x_Vectors.s Index: ecs_cellMon/Bootloader/SES/Output/Debug/Obj/STM32G0xx_Startup.d =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Debug/Obj/STM32G0xx_Startup.d (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Debug/Obj/STM32G0xx_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/STM32G0xx_Startup.o: \ + D\:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\Source\STM32G0xx_Startup.s Index: ecs_cellMon/Bootloader/SES/Output/Debug/Obj/aes.d =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Debug/Obj/aes.d (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Debug/Obj/aes.d (revision 3) @@ -0,0 +1,7 @@ +Output/Debug/Obj/aes.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\aes.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40c\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40c\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40c\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40c\segger-rtl\include\__SEGGER_RTL_Conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\aes.h Index: ecs_cellMon/Bootloader/SES/Output/Debug/Obj/bootloader.ind =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Debug/Obj/bootloader.ind (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Debug/Obj/bootloader.ind (revision 3) @@ -0,0 +1,8 @@ +"Output/Debug/Obj/system_stm32g0xx.o" +"Output/Debug/Obj/main.o" +"Output/Debug/Obj/aes.o" +"Output/Debug/Obj/SEGGER_THUMB_Startup.o" +"Output/Debug/Obj/STM32G0xx_Startup.o" +"Output/Debug/Obj/STM32G07x_Vectors.o" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.50a/segger-rtl/libs/libc_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.50a/lib/SEGGER_crtinit_v6m_little.o" Index: ecs_cellMon/Bootloader/SES/Output/Debug/Obj/main.d =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Debug/Obj/main.d (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Debug/Obj/main.d (revision 3) @@ -0,0 +1,23 @@ +Output/Debug/Obj/main.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\main.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\string.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\RTT\SEGGER_RTT.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\RTT\SEGGER_RTT_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\stdlib.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\stdarg.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\aes.h Index: ecs_cellMon/Bootloader/SES/Output/Debug/Obj/system_stm32g0xx.d =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Debug/Obj/system_stm32g0xx.d (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Debug/Obj/system_stm32g0xx.d (revision 3) @@ -0,0 +1,14 @@ +Output/Debug/Obj/system_stm32g0xx.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Source\system_stm32g0xx.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40c\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40c\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40c\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40c\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h Index: ecs_cellMon/Bootloader/SES/Output/Release/Exe/bootloader.hex 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+:1010C400F51000080400002005000000F5100008D9 +:1010D4000C000020BC0000000711000800000020E4 +:0C10E400F010000804000000DB0C000805 +:0410F0000024F400E4 +:1010F400206861680834002200E042540139FCD5BC +:02110400704732 +:1011060020686168A2680C3401E08B5C8354013A64 +:04111600FBD570474E +:0400000508000CE5FE +:00000001FF Index: ecs_cellMon/Bootloader/SES/Output/Release/Exe/bootloader.map =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Release/Exe/bootloader.map (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Release/Exe/bootloader.map (revision 3) @@ -0,0 +1,487 @@ +*********************************************************************************************** +*** *** +*** LINK INFORMATION *** +*** *** +*********************************************************************************************** + +Linker version: + + SEGGER ARM Linker 4.10.1 compiled Jun 4 2021 19:08:05 + Copyright (c) 2017-2021 SEGGER Microcontroller GmbH www.segger.com + + +*********************************************************************************************** +*** *** +*** MODULE SUMMARY *** +*** *** +*********************************************************************************************** + +Memory use by input file: + + Object File RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + SEGGER_THUMB_Startup.o 20 + SEGGER_crtinit_v6m_little.o 38 + STM32G07x_Vectors.o 260 + STM32G0xx_Startup.o 6 + aes.o 768 767 184 + main.o 2 154 32 9 + system_stm32g0xx.o 156 64 4 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (7 objects) 3 402 863 4 193 + --------------------------------------------- ---------- ---------- ---------- ---------- + libc_v6m_t_le_eabi_small.a 60 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (1 archives) 60 + --------------------------------------------- ---------- ---------- ---------- ---------- + Linker created (shared data, fills, blocks): 48 4 096 + ============================================= ========== ========== ========== ========== + Total: 3 462 911 4 4 289 + ============================================= ========== ========== ========== ========== + +Memory use by archive: + + Archive member RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + intasmops_arm.o (libc_v6m_t_le_eabi_small.a) 40 + strasmops_arm.o (libc_v6m_t_le_eabi_small.a) 20 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (2 members from 1 archives) 60 + Objects (7 files) 3 402 863 4 193 + Linker created (shared data, fills, blocks): 48 4 096 + ============================================= ========== ========== ========== ========== + Total: 3 462 911 4 4 289 + ============================================= ========== ========== ========== ========== + +Detailed memory use by linker: + + Description RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + Initialization table 48 + Memory for block 'stack' 4 096 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (linker created): 48 4 096 + --------------------------------------------- ---------- ---------- ---------- ---------- + Objects (7 files) 3 402 863 4 193 + Archives (1 files) 60 + ============================================= ========== ========== ========== ========== + Total: 3 462 911 4 4 289 + ============================================= ========== ========== ========== ========== + + +*********************************************************************************************** +*** *** +*** SECTION DETAIL *** +*** *** +*********************************************************************************************** + +Sections by address: + + Range Symbol or [section] Name Size Al Init Ac Object File + ----------------- ------------------------- ---------- -- ---- -- ----------- + 08000000-080000bf _vectors 192 512 + Code RX STM32G07x_Vectors.o + 080000c0-080000cf FW_VERSION 16 16 Cnst RO main.o + 080000d0-080000df SystemInit 16 4 Code RX system_stm32g0xx.o + 080000e0-0800016b SystemCoreClockUpdate 140 4 Code RX system_stm32g0xx.o + 0800016c-080001ab AHBPrescTable 64 4 Cnst RO system_stm32g0xx.o + 080001ac-0800061b main 1 136 4 Code RX main.o + 0800061c-08000813 Init 504 4 Code RX main.o + 08000814-080008a7 WaitForByte 148 4 Code RX main.o + 080008a8-0800093f JumpToApplication 152 4 Code RX main.o + 08000940-0800095f Transmit 32 4 Code RX main.o + 08000960-080009a3 TurnErrorLEDOn 68 4 Code RX main.o + 080009a4-080009bf Delay 28 4 Code RX main.o + 080009c0-080009cf SysTick_Handler 16 4 Code RX main.o + 080009d0-08000c2b AES128_ECB_decrypt 604 4 Code RX aes.o + 08000c2c-08000c63 AddRoundKey 56 4 Code RX aes.o + 08000c64-08000c9f InvShiftRows 60 4 Code RX aes.o + 08000ca0-08000ccf InvSubBytes 48 4 Code RX aes.o + 08000cd0-08000ce3 _start 20 4 Code RX SEGGER_THUMB_Startup.o + 08000ce4-08000ce9 reset_handler 6 2 Code RX STM32G0xx_Startup.o + 08000cea-08000ceb SVC_Handler 2 2 Code RX STM32G07x_Vectors.o + 08000cec-08000ced PendSV_Handler 2 2 Code RX STM32G07x_Vectors.o + 08000cee-08000cef WWDG_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000cf0-08000cf1 PVD_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000cf2-08000cf3 RTC_STAMP_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000cf4-08000cf5 FLASH_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000cf6-08000cf7 RCC_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000cf8-08000cf9 EXTI0_1_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000cfa-08000cfb EXTI2_3_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000cfc-08000cfd EXTI4_15_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000cfe-08000cff UCPD1_UCPD2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d00-08000d01 DMA_Channel1_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d02-08000d03 DMA_Channel2_3_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d04-08000d05 DMA_Channel4_5_6_7_IRQHandler + 2 2 Code RX STM32G07x_Vectors.o + 08000d06-08000d07 ADC_COMP_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d08-08000d09 TIM1_BRK_UP_TRG_COMP_IRQHandler + 2 2 Code RX STM32G07x_Vectors.o + 08000d0a-08000d0b TIM1_CC_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d0c-08000d0d TIM2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d0e-08000d0f TIM3_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d10-08000d11 TIM6_DAC_LPTIM1_IRQHandler + 2 2 Code RX STM32G07x_Vectors.o + 08000d12-08000d13 TIM7_LPTIM2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d14-08000d15 TIM14_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d16-08000d17 TIM15_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d18-08000d19 TIM16_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d1a-08000d1b TIM17_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d1c-08000d1d I2C1_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d1e-08000d1f I2C2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d20-08000d21 SPI1_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d22-08000d23 SPI2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d24-08000d25 USART1_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d26-08000d27 USART2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d28-08000d29 USART3_USART4_LPUART1_IRQHandler + 2 2 Code RX STM32G07x_Vectors.o + 08000d2a-08000d2b CEC_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d2c-08000d2d AES_RNG_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 08000d2e-08000d3b NMI_Handler 14 2 Code RX main.o + 08000d3c-08000d4f TransmitACK 20 2 Code RX main.o + 08000d50-08000d63 TransmitNACK 20 2 Code RX main.o + 08000d64-08000d73 HardFault_Handler 16 2 Code RX main.o + 08000d74-08000d9b __aeabi_uidiv 40 2 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 08000d9c-08000daf __aeabi_memclr 20 2 Code RX strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 08000db0-08000eae Rcon 255 1 Cnst RO aes.o + 08000eaf-08000eaf ( UNUSED .=.+1 ) 1 - ---- - - + 08000eb0-08000eb3 [.init_array] 4 4 ---- -- STM32G0xx_Startup.o + 08000eb4-08000ec3 AES_KEY 16 1 Cnst RO main.o + 08000ec4-08000fc3 sbox 256 1 Cnst RO aes.o + 08000fc4-080010c3 rsbox 256 1 Cnst RO aes.o + 080010c4-080010ef __SEGGER_init_table__ 44 4 Cnst RO [ Linker created ] + 080010f0-080010f3 __SEGGER_init_data__ 4 4 Cnst RO [ Linker created ] + 080010f4-08001105 __SEGGER_init_zero 18 2 Code RX SEGGER_crtinit_v6m_little.o + 08001106-08001119 __SEGGER_init_copy 20 2 Code RX SEGGER_crtinit_v6m_little.o + 0800111a-1fffffff ( UNUSED .=.+402648806 ) 402 648 806 + - ---- - - + 20000000-20000003 SystemCoreClock 4 4 Init RW system_stm32g0xx.o + 20000004-20000008 u 5 4 Zero ZI main.o + 20000009-2000000b ( ALIGN .=.+3 ) 3 - ---- - - + 2000000c-2000000f state 4 4 Zero ZI aes.o + 20000010-20000013 msCounter 4 4 Zero ZI main.o + 20000014-20000017 Key 4 4 Zero ZI aes.o + 20000018-200000c7 RoundKey 176 1 Zero ZI aes.o + 200000c8-20006fff ( UNUSED .=.+28472 ) 28 472 - ---- - - + 20007000-20007fff [.bss.block.stack] 4 096 8 None ZI [ Linker created ] + + +*********************************************************************************************** +*** *** +*** SYMBOL LIST *** +*** *** +*********************************************************************************************** + +Function symbols by name and then by address: + + Symbol name Address Size Align Type Bd Object File + ------------------------- ---------- ---------- ----- ---- -- ----------- + ADC_COMP_IRQHandler 0x08000D07 2 Code Wk STM32G07x_Vectors.o + AES128_ECB_decrypt 0x080009D1 604 4 Code Gb aes.o + AES_RNG_IRQHandler 0x08000D2D 2 Code Wk STM32G07x_Vectors.o + AddRoundKey 0x08000C2D 56 4 Code Lc aes.o + CEC_IRQHandler 0x08000D2B 2 Code Wk STM32G07x_Vectors.o + DMA_Channel1_IRQHandler 0x08000D01 2 Code Wk STM32G07x_Vectors.o + DMA_Channel2_3_IRQHandler 0x08000D03 2 Code Wk STM32G07x_Vectors.o + DMA_Channel4_5_6_7_IRQHandler + 0x08000D05 2 Code Wk STM32G07x_Vectors.o + Delay 0x080009A5 28 4 Code Gb main.o + EXTI0_1_IRQHandler 0x08000CF9 2 Code Wk STM32G07x_Vectors.o + EXTI2_3_IRQHandler 0x08000CFB 2 Code Wk STM32G07x_Vectors.o + EXTI4_15_IRQHandler 0x08000CFD 2 Code Wk STM32G07x_Vectors.o + FLASH_IRQHandler 0x08000CF5 2 Code Wk STM32G07x_Vectors.o + HardFault_Handler 0x08000D65 16 2 Code Gb main.o + I2C1_IRQHandler 0x08000D1D 2 Code Wk STM32G07x_Vectors.o + I2C2_IRQHandler 0x08000D1F 2 Code Wk STM32G07x_Vectors.o + Init 0x0800061D 504 4 Code Gb main.o + InvShiftRows 0x08000C65 60 4 Code Lc aes.o + InvSubBytes 0x08000CA1 48 4 Code Lc aes.o + JumpToApplication 0x080008A9 152 4 Code Gb main.o + NMI_Handler 0x08000D2F 14 2 Code Gb main.o + PVD_IRQHandler 0x08000CF1 2 Code Wk STM32G07x_Vectors.o + PendSV_Handler 0x08000CED 2 Code Wk STM32G07x_Vectors.o + RCC_IRQHandler 0x08000CF7 2 Code Wk STM32G07x_Vectors.o + RTC_STAMP_IRQHandler 0x08000CF3 2 Code Wk STM32G07x_Vectors.o + Reset_Handler 0x08000CE5 2 Code Gb STM32G0xx_Startup.o + SPI1_IRQHandler 0x08000D21 2 Code Wk STM32G07x_Vectors.o + SPI2_IRQHandler 0x08000D23 2 Code Wk STM32G07x_Vectors.o + SVC_Handler 0x08000CEB 2 Code Wk STM32G07x_Vectors.o + SysTick_Handler 0x080009C1 16 4 Code Gb main.o + SystemCoreClockUpdate 0x080000E1 140 4 Code Gb system_stm32g0xx.o + SystemInit 0x080000D1 16 4 Code Gb system_stm32g0xx.o + TIM14_IRQHandler 0x08000D15 2 Code Wk STM32G07x_Vectors.o + TIM15_IRQHandler 0x08000D17 2 Code Wk STM32G07x_Vectors.o + TIM16_IRQHandler 0x08000D19 2 Code Wk STM32G07x_Vectors.o + TIM17_IRQHandler 0x08000D1B 2 Code Wk STM32G07x_Vectors.o + TIM1_BRK_UP_TRG_COMP_IRQHandler + 0x08000D09 2 Code Wk STM32G07x_Vectors.o + TIM1_CC_IRQHandler 0x08000D0B 2 Code Wk STM32G07x_Vectors.o + TIM2_IRQHandler 0x08000D0D 2 Code Wk STM32G07x_Vectors.o + TIM3_IRQHandler 0x08000D0F 2 Code Wk STM32G07x_Vectors.o + TIM6_DAC_LPTIM1_IRQHandler + 0x08000D11 2 Code Wk STM32G07x_Vectors.o + TIM7_LPTIM2_IRQHandler 0x08000D13 2 Code Wk STM32G07x_Vectors.o + Transmit 0x08000941 32 4 Code Gb main.o + TransmitACK 0x08000D3D 20 2 Code Gb main.o + TransmitNACK 0x08000D51 20 2 Code Gb main.o + TurnErrorLEDOn 0x08000961 68 4 Code Gb main.o + UCPD1_UCPD2_IRQHandler 0x08000CFF 2 Code Wk STM32G07x_Vectors.o + USART1_IRQHandler 0x08000D25 2 Code Wk STM32G07x_Vectors.o + USART2_IRQHandler 0x08000D27 2 Code Wk STM32G07x_Vectors.o + USART3_USART4_LPUART1_IRQHandler + 0x08000D29 2 Code Wk STM32G07x_Vectors.o + WWDG_IRQHandler 0x08000CEF 2 Code Wk STM32G07x_Vectors.o + WaitForByte 0x08000815 148 4 Code Gb main.o + __SEGGER_init_copy 0x08001107 20 2 Code Wk SEGGER_crtinit_v6m_little.o + __SEGGER_init_done 0x08000CDB 4 Code Gb SEGGER_THUMB_Startup.o + __SEGGER_init_zero 0x080010F5 18 2 Code Wk SEGGER_crtinit_v6m_little.o + __aeabi_memclr 0x08000D9D 20 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memclr4 0x08000D9D 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memclr8 0x08000D9D 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memset 0x08000D9F 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memset4 0x08000D9F 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_memset8 0x08000D9F 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + __aeabi_uidiv 0x08000D75 40 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + _start 0x08000CD1 4 Code Gb SEGGER_THUMB_Startup.o + exit 0x08000CDF 4 Code Gb SEGGER_THUMB_Startup.o + main 0x080001AD 1 136 4 Code Gb main.o + memset 0x08000DA5 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + reset_handler 0x08000CE5 2 Code Gb STM32G0xx_Startup.o + +Function symbols by address and then by name: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x080000D1 SystemInit 16 4 Code Gb system_stm32g0xx.o + 0x080000E1 SystemCoreClockUpdate 140 4 Code Gb system_stm32g0xx.o + 0x080001AD main 1 136 4 Code Gb main.o + 0x0800061D Init 504 4 Code Gb main.o + 0x08000815 WaitForByte 148 4 Code Gb main.o + 0x080008A9 JumpToApplication 152 4 Code Gb main.o + 0x08000941 Transmit 32 4 Code Gb main.o + 0x08000961 TurnErrorLEDOn 68 4 Code Gb main.o + 0x080009A5 Delay 28 4 Code Gb main.o + 0x080009C1 SysTick_Handler 16 4 Code Gb main.o + 0x080009D1 AES128_ECB_decrypt 604 4 Code Gb aes.o + 0x08000C2D AddRoundKey 56 4 Code Lc aes.o + 0x08000C65 InvShiftRows 60 4 Code Lc aes.o + 0x08000CA1 InvSubBytes 48 4 Code Lc aes.o + 0x08000CD1 _start 4 Code Gb SEGGER_THUMB_Startup.o + 0x08000CDB __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + 0x08000CDF exit 4 Code Gb SEGGER_THUMB_Startup.o + 0x08000CE5 Reset_Handler 2 Code Gb STM32G0xx_Startup.o + 0x08000CE5 reset_handler 2 Code Gb STM32G0xx_Startup.o + 0x08000CEB SVC_Handler 2 Code Wk STM32G07x_Vectors.o + 0x08000CED PendSV_Handler 2 Code Wk STM32G07x_Vectors.o + 0x08000CEF WWDG_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000CF1 PVD_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000CF3 RTC_STAMP_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000CF5 FLASH_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000CF7 RCC_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000CF9 EXTI0_1_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000CFB EXTI2_3_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000CFD EXTI4_15_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000CFF UCPD1_UCPD2_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D01 DMA_Channel1_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D03 DMA_Channel2_3_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D05 DMA_Channel4_5_6_7_IRQHandler + 2 Code Wk STM32G07x_Vectors.o + 0x08000D07 ADC_COMP_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D09 TIM1_BRK_UP_TRG_COMP_IRQHandler + 2 Code Wk STM32G07x_Vectors.o + 0x08000D0B TIM1_CC_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D0D TIM2_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D0F TIM3_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D11 TIM6_DAC_LPTIM1_IRQHandler + 2 Code Wk STM32G07x_Vectors.o + 0x08000D13 TIM7_LPTIM2_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D15 TIM14_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D17 TIM15_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D19 TIM16_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D1B TIM17_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D1D I2C1_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D1F I2C2_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D21 SPI1_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D23 SPI2_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D25 USART1_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D27 USART2_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D29 USART3_USART4_LPUART1_IRQHandler + 2 Code Wk STM32G07x_Vectors.o + 0x08000D2B CEC_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D2D AES_RNG_IRQHandler 2 Code Wk STM32G07x_Vectors.o + 0x08000D2F NMI_Handler 14 2 Code Gb main.o + 0x08000D3D TransmitACK 20 2 Code Gb main.o + 0x08000D51 TransmitNACK 20 2 Code Gb main.o + 0x08000D65 HardFault_Handler 16 2 Code Gb main.o + 0x08000D75 __aeabi_uidiv 40 2 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08000D9D __aeabi_memclr 20 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08000D9D __aeabi_memclr4 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08000D9D __aeabi_memclr8 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08000D9F __aeabi_memset 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08000D9F __aeabi_memset4 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08000D9F __aeabi_memset8 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x08000DA5 memset 2 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_small.a) + 0x080010F5 __SEGGER_init_zero 18 2 Code Wk SEGGER_crtinit_v6m_little.o + 0x08001107 __SEGGER_init_copy 20 2 Code Wk SEGGER_crtinit_v6m_little.o + +Read-write data symbols by name and then by address: + + Symbol name Address Size Align Type Bd Object File + ------------------------- ---------- ---------- ----- ---- -- ----------- + Key 0x20000014 4 4 Zero Lc aes.o + RoundKey 0x20000018 176 Zero Lc aes.o + SystemCoreClock 0x20000000 4 4 Init Gb system_stm32g0xx.o + msCounter 0x20000010 4 4 Zero Gb main.o + state 0x2000000C 4 4 Zero Lc aes.o + u 0x20000004 5 4 Zero Gb main.o + +Read-write data symbols by address and then by name: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x20000000 SystemCoreClock 4 4 Init Gb system_stm32g0xx.o + 0x20000004 u 5 4 Zero Gb main.o + 0x2000000C state 4 4 Zero Lc aes.o + 0x20000010 msCounter 4 4 Zero Gb main.o + 0x20000014 Key 4 4 Zero Lc aes.o + 0x20000018 RoundKey 176 Zero Lc aes.o + +Read-only data symbols by name and then by address: + + Symbol name Address Size Align Type Bd Object File + ------------------------- ---------- ---------- ----- ---- -- ----------- + AES_KEY 0x08000EB4 16 Cnst Gb main.o + AHBPrescTable 0x0800016C 64 4 Cnst Gb system_stm32g0xx.o + FW_VERSION 0x080000C0 16 16 Cnst Gb main.o + Rcon 0x08000DB0 255 Cnst Lc aes.o + __SEGGER_init_data__ 0x080010F0 [4] 4 Cnst Lc [ Linker created ] + __SEGGER_init_table__ 0x080010C4 [44] 4 Cnst Lc [ Linker created ] + rsbox 0x08000FC4 256 Cnst Lc aes.o + sbox 0x08000EC4 256 Cnst Lc aes.o + +Read-only data symbols by address and then by name: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x080000C0 FW_VERSION 16 16 Cnst Gb main.o + 0x0800016C AHBPrescTable 64 4 Cnst Gb system_stm32g0xx.o + 0x08000DB0 Rcon 255 Cnst Lc aes.o + 0x08000EB4 AES_KEY 16 Cnst Gb main.o + 0x08000EC4 sbox 256 Cnst Lc aes.o + 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__SEGGER_init_run_loop 0x08000CD2 4 Code Lc SEGGER_THUMB_Startup.o + __STACKSIZE_PROCESS__ 0x00000000 ---- Gb [ Linker created ] + __STACKSIZE__ 0x00001000 ---- Gb [ Linker created ] + __stack_end__ 0x20008000 ---- Gb [ Linker created ] + __thread_pointer$ 0x00000000 ---- Gb [ Linker created ] + _vectors 0x08000000 [192] 512 Code Gb STM32G07x_Vectors.o + _vectors_end 0x080000C0 512 Code Lc STM32G07x_Vectors.o + +Untyped symbols by address and then by name: + + Value Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x00000000 __HEAPSIZE__ ---- Gb [ Linker created ] + 0x00000000 __STACKSIZE_PROCESS__ ---- Gb [ Linker created ] + 0x00000000 __thread_pointer$ ---- Gb [ Linker created ] + 0x00001000 __STACKSIZE__ ---- Gb [ Linker created ] + 0x0000111A __FLASH1_segment_used_size__ + ---- Gb [ Linker created ] + 0x0000111A __FLASH_segment_used_size__ + ---- Gb [ Linker created ] + 0x00003000 __FLASH1_segment_size__ ---- Gb [ Linker created ] + 0x00003000 __FLASH_segment_size__ ---- Gb [ Linker created ] + 0x00008000 __RAM1_segment_size__ ---- Gb [ Linker created ] + 0x00008000 __RAM1_segment_used_size__ + ---- Gb [ Linker created ] + 0x00008000 __RAM_segment_size__ ---- Gb [ Linker created ] + 0x00008000 __RAM_segment_used_size__ ---- Gb [ Linker created ] + 0x08000000 __FLASH1_segment_start__ ---- Gb [ Linker created ] + 0x08000000 __FLASH1_segment_used_start__ + ---- Gb [ Linker created ] + 0x08000000 __FLASH_segment_start__ ---- Gb [ Linker created ] + 0x08000000 __FLASH_segment_used_start__ + ---- Gb [ Linker created ] + 0x08000000 _vectors [192] 512 Code Gb STM32G07x_Vectors.o + 0x080000C0 _vectors_end 512 Code Lc STM32G07x_Vectors.o + 0x08000CD2 __SEGGER_init_run_loop 4 Code Lc SEGGER_THUMB_Startup.o + 0x0800111A __FLASH1_segment_used_end__ + ---- Gb [ Linker created ] + 0x0800111A __FLASH_segment_used_end__ + ---- Gb [ Linker created ] + 0x08003000 __FLASH1_segment_end__ ---- Gb [ Linker created ] + 0x08003000 __FLASH_segment_end__ ---- Gb [ Linker created ] + 0x20000000 __RAM1_segment_start__ ---- Gb [ Linker created ] + 0x20000000 __RAM1_segment_used_start__ + ---- Gb [ Linker created ] + 0x20000000 __RAM_segment_start__ ---- Gb [ Linker created ] + 0x20000000 __RAM_segment_used_start__ + ---- Gb [ Linker created ] + 0x20008000 __RAM1_segment_end__ ---- Gb [ Linker created ] + 0x20008000 __RAM1_segment_used_end__ ---- Gb [ Linker created ] + 0x20008000 __RAM_segment_end__ ---- Gb [ Linker created ] + 0x20008000 __RAM_segment_used_end__ ---- Gb [ Linker created ] + 0x20008000 __stack_end__ ---- Gb [ Linker created ] + + +*********************************************************************************************** +*** *** +*** LINK SUMMARY *** +*** *** +*********************************************************************************************** + +Memory breakdown: + + 3 462 bytes read-only code + 911 bytes read-only data + 4 293 bytes read-write data + +Region summary: + + Name Range Size Used Unused Alignment Loss + ---------- ----------------- ---------- ------------------ ------------------ ------------------ + FLASH 08000000-08002fff 12 288 4 377 35.62% 7 911 64.38% 0 0.00% + RAM 20000000-20007fff 32 768 4 293 13.10% 28 472 86.89% 3 0.01% + +Link complete: 0 errors, 0 warnings, 0 remarks Index: ecs_cellMon/Bootloader/SES/Output/Release/Obj/SEGGER_THUMB_Startup.d =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Release/Obj/SEGGER_THUMB_Startup.d (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Release/Obj/SEGGER_THUMB_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Output/Release/Obj/SEGGER_THUMB_Startup.o: \ + D\:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\SEGGER_THUMB_Startup.s Index: ecs_cellMon/Bootloader/SES/Output/Release/Obj/STM32G07x_Vectors.d =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Release/Obj/STM32G07x_Vectors.d (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Release/Obj/STM32G07x_Vectors.d (revision 3) @@ -0,0 +1,2 @@ +Output/Release/Obj/STM32G07x_Vectors.o: \ + D\:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\Source\STM32G07x_Vectors.s Index: ecs_cellMon/Bootloader/SES/Output/Release/Obj/STM32G0xx_Startup.d =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Release/Obj/STM32G0xx_Startup.d (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Release/Obj/STM32G0xx_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Output/Release/Obj/STM32G0xx_Startup.o: \ + D\:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\Source\STM32G0xx_Startup.s Index: ecs_cellMon/Bootloader/SES/Output/Release/Obj/aes.d =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Release/Obj/aes.d (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Release/Obj/aes.d (revision 3) @@ -0,0 +1,8 @@ +Output/Release/Obj/aes.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\aes.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL_Arm_Conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\aes.h Index: ecs_cellMon/Bootloader/SES/Output/Release/Obj/bootloader.ind =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Release/Obj/bootloader.ind (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Release/Obj/bootloader.ind (revision 3) @@ -0,0 +1,8 @@ +"Output/Release/Obj/system_stm32g0xx.o" +"Output/Release/Obj/main.o" +"Output/Release/Obj/aes.o" +"Output/Release/Obj/SEGGER_THUMB_Startup.o" +"Output/Release/Obj/STM32G0xx_Startup.o" +"Output/Release/Obj/STM32G07x_Vectors.o" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.50a/segger-rtl/libs/libc_v6m_t_le_eabi_small.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.50a/lib/SEGGER_crtinit_v6m_little.o" Index: ecs_cellMon/Bootloader/SES/Output/Release/Obj/main.d =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Release/Obj/main.d (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Release/Obj/main.d (revision 3) @@ -0,0 +1,22 @@ +Output/Release/Obj/main.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\main.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\string.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL_Arm_Conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\RTT\SEGGER_RTT.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\RTT\SEGGER_RTT_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\stdlib.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\stdarg.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\aes.h Index: ecs_cellMon/Bootloader/SES/Output/Release/Obj/system_stm32g0xx.d =================================================================== --- ecs_cellMon/Bootloader/SES/Output/Release/Obj/system_stm32g0xx.d (revision 3) +++ ecs_cellMon/Bootloader/SES/Output/Release/Obj/system_stm32g0xx.d (revision 3) @@ -0,0 +1,15 @@ +Output/Release/Obj/system_stm32g0xx.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Source\system_stm32g0xx.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.50a\segger-rtl\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h Index: ecs_cellMon/Bootloader/SES/SEGGER_THUMB_Startup.s =================================================================== --- ecs_cellMon/Bootloader/SES/SEGGER_THUMB_Startup.s (revision 3) +++ ecs_cellMon/Bootloader/SES/SEGGER_THUMB_Startup.s (revision 3) @@ -0,0 +1,218 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2020 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : SEGGER_THUMB_Startup.s +Purpose : Generic runtime init startup code for ARM CPUs running + in THUMB mode. + Designed to work with the SEGGER linker to produce + smallest possible executables. + + This file does not normally require any customization. + +Additional information: + Preprocessor Definitions + FULL_LIBRARY + If defined then + - argc, argv are setup by the debug_getargs. + - the exit symbol is defined and executes on return from main. + - the exit symbol calls destructors, atexit functions and then debug_exit. + + If not defined then + - argc and argv are not valid (main is assumed to not take parameters) + - the exit symbol is defined, executes on return from main and loops +*/ + + .syntax unified + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +#ifndef APP_ENTRY_POINT + #define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE + #define ARGSSPACE 128 +#endif + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern APP_ENTRY_POINT // typically main + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* _start +* +* Function description +* Entry point for the startup code. +* Usually called by the reset handler. +* Performs all initialisation, based on the entries in the +* linker-generated init table, then calls main(). +* It is device independent, so there should not be any need for an +* end-user to modify it. +* +* Additional information +* At this point, the stack pointer should already have been +* initialized: +* - For typical programs executiong from flash, the stack pointer +* has already been loaded from vector table at offset 0. +* - In other cases, such as RAM Code, this is done by the debugger +* or the device-specific startup code / reset handler. +*/ + .section .init, "ax" + .balign 2 + .global _start + .thumb_func + .code 16 +_start: + // + // Call linker init functions which in turn performs the following: + // * Perform segment init + // * Perform heap init (if used) + // * Call constructors of global Objects (if any exist) + // + ldr R4, =__SEGGER_init_table__ // Set table pointer to start of initialization table +__SEGGER_init_run_loop: + ldr R0, [R4] // Get next initialization function from table + adds R4, R4, #4 // Increment table pointer to point to function arguments + blx R0 // Call initialization function + b.n __SEGGER_init_run_loop + // + .thumb_func + .global __SEGGER_init_done +__SEGGER_init_done: + // + // Time to call main(), the application entry point. + // +#ifndef FULL_LIBRARY + // + // In a real embedded application ("Free-standing environment"), + // main() does not get any arguments, + // which means it is not necessary to init R0 and R1. + // + bl APP_ENTRY_POINT // Call to application entry point (usually main()) + // + // Fall-through to exit if main ever returns. + // + .global exit + .thumb_func +exit: + // + // In a free-standing environment, if returned from application: + // Loop forever. + // + b . +#else + // + // In a hosted environment, + // we need to load R0 and R1 with argc and argv, in order to handle + // the command line arguments. + // This is required for some programs running under control of a + // debugger, such as automated tests. + // + movs R0, #ARGSSPACE + ldr R1, =args + bl SEGGER_SEMIHOST_GetArgs + ldr R1, =args + bl APP_ENTRY_POINT // Call to application entry point (usually main()) + // + // Fall-through to exit if main ever returns. + // + .global exit + .thumb_func +exit: + // + // In a hosted environment exit gracefully, by + // saving the return value, + // calling destructurs of global objects, + // calling registered atexit functions, + // and notifying the host/debugger. + // + mov R5, R0 // Save the exit parameter/return result + // + // Call destructors + // + ldr R0, =__dtors_start__ // Pointer to destructor list + ldr R1, =__dtors_end__ +dtorLoop: + cmp R0, R1 + beq dtorEnd // Reached end of destructor list? => Done + ldr R2, [R0] // Load current destructor address into R2 + add R0, #4 // Increment pointer + push {R0-R1} // Save R0 and R1 + blx R2 // Call destructor + pop {R0-R1} // Restore R0 and R1 + b dtorLoop +dtorEnd: + // + // Call atexit functions + // + bl __SEGGER_RTL_execute_at_exit_fns + // + // Call debug_exit with return result/exit parameter + // + mov R0, R5 + bl SEGGER_SEMIHOST_Exit + // + // If execution is not terminated, loop forever + // +exit_loop: + b exit_loop // Loop forever. +#endif + +#ifdef FULL_LIBRARY + .bss +args: + .space ARGSSPACE +#endif + +/*************************** End of file ****************************/ Index: ecs_cellMon/Bootloader/SES/STM32G070KBTx_MemoryMap.xml =================================================================== --- ecs_cellMon/Bootloader/SES/STM32G070KBTx_MemoryMap.xml (revision 3) +++ ecs_cellMon/Bootloader/SES/STM32G070KBTx_MemoryMap.xml (revision 3) @@ -0,0 +1,5 @@ + + + + + Index: ecs_cellMon/Bootloader/SES/STM32G07x_Registers.xml =================================================================== --- ecs_cellMon/Bootloader/SES/STM32G07x_Registers.xml (revision 3) +++ ecs_cellMon/Bootloader/SES/STM32G07x_Registers.xml (revision 3) @@ -0,0 +1,5861 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: ecs_cellMon/Bootloader/SES/STM32G0xx/CMSIS/Device/Include/stm32g070xx.h =================================================================== --- ecs_cellMon/Bootloader/SES/STM32G0xx/CMSIS/Device/Include/stm32g070xx.h (revision 3) +++ ecs_cellMon/Bootloader/SES/STM32G0xx/CMSIS/Device/Include/stm32g070xx.h (revision 3) @@ -0,0 +1,7639 @@ +/** + ****************************************************************************** + * @file stm32g070xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32g070xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g070xx + * @{ + */ + +#ifndef STM32G070xx_H +#define STM32G070xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1 /*!< STM32G0xx provides an MPU */ +#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< STM32G0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32g070xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM6_IRQn = 17, /*!< TIM6 global Interrupts */ + TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + USART3_4_IRQn = 29, /*!< USART3, USART4 globlal Interrupts */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32g0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x24--0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x34--0x38 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ + __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */ + uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ +} TAMP_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[25]; /*!< Reserved 0x1C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */ + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) +#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) +#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART4 ((USART_TypeDef *) USART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) + +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ +#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ +#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ +#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ +#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ +#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ +#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ +#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ +#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ +#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ +#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ +#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ +#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ +#define DMAMUX_CSR_SOF5_Pos (5U) +#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ +#define DMAMUX_CSR_SOF6_Pos (6U) +#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ +#define DMAMUX_CFR_CSOF5_Pos (5U) +#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ +#define DMAMUX_CFR_CSOF6_Pos (6U) +#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0x86A8FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x86A8FFFFU */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/* Note: No specific macro feature on this device */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_PROGEMPTY_Pos (16U) +#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY1_Pos (16U) +#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER1_Pos (2U) +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1 FLASH_CR_MER1_Msk +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +/******************* Bits definition for FLASH_ECCR register ****************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk +#define FLASH_ECCR_ECCCIE_Pos (24U) +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk +#define FLASH_OPTR_nRST_STOP_Pos (13U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk +#define FLASH_OPTR_nRST_STDBY_Pos (14U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk +#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) +#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk +#define FLASH_OPTR_nBOOT_SEL_Pos (24U) +#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk +#define FLASH_OPTR_nBOOT1_Pos (25U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk +#define FLASH_OPTR_nBOOT0_Pos (26U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk + + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x003F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x003F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk + + + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_OUT2EN_Pos (31U) +#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ +#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */ +#define RTC_CR_TAMPALRM_TYPE_Pos (30U) +#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ +#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */ +#define RTC_CR_TAMPALRM_PU_Pos (29U) +#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ +#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */ +#define RTC_CR_TAMPOE_Pos (26U) +#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ +#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */ +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk + +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */ +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */ +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */ +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U +#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U +#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFLT_0 0x00000008U +#define TAMP_FLTCR_TAMPFLT_1 0x00000010U +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U +#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk + +/******************** Bits definition for TAMP_SR register ******************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ***************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ***************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ***************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ***************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G0 serie) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[21] interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos (1U) +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk /*!< RTC_WAKEUP -> exti[19] interrupt .... */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U) +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U) +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */ +#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) +#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ +#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) +#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ +#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) +#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ +#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) +#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ +#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) +#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */ +#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) +#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */ +#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) +#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */ +#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) +#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */ +#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) +#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */ +#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) +#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */ +#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) +#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ +#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */ +#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) +#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ +#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */ +#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) +#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ +#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */ +#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) +#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ +#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */ +#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) +#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ +#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */ +#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) +#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ +#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U) +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (3U) +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (4U) +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */ +#define SYSCFG_ITLINE12_SR_ADC_Pos (0U) +#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ +#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt */ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ +#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U) +#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g071xx + * @{ + */ + +#ifndef STM32G071xx_H +#define STM32G071xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1 /*!< STM32G0xx provides an MPU */ +#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< STM32G0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32g071xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt(EXTI line 16) */ + RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + UCPD1_2_IRQn = 8, /*!< UCPD1 and UCPD2 global Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts (combined with EXTI 17 & 18) */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM6_DAC_LPTIM1_IRQn = 17, /*!< TIM6, DAC and LPTIM1 global Interrupts */ + TIM7_LPTIM2_IRQn = 18, /*!< TIM7 and LPTIM2 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + USART3_4_LPUART1_IRQn = 29, /*!< USART3, USART4 and LPUART1 globlal Interrupts (combined with EXTI 28) */ + CEC_IRQn = 30, /*!< CEC Interrupt(combined with EXTI 27) */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32g0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief HDMI-CEC + */ +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ +} LPTIM_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ + __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */ + uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ +} TAMP_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[25]; /*!< Reserved 0x1C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ + +} UCPD_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */ + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM2_BASE (APBPERIPH_BASE + 0UL) +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) +#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define DAC1_BASE (APBPERIPH_BASE + 0x00007400UL) +#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL) /* Kept for legacy purpose */ +#define CEC_BASE (APBPERIPH_BASE + 0x00007800UL) +#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL) +#define LPUART1_BASE (APBPERIPH_BASE + 0x00008000UL) +#define LPTIM2_BASE (APBPERIPH_BASE + 0x00009400UL) +#define UCPD1_BASE (APBPERIPH_BASE + 0x0000A000UL) +#define UCPD2_BASE (APBPERIPH_BASE + 0x0000A400UL) +#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define VREFBUF_BASE (APBPERIPH_BASE + 0x00010030UL) +#define COMP1_BASE (SYSCFG_BASE + 0x0200UL) +#define COMP2_BASE (SYSCFG_BASE + 0x0204UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) +#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART4 ((USART_TypeDef *) USART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) + +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) +#define UCPD2 ((UCPD_TypeDef *) UCPD2_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ +#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ +#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ +#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ +#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ +#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ +#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ +#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ +#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ +#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ +#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ +#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ +#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */ + +/******************************************************************************/ +/* */ +/* HDMI-CEC (CEC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CEC_CR register *********************/ +#define CEC_CR_CECEN_Pos (0U) +#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */ +#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */ +#define CEC_CR_TXSOM_Pos (1U) +#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */ +#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */ +#define CEC_CR_TXEOM_Pos (2U) +#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */ +#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */ + +/******************* Bit definition for CEC_CFGR register *******************/ +#define CEC_CFGR_SFT_Pos (0U) +#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */ +#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */ +#define CEC_CFGR_RXTOL_Pos (3U) +#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */ +#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */ +#define CEC_CFGR_BRESTP_Pos (4U) +#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */ +#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */ +#define CEC_CFGR_BREGEN_Pos (5U) +#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */ +#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */ +#define CEC_CFGR_LBPEGEN_Pos (6U) +#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */ +#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */ +#define CEC_CFGR_BRDNOGEN_Pos (7U) +#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */ +#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */ +#define CEC_CFGR_SFTOPT_Pos (8U) +#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */ +#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */ +#define CEC_CFGR_OAR_Pos (16U) +#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */ +#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */ +#define CEC_CFGR_LSTN_Pos (31U) +#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */ +#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */ + +/******************* Bit definition for CEC_TXDR register *******************/ +#define CEC_TXDR_TXD_Pos (0U) +#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */ +#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ + +/******************* Bit definition for CEC_RXDR register *******************/ +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ + +/******************* Bit definition for CEC_ISR register ********************/ +#define CEC_ISR_RXBR_Pos (0U) +#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ +#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */ +#define CEC_ISR_RXEND_Pos (1U) +#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */ +#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */ +#define CEC_ISR_RXOVR_Pos (2U) +#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */ +#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */ +#define CEC_ISR_BRE_Pos (3U) +#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */ +#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */ +#define CEC_ISR_SBPE_Pos (4U) +#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */ +#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */ +#define CEC_ISR_LBPE_Pos (5U) +#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */ +#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */ +#define CEC_ISR_RXACKE_Pos (6U) +#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */ +#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */ +#define CEC_ISR_ARBLST_Pos (7U) +#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */ +#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */ +#define CEC_ISR_TXBR_Pos (8U) +#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */ +#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */ +#define CEC_ISR_TXEND_Pos (9U) +#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */ +#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */ +#define CEC_ISR_TXUDR_Pos (10U) +#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */ +#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */ +#define CEC_ISR_TXERR_Pos (11U) +#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */ +#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */ +#define CEC_ISR_TXACKE_Pos (12U) +#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */ +#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */ + +/******************* Bit definition for CEC_IER register ********************/ +#define CEC_IER_RXBRIE_Pos (0U) +#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */ +#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */ +#define CEC_IER_RXENDIE_Pos (1U) +#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */ +#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */ +#define CEC_IER_RXOVRIE_Pos (2U) +#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */ +#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */ +#define CEC_IER_BREIE_Pos (3U) +#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */ +#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */ +#define CEC_IER_SBPEIE_Pos (4U) +#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */ +#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/ +#define CEC_IER_LBPEIE_Pos (5U) +#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */ +#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */ +#define CEC_IER_RXACKEIE_Pos (6U) +#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */ +#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */ +#define CEC_IER_ARBLSTIE_Pos (7U) +#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */ +#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */ +#define CEC_IER_TXBRIE_Pos (8U) +#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */ +#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */ +#define CEC_IER_TXENDIE_Pos (9U) +#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */ +#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */ +#define CEC_IER_TXUDRIE_Pos (10U) +#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */ +#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */ +#define CEC_IER_TXERRIE_Pos (11U) +#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */ +#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */ +#define CEC_IER_TXACKEIE_Pos (12U) +#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */ +#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ +#define DAC_ADDITIONAL_TRIGGERS_SUPPORT + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_OUT2EN_Pos (31U) +#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ +#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */ +#define RTC_CR_TAMPALRM_TYPE_Pos (30U) +#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ +#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */ +#define RTC_CR_TAMPALRM_PU_Pos (29U) +#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ +#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */ +#define RTC_CR_TAMPOE_Pos (26U) +#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ +#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */ +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk + +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */ +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */ +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */ +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U +#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U +#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFLT_0 0x00000008U +#define TAMP_FLTCR_TAMPFLT_1 0x00000010U +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U +#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk + +/******************** Bits definition for TAMP_SR register ******************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ***************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ***************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ***************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ***************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G0 serie) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[16] Interrupt */ +#define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U) +#define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk /*!< TAMPER -> exti[21] interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos (1U) +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk /*!< RTC_WAKEUP -> exti[19] interrupt .... */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U) +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U) +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */ +#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) +#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ +#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) +#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ +#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) +#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ +#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) +#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ +#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) +#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */ +#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) +#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */ +#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) +#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */ +#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) +#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */ +#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) +#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */ +#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) +#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */ +#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) +#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ +#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */ +#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) +#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ +#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */ +#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) +#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ +#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */ +#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) +#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ +#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */ +#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) +#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ +#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */ +#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) +#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ +#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */ +#define SYSCFG_ITLINE8_SR_UCPD1_Pos (0U) +#define SYSCFG_ITLINE8_SR_UCPD1_Msk (0x1UL << SYSCFG_ITLINE8_SR_UCPD1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE8_SR_UCPD1 SYSCFG_ITLINE8_SR_UCPD1_Msk /*!< UCPD1 -> exti[32] Interrupt */ +#define SYSCFG_ITLINE8_SR_UCPD2_Pos (1U) +#define SYSCFG_ITLINE8_SR_UCPD2_Msk (0x1UL << SYSCFG_ITLINE8_SR_UCPD2_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE8_SR_UCPD2 SYSCFG_ITLINE8_SR_UCPD2_Msk /*!< UCPD2 -> exti[33] Interrupt */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U) +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (3U) +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (4U) +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */ +#define SYSCFG_ITLINE12_SR_ADC_Pos (0U) +#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ +#define SYSCFG_ITLINE12_SR_COMP1_Pos (1U) +#define SYSCFG_ITLINE12_SR_COMP1_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE12_SR_COMP1 SYSCFG_ITLINE12_SR_COMP1_Msk /*!< COMP1 Interrupt -> exti[17] */ +#define SYSCFG_ITLINE12_SR_COMP2_Pos (2U) +#define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[18] */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ +#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB SYSCFG_ITLINE15_SR_TIM2_GLB_Msk /*!< TIM2 GLB Interrupt */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_DAC_Pos (1U) +#define SYSCFG_ITLINE17_SR_DAC_Msk (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos (2U) +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk /*!< LPTIM1 -> exti[29] Interrupt */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */ +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos (1U) +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk /*!< LPTIM2 -> exti[30] Interrupt */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt */ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ +#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U) +#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos (2U) +#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE29_SR_LPUART1_GLB SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk /*!< LPUART1 GLB Interrupt -> exti[28] */ +#define SYSCFG_ITLINE30_SR_CEC_Pos (0U) +#define SYSCFG_ITLINE30_SR_CEC_Msk (0x1UL << SYSCFG_ITLINE30_SR_CEC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE30_SR_CEC SYSCFG_ITLINE30_SR_CEC_Msk /*!< CEC Interrupt-> exti[27] */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g081xx + * @{ + */ + +#ifndef STM32G081xx_H +#define STM32G081xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1 /*!< STM32G0xx provides an MPU */ +#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< STM32G0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32g081xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt(EXTI line 16) */ + RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + UCPD1_2_IRQn = 8, /*!< UCPD1 and UCPD2 global Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts (combined with EXTI 17 & 18) */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM6_DAC_LPTIM1_IRQn = 17, /*!< TIM6, DAC and LPTIM1 global Interrupts */ + TIM7_LPTIM2_IRQn = 18, /*!< TIM7 and LPTIM2 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + USART3_4_LPUART1_IRQn = 29, /*!< USART3, USART4 and LPUART1 globlal Interrupts (combined with EXTI 28) */ + CEC_IRQn = 30, /*!< CEC Interrupt(combined with EXTI 27) */ + AES_RNG_IRQn = 31, /*!< AES & RNG Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32g0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief HDMI-CEC + */ +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ +} LPTIM_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ + __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */ + uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ +} TAMP_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[25]; /*!< Reserved 0x1C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ +} AES_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ + +} UCPD_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */ + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM2_BASE (APBPERIPH_BASE + 0UL) +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) +#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define DAC1_BASE (APBPERIPH_BASE + 0x00007400UL) +#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL) /* Kept for legacy purpose */ +#define CEC_BASE (APBPERIPH_BASE + 0x00007800UL) +#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL) +#define LPUART1_BASE (APBPERIPH_BASE + 0x00008000UL) +#define LPTIM2_BASE (APBPERIPH_BASE + 0x00009400UL) +#define UCPD1_BASE (APBPERIPH_BASE + 0x0000A000UL) +#define UCPD2_BASE (APBPERIPH_BASE + 0x0000A400UL) +#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define VREFBUF_BASE (APBPERIPH_BASE + 0x00010030UL) +#define COMP1_BASE (SYSCFG_BASE + 0x0200UL) +#define COMP2_BASE (SYSCFG_BASE + 0x0204UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + +#define RNG_BASE (AHBPERIPH_BASE + 0x00005000UL) +#define AES_BASE (AHBPERIPH_BASE + 0x00006000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) +#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART4 ((USART_TypeDef *) USART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) + +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + +#define AES ((AES_TypeDef *) AES_BASE) +#define AES1 ((AES_TypeDef *) AES_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) +#define UCPD2 ((UCPD_TypeDef *) UCPD2_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ +#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ +#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ +#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ +#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ +#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ +#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ +#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ +#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ +#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ +#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ +#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ +#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */ + +/******************************************************************************/ +/* */ +/* HDMI-CEC (CEC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CEC_CR register *********************/ +#define CEC_CR_CECEN_Pos (0U) +#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */ +#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */ +#define CEC_CR_TXSOM_Pos (1U) +#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */ +#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */ +#define CEC_CR_TXEOM_Pos (2U) +#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */ +#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */ + +/******************* Bit definition for CEC_CFGR register *******************/ +#define CEC_CFGR_SFT_Pos (0U) +#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */ +#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */ +#define CEC_CFGR_RXTOL_Pos (3U) +#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */ +#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */ +#define CEC_CFGR_BRESTP_Pos (4U) +#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */ +#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */ +#define CEC_CFGR_BREGEN_Pos (5U) +#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */ +#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */ +#define CEC_CFGR_LBPEGEN_Pos (6U) +#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */ +#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */ +#define CEC_CFGR_BRDNOGEN_Pos (7U) +#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */ +#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */ +#define CEC_CFGR_SFTOPT_Pos (8U) +#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */ +#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */ +#define CEC_CFGR_OAR_Pos (16U) +#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */ +#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */ +#define CEC_CFGR_LSTN_Pos (31U) +#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */ +#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */ + +/******************* Bit definition for CEC_TXDR register *******************/ +#define CEC_TXDR_TXD_Pos (0U) +#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */ +#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ + +/******************* Bit definition for CEC_RXDR register *******************/ +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ + +/******************* Bit definition for CEC_ISR register ********************/ +#define CEC_ISR_RXBR_Pos (0U) +#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ +#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */ +#define CEC_ISR_RXEND_Pos (1U) +#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */ +#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */ +#define CEC_ISR_RXOVR_Pos (2U) +#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */ +#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */ +#define CEC_ISR_BRE_Pos (3U) +#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */ +#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */ +#define CEC_ISR_SBPE_Pos (4U) +#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */ +#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */ +#define CEC_ISR_LBPE_Pos (5U) +#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */ +#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */ +#define CEC_ISR_RXACKE_Pos (6U) +#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */ +#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */ +#define CEC_ISR_ARBLST_Pos (7U) +#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */ +#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */ +#define CEC_ISR_TXBR_Pos (8U) +#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */ +#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */ +#define CEC_ISR_TXEND_Pos (9U) +#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */ +#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */ +#define CEC_ISR_TXUDR_Pos (10U) +#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */ +#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */ +#define CEC_ISR_TXERR_Pos (11U) +#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */ +#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */ +#define CEC_ISR_TXACKE_Pos (12U) +#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */ +#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */ + +/******************* Bit definition for CEC_IER register ********************/ +#define CEC_IER_RXBRIE_Pos (0U) +#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */ +#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */ +#define CEC_IER_RXENDIE_Pos (1U) +#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */ +#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */ +#define CEC_IER_RXOVRIE_Pos (2U) +#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */ +#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */ +#define CEC_IER_BREIE_Pos (3U) +#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */ +#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */ +#define CEC_IER_SBPEIE_Pos (4U) +#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */ +#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/ +#define CEC_IER_LBPEIE_Pos (5U) +#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */ +#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */ +#define CEC_IER_RXACKEIE_Pos (6U) +#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */ +#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */ +#define CEC_IER_ARBLSTIE_Pos (7U) +#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */ +#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */ +#define CEC_IER_TXBRIE_Pos (8U) +#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */ +#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */ +#define CEC_IER_TXENDIE_Pos (9U) +#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */ +#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */ +#define CEC_IER_TXUDRIE_Pos (10U) +#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */ +#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */ +#define CEC_IER_TXERRIE_Pos (11U) +#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */ +#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */ +#define CEC_IER_TXACKEIE_Pos (12U) +#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */ +#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last block of payload. */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ +#define DAC_ADDITIONAL_TRIGGERS_SUPPORT + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_OUT2EN_Pos (31U) +#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ +#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */ +#define RTC_CR_TAMPALRM_TYPE_Pos (30U) +#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ +#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */ +#define RTC_CR_TAMPALRM_PU_Pos (29U) +#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ +#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */ +#define RTC_CR_TAMPOE_Pos (26U) +#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ +#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */ +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk + +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */ +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */ +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */ +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U +#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U +#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFLT_0 0x00000008U +#define TAMP_FLTCR_TAMPFLT_1 0x00000010U +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U +#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk + +/******************** Bits definition for TAMP_SR register ******************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ***************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ***************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ***************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ***************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G0 serie) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[16] Interrupt */ +#define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U) +#define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk /*!< TAMPER -> exti[21] interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos (1U) +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk /*!< RTC_WAKEUP -> exti[19] interrupt .... */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U) +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U) +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */ +#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) +#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ +#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) +#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ +#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) +#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ +#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) +#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ +#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) +#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */ +#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) +#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */ +#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) +#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */ +#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) +#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */ +#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) +#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */ +#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) +#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */ +#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) +#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ +#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */ +#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) +#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ +#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */ +#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) +#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ +#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */ +#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) +#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ +#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */ +#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) +#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ +#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */ +#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) +#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ +#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */ +#define SYSCFG_ITLINE8_SR_UCPD1_Pos (0U) +#define SYSCFG_ITLINE8_SR_UCPD1_Msk (0x1UL << SYSCFG_ITLINE8_SR_UCPD1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE8_SR_UCPD1 SYSCFG_ITLINE8_SR_UCPD1_Msk /*!< UCPD1 -> exti[32] Interrupt */ +#define SYSCFG_ITLINE8_SR_UCPD2_Pos (1U) +#define SYSCFG_ITLINE8_SR_UCPD2_Msk (0x1UL << SYSCFG_ITLINE8_SR_UCPD2_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE8_SR_UCPD2 SYSCFG_ITLINE8_SR_UCPD2_Msk /*!< UCPD2 -> exti[33] Interrupt */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U) +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (3U) +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (4U) +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */ +#define SYSCFG_ITLINE12_SR_ADC_Pos (0U) +#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ +#define SYSCFG_ITLINE12_SR_COMP1_Pos (1U) +#define SYSCFG_ITLINE12_SR_COMP1_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE12_SR_COMP1 SYSCFG_ITLINE12_SR_COMP1_Msk /*!< COMP1 Interrupt -> exti[17] */ +#define SYSCFG_ITLINE12_SR_COMP2_Pos (2U) +#define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[18] */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ +#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB SYSCFG_ITLINE15_SR_TIM2_GLB_Msk /*!< TIM2 GLB Interrupt */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_DAC_Pos (1U) +#define SYSCFG_ITLINE17_SR_DAC_Msk (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos (2U) +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk /*!< LPTIM1 -> exti[29] Interrupt */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */ +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos (1U) +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk /*!< LPTIM2 -> exti[30] Interrupt */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt */ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ +#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U) +#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos (2U) +#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE29_SR_LPUART1_GLB SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk /*!< LPUART1 GLB Interrupt -> exti[28] */ +#define SYSCFG_ITLINE30_SR_CEC_Pos (0U) +#define SYSCFG_ITLINE30_SR_CEC_Msk (0x1UL << SYSCFG_ITLINE30_SR_CEC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE30_SR_CEC SYSCFG_ITLINE30_SR_CEC_Msk /*!< CEC Interrupt-> exti[27] */ +#define SYSCFG_ITLINE31_SR_RNG_Pos (0U) +#define SYSCFG_ITLINE31_SR_RNG_Msk (0x1UL << SYSCFG_ITLINE31_SR_RNG_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE31_SR_RNG SYSCFG_ITLINE31_SR_RNG_Msk /*!< RNG Interrupt */ +#define SYSCFG_ITLINE31_SR_AES_Pos (1U) +#define SYSCFG_ITLINE31_SR_AES_Msk (0x1UL << SYSCFG_ITLINE31_SR_AES_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE31_SR_AES SYSCFG_ITLINE31_SR_AES_Msk /*!< AES Interrupt */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx + * @{ + */ + +#ifndef STM32G0xx_H +#define STM32G0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32G0) +#define STM32G0 +#endif /* STM32G0 */ + +/* Uncomment the line below according to the target STM32G0 device used in your + application + */ + +#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) + /* #define STM32G070xx */ /*!< STM32G070xx Devices */ + /* #define STM32G071xx */ /*!< STM32G071xx Devices */ + /* #define STM32G081xx */ /*!< STM32G081xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number $VERSION$ + */ +#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32G0_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32G0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\ + |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32G0_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32G071xx) + #include "stm32g071xx.h" +#elif defined(STM32G081xx) + #include "stm32g081xx.h" +#elif defined(STM32G070xx) + #include "stm32g070xx.h" +#else + #error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/ +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32g0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32G0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/Bootloader/SES/STM32G0xx/CMSIS/Device/Include/system_stm32g0xx.h =================================================================== --- ecs_cellMon/Bootloader/SES/STM32G0xx/CMSIS/Device/Include/system_stm32g0xx.h (revision 3) +++ ecs_cellMon/Bootloader/SES/STM32G0xx/CMSIS/Device/Include/system_stm32g0xx.h (revision 3) @@ -0,0 +1,106 @@ +/** + ****************************************************************************** + * @file system_stm32g0xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device System Source File for STM32G0xx devices. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef SYSTEM_STM32G0XX_H +#define SYSTEM_STM32G0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32G0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32G0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*SYSTEM_STM32G0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/Bootloader/SES/STM32G0xx/CMSIS/Device/Source/system_stm32g0xx.c =================================================================== --- ecs_cellMon/Bootloader/SES/STM32G0xx/CMSIS/Device/Source/system_stm32g0xx.c (revision 3) +++ ecs_cellMon/Bootloader/SES/STM32G0xx/CMSIS/Device/Source/system_stm32g0xx.c (revision 3) @@ -0,0 +1,290 @@ +/** + ****************************************************************************** + * @file system_stm32g0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB Prescaler | 1 + *----------------------------------------------------------------------------- + * HSI Division factor | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx_system + * @{ + */ + +/** @addtogroup STM32G0xx_System_Private_Includes + * @{ + */ + +#include "stm32g0xx.h" + +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ +#endif /* LSE_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000UL; + + const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL}; + const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE + * + * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp; + uint32_t pllvco; + uint32_t pllr; + uint32_t pllsource; + uint32_t pllm; + uint32_t hsidiv; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_LSI: /* LSI used as system clock */ + SystemCoreClock = LSI_VALUE; + break; + + case RCC_CFGR_SWS_LSE: /* LSE used as system clock */ + SystemCoreClock = LSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL; + + if(pllsource == 0x03UL) /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + else /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); + + SystemCoreClock = pllvco/pllr; + break; + + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + default: /* HSI used as system clock */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos)); + SystemCoreClock = (HSI_VALUE/hsidiv); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/Bootloader/SES/STM32G0xx/Scripts/STM32G0xx_Target.js =================================================================== --- ecs_cellMon/Bootloader/SES/STM32G0xx/Scripts/STM32G0xx_Target.js (revision 3) +++ ecs_cellMon/Bootloader/SES/STM32G0xx/Scripts/STM32G0xx_Target.js (revision 3) @@ -0,0 +1,50 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2019 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* - Neither the name of SEGGER Microcontroller GmbH * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. * +* IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +*********************************************************************/ + +function Reset() { + TargetInterface.resetAndStop(); +} + +function EnableTrace(traceInterfaceType) { + // TODO: Enable trace +} + Index: ecs_cellMon/Bootloader/SES/STM32G0xx/Source/STM32G07x_Vectors.s =================================================================== --- ecs_cellMon/Bootloader/SES/STM32G0xx/Source/STM32G07x_Vectors.s (revision 3) +++ ecs_cellMon/Bootloader/SES/STM32G0xx/Source/STM32G07x_Vectors.s (revision 3) @@ -0,0 +1,236 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2020 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : STM32G07x_Vectors.s +Purpose : Exception and interrupt vectors for STM32G07x devices. + +Additional information: + Preprocessor Definitions + __NO_EXTERNAL_INTERRUPTS + If defined, + the vector table will contain only the internal exceptions + and interrupts. + + __OPTIMIZATION_SMALL + If defined, + all weak definitions of interrupt handlers will share the + same implementation. + If not defined, + all weak definitions of interrupt handlers will be defined + with their own implementation. +*/ + .syntax unified + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ + +// +// Directly place a vector (word) in the vector table +// +.macro VECTOR Name= + .section .vectors, "ax" + .code 16 + .word \Name +.endm + +// +// Declare an exception handler with a weak definition +// +.macro EXC_HANDLER Name= + // + // Insert vector in vector table + // + .section .vectors, "ax" + .word \Name + // + // Insert dummy handler in init section + // + .section .init.\Name, "ax" + .thumb_func + .weak \Name +\Name: + 1: b 1b // Endless loop +.endm + +// +// Declare an interrupt handler with a weak definition +// +.macro ISR_HANDLER Name= + // + // Insert vector in vector table + // + .section .vectors, "ax" + .word \Name + // + // Insert dummy handler in init section + // +#if defined(__OPTIMIZATION_SMALL) + .section .init, "ax" + .weak \Name + .thumb_set \Name,Dummy_Handler +#else + .section .init.\Name, "ax" + .thumb_func + .weak \Name +\Name: + 1: b 1b // Endless loop +#endif +.endm + +// +// Place a reserved vector in vector table +// +.macro ISR_RESERVED + .section .vectors, "ax" + .word 0 +.endm + +// +// Place a reserved vector in vector table +// +.macro ISR_RESERVED_DUMMY + .section .vectors, "ax" + .word Dummy_Handler +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern __stack_end__ + .extern Reset_Handler + .extern HardFault_Handler + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* Setup of the vector table and weak definition of interrupt handlers +* +*/ + .section .vectors, "ax" + .code 16 + .balign 512 + .global _vectors +_vectors: + // + // Internal exceptions and interrupts + // + VECTOR __stack_end__ + VECTOR Reset_Handler + EXC_HANDLER NMI_Handler + VECTOR HardFault_Handler + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + EXC_HANDLER SVC_Handler + ISR_RESERVED + ISR_RESERVED + EXC_HANDLER PendSV_Handler + EXC_HANDLER SysTick_Handler + // + // External interrupts + // +#ifndef __NO_EXTERNAL_INTERRUPTS + ISR_HANDLER WWDG_IRQHandler + ISR_HANDLER PVD_IRQHandler + ISR_HANDLER RTC_STAMP_IRQHandler + ISR_HANDLER FLASH_IRQHandler + ISR_HANDLER RCC_IRQHandler + ISR_HANDLER EXTI0_1_IRQHandler + ISR_HANDLER EXTI2_3_IRQHandler + ISR_HANDLER EXTI4_15_IRQHandler + ISR_HANDLER UCPD1_UCPD2_IRQHandler + ISR_HANDLER DMA_Channel1_IRQHandler + ISR_HANDLER DMA_Channel2_3_IRQHandler + ISR_HANDLER DMA_Channel4_5_6_7_IRQHandler + ISR_HANDLER ADC_COMP_IRQHandler + ISR_HANDLER TIM1_BRK_UP_TRG_COMP_IRQHandler + ISR_HANDLER TIM1_CC_IRQHandler + ISR_HANDLER TIM2_IRQHandler + ISR_HANDLER TIM3_IRQHandler + ISR_HANDLER TIM6_DAC_LPTIM1_IRQHandler + ISR_HANDLER TIM7_LPTIM2_IRQHandler + ISR_HANDLER TIM14_IRQHandler + ISR_HANDLER TIM15_IRQHandler + ISR_HANDLER TIM16_IRQHandler + ISR_HANDLER TIM17_IRQHandler + ISR_HANDLER I2C1_IRQHandler + ISR_HANDLER I2C2_IRQHandler + ISR_HANDLER SPI1_IRQHandler + ISR_HANDLER SPI2_IRQHandler + ISR_HANDLER USART1_IRQHandler + ISR_HANDLER USART2_IRQHandler + ISR_HANDLER USART3_USART4_LPUART1_IRQHandler + ISR_HANDLER CEC_IRQHandler + ISR_HANDLER AES_RNG_IRQHandler +#endif + // + .section .vectors, "ax" +_vectors_end: + + +/********************************************************************* +* +* Dummy handler to be used for reserved interrupt vectors +* and weak implementation of interrupts. +* +*/ + .section .init.Dummy_Handler, "ax" + .thumb_func + .weak Dummy_Handler +Dummy_Handler: + 1: b 1b // Endless loop + + +/*************************** End of file ****************************/ Index: ecs_cellMon/Bootloader/SES/STM32G0xx/Source/STM32G0xx_Startup.s =================================================================== --- ecs_cellMon/Bootloader/SES/STM32G0xx/Source/STM32G0xx_Startup.s (revision 3) +++ ecs_cellMon/Bootloader/SES/STM32G0xx/Source/STM32G0xx_Startup.s (revision 3) @@ -0,0 +1,209 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2020 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : STM32G0xx_Startup.s +Purpose : Startup and exception handlers for STM32G0xx devices. + +Additional information: + Preprocessor Definitions + __NO_SYSTEM_INIT + If defined, + SystemInit is not called. + If not defined, + SystemInit is called. + SystemInit is usually supplied by the CMSIS files. + This file declares a weak implementation as fallback. + + __MEMORY_INIT + If defined, + MemoryInit is called after SystemInit. + void MemoryInit(void) can be implemented to enable external + memory controllers. + +*/ + + .syntax unified + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* Reset_Handler +* +* Function description +* Exception handler for reset. +* Generic bringup of a Cortex-M system. +* +* Additional information +* The stack pointer is expected to be initialized by hardware, +* i.e. read from vectortable[0]. +* For manual initialization add +* ldr R0, =__stack_end__ +* mov SP, R0 +*/ + .global reset_handler + .global Reset_Handler + .equ reset_handler, Reset_Handler + .section .init.Reset_Handler, "ax" + .balign 2 + .thumb_func +Reset_Handler: +#ifndef __NO_SYSTEM_INIT + // + // Call SystemInit + // + bl SystemInit +#endif +#ifdef __MEMORY_INIT + // + // Call MemoryInit + // + bl MemoryInit +#endif +#ifdef __VECTORS_IN_RAM + // + // Copy vector table (from Flash) to RAM + // + ldr R0, =__vectors_start__ + ldr R1, =__vectors_end__ + ldr R2, =__vectors_ram_start__ +1: + cmp R0, R1 + beq 2f + ldr R3, [R0] + str R3, [R2] + adds R0, R0, #4 + adds R2, R2, #4 + b 1b +2: +#endif + // + // Jump to runtime initialization, which calls main(). + // + b _start + + // + // Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP, + // when there is no strong definition of SystemInit. + // + .weak SystemInit + // + // Place SystmeCoreClockUpdate in .init_array + // to be called after runtime initialization + // +#ifndef __NO_SYSTEM_INIT + .section .init_array, "aw" + .balign 4 + .word SystemCoreClockUpdate +#endif + +/********************************************************************* +* +* HardFault_Handler +* +* Function description +* Simple exception handler for HardFault. +* In case of a HardFault caused by BKPT instruction without +* debugger attached, return execution, otherwise stay in loop. +* +* Additional information +* The stack pointer is expected to be initialized by hardware, +* i.e. read from vectortable[0]. +* For manual initialization add +* ldr R0, =__stack_end__ +* mov SP, R0 +*/ + .weak HardFault_Handler + .section .init.HardFault_Handler, "ax" + .balign 2 + .thumb_func +HardFault_Handler: + // + // Check if HardFault is caused by BKPT instruction + // + ldr R1, =0xE000ED2C // Load NVIC_HFSR + ldr R2, [R1] + cmp R2, #0 // Check NVIC_HFSR[31] + +hfLoop: + bmi hfLoop // Not set? Stay in HardFault Handler. + // + // Continue execution after BKPT instruction + // +#if defined(__thumb__) && !defined(__thumb2__) + movs R0, #4 + mov R1, LR + tst R0, R1 // Check EXC_RETURN in Link register bit 2. + bne Uses_PSP + mrs R0, MSP // Stacking was using MSP. + b Pass_StackPtr +Uses_PSP: + mrs R0, PSP // Stacking was using PSP. +Pass_StackPtr: +#else + tst LR, #4 // Check EXC_RETURN[2] in link register to get the return stack + ite eq + mrseq R0, MSP // Frame stored on MSP + mrsne R0, PSP // Frame stored on PSP +#endif + // + // Reset HardFault Status + // +#if defined(__thumb__) && !defined(__thumb2__) + movs R3, #1 + lsls R3, R3, #31 + orrs R2, R3 + str R2, [R1] +#else + orr R2, R2, #0x80000000 + str R2, [R1] +#endif + // + // Adjust return address + // + ldr R1, [R0, #24] // Get stored PC from stack + adds R1, #2 // Adjust PC by 2 to skip current BKPT + str R1, [R0, #24] // Write back adjusted PC to stack + // + bx LR // Return + +/*************************** End of file ****************************/ Index: ecs_cellMon/Bootloader/SES/STM32G0xx_Flash.icf =================================================================== --- ecs_cellMon/Bootloader/SES/STM32G0xx_Flash.icf (revision 3) +++ ecs_cellMon/Bootloader/SES/STM32G0xx_Flash.icf (revision 3) @@ -0,0 +1,107 @@ +// ********************************************************************** +// * SEGGER Microcontroller GmbH * +// * The Embedded Experts * +// ********************************************************************** +// * * +// * (c) 2014 - 2019 SEGGER Microcontroller GmbH * +// * (c) 2001 - 2019 Rowley Associates Limited * +// * * +// * www.segger.com Support: support@segger.com * +// * * +// ********************************************************************** +// * * +// * All rights reserved. * +// * * +// * Redistribution and use in source and binary forms, with or * +// * without modification, are permitted provided that the following * +// * conditions are met: * +// * * +// * - Redistributions of source code must retain the above copyright * +// * notice, this list of conditions and the following disclaimer. * +// * * +// * - Neither the name of SEGGER Microcontroller GmbH * +// * nor the names of its contributors may be used to endorse or * +// * promote products derived from this software without specific * +// * prior written permission. * +// * * +// * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +// * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +// * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +// * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +// * DISCLAIMED. * +// * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +// * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +// * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +// * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +// * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +// * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +// * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +// * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +// * DAMAGE. * +// * * +// ********************************************************************** + +define memory with size = 4G; + +// +// Combined regions per memory type +// +define region FLASH = FLASH1; +define region RAM = RAM1; + +// +// Block definitions +// +define block vectors { section .vectors }; // Vector table section +define block vectors_ram { section .vectors_ram }; // Vector table section +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block exidx { section .ARM.exidx, section .ARM.exidx.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +// +// Explicit initialization settings for sections +// +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +initialize by copy /* with packing=auto */ { section .data, section .data.*, section .*.data, section .*.data.* }; +initialize by copy /* with packing=auto */ { section .fast, section .fast.* }; + +// +// FLASH Placement +// +place at start of FLASH { block vectors }; // Vector table section +place in FLASH with minimum size order { section .init, section .init.*, // Init code section + section .init_rodata, section .init_rodata.*, // Init read-only section + section .text, section .text.*, // Code section + section .rodata, section .rodata.*, // Read-only data section + section .segger.*, // Auto-generated initialization + block exidx, // ARM exception unwinding block + block ctors, // Constructors block + block dtors }; // Destructors block +place in FLASH { block tdata_load }; // Thread-local-storage load image +// +// Explicit placement in FLASHn +// +place in FLASH1 { section .FLASH1, section .FLASH1.* }; + +// +// RAM Placement +// +place at start of RAM { block vectors_ram }; +place in RAM { section .non_init, section .non_init.*, // No initialization section + block tls }; // Thread-local-storage block +place in RAM with auto order { section .fast, section .fast.*, // "ramfunc" section + section .data, section .data.*, // Initialized data section + section .bss, section .bss.* + }; // Static data section +place in RAM { block heap }; // Heap reserved block +place at end of RAM { block stack }; // Stack reserved block at the end + +// +// Explicit placement in RAMn +// +place in RAM1 { section .RAM1, section .RAM1.* }; Index: ecs_cellMon/Bootloader/SES/aes.c =================================================================== --- ecs_cellMon/Bootloader/SES/aes.c (revision 3) +++ ecs_cellMon/Bootloader/SES/aes.c (revision 3) @@ -0,0 +1,592 @@ +/* + +This is an implementation of the AES128 algorithm, specifically ECB and CBC mode. + +The implementation is verified against the test vectors in: + National Institute of Standards and Technology Special Publication 800-38A 2001 ED + +ECB-AES128 +---------- + + plain-text: + 6bc1bee22e409f96e93d7e117393172a + ae2d8a571e03ac9c9eb76fac45af8e51 + 30c81c46a35ce411e5fbc1191a0a52ef + f69f2445df4f9b17ad2b417be66c3710 + + key: + 2b7e151628aed2a6abf7158809cf4f3c + + resulting cipher + 3ad77bb40d7a3660a89ecaf32466ef97 + f5d3d58503b9699de785895a96fdbaaf + 43b1cd7f598ece23881b00e3ed030688 + 7b0c785e27e8ad3f8223207104725dd4 + + +NOTE: String length must be evenly divisible by 16byte (str_len % 16 == 0) + You should pad the end of the string with zeros if this is not the case. + +*/ + + +/*****************************************************************************/ +/* Includes: */ +/*****************************************************************************/ +#include +//#include // CBC mode, for memset +#include "aes.h" +//#include + + +/*****************************************************************************/ +/* Defines: */ +/*****************************************************************************/ +// The number of columns comprising a state in AES. This is a constant in AES. Value=4 +#define Nb 4 +// The number of 32 bit words in a key. +#define Nk 4 +// Key length in bytes [128 bit] +#define KEYLEN 16 +// The number of rounds in AES Cipher. +#define Nr 10 + +// jcallan@github points out that declaring Multiply as a function +// reduces code size considerably with the Keil ARM compiler. +// See this link for more information: https://github.com/kokke/tiny-AES128-C/pull/3 +#ifndef MULTIPLY_AS_A_FUNCTION + #define MULTIPLY_AS_A_FUNCTION 0 +#endif + + +/*****************************************************************************/ +/* Private variables: */ +/*****************************************************************************/ +// state - array holding the intermediate results during decryption. +typedef uint8_t state_t[4][4]; +static state_t* state; + +// The array that stores the round keys. +static uint8_t RoundKey[176]; + +// The Key input to the AES Program +static const uint8_t* Key; + +#if defined(CBC) && CBC + // Initial Vector used only for CBC mode + static uint8_t* Iv; +#endif + +// The lookup-tables are marked const so they can be placed in read-only storage instead of RAM +// The numbers below can be computed dynamically trading ROM for RAM - +// This can be useful in (embedded) bootloader applications, where ROM is often limited. +static const uint8_t sbox[256] = { + //0 1 2 3 4 5 6 7 8 9 A B C D E F + 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, + 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, + 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, + 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, + 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, + 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, + 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, + 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, + 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, + 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, + 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, + 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, + 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, + 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, + 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, + 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 }; + +static const uint8_t rsbox[256] = +{ 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, + 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, + 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, + 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, + 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, + 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, + 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, + 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, + 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, + 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, + 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, + 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, + 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, + 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, + 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, + 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d }; + + +// The round constant word array, Rcon[i], contains the values given by +// x to th e power (i-1) being powers of x (x is denoted as {02}) in the field GF(2^8) +// Note that i starts at 1, not 0). +static const uint8_t Rcon[255] = { + 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, + 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, + 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, + 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, + 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, + 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, + 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, + 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, + 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, + 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, + 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, + 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, + 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, + 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, + 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, + 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb }; + + +/*****************************************************************************/ +/* Private functions: */ +/*****************************************************************************/ +static uint8_t getSBoxValue(uint8_t num) +{ + return sbox[num]; +} + +static uint8_t getSBoxInvert(uint8_t num) +{ + return rsbox[num]; +} + +// This function produces Nb(Nr+1) round keys. The round keys are used in each round to decrypt the states. +static void KeyExpansion(void) +{ + uint32_t i, j, k; + uint8_t tempa[4]; // Used for the column/row operations + + // The first round key is the key itself. + for(i = 0; i < Nk; ++i) + { + RoundKey[(i * 4) + 0] = Key[(i * 4) + 0]; + RoundKey[(i * 4) + 1] = Key[(i * 4) + 1]; + RoundKey[(i * 4) + 2] = Key[(i * 4) + 2]; + RoundKey[(i * 4) + 3] = Key[(i * 4) + 3]; + } + + // All other round keys are found from the previous round keys. + for(; (i < (Nb * (Nr + 1))); ++i) + { + for(j = 0; j < 4; ++j) + { + tempa[j]=RoundKey[(i-1) * 4 + j]; + } + if (i % Nk == 0) + { + // This function rotates the 4 bytes in a word to the left once. + // [a0,a1,a2,a3] becomes [a1,a2,a3,a0] + + // Function RotWord() + { + k = tempa[0]; + tempa[0] = tempa[1]; + tempa[1] = tempa[2]; + tempa[2] = tempa[3]; + tempa[3] = k; + } + + // SubWord() is a function that takes a four-byte input word and + // applies the S-box to each of the four bytes to produce an output word. + + // Function Subword() + { + tempa[0] = getSBoxValue(tempa[0]); + tempa[1] = getSBoxValue(tempa[1]); + tempa[2] = getSBoxValue(tempa[2]); + tempa[3] = getSBoxValue(tempa[3]); + } + + tempa[0] = tempa[0] ^ Rcon[i/Nk]; + } + else if (Nk > 6 && i % Nk == 4) + { + // Function Subword() + { + tempa[0] = getSBoxValue(tempa[0]); + tempa[1] = getSBoxValue(tempa[1]); + tempa[2] = getSBoxValue(tempa[2]); + tempa[3] = getSBoxValue(tempa[3]); + } + } + RoundKey[i * 4 + 0] = RoundKey[(i - Nk) * 4 + 0] ^ tempa[0]; + RoundKey[i * 4 + 1] = RoundKey[(i - Nk) * 4 + 1] ^ tempa[1]; + RoundKey[i * 4 + 2] = RoundKey[(i - Nk) * 4 + 2] ^ tempa[2]; + RoundKey[i * 4 + 3] = RoundKey[(i - Nk) * 4 + 3] ^ tempa[3]; + } +} + +// This function adds the round key to state. +// The round key is added to the state by an XOR function. +static void AddRoundKey(uint8_t round) +{ + uint8_t i,j; + for(i=0;i<4;++i) + { + for(j = 0; j < 4; ++j) + { + (*state)[i][j] ^= RoundKey[round * Nb * 4 + i * Nb + j]; + } + } +} + +// The SubBytes Function Substitutes the values in the +// state matrix with values in an S-box. +static void SubBytes(void) +{ + uint8_t i, j; + for(i = 0; i < 4; ++i) + { + for(j = 0; j < 4; ++j) + { + (*state)[j][i] = getSBoxValue((*state)[j][i]); + } + } +} + +// The ShiftRows() function shifts the rows in the state to the left. +// Each row is shifted with different offset. +// Offset = Row number. So the first row is not shifted. +static void ShiftRows(void) +{ + uint8_t temp; + + // Rotate first row 1 columns to left + temp = (*state)[0][1]; + (*state)[0][1] = (*state)[1][1]; + (*state)[1][1] = (*state)[2][1]; + (*state)[2][1] = (*state)[3][1]; + (*state)[3][1] = temp; + + // Rotate second row 2 columns to left + temp = (*state)[0][2]; + (*state)[0][2] = (*state)[2][2]; + (*state)[2][2] = temp; + + temp = (*state)[1][2]; + (*state)[1][2] = (*state)[3][2]; + (*state)[3][2] = temp; + + // Rotate third row 3 columns to left + temp = (*state)[0][3]; + (*state)[0][3] = (*state)[3][3]; + (*state)[3][3] = (*state)[2][3]; + (*state)[2][3] = (*state)[1][3]; + (*state)[1][3] = temp; +} + +static uint8_t xtime(uint8_t x) +{ + return ((x<<1) ^ (((x>>7) & 1) * 0x1b)); +} + +// MixColumns function mixes the columns of the state matrix +static void MixColumns(void) +{ + uint8_t i; + uint8_t Tmp,Tm,t; + for(i = 0; i < 4; ++i) + { + t = (*state)[i][0]; + Tmp = (*state)[i][0] ^ (*state)[i][1] ^ (*state)[i][2] ^ (*state)[i][3] ; + Tm = (*state)[i][0] ^ (*state)[i][1] ; Tm = xtime(Tm); (*state)[i][0] ^= Tm ^ Tmp ; + Tm = (*state)[i][1] ^ (*state)[i][2] ; Tm = xtime(Tm); (*state)[i][1] ^= Tm ^ Tmp ; + Tm = (*state)[i][2] ^ (*state)[i][3] ; Tm = xtime(Tm); (*state)[i][2] ^= Tm ^ Tmp ; + Tm = (*state)[i][3] ^ t ; Tm = xtime(Tm); (*state)[i][3] ^= Tm ^ Tmp ; + } +} + +// Multiply is used to multiply numbers in the field GF(2^8) +#if MULTIPLY_AS_A_FUNCTION +static uint8_t Multiply(uint8_t x, uint8_t y) +{ + return (((y & 1) * x) ^ + ((y>>1 & 1) * xtime(x)) ^ + ((y>>2 & 1) * xtime(xtime(x))) ^ + ((y>>3 & 1) * xtime(xtime(xtime(x)))) ^ + ((y>>4 & 1) * xtime(xtime(xtime(xtime(x)))))); + } +#else +#define Multiply(x, y) \ + ( ((y & 1) * x) ^ \ + ((y>>1 & 1) * xtime(x)) ^ \ + ((y>>2 & 1) * xtime(xtime(x))) ^ \ + ((y>>3 & 1) * xtime(xtime(xtime(x)))) ^ \ + ((y>>4 & 1) * xtime(xtime(xtime(xtime(x)))))) \ + +#endif + +// MixColumns function mixes the columns of the state matrix. +// The method used to multiply may be difficult to understand for the inexperienced. +// Please use the references to gain more information. +static void InvMixColumns(void) +{ + int i; + uint8_t a,b,c,d; + for(i=0;i<4;++i) + { + a = (*state)[i][0]; + b = (*state)[i][1]; + c = (*state)[i][2]; + d = (*state)[i][3]; + + (*state)[i][0] = Multiply(a, 0x0e) ^ Multiply(b, 0x0b) ^ Multiply(c, 0x0d) ^ Multiply(d, 0x09); + (*state)[i][1] = Multiply(a, 0x09) ^ Multiply(b, 0x0e) ^ Multiply(c, 0x0b) ^ Multiply(d, 0x0d); + (*state)[i][2] = Multiply(a, 0x0d) ^ Multiply(b, 0x09) ^ Multiply(c, 0x0e) ^ Multiply(d, 0x0b); + (*state)[i][3] = Multiply(a, 0x0b) ^ Multiply(b, 0x0d) ^ Multiply(c, 0x09) ^ Multiply(d, 0x0e); + } +} + + +// The SubBytes Function Substitutes the values in the +// state matrix with values in an S-box. +static void InvSubBytes(void) +{ + uint8_t i,j; + for(i=0;i<4;++i) + { + for(j=0;j<4;++j) + { + (*state)[j][i] = getSBoxInvert((*state)[j][i]); + } + } +} + +static void InvShiftRows(void) +{ + uint8_t temp; + + // Rotate first row 1 columns to right + temp=(*state)[3][1]; + (*state)[3][1]=(*state)[2][1]; + (*state)[2][1]=(*state)[1][1]; + (*state)[1][1]=(*state)[0][1]; + (*state)[0][1]=temp; + + // Rotate second row 2 columns to right + temp=(*state)[0][2]; + (*state)[0][2]=(*state)[2][2]; + (*state)[2][2]=temp; + + temp=(*state)[1][2]; + (*state)[1][2]=(*state)[3][2]; + (*state)[3][2]=temp; + + // Rotate third row 3 columns to right + temp=(*state)[0][3]; + (*state)[0][3]=(*state)[1][3]; + (*state)[1][3]=(*state)[2][3]; + (*state)[2][3]=(*state)[3][3]; + (*state)[3][3]=temp; +} + + +// Cipher is the main function that encrypts the PlainText. +static void Cipher(void) +{ + uint8_t round = 0; + + // Add the First round key to the state before starting the rounds. + AddRoundKey(0); + + // There will be Nr rounds. + // The first Nr-1 rounds are identical. + // These Nr-1 rounds are executed in the loop below. + for(round = 1; round < Nr; ++round) + { + SubBytes(); + ShiftRows(); + MixColumns(); + AddRoundKey(round); + } + + // The last round is given below. + // The MixColumns function is not here in the last round. + SubBytes(); + ShiftRows(); + AddRoundKey(Nr); +} + +static void InvCipher(void) +{ + uint8_t round=0; + + // Add the First round key to the state before starting the rounds. + AddRoundKey(Nr); + + // There will be Nr rounds. + // The first Nr-1 rounds are identical. + // These Nr-1 rounds are executed in the loop below. + for(round=Nr-1;round>0;round--) + { + InvShiftRows(); + InvSubBytes(); + AddRoundKey(round); + InvMixColumns(); + } + + // The last round is given below. + // The MixColumns function is not here in the last round. + InvShiftRows(); + InvSubBytes(); + AddRoundKey(0); +} + +static void BlockCopy(uint8_t* output, uint8_t* input) +{ + uint8_t i; + for (i=0;i + + +// #define the macros below to 1/0 to enable/disable the mode of operation. +// +// CBC enables AES128 encryption in CBC-mode of operation and handles 0-padding. +// ECB enables the basic ECB 16-byte block algorithm. Both can be enabled simultaneously. + +// The #ifndef-guard allows it to be configured before #include'ing or at compile time. +#ifndef CBC + #define CBC 0 +#endif + +#ifndef ECB + #define ECB 1 +#endif + + + +#if defined(ECB) && ECB + +//void AES128_ECB_encrypt(uint8_t* input, const uint8_t* key, uint8_t *output); +void AES128_ECB_decrypt(uint8_t* input, const uint8_t* key, uint8_t *output); + +#endif // #if defined(ECB) && ECB + + +#if defined(CBC) && CBC + +void AES128_CBC_encrypt_buffer(uint8_t* output, uint8_t* input, uint32_t length, const uint8_t* key, const uint8_t* iv); +void AES128_CBC_decrypt_buffer(uint8_t* output, uint8_t* input, uint32_t length, const uint8_t* key, const uint8_t* iv); + +#endif // #if defined(CBC) && CBC + + + +#endif //_AES_H_ +//void phex(uint8_t* str, int num); Index: ecs_cellMon/Bootloader/SES/bootloader.emProject =================================================================== --- ecs_cellMon/Bootloader/SES/bootloader.emProject (revision 3) +++ ecs_cellMon/Bootloader/SES/bootloader.emProject (revision 3) @@ -0,0 +1,96 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: ecs_cellMon/Bootloader/SES/bootloader.emSession =================================================================== --- ecs_cellMon/Bootloader/SES/bootloader.emSession (revision 3) +++ ecs_cellMon/Bootloader/SES/bootloader.emSession (revision 3) @@ -0,0 +1,74 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: ecs_cellMon/Bootloader/SES/bootloader_Debug.jlink =================================================================== --- ecs_cellMon/Bootloader/SES/bootloader_Debug.jlink (revision 3) +++ ecs_cellMon/Bootloader/SES/bootloader_Debug.jlink (revision 3) @@ -0,0 +1,40 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +WorkRAMSize = 0x8000 +WorkRAMAddr = 0x20000000 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF Index: ecs_cellMon/Bootloader/SES/bootloader_Release.jlink =================================================================== --- ecs_cellMon/Bootloader/SES/bootloader_Release.jlink (revision 3) +++ ecs_cellMon/Bootloader/SES/bootloader_Release.jlink (revision 3) @@ -0,0 +1,40 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +WorkRAMSize = 0x8000 +WorkRAMAddr = 0x20000000 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF Index: ecs_cellMon/Bootloader/SES/main.c =================================================================== --- ecs_cellMon/Bootloader/SES/main.c (revision 3) +++ ecs_cellMon/Bootloader/SES/main.c (revision 3) @@ -0,0 +1,1126 @@ +// ECS RS485 bootloader firmware for stmG0 MCUs + +#ifdef DEBUG +#include +#endif +#include + +#include "stm32g0xx.h" +#include "RTT/SEGGER_RTT.h" + +#include "main.h" +#include "aes.h" + +#ifndef DEBUG +#warning "Don't forget to turn off and turn on the device after first programming" +#endif + +// Bootloader firmware internal version +__attribute__((aligned (16))) const char FW_VERSION[16] = {"ECS.FW:01.00.01"}; // setting in linker settings prevents this line to be thrown away + +//AES128 key +const uint8_t AES_KEY[16] = {0x5c, 0x38, 0x36, 0x57, 0x60, 0x3d, 0x0e, 0x38, 0x61, 0x1e, 0x4e, 0x21, 0x62, 0x19, 0x47, 0x62}; + +union +{ + uint8_t address_and_crc[5]; + + struct __attribute__((packed)) + { + uint8_t address[4]; + uint8_t crc; + } raw; + + struct __attribute__((packed)) + { + uint32_t address; + uint8_t res; + } mem32; + + struct __attribute__((packed)) + { + uint8_t* paddress; + uint8_t res; + } mem8; +} u; + +union bigEndian +{ + uint16_t itself; + uint8_t bytes[2]; +}; + +union flashData +{ + uint64_t dwordData[256>>3]; + uint8_t byteData[256]; +}; + +// Tick counter +volatile unsigned int msCounter = 0; + +//----------------------------------------------------------------------------- + +void Init(void); +int16_t WaitForByte(unsigned int toWait); +void Transmit(uint8_t *pData, int numBytes); +void TransmitACK(void); +void TransmitNACK(void); +void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); +void Delay(uint32_t delay_in_ms); +void TurnErrorLEDOn(uint32_t blink_period, uint32_t how_long_to_keep_blinking); +void JumpToApplication(void); + +//----------------------------------------------------------------------------- + +int main(void) +{ + // UART, PORT A and PORTB initialization + Init(); + + // Saving the time bootloader has started + uint32_t bl_startup_time = msCounter; + + while(1) + { + // Waiting for bootloader initialization from host for a 10s +#ifdef DEBUG + printf("%s\nWaiting 10s for communication initialization...\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#endif + int16_t init = WaitForByte(BOOTLOADER_TIME_TO_WAIT); + if (init == -1) // Error occurred, during receiption of one byte + { +#ifdef DEBUG + printf("%s\nError during receiption of one byte!\n", RTT_CTRL_TEXT_BRIGHT_RED); +#endif + // Checking how much time elapsed since bootloader startup + if (msCounter - bl_startup_time > BOOTLOADER_TIME_TO_WAIT) + { + JumpToApplication(); // Trying to start main program, if crc is correct, if not, going back to wait more for programmer + bl_startup_time = msCounter; // Resetting start up time + } + continue; // if we still have time, we can go back to wait a bit more for correct byte + } + else if (init == -2) // Time-out has occured + { +#ifdef DEBUG + printf("%s\nTimeout of 10s!\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#endif + JumpToApplication(); + bl_startup_time = msCounter; // Resetting start up time + continue; // This command should never be reached if CRC is ok + } + else if (init != CMD_INIT) // We received one byte, but it is not one we need + { +#ifdef DEBUG + printf("%s\nWrong INIT byte received! Got %u instead of %u!\n", RTT_CTRL_TEXT_BRIGHT_RED, init, CMD_INIT); +#endif + // Checking how much time elapsed since bootloader startup + if (msCounter - bl_startup_time > BOOTLOADER_TIME_TO_WAIT) + { + JumpToApplication(); // Trying to start main program, if crc is correct, if not, going back to wait more for programmer + bl_startup_time = msCounter; // Resetting start up time + } + continue; + } + +#ifdef DEBUG + printf("%sBootloader is initialized.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#endif + + TransmitACK(); + + // Entering command mode + // We must receive two bytes + // Waiting for a fist byte + int16_t first, second; + while (1) + { + first = WaitForByte(5000); + + if (first == -2) break; // If timeout happened, then we return to init stage + else if (first == -1) continue; // If there's an error during reading from USART, then we keep reading + else + { + second = WaitForByte(5000); + + if (second < 0) continue; // If timeout or error happened, then we go back to the receiving of the first byte + else + { + uint8_t command = first; + uint8_t command_xor = ~second; + + if ((command == CMD_GETID) && (command_xor == CMD_GETID)) + { +#ifdef DEBUG + printf("%sGot GET_ID command.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#endif + uint8_t TxData[5]; + + TxData[0] = CMD_ACK; + TxData[1] = 1; + // Locating DEV_ID in memory + uint8_t *dev_id = (uint8_t*)DBG_BASE; + // Now, we can access it as byte array + TxData[2] = dev_id[1] & 0x0F; // Clearing upper nibble of the MSB + TxData[3] = dev_id[0]; + TxData[4] = CMD_ACK; + + Transmit(TxData, 5); + } + else if ((command == CMD_GET) && (command_xor == CMD_GET)) + { +#ifdef DEBUG + printf("%sGot GET command.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#endif + uint8_t TxData[15]; + + uint8_t idx = 0; + TxData[idx] = CMD_ACK; + TxData[++idx] = 11; + TxData[++idx] = BOOTLOADER_VERSION; + TxData[++idx] = CMD_GET; + TxData[++idx] = CMD_GET_VER_RPS; + TxData[++idx] = CMD_GETID; + TxData[++idx] = CMD_READ_MEMORY; + TxData[++idx] = CMD_GO; + TxData[++idx] = CMD_WRITE_MEMORY; + TxData[++idx] = CMD_ERASE; + TxData[++idx] = CMD_WRITE_PROTECT; + TxData[++idx] = CMD_WRITE_UNPROTECT; + TxData[++idx] = CMD_READOUT_PROTECT; + TxData[++idx] = CMD_READOUT_UNPROTECT; + TxData[++idx] = CMD_ACK; + + Transmit(TxData, 15); + } + else if ((command == CMD_READ_MEMORY) && (command_xor == CMD_READ_MEMORY)) + { +#ifdef DEBUG + printf("%sGot READ_MEMORY command.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#endif + uint8_t TxData; + // !!! Before sending ACK we must check RDP protection + TransmitACK(); + + int error_flag = 0; + int16_t tmp; + + memset(&u, 0, sizeof(u)); + + for (int i = 0; i < 5; i++) + { + tmp = WaitForByte(5000); + if (tmp < 0) + { + error_flag = 1; + break; + } + else u.address_and_crc[i] = tmp; + } + + if (error_flag) continue; + + uint8_t checksum = u.raw.address[0] ^ u.raw.address[1] ^ u.raw.address[2] ^ u.raw.address[3]; + + u.mem32.address = __REV(u.mem32.address); + + if (checksum == u.raw.crc) + { +#ifdef DEBUG + printf("\t%sAddress 0x%08X requested.\n", RTT_CTRL_TEXT_BRIGHT_GREEN, u.mem32.address); +#endif + TransmitACK(); + + uint8_t bytesNumber_crc[2]; + + error_flag = 0; + + for (int i = 0; i < 2; i++) + { + tmp = WaitForByte(5000); + if (tmp < 0) + { + error_flag = 1; + break; + } + else bytesNumber_crc[i] = tmp; + } + + if (error_flag) continue; + + bytesNumber_crc[1] = ~bytesNumber_crc[1]; + + if (bytesNumber_crc[0] == bytesNumber_crc[1]) + { + TransmitACK(); + + // Checking memory address access possibility + + // We do not allow reading from the device, so we send fake data + uint8_t fakeData[bytesNumber_crc[0]+1]; + memset(fakeData, 0xEC, bytesNumber_crc[0]+1); + Transmit(fakeData, bytesNumber_crc[0]+1); + //Transmit(u.mem8.paddress, bytesNumber_crc[0]+1); + } + else TransmitNACK(); + } + else + { +#ifdef DEBUG + printf("\n%s Memory address CRC error!", RTT_CTRL_TEXT_BRIGHT_RED); +#endif + TransmitNACK(); + } + } + else if ((command == CMD_GET_VER_RPS) && (command_xor == CMD_GET_VER_RPS)) + { + uint8_t TxData[5]; + + TxData[0] = CMD_ACK; + TxData[1] = BOOTLOADER_VERSION; + TxData[2] = 0x00; + TxData[3] = 0x00; + + TxData[4] = CMD_ACK; + + Transmit(TxData, 5); + } + else if ((command == CMD_ERASE) && (command_xor == CMD_ERASE)) + { +#ifdef DEBUG + printf("%sGot ERASE command.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#endif + // !!! Before sending ACK we must check RDP protection + TransmitACK(); + + int16_t numPages = WaitForByte(5000); + if (numPages < 0) continue; + else + { + uint8_t Pages[numPages + 2]; // + XOR byte + + int error_flag = 0; + int16_t tmp; + + for (int i = 0; i < (numPages + 2); i++) + { + tmp = WaitForByte(5000); + if (tmp < 0) + { + error_flag = 1; + break; + } + else Pages[i] = tmp; + } + + if (error_flag) continue; +#ifdef DEBUG + printf("\tErasing %d pages:", numPages + 1); +#endif + uint8_t xor_crc = numPages; + for (int i = 0; i < (numPages + 1); i++) + { + xor_crc ^= Pages[i]; +#ifdef DEBUG + printf(" %d", Pages[i]); +#endif + } +#ifdef DEBUG + printf("\n"); +#endif + if (xor_crc == Pages[numPages + 2 - 1]) + { + // Is FLASH_CR register locked for writing? + if (FLASH->CR & FLASH_CR_LOCK) + { + // Unlocking FLASH_CR register + FLASH->KEYR = KEY1; + FLASH->KEYR = KEY2; + } +#ifdef DEBUG + printf("\t\t%sStarting erasing.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#endif + // Erasing corresponding pages, except those containing bootloader itself + for (int i = 0; i < (numPages + 1); i++) + { + if (Pages[i] > BOOTLOADER_LAST_PAGE) // Bootloader occupies first 4-5 pages (2k) + { +#ifdef DEBUG + while (FLASH->SR & FLASH_SR_BSY1) printf("\t%sWaiting for releasing of FLASH memory.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#else + while (FLASH->SR & FLASH_SR_BSY1); +#endif + // Clearing possible old errors + FLASH->SR |= FLASH_SR_FASTERR & FLASH_SR_MISERR & FLASH_SR_PGSERR & FLASH_SR_SIZERR & FLASH_SR_PGAERR & FLASH_SR_PROGERR & FLASH_SR_OPERR; + + FLASH->CR &= ~FLASH_CR_PNB; + FLASH->CR |= Pages[i] << FLASH_CR_PNB_Pos; + + FLASH->CR |= FLASH_CR_PER; + + FLASH->CR |= FLASH_CR_STRT; +#ifdef DEBUG + while (FLASH->SR & FLASH_SR_BSY1) printf("\t\t%sWaiting for page %d to be erased...\n", RTT_CTRL_TEXT_BRIGHT_GREEN, Pages[i]); +#else + while (FLASH->SR & FLASH_SR_BSY1); +#endif +#ifdef DEBUG + printf("\t\t%sPage %d has been erased.\n", RTT_CTRL_TEXT_BRIGHT_GREEN, Pages[i]); +#endif + FLASH->CR &= ~FLASH_CR_PER; + } + } +#ifdef DEBUG + printf("\t\t%sErasing is finished.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#endif + FLASH->CR |= FLASH_CR_LOCK; + + TransmitACK(); + } + else TransmitNACK(); + } + } +#if BOOTLOADER_VERSION > 0x30 + else if ((command == CMD_EXT_ERASE) && (command_xor == CMD_EXT_ERASE)) + { + printf("%sGot EXTENDED ERASE command.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); + + // !!! Before sending ACK we must check RDP protection + TransmitACK(); + + int error_flag = 0; + int16_t tmp; + union bigEndian numPages; + + for (int i = 1; i >= 0; i--) + { + tmp = WaitForByte(5000, 250); + if (tmp < 0) + { + error_flag = 1; + break; + } + else numPages.bytes[i] = tmp; + } + + if (error_flag) continue; + + if ((numPages.itself & 0xFFF0) == 0xFFF0) + { + int16_t crc = WaitForByte(5000, 250); + + if (crc < 0) continue; + else + { + switch(numPages.itself) + { + case 0xFFFF: // Mass erase + if (crc == 0x00) + { + // Perfom erase + TransmitACK(); + } + else + { + TransmitNACK(); + } + break; + + case 0xFFFE: // Bank1 erase + if (crc == 0x01) + { + // Perfom erase + TransmitACK(); + } + else + { + TransmitNACK(); + } + break; + + case 0xFFFD: + if (crc == 0x02) + { + // Perfom erase + TransmitACK(); + } + else + { + TransmitNACK(); + } + break; + } + } + } + else + { + union bigEndian pageCodes[numPages.itself + 1]; + + int error_flag = 0; + int16_t tmp; + + for (int i = 0; i < (numPages.itself + 1); i++) + { + for (int j = 1; j >= 0; j--) + { + tmp = WaitForByte(5000, 125); + if (tmp < 0) + { + error_flag = 1; + break; + } + else pageCodes[i].bytes[j] = tmp; + } + if (error_flag) break; + } + + if (error_flag) continue; + + int16_t crc = WaitForByte(5000, 250); + + if (crc < 0) continue; + else + { + uint8_t checksum = numPages.bytes[1]; + checksum ^= numPages.bytes[0]; + for (int i = 0; i < (numPages.itself + 1); i++) + { + checksum ^= pageCodes[i].bytes[1]; + checksum ^= pageCodes[i].bytes[0]; + } + + if (checksum == crc) + { + // Is FLASH_CR register locked for writing? + if (FLASH->CR & FLASH_CR_LOCK) + { + // Unlocking FLASH_CR register + FLASH->KEYR = KEY1; + FLASH->KEYR = KEY2; + } + + printf("\t%sStarting erasing.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); + + // Erasing corresponding pages, except those containing bootloader itself + for (int i = 0; i < (numPages.itself + 1); i++) + { + if (pageCodes[i].itself > BOOTLOADER_LAST_PAGE) // Bootloader occupies first 4 pages (2k) + { + while (FLASH->SR & FLASH_SR_BSY1) printf("\t%sWaiting for releasing of FLASH memory.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); + + // Clearing possible old errors + FLASH->SR |= FLASH_SR_FASTERR & FLASH_SR_MISERR & FLASH_SR_PGSERR & FLASH_SR_SIZERR & FLASH_SR_PGAERR & FLASH_SR_PROGERR & FLASH_SR_OPERR; + + FLASH->CR &= ~FLASH_CR_PNB; + FLASH->CR |= pageCodes[i].bytes[0] << FLASH_CR_PNB_Pos; + + FLASH->CR |= FLASH_CR_PER; + + FLASH->CR |= FLASH_CR_STRT; + + while (FLASH->SR & FLASH_SR_BSY1) printf("\t%sWaiting for page %d to be erased...\n", RTT_CTRL_TEXT_BRIGHT_GREEN, pageCodes[i].bytes[0]); + + printf("\t%sPage %d has been erased.\n", RTT_CTRL_TEXT_BRIGHT_GREEN, pageCodes[i].bytes[0]); + + FLASH->CR &= ~FLASH_CR_PER; + } + } + + printf("\t%sErasing is finished.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); + + FLASH->CR |= FLASH_CR_LOCK; + + TransmitACK(); + } + else TransmitNACK(); + } + } + } +#endif + else if ((command == CMD_WRITE_MEMORY) && (command_xor == CMD_WRITE_MEMORY)) + { +#ifdef DEBUG + printf("%sGot WRITE MEMORY command.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#endif + // !!! Before sending ACK we must check RDP protection + TransmitACK(); + + int error_flag = 0; + int16_t tmp; + + memset(&u, 0, sizeof(u)); + + for (int i = 0; i < 5; i++) + { + tmp = WaitForByte(5000); + if (tmp < 0) + { + error_flag = 1; + break; + } + else u.address_and_crc[i] = tmp; + } + + if (error_flag) continue; + + uint8_t checksum = u.raw.address[0] ^ u.raw.address[1] ^ u.raw.address[2] ^ u.raw.address[3]; + + if (checksum == u.raw.crc) + { + TransmitACK(); + + int16_t bytesNumber = WaitForByte(5000); + if (bytesNumber < 0) continue; + { + if ((bytesNumber + 1) % 4) + { +#ifdef DEBUG + printf("\t%sBytes number must by multiple of 4!\n", RTT_CTRL_TEXT_BRIGHT_RED); +#endif + TransmitNACK(); + } + else + { + union flashData DataToBeWritten; + + memset(DataToBeWritten.byteData, 0xFF, 256); + + error_flag = 0; + + for (int i = 0; i < (bytesNumber + 1); i++) + { + tmp = WaitForByte(5000); + if (tmp < 0) + { + error_flag = 1; + break; + } + else DataToBeWritten.byteData[i] = tmp; + } + + if (BLUE_LED_PORT->ODR & GPIOx_ODR(GPIO_ODR_OD, BLUE_LED_PIN)) BLUE_LED_PORT->BRR = GPIOx_BRR(GPIO_BRR_BR, BLUE_LED_PIN); + else BLUE_LED_PORT->BSRR = GPIOx_BSRR(GPIO_BSRR_BS, BLUE_LED_PIN); + + if (error_flag) continue; + + // Reading checksum of the above datapacket + tmp = WaitForByte(5000); + if (tmp < 0) continue; + else + { + checksum = bytesNumber; + for (int i = 0; i < (bytesNumber+1); i++) checksum ^= DataToBeWritten.byteData[i]; + + if (checksum == tmp) + { + u.mem32.address = __REV(u.mem32.address); + // We need to define whom belongs this memory, which we are going to write + if ((u.mem32.address >= (FLASH_BASE + BOOTLOADER_PROGRAM_SIZE)) && + ((u.mem32.address + bytesNumber) < (FLASH_BASE + (FLASH_PAGE_NUMBER - MAIN_APP_PARAM_PAGE_NUM)*FLASH_PAGE_SIZE))) + { + // Here we already checked that bootloader is alowed to write in this memory area + // Data is encrypted, so we must decrypt it + + union flashData decryptedData; + memset(decryptedData.byteData, 0x00, 256); +#ifdef DEBUG + printf("\t%sDecrypting %d bytes...", RTT_CTRL_TEXT_BRIGHT_GREEN, bytesNumber + 1); +#endif + for (int i = 0; i < (bytesNumber + 1); i += 16) AES128_ECB_decrypt(DataToBeWritten.byteData + i, AES_KEY, decryptedData.byteData + i); + + // Is FLASH_CR register locked for writing? + if (FLASH->CR & FLASH_CR_LOCK) + { + // Unlocking FLASH_CR register + FLASH->KEYR = KEY1; + FLASH->KEYR = KEY2; + } +#ifdef DEBUG + printf("\t%sStarting programming of %d bytes.\n", RTT_CTRL_TEXT_BRIGHT_GREEN, bytesNumber + 1); +#endif + for (int i = 0; i < ((bytesNumber + 1)>>3); i++) + { +#ifdef DEBUG + while (FLASH->SR & FLASH_SR_BSY1) printf("\t%sWaiting for releasing of FLASH memory.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#else + while (FLASH->SR & FLASH_SR_BSY1); +#endif + + // Clearing possible old errors + FLASH->SR |= FLASH_SR_PGSERR & FLASH_SR_SIZERR & FLASH_SR_PGAERR & FLASH_SR_PROGERR; + + FLASH_Program_DoubleWord(u.mem32.address + (i<<3), decryptedData.dwordData[i]); +#ifdef DEBUG + while (FLASH->SR & FLASH_SR_BSY1) printf("\t%sWaiting for the end of programming.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#else + while (FLASH->SR & FLASH_SR_BSY1); +#endif +#ifdef DEBUG + if (FLASH->SR & FLASH_SR_PGSERR & FLASH_SR_SIZERR & FLASH_SR_PGAERR & FLASH_SR_PROGERR) printf("\t%sProgramming of failed.\n", RTT_CTRL_TEXT_BRIGHT_RED); + else printf("\t%sProgramming of 8 bytes at address 0x%08X performed ok.\n", RTT_CTRL_TEXT_BRIGHT_GREEN, u.mem32.address + (i<<3)); +#endif + } + + // Clearing PG bit + FLASH->CR &= ~FLASH_CR_PG; + + // Locking back FLASH_CR register + FLASH->CR |= FLASH_CR_LOCK; + + TransmitACK(); + } + else + { +#ifdef DEBUG + printf("%sForbidden address of 0x%08X for writing of %d bytes requested!\n", RTT_CTRL_TEXT_BRIGHT_RED, u.mem32.address, bytesNumber + 1); +#endif + TransmitACK(); + } + } + else TransmitNACK(); + } + } + } + } + else TransmitNACK(); + } + else + { +#ifdef DEBUG + printf("%sUnknown command 0x%02X!\n", RTT_CTRL_TEXT_BRIGHT_RED, command); +#endif + //if (BLUE_LED_PORT->ODR & GPIO_ODR_OD10) BLUE_LED_PORT->BRR = GPIO_BRR_BR10; + //else BLUE_LED_PORT->BSRR = GPIO_BSRR_BS10; + + TransmitNACK(); + + if (msCounter - bl_startup_time > BOOTLOADER_TIME_TO_WAIT) + { + JumpToApplication(); + bl_startup_time = msCounter; // Appending more time for bootloader to start-up; + break; // Going back to initialization stage + } + } + } // else where we received second byte + } // else where we received first byte + } // Commands while(1) loop + } // main while(1) loop, which waits for connection +} // int main + +//----------------------------------------------------------------------------- + +void JumpToApplication(void) +{ + // Enabling clocking for CRC module + RCC->AHBENR |= RCC_AHBENR_CRCEN; + // Resetting CRC unit and loading the content of INIT register into DR register + CRC->CR |= CRC_CR_RESET; + // Default POLYSIZE is 32 bit + // Default POLYNOMIAL is 0x04C11DB7 + // Default CRC initial value is 0xFFFFFFFF +#ifdef DEBUG + printf("%sStarting calculating FW CRC\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#endif + for (unsigned int i = 0; i < ((FLASH_PAGE_SIZE * (FLASH_PAGE_NUMBER - MAIN_APP_PARAM_PAGE_NUM)) - BOOTLOADER_PROGRAM_SIZE - CRC_LEN); i += 4) + { +#ifdef DEBUG + printf("\r%s\tAddress: 0x%08X ", RTT_CTRL_TEXT_BRIGHT_GREEN, MAIN_APP_START_ADDRESS + i); +#endif + /*if (!(i%256)) + { + if (BLUE_LED_PORT->ODR & GPIO_ODR_OD2) BLUE_LED_PORT->BRR = GPIO_BRR_BR2; + else BLUE_LED_PORT->BSRR = GPIO_BSRR_BS2; + Delay(35); + }*/ + // Putting next 4 bytes into CRC calculation unit + CRC->DR = __REV(*(uint32_t*)(MAIN_APP_START_ADDRESS + i)); + } +#ifdef DEBUG + printf("%sDone!\n", RTT_CTRL_TEXT_BRIGHT_GREEN); +#endif + // Extracting CRC saved on last 4 bytes of the used FLASH memory + uint32_t savedCRC = *(uint32_t*)(FLASH_BASE + (FLASH_PAGE_NUMBER - MAIN_APP_PARAM_PAGE_NUM)*FLASH_PAGE_SIZE - CRC_LEN); + + if (CRC->DR == savedCRC) + { +#ifdef DEBUG + printf("%s\tCRCs are equal.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); + Delay(500); +#endif + // Disabling clocking for CRC module + RCC->AHBENR &= ~RCC_AHBENR_CRCEN; + // Resetting SysTick settings + SysTick->CTRL = SysTick->LOAD = SysTick->VAL = 0; + __disable_irq(); + + // Changing vector table address to the beginning of the main application + SCB->VTOR = MAIN_APP_START_ADDRESS; + // Setting stack pointer + __set_MSP(*(__IO uint32_t*)MAIN_APP_START_ADDRESS); + __enable_irq(); + // Executing first command from main app + ((void(*)(void))(*(__IO uint32_t*)(MAIN_APP_START_ADDRESS + 4)))(); + + // In normal situation, program flow should never reach this loop + while(1) TurnErrorLEDOn(125, -1); + } + else + { +#ifdef DEBUG + printf("%sCRC error!\n", RTT_CTRL_TEXT_BRIGHT_RED); +#endif + TurnErrorLEDOn(250, 5000); + //return -1; + } +} + +//----------------------------------------------------------------------------- + +void Delay(uint32_t D) +{ + volatile uint32_t tick_start = msCounter; + while (msCounter - tick_start < D); +} + +//----------------------------------------------------------------------------- + +void TransmitACK(void) +{ + uint8_t TxData = CMD_ACK; + Transmit(&TxData, 1); +} + +//----------------------------------------------------------------------------- + +void TransmitNACK(void) +{ + uint8_t TxData = CMD_NACK; + Transmit(&TxData, 1); +} + +//----------------------------------------------------------------------------- + +/** + * @brief Program double-word (64-bit) at a specified address. + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed. + * @retval None + */ +void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) +{ + /* Set PG bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Program first word */ + *(uint32_t *)Address = (uint32_t)Data; + + /* Barrier to ensure programming is performed in 2 steps, in right order + (independently of compiler optimization behavior) */ + __ISB(); + + /* Program second word */ + *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U); +} + +//----------------------------------------------------------------------------- + +void Transmit(uint8_t *pData, int numBytes) +{ + // Disabling Receiver + //UART->CR1 &= ~USART_CR1_RE; +#ifdef DEBUG + const int SCREEN_LIMIT = 40; + + printf("\t%sSending %d bytes: ", RTT_CTRL_TEXT_BRIGHT_GREEN, numBytes); +#endif + for (int i = 0; i < numBytes; i++) + { + // Checking whether transmitter is free + while (!(UART->ISR & USART_ISR_TXE_TXFNF)); + + UART->TDR = pData[i]; +#ifdef DEBUG + if (i <= SCREEN_LIMIT) printf("%02X", pData[i]); +#endif + } +#ifdef DEBUG + if (numBytes > SCREEN_LIMIT) printf("...\n"); + else printf("\n"); +#endif + + //while (!(UART->ISR & USART_ISR_TC)); + // Enabling Receiver + //UART->CR1 |= USART_CR1_RE; +} + +//----------------------------------------------------------------------------- + +void SysTick_Handler(void) +{ + msCounter++; +} + +//----------------------------------------------------------------------------- + +void HardFault_Handler(void) +{ + TurnErrorLEDOn(500, -1); +} + +//----------------------------------------------------------------------------- + +void NMI_Handler(void) +{ + TurnErrorLEDOn(250, -1); +} + +//----------------------------------------------------------------------------- + +int16_t WaitForByte(unsigned int toWait) +{ + // Waiting until we receive one byte via UART + unsigned int ledStartTime = msCounter; + unsigned int loopStartTime = msCounter; + + while (!(UART->ISR & USART_ISR_RXNE_RXFNE)) + { + if (msCounter - loopStartTime >= toWait) break; + + if (msCounter - ledStartTime >= BLUE_LED_PERIOD) + { + ledStartTime = msCounter; + if (BLUE_LED_PORT->ODR & GPIOx_ODR(GPIO_ODR_OD, BLUE_LED_PIN)) BLUE_LED_PORT->BRR = GPIOx_BRR(GPIO_BRR_BR, BLUE_LED_PIN); + else BLUE_LED_PORT->BSRR = GPIOx_BSRR(GPIO_BSRR_BS, BLUE_LED_PIN); + } + } + + // Checking if timeout occured + if (msCounter - loopStartTime >= toWait) return -2; + + // Checking Overrun error + if (UART->ISR & USART_ISR_ORE) + { +#ifdef DEBUG + printf("%sOverrun error is detected!\n", RTT_CTRL_TEXT_BRIGHT_RED); +#endif + UART->ICR = USART_ICR_ORECF; + volatile int unused = UART->RDR & 0xFF; + return -1; + } + if (UART->ISR & USART_ISR_NE) + { +#ifdef DEBUG + printf("%sNoise is detected!\n", RTT_CTRL_TEXT_BRIGHT_RED); +#endif + UART->ICR = USART_ICR_NECF; + return -1; + } + if (UART->ISR & USART_ISR_FE) + { +#ifdef DEBUG + printf("%sFrame error is detected!\n", RTT_CTRL_TEXT_BRIGHT_RED); +#endif + UART->ICR = USART_ICR_FECF; + return -1; + } + if (UART->ISR & USART_ISR_PE) + { +#ifdef DEBUG + printf("%sParity error is detected!\n", RTT_CTRL_TEXT_BRIGHT_RED); +#endif + UART->ICR = USART_ICR_PECF; + return -1; + } + + return (UART->RDR & 0xFF); +} + +//----------------------------------------------------------------------------- + +void Init(void) +{ + // Systick timer initialization + SysTick_Config(SystemCoreClock/1000); + +#ifdef DEBUG + printf(RTT_CTRL_CLEAR); + printf("%sProgram started (%s)\n", RTT_CTRL_TEXT_BRIGHT_GREEN, FW_VERSION); +#endif + +#ifdef DEBUG + if (RCC->CR & RCC_CR_HSION) printf("%sHSI is turned on.\n", RTT_CTRL_TEXT_BRIGHT_GREEN); + else + { + printf("%sHSI is not turned on! Program stopped!\n", RTT_CTRL_TEXT_BRIGHT_RED); + TurnErrorLEDOn(500, -1); + } +#else + if (!(RCC->CR & RCC_CR_HSION)) TurnErrorLEDOn(500, -1); +#endif + +#ifdef DEBUG + if (RCC->CR & RCC_CR_HSIRDY) printf("HSI is ready.\n"); + else while (!(RCC->CR & RCC_CR_HSIRDY)) printf("%sWaiting for HSI to be ready!\n", RTT_CTRL_TEXT_YELLOW); +#else + while (!(RCC->CR & RCC_CR_HSIRDY)); +#endif + //printf("Checking RDP level.\n"); + + // Checking state of RDP protection + if (((FLASH->OPTR & FLASH_OPTR_RDP) == 0xAA) || ((FLASH->OPTR & FLASH_OPTR_RDP) == 0xCC)) + { +#ifdef DEBUG + // Checking whether SWD debugger is connected or not + if (SWD_PORT->IDR & SWD_PIN_MSK) + { +#endif + // Debugger is not connected + // Is FLASH_CR register locked for writing? + if (FLASH->CR & FLASH_CR_LOCK) + { + // Unlocking FLASH_CR register + FLASH->KEYR = KEY1; + FLASH->KEYR = KEY2; + } + + // Unlocking FLASH option register + if (FLASH->CR & FLASH_CR_OPTLOCK) + { + FLASH->OPTKEYR = OPTKEY1; + FLASH->OPTKEYR = OPTKEY2; + } + + // Setting RDP level to 1 + FLASH->OPTR &= ~FLASH_OPTR_RDP; + FLASH->OPTR |= 0xEC; // Any value except 0xAA and 0xCC + + while (FLASH->SR & FLASH_SR_BSY1); + + FLASH->CR |= FLASH_CR_OPTSTRT; + + while (FLASH->SR & FLASH_SR_BSY1); + + //printf("RDP is set!\n"); + + // Updating option bytes by resetting of the device + FLASH->CR |= FLASH_CR_OBL_LAUNCH; + + // If we can reach below code then something went wrong + TurnErrorLEDOn(100, -1); +#ifdef DEBUG + } +#endif + } + + // Activating clocking for PORT A and PORT B + RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | RCC_IOPENR_GPIODEN; + + // Setting PA9, PA10 and PA12 pins to Alternate Function mode (2) + UART_PORT->MODER &= ~GPIOx_MODER(GPIO_MODER_MODE, UART_TX_PIN) & + ~GPIOx_MODER(GPIO_MODER_MODE, UART_RX_PIN) & + ~GPIOx_MODER(GPIO_MODER_MODE, UART_TX_EN_PIN); + UART_PORT->MODER |= (2 << GPIOx_MODER_Pos(GPIO_MODER_MODE, UART_TX_PIN)) | + (2 << GPIOx_MODER_Pos(GPIO_MODER_MODE, UART_RX_PIN)) | + (2 << GPIOx_MODER_Pos(GPIO_MODER_MODE, UART_TX_EN_PIN)); + + // Setting pullup for PA10 (RX pin) + UART_PORT->PUPDR &= ~GPIOx_PUPDR(GPIO_PUPDR_PUPD, UART_RX_PIN); + UART_PORT->PUPDR |= (1< 7 + UART_PORT->AFR[1] &= ~GPIO_AFRH_AFSEL(GPIO_AFRH_AFSEL, UART_RX_PIN); + UART_PORT->AFR[1] |= (UART_RX_ALT_FUNC_NUM << GPIO_AFRH_AFSEL_Pos(GPIO_AFRH_AFSEL, UART_RX_PIN)); +#else + UART_PORT->AFR[0] &= ~GPIO_AFRL_AFSEL(GPIO_AFRL_AFSEL, UART_RX_PIN); + UART_PORT->AFR[0] |= (UART_RX_ALT_FUNC_NUM << GPIO_AFRH_AFSEL_Pos(GPIO_AFRH_AFSEL, UART_RX_PIN)); +#endif +#if UART_TX_PIN > 7 + UART_PORT->AFR[1] &= ~GPIO_AFRH_AFSEL(GPIO_AFRH_AFSEL, UART_TX_PIN); + UART_PORT->AFR[1] |= (UART_TX_ALT_FUNC_NUM << GPIO_AFRH_AFSEL_Pos(GPIO_AFRH_AFSEL, UART_TX_PIN)); +#else + UART_PORT->AFR[0] &= ~GPIO_AFRL_AFSEL(GPIO_AFRL_AFSEL, UART_TX_PIN); + UART_PORT->AFR[0] |= (UART_TX_ALT_FUNC_NUM << GPIO_AFRH_AFSEL_Pos(GPIO_AFRH_AFSEL, UART_TX_PIN)); +#endif +#if UART_TX_EN_PIN > 7 + UART_PORT->AFR[1] &= ~GPIO_AFRH_AFSEL(GPIO_AFRH_AFSEL, UART_TX_EN_PIN); + UART_PORT->AFR[1] |= (UART_TXEN_ALT_FUNC_NUM << GPIO_AFRH_AFSEL_Pos(GPIO_AFRH_AFSEL, UART_TX_EN_PIN)); +#else + UART_PORT->AFR[0] &= ~GPIO_AFRL_AFSEL(GPIO_AFRL_AFSEL, UART_TX_EN_PIN); + UART_PORT->AFR[0] |= (UART_TXEN_ALT_FUNC_NUM << GPIO_AFRH_AFSEL_Pos(GPIO_AFRH_AFSEL, UART_TX_EN_PIN)); +#endif + + // Setting LED PORT to output for LED + BLUE_LED_PORT->MODER &= ~GPIOx_MODER(GPIO_MODER_MODE, BLUE_LED_PIN); + RED_LED_PORT->MODER &= ~GPIOx_MODER(GPIO_MODER_MODE, RED_LED_PIN); + BLUE_LED_PORT->MODER |= (1 << GPIOx_MODER_Pos(GPIO_MODER_MODE, BLUE_LED_PIN)); + RED_LED_PORT->MODER |= (1 << GPIOx_MODER_Pos(GPIO_MODER_MODE, RED_LED_PIN)); + + // Activating clocking for UART + RCC->APBENR2 |= RCC_APBENR2_USART1EN; + + // Before changing some settings in USART we must make sure that it turned off + UART->CR1 &= ~USART_CR1_UE; + + // Setting 1 start bit, 9 data bits + UART->CR1 &= ~USART_CR1_M1; + UART->CR1 |= USART_CR1_M0; + + // Setting oversampling to 16 + UART->CR1 &= ~USART_CR1_OVER8; + + // Enabling parity control with EVEN parity + UART->CR1 |= USART_CR1_PCE; + + // Enabling transmitter and receiver + UART->CR1 |= USART_CR1_TE | USART_CR1_RE; + + UART->CR1 |= USART_CR1_DEAT | USART_CR1_DEDT; + + // + //UART->CR2 |= USART_CR2_SWAP; + + // Enabling RS485 transmitter driver control + UART->CR3 |= USART_CR3_DEM; + +#ifdef DEBUG + // Setting baud rate to 19200 + UART->BRR = 833; +#else + // Setting baud rate to 19200 + UART->BRR = 833; +#endif + + // Finally, turning USART on + UART->CR1 |= USART_CR1_UE; + + // Start up sequence + for (int i = 0; i < 5; i++) + { + BLUE_LED_PORT->BSRR = GPIOx_BSRR(GPIO_BSRR_BS, BLUE_LED_PIN); + Delay(150); + BLUE_LED_PORT->BSRR = GPIOx_BSRR(GPIO_BSRR_BR, BLUE_LED_PIN); + Delay(150); + } + +} + +//----------------------------------------------------------------------------- + +void TurnErrorLEDOn(uint32_t bp, uint32_t hl) +{ + // Turning off blue led + BLUE_LED_PORT->BSRR = GPIOx_BSRR(GPIO_BSRR_BR, BLUE_LED_PIN); + uint32_t tickStart = msCounter; + + while(msCounter - tickStart < hl) + { + RED_LED_PORT->BSRR = GPIOx_BSRR(GPIO_BSRR_BS, RED_LED_PIN); + Delay(bp); + RED_LED_PORT->BSRR = GPIOx_BSRR(GPIO_BSRR_BR, RED_LED_PIN); + Delay(bp); + } +} + +/*************************** End of file ****************************/ Index: ecs_cellMon/Bootloader/SES/main.h =================================================================== --- ecs_cellMon/Bootloader/SES/main.h (revision 3) +++ ecs_cellMon/Bootloader/SES/main.h (revision 3) @@ -0,0 +1,91 @@ +#ifndef __MAIN_H__ +#define __MAIN_H__ + +// Bootloader commands + +#define CMD_INIT 0x7F +#define CMD_ACK 0x79 +#define CMD_NACK 0x1F +#define CMD_GET 0x00 +#define CMD_GETID 0x02 +#define CMD_GET_VER_RPS 0x01 +#define CMD_READ_MEMORY 0x11 +#define CMD_GO 0x21 +#define CMD_WRITE_MEMORY 0x31 +#define CMD_ERASE 0x43 +#define CMD_EXT_ERASE 0x44 +#define CMD_WRITE_PROTECT 0x63 +#define CMD_WRITE_UNPROTECT 0x73 +#define CMD_READOUT_PROTECT 0x82 +#define CMD_READOUT_UNPROTECT 0x92 + +// Bootloader compartibility version number: 1.1 +#define BOOTLOADER_VERSION 0x11 + +#define FLASH_PAGE_SIZE (2*1024) /*!< FLASH Page Size, 2 KBytes */ +#define FLASH_PAGE_NUMBER 64 + +#define BOOTLOADER_PROGRAM_SIZE (12*1024) // 12K + +#define BOOTLOADER_LAST_PAGE ((BOOTLOADER_PROGRAM_SIZE/FLASH_PAGE_SIZE)-1) + +#define MAIN_APP_START_ADDRESS (FLASH_BASE + (FLASH_PAGE_SIZE * (BOOTLOADER_LAST_PAGE + 1))) +#define MAIN_APP_PARAM_PAGE_NUM 2 // Amount of reserved pages at the end of the main program for storing some parameters + +#ifdef DEBUG + #define BOOTLOADER_TIME_TO_WAIT 10000 // 10s +#else + #define BOOTLOADER_TIME_TO_WAIT 5000 // 5s +#endif + +#define KEY1 0x45670123U +#define KEY2 0xCDEF89ABU +#define OPTKEY1 0x08192A3BU +#define OPTKEY2 0x4C5D6E7FU + +#define BLUE_LED_PERIOD 75U +#define BLUE_LED_PORT GPIOD +#define RED_LED_PORT GPIOD +#define BLUE_LED_PIN 2 +#define RED_LED_PIN 3 + +#define UART USART1 +#define UART_PORT GPIOA +#define UART_RX_PIN 10 +#define UART_TX_PIN 9 +#define UART_TX_EN_PIN 12 +#define UART_RX_ALT_FUNC_NUM 1 +#define UART_TX_ALT_FUNC_NUM 1 +#define UART_TXEN_ALT_FUNC_NUM 1 + +// Do not EDIT - START +#define GPIOx_BSRR(mask, pin) PRE_GPIOx_BSRR(mask, pin) +#define PRE_GPIOx_BSRR(mask, pin) mask##pin +#define GPIOx_MODER(mask, pin) PRE_GPIOx_MODER(mask, pin) +#define PRE_GPIOx_MODER(mask, pin) mask##pin +#define GPIOx_MODER_Pos(mask, pin) PRE_GPIOx_MODER_Pos(mask, pin) +#define PRE_GPIOx_MODER_Pos(mask, pin) mask##pin##_Pos +#define GPIO_AFRH_AFSEL(mask, pin) PRE_GPIO_AFRH_AFSEL(mask, pin) +#define PRE_GPIO_AFRH_AFSEL(mask, pin) mask##pin +#define GPIO_AFRL_AFSEL(mask, pin) PRE_GPIO_AFRL_AFSEL(mask, pin) +#define PRE_GPIO_AFRL_AFSEL(mask, pin) mask##pin +#define GPIO_AFRH_AFSEL_Pos(mask, pin) PRE_GPIO_AFRH_AFSEL_Pos(mask, pin) +#define PRE_GPIO_AFRH_AFSEL_Pos(mask, pin) mask##pin##_Pos +#define GPIO_AFRL_AFSEL_Pos(mask, pin) PRE_GPIO_AFRL_AFSEL_Pos(mask, pin) +#define PRE_GPIO_AFRL_AFSEL_Pos(mask, pin) mask##pin##_Pos +#define GPIOx_PUPDR(mask, pin) PRE_GPIOx_PUPDR(mask, pin) +#define PRE_GPIOx_PUPDR(mask, pin) mask##pin +#define GPIOx_PUPDR_Pos(mask, pin) PRE_GPIOx_PUPDR_Pos(mask, pin) +#define PRE_GPIOx_PUPDR_Pos(mask, pin) mask##pin##_Pos +#define GPIOx_ODR(mask, pin) PRE_GPIOx_ODR(mask, pin) +#define PRE_GPIOx_ODR(mask, pin) mask##pin +#define GPIOx_BRR(mask, pin) PRE_GPIOx_BRR(mask, pin) +#define PRE_GPIOx_BRR(mask, pin) mask##pin +// Do not EDIT - END + +#define SWD_PORT GPIOA +#define SWD_PIN_MSK GPIO_IDR_ID13 + +#define CRC_LEN 4 + +#endif Index: ecs_cellMon/Bootloader/SES/output.txt =================================================================== --- ecs_cellMon/Bootloader/SES/output.txt (revision 3) +++ ecs_cellMon/Bootloader/SES/output.txt (revision 3) @@ -0,0 +1,37049 @@ + Programming of 8 bytes at address 0x08007490 performed ok. + Programming of 8 bytes at address 0x08007498 performed ok. + Programming of 8 bytes at address 0x080074A0 performed ok. + Programming of 8 bytes at address 0x080074A8 performed ok. + Programming of 8 bytes at address 0x080074B0 performed ok. + Programming of 8 bytes at address 0x080074B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080074F0 performed ok. + Programming of 8 bytes at address 0x080074F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08007500 performed ok. + Programming of 8 bytes at address 0x08007508 performed ok. + Programming of 8 bytes at address 0x08007510 performed ok. + Programming of 8 bytes at address 0x08007518 performed ok. + Programming of 8 bytes at address 0x08007520 performed ok. + Programming of 8 bytes at address 0x08007528 performed ok. + Programming of 8 bytes at address 0x08007530 performed ok. + Programming of 8 bytes at address 0x08007538 performed ok. + Programming of 8 bytes at address 0x08007540 performed ok. + Programming of 8 bytes at address 0x08007548 performed ok. + Programming of 8 bytes at address 0x08007550 performed ok. + Programming of 8 bytes at address 0x08007558 performed ok. + Programming of 8 bytes at address 0x08007560 performed ok. + Programming of 8 bytes at address 0x08007568 performed ok. + Programming of 8 bytes at address 0x08007570 performed ok. + Programming of 8 bytes at address 0x08007578 performed ok. + Programming of 8 bytes at address 0x08007580 performed ok. + Programming of 8 bytes at address 0x08007588 performed ok. + Programming of 8 bytes at address 0x08007590 performed ok. +k. + Programming of 8 bytes at address 0x080075A0 performed ok. + Programming of 8 bytes at address 0x080075A8 performed ok. + Programming of 8 bytes at address 0x080075B0 performed ok. + Programming of 8 bytes at address 0x080075B8 performed ok. + Programming of 8 bytes at address 0x080075C0 performed ok. + Programming of 8 bytes at address 0x080075C8 performed ok. + Programming of 8 bytes at address 0x080075D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08007600 performed ok. + Programming of 8 bytes at address 0x08007608 performed ok. + Programming of 8 bytes at address 0x08007610 performed ok. + Programming of 8 bytes at address 0x08007618 performed ok. + Programming of 8 bytes at address 0x08007620 performed ok. + Programming of 8 bytes at address 0x08007628 performed ok. + Programming of 8 bytes at address 0x08007630 performed ok. + Programming of 8 bytes at address 0x08007638 performed ok. + Programming of 8 bytes at address 0x08007640 performed ok. + Programming of 8 bytes at address 0x08007648 performed ok. + Programming of 8 bytes at address 0x08007650 performed ok. + Programming of 8 bytes at address 0x08007658 performed ok. + Programming of 8 bytes at address 0x08007660 performed ok. + Programming of 8 bytes at address 0x08007668 performed ok. + Programming of 8 bytes at address 0x08007670 performed ok. + Programming of 8 bytes at address 0x08007678 performed ok. + Programming of 8 bytes at address 0x08007680 performed ok. + Programming of 8 bytes at address 0x08007688 performed ok. + Programming of 8 bytes at address 0x08007690 performed ok. + Programming of 8 bytes at address 0x08007698 performed ok. +k. +k. + Programming of 8 bytes at address 0x080076B0 performed ok. + Programming of 8 bytes at address 0x080076B8 performed ok. + Programming of 8 bytes at address 0x080076C0 performed ok. + Programming of 8 bytes at address 0x080076C8 performed ok. + Programming of 8 bytes at address 0x080076D0 performed ok. + Programming of 8 bytes at address 0x080076D8 performed ok. + Programming of 8 bytes at address 0x080076E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08007700 performed ok. + Programming of 8 bytes at address 0x08007708 performed ok. + Programming of 8 bytes at address 0x08007710 performed ok. + Programming of 8 bytes at address 0x08007718 performed ok. + Programming of 8 bytes at address 0x08007720 performed ok. + Programming of 8 bytes at address 0x08007728 performed ok. + Programming of 8 bytes at address 0x08007730 performed ok. + Programming of 8 bytes at address 0x08007738 performed ok. + Programming of 8 bytes at address 0x08007740 performed ok. + Programming of 8 bytes at address 0x08007748 performed ok. + Programming of 8 bytes at address 0x08007750 performed ok. + Programming of 8 bytes at address 0x08007758 performed ok. + Programming of 8 bytes at address 0x08007760 performed ok. + Programming of 8 bytes at address 0x08007768 performed ok. + Programming of 8 bytes at address 0x08007770 performed ok. + Programming of 8 bytes at address 0x08007778 performed ok. + Programming of 8 bytes at address 0x08007780 performed ok. + Programming of 8 bytes at address 0x08007788 performed ok. + Programming of 8 bytes at address 0x08007790 performed ok. +k. + Programming of 8 bytes at address 0x080077A0 performed ok. + Programming of 8 bytes at address 0x080077A8 performed ok. + Programming of 8 bytes at address 0x080077B0 performed ok. + Programming of 8 bytes at address 0x080077B8 performed ok. + Programming of 8 bytes at address 0x080077C0 performed ok. + Programming of 8 bytes at address 0x080077C8 performed ok. + Programming of 8 bytes at address 0x080077D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08007800 performed ok. + Programming of 8 bytes at address 0x08007808 performed ok. + Programming of 8 bytes at address 0x08007810 performed ok. + Programming of 8 bytes at address 0x08007818 performed ok. + Programming of 8 bytes at address 0x08007820 performed ok. + Programming of 8 bytes at address 0x08007828 performed ok. + Programming of 8 bytes at address 0x08007830 performed ok. + Programming of 8 bytes at address 0x08007838 performed ok. + Programming of 8 bytes at address 0x08007840 performed ok. + Programming of 8 bytes at address 0x08007848 performed ok. + Programming of 8 bytes at address 0x08007850 performed ok. + Programming of 8 bytes at address 0x08007858 performed ok. + Programming of 8 bytes at address 0x08007860 performed ok. + Programming of 8 bytes at address 0x08007868 performed ok. + Programming of 8 bytes at address 0x08007870 performed ok. + Programming of 8 bytes at address 0x08007878 performed ok. + Programming of 8 bytes at address 0x08007880 performed ok. + Programming of 8 bytes at address 0x08007888 performed ok. + Programming of 8 bytes at address 0x08007890 performed ok. +k. + Programming of 8 bytes at address 0x080078A0 performed ok. + Programming of 8 bytes at address 0x080078A8 performed ok. + Programming of 8 bytes at address 0x080078B0 performed ok. + Programming of 8 bytes at address 0x080078B8 performed ok. + Programming of 8 bytes at address 0x080078C0 performed ok. + Programming of 8 bytes at address 0x080078C8 performed ok. + Programming of 8 bytes at address 0x080078D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08007900 performed ok. + Programming of 8 bytes at address 0x08007908 performed ok. + Programming of 8 bytes at address 0x08007910 performed ok. + Programming of 8 bytes at address 0x08007918 performed ok. + Programming of 8 bytes at address 0x08007920 performed ok. + Programming of 8 bytes at address 0x08007928 performed ok. + Programming of 8 bytes at address 0x08007930 performed ok. + Programming of 8 bytes at address 0x08007938 performed ok. + Programming of 8 bytes at address 0x08007940 performed ok. + Programming of 8 bytes at address 0x08007948 performed ok. + Programming of 8 bytes at address 0x08007950 performed ok. + Programming of 8 bytes at address 0x08007958 performed ok. + Programming of 8 bytes at address 0x08007960 performed ok. + Programming of 8 bytes at address 0x08007968 performed ok. + Programming of 8 bytes at address 0x08007970 performed ok. + Programming of 8 bytes at address 0x08007978 performed ok. + Programming of 8 bytes at address 0x08007980 performed ok. + Programming of 8 bytes at address 0x08007988 performed ok. + Programming of 8 bytes at address 0x08007990 performed ok. + Programming of 8 bytes at address 0x08007998 performed ok. + Programming of 8 bytes at address 0x080079A0 performed ok. +k. +k. + Programming of 8 bytes at address 0x080079B8 performed ok. + Programming of 8 bytes at address 0x080079C0 performed ok. + Programming of 8 bytes at address 0x080079C8 performed ok. + Programming of 8 bytes at address 0x080079D0 performed ok. + Programming of 8 bytes at address 0x080079D8 performed ok. + Programming of 8 bytes at address 0x080079E0 performed ok. + Programming of 8 bytes at address 0x080079E8 performed ok. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08007A00 performed ok. + Programming of 8 bytes at address 0x08007A08 performed ok. + Programming of 8 bytes at address 0x08007A10 performed ok. + Programming of 8 bytes at address 0x08007A18 performed ok. + Programming of 8 bytes at address 0x08007A20 performed ok. + Programming of 8 bytes at address 0x08007A28 performed ok. + Programming of 8 bytes at address 0x08007A30 performed ok. + Programming of 8 bytes at address 0x08007A38 performed ok. + Programming of 8 bytes at address 0x08007A40 performed ok. + Programming of 8 bytes at address 0x08007A48 performed ok. + Programming of 8 bytes at address 0x08007A50 performed ok. + Programming of 8 bytes at address 0x08007A58 performed ok. + Programming of 8 bytes at address 0x08007A60 performed ok. + Programming of 8 bytes at address 0x08007A68 performed ok. + Programming of 8 bytes at address 0x08007A70 performed ok. + Programming of 8 bytes at address 0x08007A78 performed ok. + Programming of 8 bytes at address 0x08007A80 performed ok. + Programming of 8 bytes at address 0x08007A88 performed ok. + Programming of 8 bytes at address 0x08007A90 performed ok. + Programming of 8 bytes at address 0x08007A98 performed ok. + Programming of 8 bytes at address 0x08007AA0 performed ok. + Programming of 8 bytes at address 0x08007AA8 performed ok. + Programming of 8 bytes at address 0x08007AB0 performed ok. + Programming of 8 bytes at address 0x08007AB8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08007B00 performed ok. + Programming of 8 bytes at address 0x08007B08 performed ok. + Programming of 8 bytes at address 0x08007B10 performed ok. + Programming of 8 bytes at address 0x08007B18 performed ok. + Programming of 8 bytes at address 0x08007B20 performed ok. + Programming of 8 bytes at address 0x08007B28 performed ok. + Programming of 8 bytes at address 0x08007B30 performed ok. + Programming of 8 bytes at address 0x08007B38 performed ok. + Programming of 8 bytes at address 0x08007B40 performed ok. + Programming of 8 bytes at address 0x08007B48 performed ok. + Programming of 8 bytes at address 0x08007B50 performed ok. + Programming of 8 bytes at address 0x08007B58 performed ok. + Programming of 8 bytes at address 0x08007B60 performed ok. + Programming of 8 bytes at address 0x08007B68 performed ok. + Programming of 8 bytes at address 0x08007B70 performed ok. + Programming of 8 bytes at address 0x08007B78 performed ok. + Programming of 8 bytes at address 0x08007B80 performed ok. + Programming of 8 bytes at address 0x08007B88 performed ok. + Programming of 8 bytes at address 0x08007B90 performed ok. + Programming of 8 bytes at address 0x08007B98 performed ok. + Programming of 8 bytes at address 0x08007BA0 performed ok. + Programming of 8 bytes at address 0x08007BA8 performed ok. + Programming of 8 bytes at address 0x08007BB0 performed ok. + Programming of 8 bytes at address 0x08007BB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08007BF0 performed ok. + Programming of 8 bytes at address 0x08007BF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08007C00 performed ok. + Programming of 8 bytes at address 0x08007C08 performed ok. + Programming of 8 bytes at address 0x08007C10 performed ok. + Programming of 8 bytes at address 0x08007C18 performed ok. + Programming of 8 bytes at address 0x08007C20 performed ok. + Programming of 8 bytes at address 0x08007C28 performed ok. + Programming of 8 bytes at address 0x08007C30 performed ok. + Programming of 8 bytes at address 0x08007C38 performed ok. + Programming of 8 bytes at address 0x08007C40 performed ok. + Programming of 8 bytes at address 0x08007C48 performed ok. + Programming of 8 bytes at address 0x08007C50 performed ok. + Programming of 8 bytes at address 0x08007C58 performed ok. + Programming of 8 bytes at address 0x08007C60 performed ok. + Programming of 8 bytes at address 0x08007C68 performed ok. + Programming of 8 bytes at address 0x08007C70 performed ok. + Programming of 8 bytes at address 0x08007C78 performed ok. + Programming of 8 bytes at address 0x08007C80 performed ok. + Programming of 8 bytes at address 0x08007C88 performed ok. + Programming of 8 bytes at address 0x08007C90 performed ok. + Programming of 8 bytes at address 0x08007C98 performed ok. +k. + Programming of 8 bytes at address 0x08007CA8 performed ok. + Programming of 8 bytes at address 0x08007CB0 performed ok. + Programming of 8 bytes at address 0x08007CB8 performed ok. + Programming of 8 bytes at address 0x08007CC0 performed ok. + Programming of 8 bytes at address 0x08007CC8 performed ok. + Programming of 8 bytes at address 0x08007CD0 performed ok. + Programming of 8 bytes at address 0x08007CD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08007D00 performed ok. + Programming of 8 bytes at address 0x08007D08 performed ok. + Programming of 8 bytes at address 0x08007D10 performed ok. + Programming of 8 bytes at address 0x08007D18 performed ok. + Programming of 8 bytes at address 0x08007D20 performed ok. + Programming of 8 bytes at address 0x08007D28 performed ok. + Programming of 8 bytes at address 0x08007D30 performed ok. + Programming of 8 bytes at address 0x08007D38 performed ok. + Programming of 8 bytes at address 0x08007D40 performed ok. + Programming of 8 bytes at address 0x08007D48 performed ok. + Programming of 8 bytes at address 0x08007D50 performed ok. + Programming of 8 bytes at address 0x08007D58 performed ok. + Programming of 8 bytes at address 0x08007D60 performed ok. + Programming of 8 bytes at address 0x08007D68 performed ok. + Programming of 8 bytes at address 0x08007D70 performed ok. + Programming of 8 bytes at address 0x08007D78 performed ok. + Programming of 8 bytes at address 0x08007D80 performed ok. + Programming of 8 bytes at address 0x08007D88 performed ok. + Programming of 8 bytes at address 0x08007D90 performed ok. + Programming of 8 bytes at address 0x08007D98 performed ok. + Programming of 8 bytes at address 0x08007DA0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08007DC8 performed ok. + Programming of 8 bytes at address 0x08007DD0 performed ok. + Programming of 8 bytes at address 0x08007DD8 performed ok. + Programming of 8 bytes at address 0x08007DE0 performed ok. + Programming of 8 bytes at address 0x08007DE8 performed ok. + Programming of 8 bytes at address 0x08007DF0 performed ok. + Programming of 8 bytes at address 0x08007DF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08007E00 performed ok. + Programming of 8 bytes at address 0x08007E08 performed ok. + Programming of 8 bytes at address 0x08007E10 performed ok. + Programming of 8 bytes at address 0x08007E18 performed ok. + Programming of 8 bytes at address 0x08007E20 performed ok. + Programming of 8 bytes at address 0x08007E28 performed ok. + Programming of 8 bytes at address 0x08007E30 performed ok. + Programming of 8 bytes at address 0x08007E38 performed ok. + Programming of 8 bytes at address 0x08007E40 performed ok. + Programming of 8 bytes at address 0x08007E48 performed ok. + Programming of 8 bytes at address 0x08007E50 performed ok. + Programming of 8 bytes at address 0x08007E58 performed ok. + Programming of 8 bytes at address 0x08007E60 performed ok. + Programming of 8 bytes at address 0x08007E68 performed ok. + Programming of 8 bytes at address 0x08007E70 performed ok. + Programming of 8 bytes at address 0x08007E78 performed ok. + Programming of 8 bytes at address 0x08007E80 performed ok. + Programming of 8 bytes at address 0x08007E88 performed ok. + Programming of 8 bytes at address 0x08007E90 performed ok. + Programming of 8 bytes at address 0x08007E98 performed ok. + Programming of 8 bytes at address 0x08007EA0 performed ok. + Programming of 8 bytes at address 0x08007EA8 performed ok. + Programming of 8 bytes at address 0x08007EB0 performed ok. + Programming of 8 bytes at address 0x08007EB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08007EF0 performed ok. + Programming of 8 bytes at address 0x08007EF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08007F00 performed ok. + Programming of 8 bytes at address 0x08007F08 performed ok. + Programming of 8 bytes at address 0x08007F10 performed ok. + Programming of 8 bytes at address 0x08007F18 performed ok. + Programming of 8 bytes at address 0x08007F20 performed ok. + Programming of 8 bytes at address 0x08007F28 performed ok. + Programming of 8 bytes at address 0x08007F30 performed ok. + Programming of 8 bytes at address 0x08007F38 performed ok. + Programming of 8 bytes at address 0x08007F40 performed ok. + Programming of 8 bytes at address 0x08007F48 performed ok. + Programming of 8 bytes at address 0x08007F50 performed ok. + Programming of 8 bytes at address 0x08007F58 performed ok. + Programming of 8 bytes at address 0x08007F60 performed ok. + Programming of 8 bytes at address 0x08007F68 performed ok. + Programming of 8 bytes at address 0x08007F70 performed ok. + Programming of 8 bytes at address 0x08007F78 performed ok. + Programming of 8 bytes at address 0x08007F80 performed ok. + Programming of 8 bytes at address 0x08007F88 performed ok. + Programming of 8 bytes at address 0x08007F90 performed ok. +k. + Programming of 8 bytes at address 0x08007FA0 performed ok. + Programming of 8 bytes at address 0x08007FA8 performed ok. + Programming of 8 bytes at address 0x08007FB0 performed ok. + Programming of 8 bytes at address 0x08007FB8 performed ok. + Programming of 8 bytes at address 0x08007FC0 performed ok. + Programming of 8 bytes at address 0x08007FC8 performed ok. + Programming of 8 bytes at address 0x08007FD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008000 performed ok. + Programming of 8 bytes at address 0x08008008 performed ok. + Programming of 8 bytes at address 0x08008010 performed ok. + Programming of 8 bytes at address 0x08008018 performed ok. + Programming of 8 bytes at address 0x08008020 performed ok. + Programming of 8 bytes at address 0x08008028 performed ok. + Programming of 8 bytes at address 0x08008030 performed ok. + Programming of 8 bytes at address 0x08008038 performed ok. + Programming of 8 bytes at address 0x08008040 performed ok. + Programming of 8 bytes at address 0x08008048 performed ok. + Programming of 8 bytes at address 0x08008050 performed ok. + Programming of 8 bytes at address 0x08008058 performed ok. + Programming of 8 bytes at address 0x08008060 performed ok. + Programming of 8 bytes at address 0x08008068 performed ok. + Programming of 8 bytes at address 0x08008070 performed ok. + Programming of 8 bytes at address 0x08008078 performed ok. + Programming of 8 bytes at address 0x08008080 performed ok. + Programming of 8 bytes at address 0x08008088 performed ok. + Programming of 8 bytes at address 0x08008090 performed ok. + Programming of 8 bytes at address 0x08008098 performed ok. + Programming of 8 bytes at address 0x080080A0 performed ok. + Programming of 8 bytes at address 0x080080A8 performed ok. + Programming of 8 bytes at address 0x080080B0 performed ok. + Programming of 8 bytes at address 0x080080B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080080F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008100 performed ok. + Programming of 8 bytes at address 0x08008108 performed ok. + Programming of 8 bytes at address 0x08008110 performed ok. + Programming of 8 bytes at address 0x08008118 performed ok. + Programming of 8 bytes at address 0x08008120 performed ok. + Programming of 8 bytes at address 0x08008128 performed ok. + Programming of 8 bytes at address 0x08008130 performed ok. + Programming of 8 bytes at address 0x08008138 performed ok. + Programming of 8 bytes at address 0x08008140 performed ok. + Programming of 8 bytes at address 0x08008148 performed ok. + Programming of 8 bytes at address 0x08008150 performed ok. + Programming of 8 bytes at address 0x08008158 performed ok. + Programming of 8 bytes at address 0x08008160 performed ok. + Programming of 8 bytes at address 0x08008168 performed ok. + Programming of 8 bytes at address 0x08008170 performed ok. + Programming of 8 bytes at address 0x08008178 performed ok. + Programming of 8 bytes at address 0x08008180 performed ok. + Programming of 8 bytes at address 0x08008188 performed ok. + Programming of 8 bytes at address 0x08008190 performed ok. +k. + Programming of 8 bytes at address 0x080081A0 performed ok. + Programming of 8 bytes at address 0x080081A8 performed ok. + Programming of 8 bytes at address 0x080081B0 performed ok. + Programming of 8 bytes at address 0x080081B8 performed ok. + Programming of 8 bytes at address 0x080081C0 performed ok. + Programming of 8 bytes at address 0x080081C8 performed ok. + Programming of 8 bytes at address 0x080081D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008200 performed ok. + Programming of 8 bytes at address 0x08008208 performed ok. + Programming of 8 bytes at address 0x08008210 performed ok. + Programming of 8 bytes at address 0x08008218 performed ok. + Programming of 8 bytes at address 0x08008220 performed ok. + Programming of 8 bytes at address 0x08008228 performed ok. + Programming of 8 bytes at address 0x08008230 performed ok. + Programming of 8 bytes at address 0x08008238 performed ok. + Programming of 8 bytes at address 0x08008240 performed ok. + Programming of 8 bytes at address 0x08008248 performed ok. + Programming of 8 bytes at address 0x08008250 performed ok. + Programming of 8 bytes at address 0x08008258 performed ok. + Programming of 8 bytes at address 0x08008260 performed ok. + Programming of 8 bytes at address 0x08008268 performed ok. + Programming of 8 bytes at address 0x08008270 performed ok. + Programming of 8 bytes at address 0x08008278 performed ok. + Programming of 8 bytes at address 0x08008280 performed ok. + Programming of 8 bytes at address 0x08008288 performed ok. + Programming of 8 bytes at address 0x08008290 performed ok. + Programming of 8 bytes at address 0x08008298 performed ok. +k. + Programming of 8 bytes at address 0x080082A8 performed ok. + Programming of 8 bytes at address 0x080082B0 performed ok. + Programming of 8 bytes at address 0x080082B8 performed ok. + Programming of 8 bytes at address 0x080082C0 performed ok. + Programming of 8 bytes at address 0x080082C8 performed ok. + Programming of 8 bytes at address 0x080082D0 performed ok. + Programming of 8 bytes at address 0x080082D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008300 performed ok. + Programming of 8 bytes at address 0x08008308 performed ok. + Programming of 8 bytes at address 0x08008310 performed ok. + Programming of 8 bytes at address 0x08008318 performed ok. + Programming of 8 bytes at address 0x08008320 performed ok. + Programming of 8 bytes at address 0x08008328 performed ok. + Programming of 8 bytes at address 0x08008330 performed ok. + Programming of 8 bytes at address 0x08008338 performed ok. + Programming of 8 bytes at address 0x08008340 performed ok. + Programming of 8 bytes at address 0x08008348 performed ok. + Programming of 8 bytes at address 0x08008350 performed ok. + Programming of 8 bytes at address 0x08008358 performed ok. + Programming of 8 bytes at address 0x08008360 performed ok. + Programming of 8 bytes at address 0x08008368 performed ok. + Programming of 8 bytes at address 0x08008370 performed ok. + Programming of 8 bytes at address 0x08008378 performed ok. + Programming of 8 bytes at address 0x08008380 performed ok. + Programming of 8 bytes at address 0x08008388 performed ok. + Programming of 8 bytes at address 0x08008390 performed ok. +k. + Programming of 8 bytes at address 0x080083A0 performed ok. + Programming of 8 bytes at address 0x080083A8 performed ok. + Programming of 8 bytes at address 0x080083B0 performed ok. + Programming of 8 bytes at address 0x080083B8 performed ok. + Programming of 8 bytes at address 0x080083C0 performed ok. + Programming of 8 bytes at address 0x080083C8 performed ok. + Programming of 8 bytes at address 0x080083D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008400 performed ok. + Programming of 8 bytes at address 0x08008408 performed ok. + Programming of 8 bytes at address 0x08008410 performed ok. + Programming of 8 bytes at address 0x08008418 performed ok. + Programming of 8 bytes at address 0x08008420 performed ok. + Programming of 8 bytes at address 0x08008428 performed ok. + Programming of 8 bytes at address 0x08008430 performed ok. + Programming of 8 bytes at address 0x08008438 performed ok. + Programming of 8 bytes at address 0x08008440 performed ok. + Programming of 8 bytes at address 0x08008448 performed ok. + Programming of 8 bytes at address 0x08008450 performed ok. + Programming of 8 bytes at address 0x08008458 performed ok. + Programming of 8 bytes at address 0x08008460 performed ok. + Programming of 8 bytes at address 0x08008468 performed ok. + Programming of 8 bytes at address 0x08008470 performed ok. + Programming of 8 bytes at address 0x08008478 performed ok. + Programming of 8 bytes at address 0x08008480 performed ok. + Programming of 8 bytes at address 0x08008488 performed ok. + Programming of 8 bytes at address 0x08008490 performed ok. +k. +k. + Programming of 8 bytes at address 0x080084A8 performed ok. + Programming of 8 bytes at address 0x080084B0 performed ok. + Programming of 8 bytes at address 0x080084B8 performed ok. + Programming of 8 bytes at address 0x080084C0 performed ok. + Programming of 8 bytes at address 0x080084C8 performed ok. + Programming of 8 bytes at address 0x080084D0 performed ok. + Programming of 8 bytes at address 0x080084D8 performed ok. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008500 performed ok. + Programming of 8 bytes at address 0x08008508 performed ok. + Programming of 8 bytes at address 0x08008510 performed ok. + Programming of 8 bytes at address 0x08008518 performed ok. + Programming of 8 bytes at address 0x08008520 performed ok. + Programming of 8 bytes at address 0x08008528 performed ok. + Programming of 8 bytes at address 0x08008530 performed ok. + Programming of 8 bytes at address 0x08008538 performed ok. + Programming of 8 bytes at address 0x08008540 performed ok. + Programming of 8 bytes at address 0x08008548 performed ok. + Programming of 8 bytes at address 0x08008550 performed ok. + Programming of 8 bytes at address 0x08008558 performed ok. + Programming of 8 bytes at address 0x08008560 performed ok. + Programming of 8 bytes at address 0x08008568 performed ok. + Programming of 8 bytes at address 0x08008570 performed ok. + Programming of 8 bytes at address 0x08008578 performed ok. + Programming of 8 bytes at address 0x08008580 performed ok. + Programming of 8 bytes at address 0x08008588 performed ok. + Programming of 8 bytes at address 0x08008590 performed ok. + Programming of 8 bytes at address 0x08008598 performed ok. + Programming of 8 bytes at address 0x080085A0 performed ok. + Programming of 8 bytes at address 0x080085A8 performed ok. + Programming of 8 bytes at address 0x080085B0 performed ok. + Programming of 8 bytes at address 0x080085B8 performed ok. + Programming of 8 bytes at address 0x080085C0 performed ok. + Programming of 8 bytes at address 0x080085C8 performed ok. +k. +k. +k. +k. +k. +k. + +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008600 performed ok. + Programming of 8 bytes at address 0x08008608 performed ok. + Programming of 8 bytes at address 0x08008610 performed ok. + Programming of 8 bytes at address 0x08008618 performed ok. + Programming of 8 bytes at address 0x08008620 performed ok. + Programming of 8 bytes at address 0x08008628 performed ok. + Programming of 8 bytes at address 0x08008630 performed ok. + Programming of 8 bytes at address 0x08008638 performed ok. + Programming of 8 bytes at address 0x08008640 performed ok. + Programming of 8 bytes at address 0x08008648 performed ok. + Programming of 8 bytes at address 0x08008650 performed ok. + Programming of 8 bytes at address 0x08008658 performed ok. + Programming of 8 bytes at address 0x08008660 performed ok. + Programming of 8 bytes at address 0x08008668 performed ok. + Programming of 8 bytes at address 0x08008670 performed ok. + Programming of 8 bytes at address 0x08008678 performed ok. + Programming of 8 bytes at address 0x08008680 performed ok. + Programming of 8 bytes at address 0x08008688 performed ok. + Programming of 8 bytes at address 0x08008690 performed ok. + Programming of 8 bytes at address 0x08008698 performed ok. + Programming of 8 bytes at address 0x080086A0 performed ok. + Programming of 8 bytes at address 0x080086A8 performed ok. + Programming of 8 bytes at address 0x080086B0 performed ok. + Programming of 8 bytes at address 0x080086B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080086F0 performed ok. + Programming of 8 bytes at address 0x080086F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008700 performed ok. + Programming of 8 bytes at address 0x08008708 performed ok. + Programming of 8 bytes at address 0x08008710 performed ok. + Programming of 8 bytes at address 0x08008718 performed ok. + Programming of 8 bytes at address 0x08008720 performed ok. + Programming of 8 bytes at address 0x08008728 performed ok. + Programming of 8 bytes at address 0x08008730 performed ok. + Programming of 8 bytes at address 0x08008738 performed ok. + Programming of 8 bytes at address 0x08008740 performed ok. + Programming of 8 bytes at address 0x08008748 performed ok. + Programming of 8 bytes at address 0x08008750 performed ok. + Programming of 8 bytes at address 0x08008758 performed ok. + Programming of 8 bytes at address 0x08008760 performed ok. + Programming of 8 bytes at address 0x08008768 performed ok. + Programming of 8 bytes at address 0x08008770 performed ok. + Programming of 8 bytes at address 0x08008778 performed ok. + Programming of 8 bytes at address 0x08008780 performed ok. + Programming of 8 bytes at address 0x08008788 performed ok. + Programming of 8 bytes at address 0x08008790 performed ok. +k. + Programming of 8 bytes at address 0x080087A0 performed ok. + Programming of 8 bytes at address 0x080087A8 performed ok. + Programming of 8 bytes at address 0x080087B0 performed ok. + Programming of 8 bytes at address 0x080087B8 performed ok. + Programming of 8 bytes at address 0x080087C0 performed ok. + Programming of 8 bytes at address 0x080087C8 performed ok. + Programming of 8 bytes at address 0x080087D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008800 performed ok. + Programming of 8 bytes at address 0x08008808 performed ok. + Programming of 8 bytes at address 0x08008810 performed ok. + Programming of 8 bytes at address 0x08008818 performed ok. + Programming of 8 bytes at address 0x08008820 performed ok. + Programming of 8 bytes at address 0x08008828 performed ok. + Programming of 8 bytes at address 0x08008830 performed ok. + Programming of 8 bytes at address 0x08008838 performed ok. + Programming of 8 bytes at address 0x08008840 performed ok. + Programming of 8 bytes at address 0x08008848 performed ok. + Programming of 8 bytes at address 0x08008850 performed ok. + Programming of 8 bytes at address 0x08008858 performed ok. + Programming of 8 bytes at address 0x08008860 performed ok. + Programming of 8 bytes at address 0x08008868 performed ok. + Programming of 8 bytes at address 0x08008870 performed ok. + Programming of 8 bytes at address 0x08008878 performed ok. + Programming of 8 bytes at address 0x08008880 performed ok. + Programming of 8 bytes at address 0x08008888 performed ok. + Programming of 8 bytes at address 0x08008890 performed ok. +k. + Programming of 8 bytes at address 0x080088A0 performed ok. + Programming of 8 bytes at address 0x080088A8 performed ok. + Programming of 8 bytes at address 0x080088B0 performed ok. + Programming of 8 bytes at address 0x080088B8 performed ok. + Programming of 8 bytes at address 0x080088C0 performed ok. + Programming of 8 bytes at address 0x080088C8 performed ok. + Programming of 8 bytes at address 0x080088D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008900 performed ok. + Programming of 8 bytes at address 0x08008908 performed ok. + Programming of 8 bytes at address 0x08008910 performed ok. + Programming of 8 bytes at address 0x08008918 performed ok. + Programming of 8 bytes at address 0x08008920 performed ok. + Programming of 8 bytes at address 0x08008928 performed ok. + Programming of 8 bytes at address 0x08008930 performed ok. + Programming of 8 bytes at address 0x08008938 performed ok. + Programming of 8 bytes at address 0x08008940 performed ok. + Programming of 8 bytes at address 0x08008948 performed ok. + Programming of 8 bytes at address 0x08008950 performed ok. + Programming of 8 bytes at address 0x08008958 performed ok. + Programming of 8 bytes at address 0x08008960 performed ok. + Programming of 8 bytes at address 0x08008968 performed ok. + Programming of 8 bytes at address 0x08008970 performed ok. + Programming of 8 bytes at address 0x08008978 performed ok. + Programming of 8 bytes at address 0x08008980 performed ok. + Programming of 8 bytes at address 0x08008988 performed ok. + Programming of 8 bytes at address 0x08008990 performed ok. + Programming of 8 bytes at address 0x08008998 performed ok. +k. + Programming of 8 bytes at address 0x080089A8 performed ok. + Programming of 8 bytes at address 0x080089B0 performed ok. + Programming of 8 bytes at address 0x080089B8 performed ok. + Programming of 8 bytes at address 0x080089C0 performed ok. + Programming of 8 bytes at address 0x080089C8 performed ok. + Programming of 8 bytes at address 0x080089D0 performed ok. + Programming of 8 bytes at address 0x080089D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008A00 performed ok. + Programming of 8 bytes at address 0x08008A08 performed ok. + Programming of 8 bytes at address 0x08008A10 performed ok. + Programming of 8 bytes at address 0x08008A18 performed ok. + Programming of 8 bytes at address 0x08008A20 performed ok. + Programming of 8 bytes at address 0x08008A28 performed ok. + Programming of 8 bytes at address 0x08008A30 performed ok. + Programming of 8 bytes at address 0x08008A38 performed ok. + Programming of 8 bytes at address 0x08008A40 performed ok. + Programming of 8 bytes at address 0x08008A48 performed ok. + Programming of 8 bytes at address 0x08008A50 performed ok. + Programming of 8 bytes at address 0x08008A58 performed ok. + Programming of 8 bytes at address 0x08008A60 performed ok. + Programming of 8 bytes at address 0x08008A68 performed ok. + Programming of 8 bytes at address 0x08008A70 performed ok. + Programming of 8 bytes at address 0x08008A78 performed ok. + Programming of 8 bytes at address 0x08008A80 performed ok. + Programming of 8 bytes at address 0x08008A88 performed ok. + Programming of 8 bytes at address 0x08008A90 performed ok. + Programming of 8 bytes at address 0x08008A98 performed ok. + Programming of 8 bytes at address 0x08008AA0 performed ok. + Programming of 8 bytes at address 0x08008AA8 performed ok. + Programming of 8 bytes at address 0x08008AB0 performed ok. + Programming of 8 bytes at address 0x08008AB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08008AF0 performed ok. + Programming of 8 bytes at address 0x08008AF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008B00 performed ok. + Programming of 8 bytes at address 0x08008B08 performed ok. + Programming of 8 bytes at address 0x08008B10 performed ok. + Programming of 8 bytes at address 0x08008B18 performed ok. + Programming of 8 bytes at address 0x08008B20 performed ok. + Programming of 8 bytes at address 0x08008B28 performed ok. + Programming of 8 bytes at address 0x08008B30 performed ok. + Programming of 8 bytes at address 0x08008B38 performed ok. + Programming of 8 bytes at address 0x08008B40 performed ok. + Programming of 8 bytes at address 0x08008B48 performed ok. + Programming of 8 bytes at address 0x08008B50 performed ok. + Programming of 8 bytes at address 0x08008B58 performed ok. + Programming of 8 bytes at address 0x08008B60 performed ok. + Programming of 8 bytes at address 0x08008B68 performed ok. + Programming of 8 bytes at address 0x08008B70 performed ok. + Programming of 8 bytes at address 0x08008B78 performed ok. + Programming of 8 bytes at address 0x08008B80 performed ok. + Programming of 8 bytes at address 0x08008B88 performed ok. + Programming of 8 bytes at address 0x08008B90 performed ok. + Programming of 8 bytes at address 0x08008B98 performed ok. + Programming of 8 bytes at address 0x08008BA0 performed ok. + Programming of 8 bytes at address 0x08008BA8 performed ok. + Programming of 8 bytes at address 0x08008BB0 performed ok. + Programming of 8 bytes at address 0x08008BB8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008C00 performed ok. + Programming of 8 bytes at address 0x08008C08 performed ok. + Programming of 8 bytes at address 0x08008C10 performed ok. + Programming of 8 bytes at address 0x08008C18 performed ok. + Programming of 8 bytes at address 0x08008C20 performed ok. + Programming of 8 bytes at address 0x08008C28 performed ok. + Programming of 8 bytes at address 0x08008C30 performed ok. + Programming of 8 bytes at address 0x08008C38 performed ok. + Programming of 8 bytes at address 0x08008C40 performed ok. + Programming of 8 bytes at address 0x08008C48 performed ok. + Programming of 8 bytes at address 0x08008C50 performed ok. + Programming of 8 bytes at address 0x08008C58 performed ok. + Programming of 8 bytes at address 0x08008C60 performed ok. + Programming of 8 bytes at address 0x08008C68 performed ok. + Programming of 8 bytes at address 0x08008C70 performed ok. + Programming of 8 bytes at address 0x08008C78 performed ok. + Programming of 8 bytes at address 0x08008C80 performed ok. + Programming of 8 bytes at address 0x08008C88 performed ok. + Programming of 8 bytes at address 0x08008C90 performed ok. + Programming of 8 bytes at address 0x08008C98 performed ok. + Programming of 8 bytes at address 0x08008CA0 performed ok. + Programming of 8 bytes at address 0x08008CA8 performed ok. + Programming of 8 bytes at address 0x08008CB0 performed ok. + Programming of 8 bytes at address 0x08008CB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08008CF0 performed ok. + Programming of 8 bytes at address 0x08008CF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008D00 performed ok. + Programming of 8 bytes at address 0x08008D08 performed ok. + Programming of 8 bytes at address 0x08008D10 performed ok. + Programming of 8 bytes at address 0x08008D18 performed ok. + Programming of 8 bytes at address 0x08008D20 performed ok. + Programming of 8 bytes at address 0x08008D28 performed ok. + Programming of 8 bytes at address 0x08008D30 performed ok. + Programming of 8 bytes at address 0x08008D38 performed ok. + Programming of 8 bytes at address 0x08008D40 performed ok. + Programming of 8 bytes at address 0x08008D48 performed ok. + Programming of 8 bytes at address 0x08008D50 performed ok. + Programming of 8 bytes at address 0x08008D58 performed ok. + Programming of 8 bytes at address 0x08008D60 performed ok. + Programming of 8 bytes at address 0x08008D68 performed ok. + Programming of 8 bytes at address 0x08008D70 performed ok. + Programming of 8 bytes at address 0x08008D78 performed ok. + Programming of 8 bytes at address 0x08008D80 performed ok. + Programming of 8 bytes at address 0x08008D88 performed ok. + Programming of 8 bytes at address 0x08008D90 performed ok. + Programming of 8 bytes at address 0x08008D98 performed ok. + Programming of 8 bytes at address 0x08008DA0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08008DC8 performed ok. + Programming of 8 bytes at address 0x08008DD0 performed ok. + Programming of 8 bytes at address 0x08008DD8 performed ok. + Programming of 8 bytes at address 0x08008DE0 performed ok. + Programming of 8 bytes at address 0x08008DE8 performed ok. + Programming of 8 bytes at address 0x08008DF0 performed ok. + Programming of 8 bytes at address 0x08008DF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008E00 performed ok. + Programming of 8 bytes at address 0x08008E08 performed ok. + Programming of 8 bytes at address 0x08008E10 performed ok. + Programming of 8 bytes at address 0x08008E18 performed ok. + Programming of 8 bytes at address 0x08008E20 performed ok. + Programming of 8 bytes at address 0x08008E28 performed ok. + Programming of 8 bytes at address 0x08008E30 performed ok. + Programming of 8 bytes at address 0x08008E38 performed ok. + Programming of 8 bytes at address 0x08008E40 performed ok. + Programming of 8 bytes at address 0x08008E48 performed ok. + Programming of 8 bytes at address 0x08008E50 performed ok. + Programming of 8 bytes at address 0x08008E58 performed ok. + Programming of 8 bytes at address 0x08008E60 performed ok. + Programming of 8 bytes at address 0x08008E68 performed ok. + Programming of 8 bytes at address 0x08008E70 performed ok. + Programming of 8 bytes at address 0x08008E78 performed ok. + Programming of 8 bytes at address 0x08008E80 performed ok. + Programming of 8 bytes at address 0x08008E88 performed ok. + Programming of 8 bytes at address 0x08008E90 performed ok. +k. + Programming of 8 bytes at address 0x08008EA0 performed ok. + Programming of 8 bytes at address 0x08008EA8 performed ok. + Programming of 8 bytes at address 0x08008EB0 performed ok. + Programming of 8 bytes at address 0x08008EB8 performed ok. + Programming of 8 bytes at address 0x08008EC0 performed ok. + Programming of 8 bytes at address 0x08008EC8 performed ok. + Programming of 8 bytes at address 0x08008ED0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08008F00 performed ok. + Programming of 8 bytes at address 0x08008F08 performed ok. + Programming of 8 bytes at address 0x08008F10 performed ok. + Programming of 8 bytes at address 0x08008F18 performed ok. + Programming of 8 bytes at address 0x08008F20 performed ok. + Programming of 8 bytes at address 0x08008F28 performed ok. + Programming of 8 bytes at address 0x08008F30 performed ok. + Programming of 8 bytes at address 0x08008F38 performed ok. + Programming of 8 bytes at address 0x08008F40 performed ok. + Programming of 8 bytes at address 0x08008F48 performed ok. + Programming of 8 bytes at address 0x08008F50 performed ok. + Programming of 8 bytes at address 0x08008F58 performed ok. + Programming of 8 bytes at address 0x08008F60 performed ok. + Programming of 8 bytes at address 0x08008F68 performed ok. + Programming of 8 bytes at address 0x08008F70 performed ok. + Programming of 8 bytes at address 0x08008F78 performed ok. + Programming of 8 bytes at address 0x08008F80 performed ok. + Programming of 8 bytes at address 0x08008F88 performed ok. + Programming of 8 bytes at address 0x08008F90 performed ok. + Programming of 8 bytes at address 0x08008F98 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08008FB8 performed ok. + Programming of 8 bytes at address 0x08008FC0 performed ok. + Programming of 8 bytes at address 0x08008FC8 performed ok. + Programming of 8 bytes at address 0x08008FD0 performed ok. + Programming of 8 bytes at address 0x08008FD8 performed ok. + Programming of 8 bytes at address 0x08008FE0 performed ok. + Programming of 8 bytes at address 0x08008FE8 performed ok. + Programming of 8 bytes at address 0x08008FF0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009000 performed ok. + Programming of 8 bytes at address 0x08009008 performed ok. + Programming of 8 bytes at address 0x08009010 performed ok. + Programming of 8 bytes at address 0x08009018 performed ok. + Programming of 8 bytes at address 0x08009020 performed ok. + Programming of 8 bytes at address 0x08009028 performed ok. + Programming of 8 bytes at address 0x08009030 performed ok. + Programming of 8 bytes at address 0x08009038 performed ok. + Programming of 8 bytes at address 0x08009040 performed ok. + Programming of 8 bytes at address 0x08009048 performed ok. + Programming of 8 bytes at address 0x08009050 performed ok. + Programming of 8 bytes at address 0x08009058 performed ok. + Programming of 8 bytes at address 0x08009060 performed ok. + Programming of 8 bytes at address 0x08009068 performed ok. + Programming of 8 bytes at address 0x08009070 performed ok. + Programming of 8 bytes at address 0x08009078 performed ok. + Programming of 8 bytes at address 0x08009080 performed ok. + Programming of 8 bytes at address 0x08009088 performed ok. +k. + Programming of 8 bytes at address 0x08009098 performed ok. + Programming of 8 bytes at address 0x080090A0 performed ok. + Programming of 8 bytes at address 0x080090A8 performed ok. + Programming of 8 bytes at address 0x080090B0 performed ok. + Programming of 8 bytes at address 0x080090B8 performed ok. + Programming of 8 bytes at address 0x080090C0 performed ok. + Programming of 8 bytes at address 0x080090C8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009100 performed ok. + Programming of 8 bytes at address 0x08009108 performed ok. + Programming of 8 bytes at address 0x08009110 performed ok. + Programming of 8 bytes at address 0x08009118 performed ok. + Programming of 8 bytes at address 0x08009120 performed ok. + Programming of 8 bytes at address 0x08009128 performed ok. + Programming of 8 bytes at address 0x08009130 performed ok. + Programming of 8 bytes at address 0x08009138 performed ok. + Programming of 8 bytes at address 0x08009140 performed ok. + Programming of 8 bytes at address 0x08009148 performed ok. + Programming of 8 bytes at address 0x08009150 performed ok. + Programming of 8 bytes at address 0x08009158 performed ok. + Programming of 8 bytes at address 0x08009160 performed ok. + Programming of 8 bytes at address 0x08009168 performed ok. + Programming of 8 bytes at address 0x08009170 performed ok. + Programming of 8 bytes at address 0x08009178 performed ok. + Programming of 8 bytes at address 0x08009180 performed ok. + Programming of 8 bytes at address 0x08009188 performed ok. + Programming of 8 bytes at address 0x08009190 performed ok. + Programming of 8 bytes at address 0x08009198 performed ok. + Programming of 8 bytes at address 0x080091A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080091C0 performed ok. + Programming of 8 bytes at address 0x080091C8 performed ok. + Programming of 8 bytes at address 0x080091D0 performed ok. + Programming of 8 bytes at address 0x080091D8 performed ok. + Programming of 8 bytes at address 0x080091E0 performed ok. + Programming of 8 bytes at address 0x080091E8 performed ok. + Programming of 8 bytes at address 0x080091F0 performed ok. + Programming of 8 bytes at address 0x080091F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009200 performed ok. + Programming of 8 bytes at address 0x08009208 performed ok. + Programming of 8 bytes at address 0x08009210 performed ok. + Programming of 8 bytes at address 0x08009218 performed ok. + Programming of 8 bytes at address 0x08009220 performed ok. + Programming of 8 bytes at address 0x08009228 performed ok. + Programming of 8 bytes at address 0x08009230 performed ok. + Programming of 8 bytes at address 0x08009238 performed ok. + Programming of 8 bytes at address 0x08009240 performed ok. + Programming of 8 bytes at address 0x08009248 performed ok. + Programming of 8 bytes at address 0x08009250 performed ok. + Programming of 8 bytes at address 0x08009258 performed ok. + Programming of 8 bytes at address 0x08009260 performed ok. + Programming of 8 bytes at address 0x08009268 performed ok. + Programming of 8 bytes at address 0x08009270 performed ok. + Programming of 8 bytes at address 0x08009278 performed ok. + Programming of 8 bytes at address 0x08009280 performed ok. + Programming of 8 bytes at address 0x08009288 performed ok. + Programming of 8 bytes at address 0x08009290 performed ok. + Programming of 8 bytes at address 0x08009298 performed ok. +k. + Programming of 8 bytes at address 0x080092A8 performed ok. + Programming of 8 bytes at address 0x080092B0 performed ok. + Programming of 8 bytes at address 0x080092B8 performed ok. + Programming of 8 bytes at address 0x080092C0 performed ok. + Programming of 8 bytes at address 0x080092C8 performed ok. + Programming of 8 bytes at address 0x080092D0 performed ok. + Programming of 8 bytes at address 0x080092D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009300 performed ok. + Programming of 8 bytes at address 0x08009308 performed ok. + Programming of 8 bytes at address 0x08009310 performed ok. + Programming of 8 bytes at address 0x08009318 performed ok. + Programming of 8 bytes at address 0x08009320 performed ok. + Programming of 8 bytes at address 0x08009328 performed ok. + Programming of 8 bytes at address 0x08009330 performed ok. + Programming of 8 bytes at address 0x08009338 performed ok. + Programming of 8 bytes at address 0x08009340 performed ok. + Programming of 8 bytes at address 0x08009348 performed ok. + Programming of 8 bytes at address 0x08009350 performed ok. + Programming of 8 bytes at address 0x08009358 performed ok. + Programming of 8 bytes at address 0x08009360 performed ok. + Programming of 8 bytes at address 0x08009368 performed ok. + Programming of 8 bytes at address 0x08009370 performed ok. + Programming of 8 bytes at address 0x08009378 performed ok. + Programming of 8 bytes at address 0x08009380 performed ok. + Programming of 8 bytes at address 0x08009388 performed ok. + Programming of 8 bytes at address 0x08009390 performed ok. + Programming of 8 bytes at address 0x08009398 performed ok. + Programming of 8 bytes at address 0x080093A0 performed ok. + Programming of 8 bytes at address 0x080093A8 performed ok. + Programming of 8 bytes at address 0x080093B0 performed ok. + Programming of 8 bytes at address 0x080093B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009400 performed ok. + Programming of 8 bytes at address 0x08009408 performed ok. + Programming of 8 bytes at address 0x08009410 performed ok. + Programming of 8 bytes at address 0x08009418 performed ok. + Programming of 8 bytes at address 0x08009420 performed ok. + Programming of 8 bytes at address 0x08009428 performed ok. + Programming of 8 bytes at address 0x08009430 performed ok. + Programming of 8 bytes at address 0x08009438 performed ok. + Programming of 8 bytes at address 0x08009440 performed ok. + Programming of 8 bytes at address 0x08009448 performed ok. + Programming of 8 bytes at address 0x08009450 performed ok. + Programming of 8 bytes at address 0x08009458 performed ok. + Programming of 8 bytes at address 0x08009460 performed ok. + Programming of 8 bytes at address 0x08009468 performed ok. + Programming of 8 bytes at address 0x08009470 performed ok. + Programming of 8 bytes at address 0x08009478 performed ok. + Programming of 8 bytes at address 0x08009480 performed ok. + Programming of 8 bytes at address 0x08009488 performed ok. + Programming of 8 bytes at address 0x08009490 performed ok. + Programming of 8 bytes at address 0x08009498 performed ok. +k. +k. + Programming of 8 bytes at address 0x080094B0 performed ok. + Programming of 8 bytes at address 0x080094B8 performed ok. + Programming of 8 bytes at address 0x080094C0 performed ok. + Programming of 8 bytes at address 0x080094C8 performed ok. + Programming of 8 bytes at address 0x080094D0 performed ok. + Programming of 8 bytes at address 0x080094D8 performed ok. + Programming of 8 bytes at address 0x080094E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009500 performed ok. + Programming of 8 bytes at address 0x08009508 performed ok. + Programming of 8 bytes at address 0x08009510 performed ok. + Programming of 8 bytes at address 0x08009518 performed ok. + Programming of 8 bytes at address 0x08009520 performed ok. + Programming of 8 bytes at address 0x08009528 performed ok. + Programming of 8 bytes at address 0x08009530 performed ok. + Programming of 8 bytes at address 0x08009538 performed ok. + Programming of 8 bytes at address 0x08009540 performed ok. + Programming of 8 bytes at address 0x08009548 performed ok. + Programming of 8 bytes at address 0x08009550 performed ok. + Programming of 8 bytes at address 0x08009558 performed ok. + Programming of 8 bytes at address 0x08009560 performed ok. + Programming of 8 bytes at address 0x08009568 performed ok. + Programming of 8 bytes at address 0x08009570 performed ok. + Programming of 8 bytes at address 0x08009578 performed ok. + Programming of 8 bytes at address 0x08009580 performed ok. + Programming of 8 bytes at address 0x08009588 performed ok. + Programming of 8 bytes at address 0x08009590 performed ok. +k. + Programming of 8 bytes at address 0x080095A0 performed ok. + Programming of 8 bytes at address 0x080095A8 performed ok. + Programming of 8 bytes at address 0x080095B0 performed ok. + Programming of 8 bytes at address 0x080095B8 performed ok. + Programming of 8 bytes at address 0x080095C0 performed ok. + Programming of 8 bytes at address 0x080095C8 performed ok. + Programming of 8 bytes at address 0x080095D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009600 performed ok. + Programming of 8 bytes at address 0x08009608 performed ok. + Programming of 8 bytes at address 0x08009610 performed ok. + Programming of 8 bytes at address 0x08009618 performed ok. + Programming of 8 bytes at address 0x08009620 performed ok. + Programming of 8 bytes at address 0x08009628 performed ok. + Programming of 8 bytes at address 0x08009630 performed ok. + Programming of 8 bytes at address 0x08009638 performed ok. + Programming of 8 bytes at address 0x08009640 performed ok. + Programming of 8 bytes at address 0x08009648 performed ok. + Programming of 8 bytes at address 0x08009650 performed ok. + Programming of 8 bytes at address 0x08009658 performed ok. + Programming of 8 bytes at address 0x08009660 performed ok. + Programming of 8 bytes at address 0x08009668 performed ok. + Programming of 8 bytes at address 0x08009670 performed ok. + Programming of 8 bytes at address 0x08009678 performed ok. + Programming of 8 bytes at address 0x08009680 performed ok. + Programming of 8 bytes at address 0x08009688 performed ok. + Programming of 8 bytes at address 0x08009690 performed ok. + Programming of 8 bytes at address 0x08009698 performed ok. +k. + Programming of 8 bytes at address 0x080096A8 performed ok. + Programming of 8 bytes at address 0x080096B0 performed ok. + Programming of 8 bytes at address 0x080096B8 performed ok. + Programming of 8 bytes at address 0x080096C0 performed ok. + Programming of 8 bytes at address 0x080096C8 performed ok. + Programming of 8 bytes at address 0x080096D0 performed ok. + Programming of 8 bytes at address 0x080096D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009700 performed ok. + Programming of 8 bytes at address 0x08009708 performed ok. + Programming of 8 bytes at address 0x08009710 performed ok. + Programming of 8 bytes at address 0x08009718 performed ok. + Programming of 8 bytes at address 0x08009720 performed ok. + Programming of 8 bytes at address 0x08009728 performed ok. + Programming of 8 bytes at address 0x08009730 performed ok. + Programming of 8 bytes at address 0x08009738 performed ok. + Programming of 8 bytes at address 0x08009740 performed ok. + Programming of 8 bytes at address 0x08009748 performed ok. + Programming of 8 bytes at address 0x08009750 performed ok. + Programming of 8 bytes at address 0x08009758 performed ok. + Programming of 8 bytes at address 0x08009760 performed ok. + Programming of 8 bytes at address 0x08009768 performed ok. + Programming of 8 bytes at address 0x08009770 performed ok. + Programming of 8 bytes at address 0x08009778 performed ok. + Programming of 8 bytes at address 0x08009780 performed ok. + Programming of 8 bytes at address 0x08009788 performed ok. + Programming of 8 bytes at address 0x08009790 performed ok. + Programming of 8 bytes at address 0x08009798 performed ok. + Programming of 8 bytes at address 0x080097A0 performed ok. + Programming of 8 bytes at address 0x080097A8 performed ok. + Programming of 8 bytes at address 0x080097B0 performed ok. + Programming of 8 bytes at address 0x080097B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009800 performed ok. + Programming of 8 bytes at address 0x08009808 performed ok. + Programming of 8 bytes at address 0x08009810 performed ok. + Programming of 8 bytes at address 0x08009818 performed ok. + Programming of 8 bytes at address 0x08009820 performed ok. + Programming of 8 bytes at address 0x08009828 performed ok. + Programming of 8 bytes at address 0x08009830 performed ok. + Programming of 8 bytes at address 0x08009838 performed ok. + Programming of 8 bytes at address 0x08009840 performed ok. + Programming of 8 bytes at address 0x08009848 performed ok. + Programming of 8 bytes at address 0x08009850 performed ok. + Programming of 8 bytes at address 0x08009858 performed ok. + Programming of 8 bytes at address 0x08009860 performed ok. + Programming of 8 bytes at address 0x08009868 performed ok. + Programming of 8 bytes at address 0x08009870 performed ok. + Programming of 8 bytes at address 0x08009878 performed ok. + Programming of 8 bytes at address 0x08009880 performed ok. + Programming of 8 bytes at address 0x08009888 performed ok. + Programming of 8 bytes at address 0x08009890 performed ok. + Programming of 8 bytes at address 0x08009898 performed ok. + Programming of 8 bytes at address 0x080098A0 performed ok. + Programming of 8 bytes at address 0x080098A8 performed ok. + Programming of 8 bytes at address 0x080098B0 performed ok. + Programming of 8 bytes at address 0x080098B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080098F0 performed ok. + Programming of 8 bytes at address 0x080098F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009900 performed ok. + Programming of 8 bytes at address 0x08009908 performed ok. + Programming of 8 bytes at address 0x08009910 performed ok. + Programming of 8 bytes at address 0x08009918 performed ok. + Programming of 8 bytes at address 0x08009920 performed ok. + Programming of 8 bytes at address 0x08009928 performed ok. + Programming of 8 bytes at address 0x08009930 performed ok. + Programming of 8 bytes at address 0x08009938 performed ok. + Programming of 8 bytes at address 0x08009940 performed ok. + Programming of 8 bytes at address 0x08009948 performed ok. + Programming of 8 bytes at address 0x08009950 performed ok. + Programming of 8 bytes at address 0x08009958 performed ok. + Programming of 8 bytes at address 0x08009960 performed ok. + Programming of 8 bytes at address 0x08009968 performed ok. + Programming of 8 bytes at address 0x08009970 performed ok. + Programming of 8 bytes at address 0x08009978 performed ok. + Programming of 8 bytes at address 0x08009980 performed ok. + Programming of 8 bytes at address 0x08009988 performed ok. + Programming of 8 bytes at address 0x08009990 performed ok. + Programming of 8 bytes at address 0x08009998 performed ok. + Programming of 8 bytes at address 0x080099A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080099C0 performed ok. + Programming of 8 bytes at address 0x080099C8 performed ok. + Programming of 8 bytes at address 0x080099D0 performed ok. + Programming of 8 bytes at address 0x080099D8 performed ok. + Programming of 8 bytes at address 0x080099E0 performed ok. + Programming of 8 bytes at address 0x080099E8 performed ok. + Programming of 8 bytes at address 0x080099F0 performed ok. + Programming of 8 bytes at address 0x080099F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009A00 performed ok. + Programming of 8 bytes at address 0x08009A08 performed ok. + Programming of 8 bytes at address 0x08009A10 performed ok. + Programming of 8 bytes at address 0x08009A18 performed ok. + Programming of 8 bytes at address 0x08009A20 performed ok. + Programming of 8 bytes at address 0x08009A28 performed ok. + Programming of 8 bytes at address 0x08009A30 performed ok. + Programming of 8 bytes at address 0x08009A38 performed ok. + Programming of 8 bytes at address 0x08009A40 performed ok. + Programming of 8 bytes at address 0x08009A48 performed ok. + Programming of 8 bytes at address 0x08009A50 performed ok. + Programming of 8 bytes at address 0x08009A58 performed ok. + Programming of 8 bytes at address 0x08009A60 performed ok. + Programming of 8 bytes at address 0x08009A68 performed ok. + Programming of 8 bytes at address 0x08009A70 performed ok. + Programming of 8 bytes at address 0x08009A78 performed ok. + Programming of 8 bytes at address 0x08009A80 performed ok. + Programming of 8 bytes at address 0x08009A88 performed ok. +k. + Programming of 8 bytes at address 0x08009A98 performed ok. + Programming of 8 bytes at address 0x08009AA0 performed ok. + Programming of 8 bytes at address 0x08009AA8 performed ok. + Programming of 8 bytes at address 0x08009AB0 performed ok. + Programming of 8 bytes at address 0x08009AB8 performed ok. + Programming of 8 bytes at address 0x08009AC0 performed ok. + Programming of 8 bytes at address 0x08009AC8 performed ok. +k. +k. +k. +k. + +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009B00 performed ok. + Programming of 8 bytes at address 0x08009B08 performed ok. + Programming of 8 bytes at address 0x08009B10 performed ok. + Programming of 8 bytes at address 0x08009B18 performed ok. + Programming of 8 bytes at address 0x08009B20 performed ok. + Programming of 8 bytes at address 0x08009B28 performed ok. + Programming of 8 bytes at address 0x08009B30 performed ok. + Programming of 8 bytes at address 0x08009B38 performed ok. + Programming of 8 bytes at address 0x08009B40 performed ok. + Programming of 8 bytes at address 0x08009B48 performed ok. + Programming of 8 bytes at address 0x08009B50 performed ok. + Programming of 8 bytes at address 0x08009B58 performed ok. + Programming of 8 bytes at address 0x08009B60 performed ok. + Programming of 8 bytes at address 0x08009B68 performed ok. + Programming of 8 bytes at address 0x08009B70 performed ok. + Programming of 8 bytes at address 0x08009B78 performed ok. + Programming of 8 bytes at address 0x08009B80 performed ok. + Programming of 8 bytes at address 0x08009B88 performed ok. + Programming of 8 bytes at address 0x08009B90 performed ok. + Programming of 8 bytes at address 0x08009B98 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08009BB8 performed ok. + Programming of 8 bytes at address 0x08009BC0 performed ok. + Programming of 8 bytes at address 0x08009BC8 performed ok. + Programming of 8 bytes at address 0x08009BD0 performed ok. + Programming of 8 bytes at address 0x08009BD8 performed ok. + Programming of 8 bytes at address 0x08009BE0 performed ok. + Programming of 8 bytes at address 0x08009BE8 performed ok. + Programming of 8 bytes at address 0x08009BF0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009C00 performed ok. + Programming of 8 bytes at address 0x08009C08 performed ok. + Programming of 8 bytes at address 0x08009C10 performed ok. + Programming of 8 bytes at address 0x08009C18 performed ok. + Programming of 8 bytes at address 0x08009C20 performed ok. + Programming of 8 bytes at address 0x08009C28 performed ok. + Programming of 8 bytes at address 0x08009C30 performed ok. + Programming of 8 bytes at address 0x08009C38 performed ok. + Programming of 8 bytes at address 0x08009C40 performed ok. + Programming of 8 bytes at address 0x08009C48 performed ok. + Programming of 8 bytes at address 0x08009C50 performed ok. + Programming of 8 bytes at address 0x08009C58 performed ok. + Programming of 8 bytes at address 0x08009C60 performed ok. + Programming of 8 bytes at address 0x08009C68 performed ok. + Programming of 8 bytes at address 0x08009C70 performed ok. + Programming of 8 bytes at address 0x08009C78 performed ok. + Programming of 8 bytes at address 0x08009C80 performed ok. + Programming of 8 bytes at address 0x08009C88 performed ok. + Programming of 8 bytes at address 0x08009C90 performed ok. + Programming of 8 bytes at address 0x08009C98 performed ok. + Programming of 8 bytes at address 0x08009CA0 performed ok. + Programming of 8 bytes at address 0x08009CA8 performed ok. + Programming of 8 bytes at address 0x08009CB0 performed ok. + Programming of 8 bytes at address 0x08009CB8 performed ok. + Programming of 8 bytes at address 0x08009CC0 performed ok. + Programming of 8 bytes at address 0x08009CC8 performed ok. +k. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009D00 performed ok. + Programming of 8 bytes at address 0x08009D08 performed ok. + Programming of 8 bytes at address 0x08009D10 performed ok. + Programming of 8 bytes at address 0x08009D18 performed ok. + Programming of 8 bytes at address 0x08009D20 performed ok. + Programming of 8 bytes at address 0x08009D28 performed ok. + Programming of 8 bytes at address 0x08009D30 performed ok. + Programming of 8 bytes at address 0x08009D38 performed ok. + Programming of 8 bytes at address 0x08009D40 performed ok. + Programming of 8 bytes at address 0x08009D48 performed ok. + Programming of 8 bytes at address 0x08009D50 performed ok. + Programming of 8 bytes at address 0x08009D58 performed ok. + Programming of 8 bytes at address 0x08009D60 performed ok. + Programming of 8 bytes at address 0x08009D68 performed ok. + Programming of 8 bytes at address 0x08009D70 performed ok. + Programming of 8 bytes at address 0x08009D78 performed ok. + Programming of 8 bytes at address 0x08009D80 performed ok. + Programming of 8 bytes at address 0x08009D88 performed ok. + Programming of 8 bytes at address 0x08009D90 performed ok. + Programming of 8 bytes at address 0x08009D98 performed ok. + Programming of 8 bytes at address 0x08009DA0 performed ok. + Programming of 8 bytes at address 0x08009DA8 performed ok. + Programming of 8 bytes at address 0x08009DB0 performed ok. + Programming of 8 bytes at address 0x08009DB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08009DF0 performed ok. + Programming of 8 bytes at address 0x08009DF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009E00 performed ok. + Programming of 8 bytes at address 0x08009E08 performed ok. + Programming of 8 bytes at address 0x08009E10 performed ok. + Programming of 8 bytes at address 0x08009E18 performed ok. + Programming of 8 bytes at address 0x08009E20 performed ok. + Programming of 8 bytes at address 0x08009E28 performed ok. + Programming of 8 bytes at address 0x08009E30 performed ok. + Programming of 8 bytes at address 0x08009E38 performed ok. + Programming of 8 bytes at address 0x08009E40 performed ok. + Programming of 8 bytes at address 0x08009E48 performed ok. + Programming of 8 bytes at address 0x08009E50 performed ok. + Programming of 8 bytes at address 0x08009E58 performed ok. + Programming of 8 bytes at address 0x08009E60 performed ok. + Programming of 8 bytes at address 0x08009E68 performed ok. + Programming of 8 bytes at address 0x08009E70 performed ok. + Programming of 8 bytes at address 0x08009E78 performed ok. + Programming of 8 bytes at address 0x08009E80 performed ok. + Programming of 8 bytes at address 0x08009E88 performed ok. + Programming of 8 bytes at address 0x08009E90 performed ok. + Programming of 8 bytes at address 0x08009E98 performed ok. + Programming of 8 bytes at address 0x08009EA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08009EC0 performed ok. + Programming of 8 bytes at address 0x08009EC8 performed ok. + Programming of 8 bytes at address 0x08009ED0 performed ok. + Programming of 8 bytes at address 0x08009ED8 performed ok. + Programming of 8 bytes at address 0x08009EE0 performed ok. + Programming of 8 bytes at address 0x08009EE8 performed ok. + Programming of 8 bytes at address 0x08009EF0 performed ok. + Programming of 8 bytes at address 0x08009EF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08009F00 performed ok. + Programming of 8 bytes at address 0x08009F08 performed ok. + Programming of 8 bytes at address 0x08009F10 performed ok. + Programming of 8 bytes at address 0x08009F18 performed ok. + Programming of 8 bytes at address 0x08009F20 performed ok. + Programming of 8 bytes at address 0x08009F28 performed ok. + Programming of 8 bytes at address 0x08009F30 performed ok. + Programming of 8 bytes at address 0x08009F38 performed ok. + Programming of 8 bytes at address 0x08009F40 performed ok. + Programming of 8 bytes at address 0x08009F48 performed ok. + Programming of 8 bytes at address 0x08009F50 performed ok. + Programming of 8 bytes at address 0x08009F58 performed ok. + Programming of 8 bytes at address 0x08009F60 performed ok. + Programming of 8 bytes at address 0x08009F68 performed ok. + Programming of 8 bytes at address 0x08009F70 performed ok. + Programming of 8 bytes at address 0x08009F78 performed ok. + Programming of 8 bytes at address 0x08009F80 performed ok. + Programming of 8 bytes at address 0x08009F88 performed ok. + Programming of 8 bytes at address 0x08009F90 performed ok. +k. + Programming of 8 bytes at address 0x08009FA0 performed ok. + Programming of 8 bytes at address 0x08009FA8 performed ok. + Programming of 8 bytes at address 0x08009FB0 performed ok. + Programming of 8 bytes at address 0x08009FB8 performed ok. + Programming of 8 bytes at address 0x08009FC0 performed ok. + Programming of 8 bytes at address 0x08009FC8 performed ok. + Programming of 8 bytes at address 0x08009FD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800A000 performed ok. + Programming of 8 bytes at address 0x0800A008 performed ok. + Programming of 8 bytes at address 0x0800A010 performed ok. + Programming of 8 bytes at address 0x0800A018 performed ok. + Programming of 8 bytes at address 0x0800A020 performed ok. + Programming of 8 bytes at address 0x0800A028 performed ok. + Programming of 8 bytes at address 0x0800A030 performed ok. + Programming of 8 bytes at address 0x0800A038 performed ok. + Programming of 8 bytes at address 0x0800A040 performed ok. + Programming of 8 bytes at address 0x0800A048 performed ok. + Programming of 8 bytes at address 0x0800A050 performed ok. + Programming of 8 bytes at address 0x0800A058 performed ok. + Programming of 8 bytes at address 0x0800A060 performed ok. + Programming of 8 bytes at address 0x0800A068 performed ok. + Programming of 8 bytes at address 0x0800A070 performed ok. + Programming of 8 bytes at address 0x0800A078 performed ok. + Programming of 8 bytes at address 0x0800A080 performed ok. + Programming of 8 bytes at address 0x0800A088 performed ok. + Programming of 8 bytes at address 0x0800A090 performed ok. + Programming of 8 bytes at address 0x0800A098 performed ok. + Programming of 8 bytes at address 0x0800A0A0 performed ok. + Programming of 8 bytes at address 0x0800A0A8 performed ok. + Programming of 8 bytes at address 0x0800A0B0 performed ok. + Programming of 8 bytes at address 0x0800A0B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800A0F0 performed ok. + Programming of 8 bytes at address 0x0800A0F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800A100 performed ok. + Programming of 8 bytes at address 0x0800A108 performed ok. + Programming of 8 bytes at address 0x0800A110 performed ok. + Programming of 8 bytes at address 0x0800A118 performed ok. + Programming of 8 bytes at address 0x0800A120 performed ok. + Programming of 8 bytes at address 0x0800A128 performed ok. + Programming of 8 bytes at address 0x0800A130 performed ok. + Programming of 8 bytes at address 0x0800A138 performed ok. + Programming of 8 bytes at address 0x0800A140 performed ok. + Programming of 8 bytes at address 0x0800A148 performed ok. + Programming of 8 bytes at address 0x0800A150 performed ok. + Programming of 8 bytes at address 0x0800A158 performed ok. + Programming of 8 bytes at address 0x0800A160 performed ok. + Programming of 8 bytes at address 0x0800A168 performed ok. + Programming of 8 bytes at address 0x0800A170 performed ok. + Programming of 8 bytes at address 0x0800A178 performed ok. + Programming of 8 bytes at address 0x0800A180 performed ok. + Programming of 8 bytes at address 0x0800A188 performed ok. + Programming of 8 bytes at address 0x0800A190 performed ok. + Programming of 8 bytes at address 0x0800A198 performed ok. + Programming of 8 bytes at address 0x0800A1A0 performed ok. + Programming of 8 bytes at address 0x0800A1A8 performed ok. + Programming of 8 bytes at address 0x0800A1B0 performed ok. + Programming of 8 bytes at address 0x0800A1B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800A1F0 performed ok. + Programming of 8 bytes at address 0x0800A1F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800A200 performed ok. + Programming of 8 bytes at address 0x0800A208 performed ok. + Programming of 8 bytes at address 0x0800A210 performed ok. + Programming of 8 bytes at address 0x0800A218 performed ok. + Programming of 8 bytes at address 0x0800A220 performed ok. + Programming of 8 bytes at address 0x0800A228 performed ok. + Programming of 8 bytes at address 0x0800A230 performed ok. + Programming of 8 bytes at address 0x0800A238 performed ok. + Programming of 8 bytes at address 0x0800A240 performed ok. + Programming of 8 bytes at address 0x0800A248 performed ok. + Programming of 8 bytes at address 0x0800A250 performed ok. + Programming of 8 bytes at address 0x0800A258 performed ok. + Programming of 8 bytes at address 0x0800A260 performed ok. + Programming of 8 bytes at address 0x0800A268 performed ok. + Programming of 8 bytes at address 0x0800A270 performed ok. + Programming of 8 bytes at address 0x0800A278 performed ok. + Programming of 8 bytes at address 0x0800A280 performed ok. + Programming of 8 bytes at address 0x0800A288 performed ok. + Programming of 8 bytes at address 0x0800A290 performed ok. + Programming of 8 bytes at address 0x0800A298 performed ok. + Programming of 8 bytes at address 0x0800A2A0 performed ok. + Programming of 8 bytes at address 0x0800A2A8 performed ok. + Programming of 8 bytes at address 0x0800A2B0 performed ok. + Programming of 8 bytes at address 0x0800A2B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800A2F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800A300 performed ok. + Programming of 8 bytes at address 0x0800A308 performed ok. + Programming of 8 bytes at address 0x0800A310 performed ok. + Programming of 8 bytes at address 0x0800A318 performed ok. + Programming of 8 bytes at address 0x0800A320 performed ok. + Programming of 8 bytes at address 0x0800A328 performed ok. + Programming of 8 bytes at address 0x0800A330 performed ok. + Programming of 8 bytes at address 0x0800A338 performed ok. + Programming of 8 bytes at address 0x0800A340 performed ok. + Programming of 8 bytes at address 0x0800A348 performed ok. + Programming of 8 bytes at address 0x0800A350 performed ok. + Programming of 8 bytes at address 0x0800A358 performed ok. + Programming of 8 bytes at address 0x0800A360 performed ok. + Programming of 8 bytes at address 0x0800A368 performed ok. + Programming of 8 bytes at address 0x0800A370 performed ok. + Programming of 8 bytes at address 0x0800A378 performed ok. + Programming of 8 bytes at address 0x0800A380 performed ok. + Programming of 8 bytes at address 0x0800A388 performed ok. + Programming of 8 bytes at address 0x0800A390 performed ok. + Programming of 8 bytes at address 0x0800A398 performed ok. +k. + Programming of 8 bytes at address 0x0800A3A8 performed ok. + Programming of 8 bytes at address 0x0800A3B0 performed ok. + Programming of 8 bytes at address 0x0800A3B8 performed ok. + Programming of 8 bytes at address 0x0800A3C0 performed ok. + Programming of 8 bytes at address 0x0800A3C8 performed ok. + Programming of 8 bytes at address 0x0800A3D0 performed ok. + Programming of 8 bytes at address 0x0800A3D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800A400 performed ok. + Programming of 8 bytes at address 0x0800A408 performed ok. + Programming of 8 bytes at address 0x0800A410 performed ok. + Programming of 8 bytes at address 0x0800A418 performed ok. + Programming of 8 bytes at address 0x0800A420 performed ok. + Programming of 8 bytes at address 0x0800A428 performed ok. + Programming of 8 bytes at address 0x0800A430 performed ok. + Programming of 8 bytes at address 0x0800A438 performed ok. + Programming of 8 bytes at address 0x0800A440 performed ok. + Programming of 8 bytes at address 0x0800A448 performed ok. + Programming of 8 bytes at address 0x0800A450 performed ok. + Programming of 8 bytes at address 0x0800A458 performed ok. + Programming of 8 bytes at address 0x0800A460 performed ok. + Programming of 8 bytes at address 0x0800A468 performed ok. + Programming of 8 bytes at address 0x0800A470 performed ok. + Programming of 8 bytes at address 0x0800A478 performed ok. + Programming of 8 bytes at address 0x0800A480 performed ok. + Programming of 8 bytes at address 0x0800A488 performed ok. + Programming of 8 bytes at address 0x0800A490 performed ok. + Programming of 8 bytes at address 0x0800A498 performed ok. +k. +k. + Programming of 8 bytes at address 0x0800A4B0 performed ok. + Programming of 8 bytes at address 0x0800A4B8 performed ok. + Programming of 8 bytes at address 0x0800A4C0 performed ok. + Programming of 8 bytes at address 0x0800A4C8 performed ok. + Programming of 8 bytes at address 0x0800A4D0 performed ok. + Programming of 8 bytes at address 0x0800A4D8 performed ok. + Programming of 8 bytes at address 0x0800A4E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800A500 performed ok. + Programming of 8 bytes at address 0x0800A508 performed ok. + Programming of 8 bytes at address 0x0800A510 performed ok. + Programming of 8 bytes at address 0x0800A518 performed ok. + Programming of 8 bytes at address 0x0800A520 performed ok. + Programming of 8 bytes at address 0x0800A528 performed ok. + Programming of 8 bytes at address 0x0800A530 performed ok. + Programming of 8 bytes at address 0x0800A538 performed ok. + Programming of 8 bytes at address 0x0800A540 performed ok. + Programming of 8 bytes at address 0x0800A548 performed ok. + Programming of 8 bytes at address 0x0800A550 performed ok. + Programming of 8 bytes at address 0x0800A558 performed ok. + Programming of 8 bytes at address 0x0800A560 performed ok. + Programming of 8 bytes at address 0x0800A568 performed ok. + Programming of 8 bytes at address 0x0800A570 performed ok. + Programming of 8 bytes at address 0x0800A578 performed ok. + Programming of 8 bytes at address 0x0800A580 performed ok. + Programming of 8 bytes at address 0x0800A588 performed ok. + Programming of 8 bytes at address 0x0800A590 performed ok. + Programming of 8 bytes at address 0x0800A598 performed ok. +k. + Programming of 8 bytes at address 0x0800A5A8 performed ok. + Programming of 8 bytes at address 0x0800A5B0 performed ok. + Programming of 8 bytes at address 0x0800A5B8 performed ok. + Programming of 8 bytes at address 0x0800A5C0 performed ok. + Programming of 8 bytes at address 0x0800A5C8 performed ok. + Programming of 8 bytes at address 0x0800A5D0 performed ok. + Programming of 8 bytes at address 0x0800A5D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800A600 performed ok. + Programming of 8 bytes at address 0x0800A608 performed ok. + Programming of 8 bytes at address 0x0800A610 performed ok. + Programming of 8 bytes at address 0x0800A618 performed ok. + Programming of 8 bytes at address 0x0800A620 performed ok. + Programming of 8 bytes at address 0x0800A628 performed ok. + Programming of 8 bytes at address 0x0800A630 performed ok. + Programming of 8 bytes at address 0x0800A638 performed ok. + Programming of 8 bytes at address 0x0800A640 performed ok. + Programming of 8 bytes at address 0x0800A648 performed ok. + Programming of 8 bytes at address 0x0800A650 performed ok. + Programming of 8 bytes at address 0x0800A658 performed ok. + Programming of 8 bytes at address 0x0800A660 performed ok. + Programming of 8 bytes at address 0x0800A668 performed ok. + Programming of 8 bytes at address 0x0800A670 performed ok. + Programming of 8 bytes at address 0x0800A678 performed ok. + Programming of 8 bytes at address 0x0800A680 performed ok. + Programming of 8 bytes at address 0x0800A688 performed ok. + Programming of 8 bytes at address 0x0800A690 performed ok. + Programming of 8 bytes at address 0x0800A698 performed ok. + Programming of 8 bytes at address 0x0800A6A0 performed ok. + Programming of 8 bytes at address 0x0800A6A8 performed ok. + Programming of 8 bytes at address 0x0800A6B0 performed ok. + Programming of 8 bytes at address 0x0800A6B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800A6F0 performed ok. + Programming of 8 bytes at address 0x0800A6F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800A700 performed ok. + Programming of 8 bytes at address 0x0800A708 performed ok. + Programming of 8 bytes at address 0x0800A710 performed ok. + Programming of 8 bytes at address 0x0800A718 performed ok. + Programming of 8 bytes at address 0x0800A720 performed ok. + Programming of 8 bytes at address 0x0800A728 performed ok. + Programming of 8 bytes at address 0x0800A730 performed ok. + Programming of 8 bytes at address 0x0800A738 performed ok. + Programming of 8 bytes at address 0x0800A740 performed ok. + Programming of 8 bytes at address 0x0800A748 performed ok. + Programming of 8 bytes at address 0x0800A750 performed ok. + Programming of 8 bytes at address 0x0800A758 performed ok. + Programming of 8 bytes at address 0x0800A760 performed ok. + Programming of 8 bytes at address 0x0800A768 performed ok. + Programming of 8 bytes at address 0x0800A770 performed ok. + Programming of 8 bytes at address 0x0800A778 performed ok. + Programming of 8 bytes at address 0x0800A780 performed ok. + Programming of 8 bytes at address 0x0800A788 performed ok. + Programming of 8 bytes at address 0x0800A790 performed ok. + Programming of 8 bytes at address 0x0800A798 performed ok. + Programming of 8 bytes at address 0x0800A7A0 performed ok. + Programming of 8 bytes at address 0x0800A7A8 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800A7D0 performed ok. + Programming of 8 bytes at address 0x0800A7D8 performed ok. + Programming of 8 bytes at address 0x0800A7E0 performed ok. + Programming of 8 bytes at address 0x0800A7E8 performed ok. + Programming of 8 bytes at address 0x0800A7F0 performed ok. + Programming of 8 bytes at address 0x0800A7F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800A800 performed ok. + Programming of 8 bytes at address 0x0800A808 performed ok. + Programming of 8 bytes at address 0x0800A810 performed ok. + Programming of 8 bytes at address 0x0800A818 performed ok. + Programming of 8 bytes at address 0x0800A820 performed ok. + Programming of 8 bytes at address 0x0800A828 performed ok. + Programming of 8 bytes at address 0x0800A830 performed ok. + Programming of 8 bytes at address 0x0800A838 performed ok. + Programming of 8 bytes at address 0x0800A840 performed ok. + Programming of 8 bytes at address 0x0800A848 performed ok. + Programming of 8 bytes at address 0x0800A850 performed ok. + Programming of 8 bytes at address 0x0800A858 performed ok. + Programming of 8 bytes at address 0x0800A860 performed ok. + Programming of 8 bytes at address 0x0800A868 performed ok. + Programming of 8 bytes at address 0x0800A870 performed ok. + Programming of 8 bytes at address 0x0800A878 performed ok. + Programming of 8 bytes at address 0x0800A880 performed ok. + Programming of 8 bytes at address 0x0800A888 performed ok. + Programming of 8 bytes at address 0x0800A890 performed ok. + Programming of 8 bytes at address 0x0800A898 performed ok. + Programming of 8 bytes at address 0x0800A8A0 performed ok. + Programming of 8 bytes at address 0x0800A8A8 performed ok. + Programming of 8 bytes at address 0x0800A8B0 performed ok. + Programming of 8 bytes at address 0x0800A8B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800A8F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800A900 performed ok. + Programming of 8 bytes at address 0x0800A908 performed ok. + Programming of 8 bytes at address 0x0800A910 performed ok. + Programming of 8 bytes at address 0x0800A918 performed ok. + Programming of 8 bytes at address 0x0800A920 performed ok. + Programming of 8 bytes at address 0x0800A928 performed ok. + Programming of 8 bytes at address 0x0800A930 performed ok. + Programming of 8 bytes at address 0x0800A938 performed ok. + Programming of 8 bytes at address 0x0800A940 performed ok. + Programming of 8 bytes at address 0x0800A948 performed ok. + Programming of 8 bytes at address 0x0800A950 performed ok. + Programming of 8 bytes at address 0x0800A958 performed ok. + Programming of 8 bytes at address 0x0800A960 performed ok. + Programming of 8 bytes at address 0x0800A968 performed ok. + Programming of 8 bytes at address 0x0800A970 performed ok. + Programming of 8 bytes at address 0x0800A978 performed ok. + Programming of 8 bytes at address 0x0800A980 performed ok. + Programming of 8 bytes at address 0x0800A988 performed ok. + Programming of 8 bytes at address 0x0800A990 performed ok. +k. + Programming of 8 bytes at address 0x0800A9A0 performed ok. + Programming of 8 bytes at address 0x0800A9A8 performed ok. + Programming of 8 bytes at address 0x0800A9B0 performed ok. + Programming of 8 bytes at address 0x0800A9B8 performed ok. + Programming of 8 bytes at address 0x0800A9C0 performed ok. + Programming of 8 bytes at address 0x0800A9C8 performed ok. + Programming of 8 bytes at address 0x0800A9D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800AA00 performed ok. + Programming of 8 bytes at address 0x0800AA08 performed ok. + Programming of 8 bytes at address 0x0800AA10 performed ok. + Programming of 8 bytes at address 0x0800AA18 performed ok. + Programming of 8 bytes at address 0x0800AA20 performed ok. + Programming of 8 bytes at address 0x0800AA28 performed ok. + Programming of 8 bytes at address 0x0800AA30 performed ok. + Programming of 8 bytes at address 0x0800AA38 performed ok. + Programming of 8 bytes at address 0x0800AA40 performed ok. + Programming of 8 bytes at address 0x0800AA48 performed ok. + Programming of 8 bytes at address 0x0800AA50 performed ok. + Programming of 8 bytes at address 0x0800AA58 performed ok. + Programming of 8 bytes at address 0x0800AA60 performed ok. + Programming of 8 bytes at address 0x0800AA68 performed ok. + Programming of 8 bytes at address 0x0800AA70 performed ok. + Programming of 8 bytes at address 0x0800AA78 performed ok. + Programming of 8 bytes at address 0x0800AA80 performed ok. + Programming of 8 bytes at address 0x0800AA88 performed ok. + Programming of 8 bytes at address 0x0800AA90 performed ok. + Programming of 8 bytes at address 0x0800AA98 performed ok. + Programming of 8 bytes at address 0x0800AAA0 performed ok. + Programming of 8 bytes at address 0x0800AAA8 performed ok. + Programming of 8 bytes at address 0x0800AAB0 performed ok. + Programming of 8 bytes at address 0x0800AAB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800AAF0 performed ok. + Programming of 8 bytes at address 0x0800AAF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800AB00 performed ok. + Programming of 8 bytes at address 0x0800AB08 performed ok. + Programming of 8 bytes at address 0x0800AB10 performed ok. + Programming of 8 bytes at address 0x0800AB18 performed ok. + Programming of 8 bytes at address 0x0800AB20 performed ok. + Programming of 8 bytes at address 0x0800AB28 performed ok. + Programming of 8 bytes at address 0x0800AB30 performed ok. + Programming of 8 bytes at address 0x0800AB38 performed ok. + Programming of 8 bytes at address 0x0800AB40 performed ok. + Programming of 8 bytes at address 0x0800AB48 performed ok. + Programming of 8 bytes at address 0x0800AB50 performed ok. + Programming of 8 bytes at address 0x0800AB58 performed ok. + Programming of 8 bytes at address 0x0800AB60 performed ok. + Programming of 8 bytes at address 0x0800AB68 performed ok. + Programming of 8 bytes at address 0x0800AB70 performed ok. + Programming of 8 bytes at address 0x0800AB78 performed ok. + Programming of 8 bytes at address 0x0800AB80 performed ok. + Programming of 8 bytes at address 0x0800AB88 performed ok. + Programming of 8 bytes at address 0x0800AB90 performed ok. + Programming of 8 bytes at address 0x0800AB98 performed ok. +k. +k. + Programming of 8 bytes at address 0x0800ABB0 performed ok. + Programming of 8 bytes at address 0x0800ABB8 performed ok. + Programming of 8 bytes at address 0x0800ABC0 performed ok. + Programming of 8 bytes at address 0x0800ABC8 performed ok. + Programming of 8 bytes at address 0x0800ABD0 performed ok. + Programming of 8 bytes at address 0x0800ABD8 performed ok. + Programming of 8 bytes at address 0x0800ABE0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800AC00 performed ok. + Programming of 8 bytes at address 0x0800AC08 performed ok. + Programming of 8 bytes at address 0x0800AC10 performed ok. + Programming of 8 bytes at address 0x0800AC18 performed ok. + Programming of 8 bytes at address 0x0800AC20 performed ok. + Programming of 8 bytes at address 0x0800AC28 performed ok. + Programming of 8 bytes at address 0x0800AC30 performed ok. + Programming of 8 bytes at address 0x0800AC38 performed ok. + Programming of 8 bytes at address 0x0800AC40 performed ok. + Programming of 8 bytes at address 0x0800AC48 performed ok. + Programming of 8 bytes at address 0x0800AC50 performed ok. + Programming of 8 bytes at address 0x0800AC58 performed ok. + Programming of 8 bytes at address 0x0800AC60 performed ok. + Programming of 8 bytes at address 0x0800AC68 performed ok. + Programming of 8 bytes at address 0x0800AC70 performed ok. + Programming of 8 bytes at address 0x0800AC78 performed ok. + Programming of 8 bytes at address 0x0800AC80 performed ok. + Programming of 8 bytes at address 0x0800AC88 performed ok. + Programming of 8 bytes at address 0x0800AC90 performed ok. + Programming of 8 bytes at address 0x0800AC98 performed ok. + Programming of 8 bytes at address 0x0800ACA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800ACC0 performed ok. + Programming of 8 bytes at address 0x0800ACC8 performed ok. + Programming of 8 bytes at address 0x0800ACD0 performed ok. + Programming of 8 bytes at address 0x0800ACD8 performed ok. + Programming of 8 bytes at address 0x0800ACE0 performed ok. + Programming of 8 bytes at address 0x0800ACE8 performed ok. + Programming of 8 bytes at address 0x0800ACF0 performed ok. + Programming of 8 bytes at address 0x0800ACF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800AD00 performed ok. + Programming of 8 bytes at address 0x0800AD08 performed ok. + Programming of 8 bytes at address 0x0800AD10 performed ok. + Programming of 8 bytes at address 0x0800AD18 performed ok. + Programming of 8 bytes at address 0x0800AD20 performed ok. + Programming of 8 bytes at address 0x0800AD28 performed ok. + Programming of 8 bytes at address 0x0800AD30 performed ok. + Programming of 8 bytes at address 0x0800AD38 performed ok. + Programming of 8 bytes at address 0x0800AD40 performed ok. + Programming of 8 bytes at address 0x0800AD48 performed ok. + Programming of 8 bytes at address 0x0800AD50 performed ok. + Programming of 8 bytes at address 0x0800AD58 performed ok. + Programming of 8 bytes at address 0x0800AD60 performed ok. + Programming of 8 bytes at address 0x0800AD68 performed ok. + Programming of 8 bytes at address 0x0800AD70 performed ok. + Programming of 8 bytes at address 0x0800AD78 performed ok. + Programming of 8 bytes at address 0x0800AD80 performed ok. + Programming of 8 bytes at address 0x0800AD88 performed ok. + Programming of 8 bytes at address 0x0800AD90 performed ok. + Programming of 8 bytes at address 0x0800AD98 performed ok. + Programming of 8 bytes at address 0x0800ADA0 performed ok. + Programming of 8 bytes at address 0x0800ADA8 performed ok. + Programming of 8 bytes at address 0x0800ADB0 performed ok. + Programming of 8 bytes at address 0x0800ADB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800ADF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800AE00 performed ok. + Programming of 8 bytes at address 0x0800AE08 performed ok. + Programming of 8 bytes at address 0x0800AE10 performed ok. + Programming of 8 bytes at address 0x0800AE18 performed ok. + Programming of 8 bytes at address 0x0800AE20 performed ok. + Programming of 8 bytes at address 0x0800AE28 performed ok. + Programming of 8 bytes at address 0x0800AE30 performed ok. + Programming of 8 bytes at address 0x0800AE38 performed ok. + Programming of 8 bytes at address 0x0800AE40 performed ok. + Programming of 8 bytes at address 0x0800AE48 performed ok. + Programming of 8 bytes at address 0x0800AE50 performed ok. + Programming of 8 bytes at address 0x0800AE58 performed ok. + Programming of 8 bytes at address 0x0800AE60 performed ok. + Programming of 8 bytes at address 0x0800AE68 performed ok. + Programming of 8 bytes at address 0x0800AE70 performed ok. + Programming of 8 bytes at address 0x0800AE78 performed ok. + Programming of 8 bytes at address 0x0800AE80 performed ok. + Programming of 8 bytes at address 0x0800AE88 performed ok. + Programming of 8 bytes at address 0x0800AE90 performed ok. + Programming of 8 bytes at address 0x0800AE98 performed ok. + Programming of 8 bytes at address 0x0800AEA0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800AEC8 performed ok. + Programming of 8 bytes at address 0x0800AED0 performed ok. + Programming of 8 bytes at address 0x0800AED8 performed ok. + Programming of 8 bytes at address 0x0800AEE0 performed ok. + Programming of 8 bytes at address 0x0800AEE8 performed ok. + Programming of 8 bytes at address 0x0800AEF0 performed ok. + Programming of 8 bytes at address 0x0800AEF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800AF00 performed ok. + Programming of 8 bytes at address 0x0800AF08 performed ok. + Programming of 8 bytes at address 0x0800AF10 performed ok. + Programming of 8 bytes at address 0x0800AF18 performed ok. + Programming of 8 bytes at address 0x0800AF20 performed ok. + Programming of 8 bytes at address 0x0800AF28 performed ok. + Programming of 8 bytes at address 0x0800AF30 performed ok. + Programming of 8 bytes at address 0x0800AF38 performed ok. + Programming of 8 bytes at address 0x0800AF40 performed ok. + Programming of 8 bytes at address 0x0800AF48 performed ok. + Programming of 8 bytes at address 0x0800AF50 performed ok. + Programming of 8 bytes at address 0x0800AF58 performed ok. + Programming of 8 bytes at address 0x0800AF60 performed ok. + Programming of 8 bytes at address 0x0800AF68 performed ok. + Programming of 8 bytes at address 0x0800AF70 performed ok. + Programming of 8 bytes at address 0x0800AF78 performed ok. + Programming of 8 bytes at address 0x0800AF80 performed ok. + Programming of 8 bytes at address 0x0800AF88 performed ok. + Programming of 8 bytes at address 0x0800AF90 performed ok. + Programming of 8 bytes at address 0x0800AF98 performed ok. + Programming of 8 bytes at address 0x0800AFA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800AFC0 performed ok. + Programming of 8 bytes at address 0x0800AFC8 performed ok. + Programming of 8 bytes at address 0x0800AFD0 performed ok. + Programming of 8 bytes at address 0x0800AFD8 performed ok. + Programming of 8 bytes at address 0x0800AFE0 performed ok. + Programming of 8 bytes at address 0x0800AFE8 performed ok. + Programming of 8 bytes at address 0x0800AFF0 performed ok. + Programming of 8 bytes at address 0x0800AFF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800B000 performed ok. + Programming of 8 bytes at address 0x0800B008 performed ok. + Programming of 8 bytes at address 0x0800B010 performed ok. + Programming of 8 bytes at address 0x0800B018 performed ok. + Programming of 8 bytes at address 0x0800B020 performed ok. + Programming of 8 bytes at address 0x0800B028 performed ok. + Programming of 8 bytes at address 0x0800B030 performed ok. + Programming of 8 bytes at address 0x0800B038 performed ok. + Programming of 8 bytes at address 0x0800B040 performed ok. + Programming of 8 bytes at address 0x0800B048 performed ok. + Programming of 8 bytes at address 0x0800B050 performed ok. + Programming of 8 bytes at address 0x0800B058 performed ok. + Programming of 8 bytes at address 0x0800B060 performed ok. + Programming of 8 bytes at address 0x0800B068 performed ok. + Programming of 8 bytes at address 0x0800B070 performed ok. + Programming of 8 bytes at address 0x0800B078 performed ok. + Programming of 8 bytes at address 0x0800B080 performed ok. + Programming of 8 bytes at address 0x0800B088 performed ok. + Programming of 8 bytes at address 0x0800B090 performed ok. + Programming of 8 bytes at address 0x0800B098 performed ok. + Programming of 8 bytes at address 0x0800B0A0 performed ok. + Programming of 8 bytes at address 0x0800B0A8 performed ok. + Programming of 8 bytes at address 0x0800B0B0 performed ok. + Programming of 8 bytes at address 0x0800B0B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800B0F0 performed ok. + Programming of 8 bytes at address 0x0800B0F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800B100 performed ok. + Programming of 8 bytes at address 0x0800B108 performed ok. + Programming of 8 bytes at address 0x0800B110 performed ok. + Programming of 8 bytes at address 0x0800B118 performed ok. + Programming of 8 bytes at address 0x0800B120 performed ok. + Programming of 8 bytes at address 0x0800B128 performed ok. + Programming of 8 bytes at address 0x0800B130 performed ok. + Programming of 8 bytes at address 0x0800B138 performed ok. + Programming of 8 bytes at address 0x0800B140 performed ok. + Programming of 8 bytes at address 0x0800B148 performed ok. + Programming of 8 bytes at address 0x0800B150 performed ok. + Programming of 8 bytes at address 0x0800B158 performed ok. + Programming of 8 bytes at address 0x0800B160 performed ok. + Programming of 8 bytes at address 0x0800B168 performed ok. + Programming of 8 bytes at address 0x0800B170 performed ok. + Programming of 8 bytes at address 0x0800B178 performed ok. + Programming of 8 bytes at address 0x0800B180 performed ok. + Programming of 8 bytes at address 0x0800B188 performed ok. + Programming of 8 bytes at address 0x0800B190 performed ok. + Programming of 8 bytes at address 0x0800B198 performed ok. + Programming of 8 bytes at address 0x0800B1A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800B1C0 performed ok. + Programming of 8 bytes at address 0x0800B1C8 performed ok. + Programming of 8 bytes at address 0x0800B1D0 performed ok. + Programming of 8 bytes at address 0x0800B1D8 performed ok. + Programming of 8 bytes at address 0x0800B1E0 performed ok. + Programming of 8 bytes at address 0x0800B1E8 performed ok. + Programming of 8 bytes at address 0x0800B1F0 performed ok. + Programming of 8 bytes at address 0x0800B1F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800B200 performed ok. + Programming of 8 bytes at address 0x0800B208 performed ok. + Programming of 8 bytes at address 0x0800B210 performed ok. + Programming of 8 bytes at address 0x0800B218 performed ok. + Programming of 8 bytes at address 0x0800B220 performed ok. + Programming of 8 bytes at address 0x0800B228 performed ok. + Programming of 8 bytes at address 0x0800B230 performed ok. + Programming of 8 bytes at address 0x0800B238 performed ok. + Programming of 8 bytes at address 0x0800B240 performed ok. + Programming of 8 bytes at address 0x0800B248 performed ok. + Programming of 8 bytes at address 0x0800B250 performed ok. + Programming of 8 bytes at address 0x0800B258 performed ok. + Programming of 8 bytes at address 0x0800B260 performed ok. + Programming of 8 bytes at address 0x0800B268 performed ok. + Programming of 8 bytes at address 0x0800B270 performed ok. + Programming of 8 bytes at address 0x0800B278 performed ok. + Programming of 8 bytes at address 0x0800B280 performed ok. + Programming of 8 bytes at address 0x0800B288 performed ok. + Programming of 8 bytes at address 0x0800B290 performed ok. +k. + Programming of 8 bytes at address 0x0800B2A0 performed ok. + Programming of 8 bytes at address 0x0800B2A8 performed ok. + Programming of 8 bytes at address 0x0800B2B0 performed ok. + Programming of 8 bytes at address 0x0800B2B8 performed ok. + Programming of 8 bytes at address 0x0800B2C0 performed ok. + Programming of 8 bytes at address 0x0800B2C8 performed ok. + Programming of 8 bytes at address 0x0800B2D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800B300 performed ok. + Programming of 8 bytes at address 0x0800B308 performed ok. + Programming of 8 bytes at address 0x0800B310 performed ok. + Programming of 8 bytes at address 0x0800B318 performed ok. + Programming of 8 bytes at address 0x0800B320 performed ok. + Programming of 8 bytes at address 0x0800B328 performed ok. + Programming of 8 bytes at address 0x0800B330 performed ok. + Programming of 8 bytes at address 0x0800B338 performed ok. + Programming of 8 bytes at address 0x0800B340 performed ok. + Programming of 8 bytes at address 0x0800B348 performed ok. + Programming of 8 bytes at address 0x0800B350 performed ok. + Programming of 8 bytes at address 0x0800B358 performed ok. + Programming of 8 bytes at address 0x0800B360 performed ok. + Programming of 8 bytes at address 0x0800B368 performed ok. + Programming of 8 bytes at address 0x0800B370 performed ok. + Programming of 8 bytes at address 0x0800B378 performed ok. + Programming of 8 bytes at address 0x0800B380 performed ok. + Programming of 8 bytes at address 0x0800B388 performed ok. + Programming of 8 bytes at address 0x0800B390 performed ok. + Programming of 8 bytes at address 0x0800B398 performed ok. + Programming of 8 bytes at address 0x0800B3A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800B3C0 performed ok. + Programming of 8 bytes at address 0x0800B3C8 performed ok. + Programming of 8 bytes at address 0x0800B3D0 performed ok. + Programming of 8 bytes at address 0x0800B3D8 performed ok. + Programming of 8 bytes at address 0x0800B3E0 performed ok. + Programming of 8 bytes at address 0x0800B3E8 performed ok. + Programming of 8 bytes at address 0x0800B3F0 performed ok. + Programming of 8 bytes at address 0x0800B3F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800B400 performed ok. + Programming of 8 bytes at address 0x0800B408 performed ok. + Programming of 8 bytes at address 0x0800B410 performed ok. + Programming of 8 bytes at address 0x0800B418 performed ok. + Programming of 8 bytes at address 0x0800B420 performed ok. + Programming of 8 bytes at address 0x0800B428 performed ok. + Programming of 8 bytes at address 0x0800B430 performed ok. + Programming of 8 bytes at address 0x0800B438 performed ok. + Programming of 8 bytes at address 0x0800B440 performed ok. + Programming of 8 bytes at address 0x0800B448 performed ok. + Programming of 8 bytes at address 0x0800B450 performed ok. + Programming of 8 bytes at address 0x0800B458 performed ok. + Programming of 8 bytes at address 0x0800B460 performed ok. + Programming of 8 bytes at address 0x0800B468 performed ok. + Programming of 8 bytes at address 0x0800B470 performed ok. + Programming of 8 bytes at address 0x0800B478 performed ok. + Programming of 8 bytes at address 0x0800B480 performed ok. + Programming of 8 bytes at address 0x0800B488 performed ok. + Programming of 8 bytes at address 0x0800B490 performed ok. + Programming of 8 bytes at address 0x0800B498 performed ok. + Programming of 8 bytes at address 0x0800B4A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800B4C0 performed ok. + Programming of 8 bytes at address 0x0800B4C8 performed ok. + Programming of 8 bytes at address 0x0800B4D0 performed ok. + Programming of 8 bytes at address 0x0800B4D8 performed ok. + Programming of 8 bytes at address 0x0800B4E0 performed ok. + Programming of 8 bytes at address 0x0800B4E8 performed ok. + Programming of 8 bytes at address 0x0800B4F0 performed ok. + Programming of 8 bytes at address 0x0800B4F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800B500 performed ok. + Programming of 8 bytes at address 0x0800B508 performed ok. + Programming of 8 bytes at address 0x0800B510 performed ok. + Programming of 8 bytes at address 0x0800B518 performed ok. + Programming of 8 bytes at address 0x0800B520 performed ok. + Programming of 8 bytes at address 0x0800B528 performed ok. + Programming of 8 bytes at address 0x0800B530 performed ok. + Programming of 8 bytes at address 0x0800B538 performed ok. + Programming of 8 bytes at address 0x0800B540 performed ok. + Programming of 8 bytes at address 0x0800B548 performed ok. + Programming of 8 bytes at address 0x0800B550 performed ok. + Programming of 8 bytes at address 0x0800B558 performed ok. + Programming of 8 bytes at address 0x0800B560 performed ok. + Programming of 8 bytes at address 0x0800B568 performed ok. + Programming of 8 bytes at address 0x0800B570 performed ok. + Programming of 8 bytes at address 0x0800B578 performed ok. + Programming of 8 bytes at address 0x0800B580 performed ok. + Programming of 8 bytes at address 0x0800B588 performed ok. + Programming of 8 bytes at address 0x0800B590 performed ok. + Programming of 8 bytes at address 0x0800B598 performed ok. + Programming of 8 bytes at address 0x0800B5A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800B5C0 performed ok. + Programming of 8 bytes at address 0x0800B5C8 performed ok. + Programming of 8 bytes at address 0x0800B5D0 performed ok. + Programming of 8 bytes at address 0x0800B5D8 performed ok. + Programming of 8 bytes at address 0x0800B5E0 performed ok. + Programming of 8 bytes at address 0x0800B5E8 performed ok. + Programming of 8 bytes at address 0x0800B5F0 performed ok. + Programming of 8 bytes at address 0x0800B5F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800B600 performed ok. + Programming of 8 bytes at address 0x0800B608 performed ok. + Programming of 8 bytes at address 0x0800B610 performed ok. + Programming of 8 bytes at address 0x0800B618 performed ok. + Programming of 8 bytes at address 0x0800B620 performed ok. + Programming of 8 bytes at address 0x0800B628 performed ok. + Programming of 8 bytes at address 0x0800B630 performed ok. + Programming of 8 bytes at address 0x0800B638 performed ok. + Programming of 8 bytes at address 0x0800B640 performed ok. + Programming of 8 bytes at address 0x0800B648 performed ok. + Programming of 8 bytes at address 0x0800B650 performed ok. + Programming of 8 bytes at address 0x0800B658 performed ok. + Programming of 8 bytes at address 0x0800B660 performed ok. + Programming of 8 bytes at address 0x0800B668 performed ok. + Programming of 8 bytes at address 0x0800B670 performed ok. + Programming of 8 bytes at address 0x0800B678 performed ok. + Programming of 8 bytes at address 0x0800B680 performed ok. + Programming of 8 bytes at address 0x0800B688 performed ok. + Programming of 8 bytes at address 0x0800B690 performed ok. + Programming of 8 bytes at address 0x0800B698 performed ok. + Programming of 8 bytes at address 0x0800B6A0 performed ok. + Programming of 8 bytes at address 0x0800B6A8 performed ok. + Programming of 8 bytes at address 0x0800B6B0 performed ok. + Programming of 8 bytes at address 0x0800B6B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800B700 performed ok. + Programming of 8 bytes at address 0x0800B708 performed ok. + Programming of 8 bytes at address 0x0800B710 performed ok. + Programming of 8 bytes at address 0x0800B718 performed ok. + Programming of 8 bytes at address 0x0800B720 performed ok. + Programming of 8 bytes at address 0x0800B728 performed ok. + Programming of 8 bytes at address 0x0800B730 performed ok. + Programming of 8 bytes at address 0x0800B738 performed ok. + Programming of 8 bytes at address 0x0800B740 performed ok. + Programming of 8 bytes at address 0x0800B748 performed ok. + Programming of 8 bytes at address 0x0800B750 performed ok. + Programming of 8 bytes at address 0x0800B758 performed ok. + Programming of 8 bytes at address 0x0800B760 performed ok. + Programming of 8 bytes at address 0x0800B768 performed ok. + Programming of 8 bytes at address 0x0800B770 performed ok. + Programming of 8 bytes at address 0x0800B778 performed ok. + Programming of 8 bytes at address 0x0800B780 performed ok. + Programming of 8 bytes at address 0x0800B788 performed ok. + Programming of 8 bytes at address 0x0800B790 performed ok. + Programming of 8 bytes at address 0x0800B798 performed ok. + Programming of 8 bytes at address 0x0800B7A0 performed ok. + Programming of 8 bytes at address 0x0800B7A8 performed ok. + Programming of 8 bytes at address 0x0800B7B0 performed ok. + Programming of 8 bytes at address 0x0800B7B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800B7F0 performed ok. + Programming of 8 bytes at address 0x0800B7F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800B800 performed ok. + Programming of 8 bytes at address 0x0800B808 performed ok. + Programming of 8 bytes at address 0x0800B810 performed ok. + Programming of 8 bytes at address 0x0800B818 performed ok. + Programming of 8 bytes at address 0x0800B820 performed ok. + Programming of 8 bytes at address 0x0800B828 performed ok. + Programming of 8 bytes at address 0x0800B830 performed ok. + Programming of 8 bytes at address 0x0800B838 performed ok. + Programming of 8 bytes at address 0x0800B840 performed ok. + Programming of 8 bytes at address 0x0800B848 performed ok. + Programming of 8 bytes at address 0x0800B850 performed ok. + Programming of 8 bytes at address 0x0800B858 performed ok. + Programming of 8 bytes at address 0x0800B860 performed ok. + Programming of 8 bytes at address 0x0800B868 performed ok. + Programming of 8 bytes at address 0x0800B870 performed ok. + Programming of 8 bytes at address 0x0800B878 performed ok. + Programming of 8 bytes at address 0x0800B880 performed ok. + Programming of 8 bytes at address 0x0800B888 performed ok. + Programming of 8 bytes at address 0x0800B890 performed ok. + Programming of 8 bytes at address 0x0800B898 performed ok. + Programming of 8 bytes at address 0x0800B8A0 performed ok. + Programming of 8 bytes at address 0x0800B8A8 performed ok. + Programming of 8 bytes at address 0x0800B8B0 performed ok. + Programming of 8 bytes at address 0x0800B8B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800B8F0 performed ok. + Programming of 8 bytes at address 0x0800B8F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800B900 performed ok. + Programming of 8 bytes at address 0x0800B908 performed ok. + Programming of 8 bytes at address 0x0800B910 performed ok. + Programming of 8 bytes at address 0x0800B918 performed ok. + Programming of 8 bytes at address 0x0800B920 performed ok. + Programming of 8 bytes at address 0x0800B928 performed ok. + Programming of 8 bytes at address 0x0800B930 performed ok. + Programming of 8 bytes at address 0x0800B938 performed ok. + Programming of 8 bytes at address 0x0800B940 performed ok. + Programming of 8 bytes at address 0x0800B948 performed ok. + Programming of 8 bytes at address 0x0800B950 performed ok. + Programming of 8 bytes at address 0x0800B958 performed ok. + Programming of 8 bytes at address 0x0800B960 performed ok. + Programming of 8 bytes at address 0x0800B968 performed ok. + Programming of 8 bytes at address 0x0800B970 performed ok. + Programming of 8 bytes at address 0x0800B978 performed ok. + Programming of 8 bytes at address 0x0800B980 performed ok. + Programming of 8 bytes at address 0x0800B988 performed ok. + Programming of 8 bytes at address 0x0800B990 performed ok. + Programming of 8 bytes at address 0x0800B998 performed ok. +k. + Programming of 8 bytes at address 0x0800B9A8 performed ok. + Programming of 8 bytes at address 0x0800B9B0 performed ok. + Programming of 8 bytes at address 0x0800B9B8 performed ok. + Programming of 8 bytes at address 0x0800B9C0 performed ok. + Programming of 8 bytes at address 0x0800B9C8 performed ok. + Programming of 8 bytes at address 0x0800B9D0 performed ok. + Programming of 8 bytes at address 0x0800B9D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800BA00 performed ok. + Programming of 8 bytes at address 0x0800BA08 performed ok. + Programming of 8 bytes at address 0x0800BA10 performed ok. + Programming of 8 bytes at address 0x0800BA18 performed ok. + Programming of 8 bytes at address 0x0800BA20 performed ok. + Programming of 8 bytes at address 0x0800BA28 performed ok. + Programming of 8 bytes at address 0x0800BA30 performed ok. + Programming of 8 bytes at address 0x0800BA38 performed ok. + Programming of 8 bytes at address 0x0800BA40 performed ok. + Programming of 8 bytes at address 0x0800BA48 performed ok. + Programming of 8 bytes at address 0x0800BA50 performed ok. + Programming of 8 bytes at address 0x0800BA58 performed ok. + Programming of 8 bytes at address 0x0800BA60 performed ok. + Programming of 8 bytes at address 0x0800BA68 performed ok. + Programming of 8 bytes at address 0x0800BA70 performed ok. + Programming of 8 bytes at address 0x0800BA78 performed ok. + Programming of 8 bytes at address 0x0800BA80 performed ok. + Programming of 8 bytes at address 0x0800BA88 performed ok. + Programming of 8 bytes at address 0x0800BA90 performed ok. + Programming of 8 bytes at address 0x0800BA98 performed ok. +k. + Programming of 8 bytes at address 0x0800BAA8 performed ok. + Programming of 8 bytes at address 0x0800BAB0 performed ok. + Programming of 8 bytes at address 0x0800BAB8 performed ok. + Programming of 8 bytes at address 0x0800BAC0 performed ok. + Programming of 8 bytes at address 0x0800BAC8 performed ok. + Programming of 8 bytes at address 0x0800BAD0 performed ok. + Programming of 8 bytes at address 0x0800BAD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800BB00 performed ok. + Programming of 8 bytes at address 0x0800BB08 performed ok. + Programming of 8 bytes at address 0x0800BB10 performed ok. + Programming of 8 bytes at address 0x0800BB18 performed ok. + Programming of 8 bytes at address 0x0800BB20 performed ok. + Programming of 8 bytes at address 0x0800BB28 performed ok. + Programming of 8 bytes at address 0x0800BB30 performed ok. + Programming of 8 bytes at address 0x0800BB38 performed ok. + Programming of 8 bytes at address 0x0800BB40 performed ok. + Programming of 8 bytes at address 0x0800BB48 performed ok. + Programming of 8 bytes at address 0x0800BB50 performed ok. + Programming of 8 bytes at address 0x0800BB58 performed ok. + Programming of 8 bytes at address 0x0800BB60 performed ok. + Programming of 8 bytes at address 0x0800BB68 performed ok. + Programming of 8 bytes at address 0x0800BB70 performed ok. + Programming of 8 bytes at address 0x0800BB78 performed ok. + Programming of 8 bytes at address 0x0800BB80 performed ok. + Programming of 8 bytes at address 0x0800BB88 performed ok. + Programming of 8 bytes at address 0x0800BB90 performed ok. +k. + Programming of 8 bytes at address 0x0800BBA0 performed ok. + Programming of 8 bytes at address 0x0800BBA8 performed ok. + Programming of 8 bytes at address 0x0800BBB0 performed ok. + Programming of 8 bytes at address 0x0800BBB8 performed ok. + Programming of 8 bytes at address 0x0800BBC0 performed ok. + Programming of 8 bytes at address 0x0800BBC8 performed ok. + Programming of 8 bytes at address 0x0800BBD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800BC00 performed ok. + Programming of 8 bytes at address 0x0800BC08 performed ok. + Programming of 8 bytes at address 0x0800BC10 performed ok. + Programming of 8 bytes at address 0x0800BC18 performed ok. + Programming of 8 bytes at address 0x0800BC20 performed ok. + Programming of 8 bytes at address 0x0800BC28 performed ok. + Programming of 8 bytes at address 0x0800BC30 performed ok. + Programming of 8 bytes at address 0x0800BC38 performed ok. + Programming of 8 bytes at address 0x0800BC40 performed ok. + Programming of 8 bytes at address 0x0800BC48 performed ok. + Programming of 8 bytes at address 0x0800BC50 performed ok. + Programming of 8 bytes at address 0x0800BC58 performed ok. + Programming of 8 bytes at address 0x0800BC60 performed ok. + Programming of 8 bytes at address 0x0800BC68 performed ok. + Programming of 8 bytes at address 0x0800BC70 performed ok. + Programming of 8 bytes at address 0x0800BC78 performed ok. + Programming of 8 bytes at address 0x0800BC80 performed ok. + Programming of 8 bytes at address 0x0800BC88 performed ok. + Programming of 8 bytes at address 0x0800BC90 performed ok. + Programming of 8 bytes at address 0x0800BC98 performed ok. + Programming of 8 bytes at address 0x0800BCA0 performed ok. + Programming of 8 bytes at address 0x0800BCA8 performed ok. + Programming of 8 bytes at address 0x0800BCB0 performed ok. + Programming of 8 bytes at address 0x0800BCB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800BCF0 performed ok. + Programming of 8 bytes at address 0x0800BCF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800BD00 performed ok. + Programming of 8 bytes at address 0x0800BD08 performed ok. + Programming of 8 bytes at address 0x0800BD10 performed ok. + Programming of 8 bytes at address 0x0800BD18 performed ok. + Programming of 8 bytes at address 0x0800BD20 performed ok. + Programming of 8 bytes at address 0x0800BD28 performed ok. + Programming of 8 bytes at address 0x0800BD30 performed ok. + Programming of 8 bytes at address 0x0800BD38 performed ok. + Programming of 8 bytes at address 0x0800BD40 performed ok. + Programming of 8 bytes at address 0x0800BD48 performed ok. + Programming of 8 bytes at address 0x0800BD50 performed ok. + Programming of 8 bytes at address 0x0800BD58 performed ok. + Programming of 8 bytes at address 0x0800BD60 performed ok. + Programming of 8 bytes at address 0x0800BD68 performed ok. + Programming of 8 bytes at address 0x0800BD70 performed ok. + Programming of 8 bytes at address 0x0800BD78 performed ok. + Programming of 8 bytes at address 0x0800BD80 performed ok. + Programming of 8 bytes at address 0x0800BD88 performed ok. + Programming of 8 bytes at address 0x0800BD90 performed ok. + Programming of 8 bytes at address 0x0800BD98 performed ok. + Programming of 8 bytes at address 0x0800BDA0 performed ok. + Programming of 8 bytes at address 0x0800BDA8 performed ok. + Programming of 8 bytes at address 0x0800BDB0 performed ok. + Programming of 8 bytes at address 0x0800BDB8 performed ok. + Programming of 8 bytes at address 0x0800BDC0 performed ok. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800BDF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800BE00 performed ok. + Programming of 8 bytes at address 0x0800BE08 performed ok. + Programming of 8 bytes at address 0x0800BE10 performed ok. + Programming of 8 bytes at address 0x0800BE18 performed ok. + Programming of 8 bytes at address 0x0800BE20 performed ok. + Programming of 8 bytes at address 0x0800BE28 performed ok. + Programming of 8 bytes at address 0x0800BE30 performed ok. + Programming of 8 bytes at address 0x0800BE38 performed ok. + Programming of 8 bytes at address 0x0800BE40 performed ok. + Programming of 8 bytes at address 0x0800BE48 performed ok. + Programming of 8 bytes at address 0x0800BE50 performed ok. + Programming of 8 bytes at address 0x0800BE58 performed ok. + Programming of 8 bytes at address 0x0800BE60 performed ok. + Programming of 8 bytes at address 0x0800BE68 performed ok. + Programming of 8 bytes at address 0x0800BE70 performed ok. + Programming of 8 bytes at address 0x0800BE78 performed ok. + Programming of 8 bytes at address 0x0800BE80 performed ok. + Programming of 8 bytes at address 0x0800BE88 performed ok. + Programming of 8 bytes at address 0x0800BE90 performed ok. + Programming of 8 bytes at address 0x0800BE98 performed ok. + Programming of 8 bytes at address 0x0800BEA0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800BEC8 performed ok. + Programming of 8 bytes at address 0x0800BED0 performed ok. + Programming of 8 bytes at address 0x0800BED8 performed ok. + Programming of 8 bytes at address 0x0800BEE0 performed ok. + Programming of 8 bytes at address 0x0800BEE8 performed ok. + Programming of 8 bytes at address 0x0800BEF0 performed ok. + Programming of 8 bytes at address 0x0800BEF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800BF00 performed ok. + Programming of 8 bytes at address 0x0800BF08 performed ok. + Programming of 8 bytes at address 0x0800BF10 performed ok. + Programming of 8 bytes at address 0x0800BF18 performed ok. + Programming of 8 bytes at address 0x0800BF20 performed ok. + Programming of 8 bytes at address 0x0800BF28 performed ok. + Programming of 8 bytes at address 0x0800BF30 performed ok. + Programming of 8 bytes at address 0x0800BF38 performed ok. + Programming of 8 bytes at address 0x0800BF40 performed ok. + Programming of 8 bytes at address 0x0800BF48 performed ok. + Programming of 8 bytes at address 0x0800BF50 performed ok. + Programming of 8 bytes at address 0x0800BF58 performed ok. + Programming of 8 bytes at address 0x0800BF60 performed ok. + Programming of 8 bytes at address 0x0800BF68 performed ok. + Programming of 8 bytes at address 0x0800BF70 performed ok. + Programming of 8 bytes at address 0x0800BF78 performed ok. + Programming of 8 bytes at address 0x0800BF80 performed ok. + Programming of 8 bytes at address 0x0800BF88 performed ok. + Programming of 8 bytes at address 0x0800BF90 performed ok. + Programming of 8 bytes at address 0x0800BF98 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800BFB8 performed ok. + Programming of 8 bytes at address 0x0800BFC0 performed ok. + Programming of 8 bytes at address 0x0800BFC8 performed ok. + Programming of 8 bytes at address 0x0800BFD0 performed ok. + Programming of 8 bytes at address 0x0800BFD8 performed ok. + Programming of 8 bytes at address 0x0800BFE0 performed ok. + Programming of 8 bytes at address 0x0800BFE8 performed ok. + Programming of 8 bytes at address 0x0800BFF0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800C000 performed ok. + Programming of 8 bytes at address 0x0800C008 performed ok. + Programming of 8 bytes at address 0x0800C010 performed ok. + Programming of 8 bytes at address 0x0800C018 performed ok. + Programming of 8 bytes at address 0x0800C020 performed ok. + Programming of 8 bytes at address 0x0800C028 performed ok. + Programming of 8 bytes at address 0x0800C030 performed ok. + Programming of 8 bytes at address 0x0800C038 performed ok. + Programming of 8 bytes at address 0x0800C040 performed ok. + Programming of 8 bytes at address 0x0800C048 performed ok. + Programming of 8 bytes at address 0x0800C050 performed ok. + Programming of 8 bytes at address 0x0800C058 performed ok. + Programming of 8 bytes at address 0x0800C060 performed ok. + Programming of 8 bytes at address 0x0800C068 performed ok. + Programming of 8 bytes at address 0x0800C070 performed ok. + Programming of 8 bytes at address 0x0800C078 performed ok. + Programming of 8 bytes at address 0x0800C080 performed ok. + Programming of 8 bytes at address 0x0800C088 performed ok. + Programming of 8 bytes at address 0x0800C090 performed ok. + Programming of 8 bytes at address 0x0800C098 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800C0B8 performed ok. + Programming of 8 bytes at address 0x0800C0C0 performed ok. + Programming of 8 bytes at address 0x0800C0C8 performed ok. + Programming of 8 bytes at address 0x0800C0D0 performed ok. + Programming of 8 bytes at address 0x0800C0D8 performed ok. + Programming of 8 bytes at address 0x0800C0E0 performed ok. + Programming of 8 bytes at address 0x0800C0E8 performed ok. + Programming of 8 bytes at address 0x0800C0F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800C100 performed ok. + Programming of 8 bytes at address 0x0800C108 performed ok. + Programming of 8 bytes at address 0x0800C110 performed ok. + Programming of 8 bytes at address 0x0800C118 performed ok. + Programming of 8 bytes at address 0x0800C120 performed ok. + Programming of 8 bytes at address 0x0800C128 performed ok. + Programming of 8 bytes at address 0x0800C130 performed ok. + Programming of 8 bytes at address 0x0800C138 performed ok. + Programming of 8 bytes at address 0x0800C140 performed ok. + Programming of 8 bytes at address 0x0800C148 performed ok. + Programming of 8 bytes at address 0x0800C150 performed ok. + Programming of 8 bytes at address 0x0800C158 performed ok. + Programming of 8 bytes at address 0x0800C160 performed ok. + Programming of 8 bytes at address 0x0800C168 performed ok. + Programming of 8 bytes at address 0x0800C170 performed ok. + Programming of 8 bytes at address 0x0800C178 performed ok. + Programming of 8 bytes at address 0x0800C180 performed ok. + Programming of 8 bytes at address 0x0800C188 performed ok. + Programming of 8 bytes at address 0x0800C190 performed ok. + Programming of 8 bytes at address 0x0800C198 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800C1B8 performed ok. + Programming of 8 bytes at address 0x0800C1C0 performed ok. + Programming of 8 bytes at address 0x0800C1C8 performed ok. + Programming of 8 bytes at address 0x0800C1D0 performed ok. + Programming of 8 bytes at address 0x0800C1D8 performed ok. + Programming of 8 bytes at address 0x0800C1E0 performed ok. + Programming of 8 bytes at address 0x0800C1E8 performed ok. + Programming of 8 bytes at address 0x0800C1F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800C200 performed ok. + Programming of 8 bytes at address 0x0800C208 performed ok. + Programming of 8 bytes at address 0x0800C210 performed ok. + Programming of 8 bytes at address 0x0800C218 performed ok. + Programming of 8 bytes at address 0x0800C220 performed ok. + Programming of 8 bytes at address 0x0800C228 performed ok. + Programming of 8 bytes at address 0x0800C230 performed ok. + Programming of 8 bytes at address 0x0800C238 performed ok. + Programming of 8 bytes at address 0x0800C240 performed ok. + Programming of 8 bytes at address 0x0800C248 performed ok. + Programming of 8 bytes at address 0x0800C250 performed ok. + Programming of 8 bytes at address 0x0800C258 performed ok. + Programming of 8 bytes at address 0x0800C260 performed ok. + Programming of 8 bytes at address 0x0800C268 performed ok. + Programming of 8 bytes at address 0x0800C270 performed ok. + Programming of 8 bytes at address 0x0800C278 performed ok. + Programming of 8 bytes at address 0x0800C280 performed ok. + Programming of 8 bytes at address 0x0800C288 performed ok. + Programming of 8 bytes at address 0x0800C290 performed ok. + Programming of 8 bytes at address 0x0800C298 performed ok. + Programming of 8 bytes at address 0x0800C2A0 performed ok. + Programming of 8 bytes at address 0x0800C2A8 performed ok. + Programming of 8 bytes at address 0x0800C2B0 performed ok. + Programming of 8 bytes at address 0x0800C2B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800C2F0 performed ok. + Programming of 8 bytes at address 0x0800C2F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800C300 performed ok. + Programming of 8 bytes at address 0x0800C308 performed ok. + Programming of 8 bytes at address 0x0800C310 performed ok. + Programming of 8 bytes at address 0x0800C318 performed ok. + Programming of 8 bytes at address 0x0800C320 performed ok. + Programming of 8 bytes at address 0x0800C328 performed ok. + Programming of 8 bytes at address 0x0800C330 performed ok. + Programming of 8 bytes at address 0x0800C338 performed ok. + Programming of 8 bytes at address 0x0800C340 performed ok. + Programming of 8 bytes at address 0x0800C348 performed ok. + Programming of 8 bytes at address 0x0800C350 performed ok. + Programming of 8 bytes at address 0x0800C358 performed ok. + Programming of 8 bytes at address 0x0800C360 performed ok. + Programming of 8 bytes at address 0x0800C368 performed ok. + Programming of 8 bytes at address 0x0800C370 performed ok. + Programming of 8 bytes at address 0x0800C378 performed ok. + Programming of 8 bytes at address 0x0800C380 performed ok. + Programming of 8 bytes at address 0x0800C388 performed ok. + Programming of 8 bytes at address 0x0800C390 performed ok. + Programming of 8 bytes at address 0x0800C398 performed ok. +k. + Programming of 8 bytes at address 0x0800C3A8 performed ok. + Programming of 8 bytes at address 0x0800C3B0 performed ok. + Programming of 8 bytes at address 0x0800C3B8 performed ok. + Programming of 8 bytes at address 0x0800C3C0 performed ok. + Programming of 8 bytes at address 0x0800C3C8 performed ok. + Programming of 8 bytes at address 0x0800C3D0 performed ok. + Programming of 8 bytes at address 0x0800C3D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800C400 performed ok. + Programming of 8 bytes at address 0x0800C408 performed ok. + Programming of 8 bytes at address 0x0800C410 performed ok. + Programming of 8 bytes at address 0x0800C418 performed ok. + Programming of 8 bytes at address 0x0800C420 performed ok. + Programming of 8 bytes at address 0x0800C428 performed ok. + Programming of 8 bytes at address 0x0800C430 performed ok. + Programming of 8 bytes at address 0x0800C438 performed ok. + Programming of 8 bytes at address 0x0800C440 performed ok. + Programming of 8 bytes at address 0x0800C448 performed ok. + Programming of 8 bytes at address 0x0800C450 performed ok. + Programming of 8 bytes at address 0x0800C458 performed ok. + Programming of 8 bytes at address 0x0800C460 performed ok. + Programming of 8 bytes at address 0x0800C468 performed ok. + Programming of 8 bytes at address 0x0800C470 performed ok. + Programming of 8 bytes at address 0x0800C478 performed ok. + Programming of 8 bytes at address 0x0800C480 performed ok. + Programming of 8 bytes at address 0x0800C488 performed ok. + Programming of 8 bytes at address 0x0800C490 performed ok. + Programming of 8 bytes at address 0x0800C498 performed ok. +k. + Programming of 8 bytes at address 0x0800C4A8 performed ok. + Programming of 8 bytes at address 0x0800C4B0 performed ok. + Programming of 8 bytes at address 0x0800C4B8 performed ok. + Programming of 8 bytes at address 0x0800C4C0 performed ok. + Programming of 8 bytes at address 0x0800C4C8 performed ok. + Programming of 8 bytes at address 0x0800C4D0 performed ok. + Programming of 8 bytes at address 0x0800C4D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800C500 performed ok. + Programming of 8 bytes at address 0x0800C508 performed ok. + Programming of 8 bytes at address 0x0800C510 performed ok. + Programming of 8 bytes at address 0x0800C518 performed ok. + Programming of 8 bytes at address 0x0800C520 performed ok. + Programming of 8 bytes at address 0x0800C528 performed ok. + Programming of 8 bytes at address 0x0800C530 performed ok. + Programming of 8 bytes at address 0x0800C538 performed ok. + Programming of 8 bytes at address 0x0800C540 performed ok. + Programming of 8 bytes at address 0x0800C548 performed ok. + Programming of 8 bytes at address 0x0800C550 performed ok. + Programming of 8 bytes at address 0x0800C558 performed ok. + Programming of 8 bytes at address 0x0800C560 performed ok. + Programming of 8 bytes at address 0x0800C568 performed ok. + Programming of 8 bytes at address 0x0800C570 performed ok. + Programming of 8 bytes at address 0x0800C578 performed ok. + Programming of 8 bytes at address 0x0800C580 performed ok. + Programming of 8 bytes at address 0x0800C588 performed ok. + Programming of 8 bytes at address 0x0800C590 performed ok. + Programming of 8 bytes at address 0x0800C598 performed ok. + Programming of 8 bytes at address 0x0800C5A0 performed ok. + Programming of 8 bytes at address 0x0800C5A8 performed ok. + Programming of 8 bytes at address 0x0800C5B0 performed ok. + Programming of 8 bytes at address 0x0800C5B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800C5F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800C600 performed ok. + Programming of 8 bytes at address 0x0800C608 performed ok. + Programming of 8 bytes at address 0x0800C610 performed ok. + Programming of 8 bytes at address 0x0800C618 performed ok. + Programming of 8 bytes at address 0x0800C620 performed ok. + Programming of 8 bytes at address 0x0800C628 performed ok. + Programming of 8 bytes at address 0x0800C630 performed ok. + Programming of 8 bytes at address 0x0800C638 performed ok. + Programming of 8 bytes at address 0x0800C640 performed ok. + Programming of 8 bytes at address 0x0800C648 performed ok. + Programming of 8 bytes at address 0x0800C650 performed ok. + Programming of 8 bytes at address 0x0800C658 performed ok. + Programming of 8 bytes at address 0x0800C660 performed ok. + Programming of 8 bytes at address 0x0800C668 performed ok. + Programming of 8 bytes at address 0x0800C670 performed ok. + Programming of 8 bytes at address 0x0800C678 performed ok. + Programming of 8 bytes at address 0x0800C680 performed ok. + Programming of 8 bytes at address 0x0800C688 performed ok. + Programming of 8 bytes at address 0x0800C690 performed ok. + Programming of 8 bytes at address 0x0800C698 performed ok. +k. + Programming of 8 bytes at address 0x0800C6A8 performed ok. + Programming of 8 bytes at address 0x0800C6B0 performed ok. + Programming of 8 bytes at address 0x0800C6B8 performed ok. + Programming of 8 bytes at address 0x0800C6C0 performed ok. + Programming of 8 bytes at address 0x0800C6C8 performed ok. + Programming of 8 bytes at address 0x0800C6D0 performed ok. + Programming of 8 bytes at address 0x0800C6D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800C700 performed ok. + Programming of 8 bytes at address 0x0800C708 performed ok. + Programming of 8 bytes at address 0x0800C710 performed ok. + Programming of 8 bytes at address 0x0800C718 performed ok. + Programming of 8 bytes at address 0x0800C720 performed ok. + Programming of 8 bytes at address 0x0800C728 performed ok. + Programming of 8 bytes at address 0x0800C730 performed ok. + Programming of 8 bytes at address 0x0800C738 performed ok. + Programming of 8 bytes at address 0x0800C740 performed ok. + Programming of 8 bytes at address 0x0800C748 performed ok. + Programming of 8 bytes at address 0x0800C750 performed ok. + Programming of 8 bytes at address 0x0800C758 performed ok. + Programming of 8 bytes at address 0x0800C760 performed ok. + Programming of 8 bytes at address 0x0800C768 performed ok. + Programming of 8 bytes at address 0x0800C770 performed ok. + Programming of 8 bytes at address 0x0800C778 performed ok. + Programming of 8 bytes at address 0x0800C780 performed ok. + Programming of 8 bytes at address 0x0800C788 performed ok. + Programming of 8 bytes at address 0x0800C790 performed ok. + Programming of 8 bytes at address 0x0800C798 performed ok. + Programming of 8 bytes at address 0x0800C7A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800C7C0 performed ok. + Programming of 8 bytes at address 0x0800C7C8 performed ok. + Programming of 8 bytes at address 0x0800C7D0 performed ok. + Programming of 8 bytes at address 0x0800C7D8 performed ok. + Programming of 8 bytes at address 0x0800C7E0 performed ok. + Programming of 8 bytes at address 0x0800C7E8 performed ok. + Programming of 8 bytes at address 0x0800C7F0 performed ok. + Programming of 8 bytes at address 0x0800C7F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800C800 performed ok. + Programming of 8 bytes at address 0x0800C808 performed ok. + Programming of 8 bytes at address 0x0800C810 performed ok. + Programming of 8 bytes at address 0x0800C818 performed ok. + Programming of 8 bytes at address 0x0800C820 performed ok. + Programming of 8 bytes at address 0x0800C828 performed ok. + Programming of 8 bytes at address 0x0800C830 performed ok. + Programming of 8 bytes at address 0x0800C838 performed ok. + Programming of 8 bytes at address 0x0800C840 performed ok. + Programming of 8 bytes at address 0x0800C848 performed ok. + Programming of 8 bytes at address 0x0800C850 performed ok. + Programming of 8 bytes at address 0x0800C858 performed ok. + Programming of 8 bytes at address 0x0800C860 performed ok. + Programming of 8 bytes at address 0x0800C868 performed ok. + Programming of 8 bytes at address 0x0800C870 performed ok. + Programming of 8 bytes at address 0x0800C878 performed ok. + Programming of 8 bytes at address 0x0800C880 performed ok. + Programming of 8 bytes at address 0x0800C888 performed ok. + Programming of 8 bytes at address 0x0800C890 performed ok. + Programming of 8 bytes at address 0x0800C898 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800C8B8 performed ok. + Programming of 8 bytes at address 0x0800C8C0 performed ok. + Programming of 8 bytes at address 0x0800C8C8 performed ok. + Programming of 8 bytes at address 0x0800C8D0 performed ok. + Programming of 8 bytes at address 0x0800C8D8 performed ok. + Programming of 8 bytes at address 0x0800C8E0 performed ok. + Programming of 8 bytes at address 0x0800C8E8 performed ok. + Programming of 8 bytes at address 0x0800C8F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800C900 performed ok. + Programming of 8 bytes at address 0x0800C908 performed ok. + Programming of 8 bytes at address 0x0800C910 performed ok. + Programming of 8 bytes at address 0x0800C918 performed ok. + Programming of 8 bytes at address 0x0800C920 performed ok. + Programming of 8 bytes at address 0x0800C928 performed ok. + Programming of 8 bytes at address 0x0800C930 performed ok. + Programming of 8 bytes at address 0x0800C938 performed ok. + Programming of 8 bytes at address 0x0800C940 performed ok. + Programming of 8 bytes at address 0x0800C948 performed ok. + Programming of 8 bytes at address 0x0800C950 performed ok. + Programming of 8 bytes at address 0x0800C958 performed ok. + Programming of 8 bytes at address 0x0800C960 performed ok. + Programming of 8 bytes at address 0x0800C968 performed ok. + Programming of 8 bytes at address 0x0800C970 performed ok. + Programming of 8 bytes at address 0x0800C978 performed ok. + Programming of 8 bytes at address 0x0800C980 performed ok. + Programming of 8 bytes at address 0x0800C988 performed ok. + Programming of 8 bytes at address 0x0800C990 performed ok. + Programming of 8 bytes at address 0x0800C998 performed ok. + Programming of 8 bytes at address 0x0800C9A0 performed ok. + Programming of 8 bytes at address 0x0800C9A8 performed ok. + Programming of 8 bytes at address 0x0800C9B0 performed ok. + Programming of 8 bytes at address 0x0800C9B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800C9F0 performed ok. + Programming of 8 bytes at address 0x0800C9F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800CA00 performed ok. + Programming of 8 bytes at address 0x0800CA08 performed ok. + Programming of 8 bytes at address 0x0800CA10 performed ok. + Programming of 8 bytes at address 0x0800CA18 performed ok. + Programming of 8 bytes at address 0x0800CA20 performed ok. + Programming of 8 bytes at address 0x0800CA28 performed ok. + Programming of 8 bytes at address 0x0800CA30 performed ok. + Programming of 8 bytes at address 0x0800CA38 performed ok. + Programming of 8 bytes at address 0x0800CA40 performed ok. + Programming of 8 bytes at address 0x0800CA48 performed ok. + Programming of 8 bytes at address 0x0800CA50 performed ok. + Programming of 8 bytes at address 0x0800CA58 performed ok. + Programming of 8 bytes at address 0x0800CA60 performed ok. + Programming of 8 bytes at address 0x0800CA68 performed ok. + Programming of 8 bytes at address 0x0800CA70 performed ok. + Programming of 8 bytes at address 0x0800CA78 performed ok. + Programming of 8 bytes at address 0x0800CA80 performed ok. + Programming of 8 bytes at address 0x0800CA88 performed ok. + Programming of 8 bytes at address 0x0800CA90 performed ok. + Programming of 8 bytes at address 0x0800CA98 performed ok. +k. + Programming of 8 bytes at address 0x0800CAA8 performed ok. + Programming of 8 bytes at address 0x0800CAB0 performed ok. + Programming of 8 bytes at address 0x0800CAB8 performed ok. + Programming of 8 bytes at address 0x0800CAC0 performed ok. + Programming of 8 bytes at address 0x0800CAC8 performed ok. + Programming of 8 bytes at address 0x0800CAD0 performed ok. + Programming of 8 bytes at address 0x0800CAD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800CB00 performed ok. + Programming of 8 bytes at address 0x0800CB08 performed ok. + Programming of 8 bytes at address 0x0800CB10 performed ok. + Programming of 8 bytes at address 0x0800CB18 performed ok. + Programming of 8 bytes at address 0x0800CB20 performed ok. + Programming of 8 bytes at address 0x0800CB28 performed ok. + Programming of 8 bytes at address 0x0800CB30 performed ok. + Programming of 8 bytes at address 0x0800CB38 performed ok. + Programming of 8 bytes at address 0x0800CB40 performed ok. + Programming of 8 bytes at address 0x0800CB48 performed ok. + Programming of 8 bytes at address 0x0800CB50 performed ok. + Programming of 8 bytes at address 0x0800CB58 performed ok. + Programming of 8 bytes at address 0x0800CB60 performed ok. + Programming of 8 bytes at address 0x0800CB68 performed ok. + Programming of 8 bytes at address 0x0800CB70 performed ok. + Programming of 8 bytes at address 0x0800CB78 performed ok. + Programming of 8 bytes at address 0x0800CB80 performed ok. + Programming of 8 bytes at address 0x0800CB88 performed ok. + Programming of 8 bytes at address 0x0800CB90 performed ok. + Programming of 8 bytes at address 0x0800CB98 performed ok. + Programming of 8 bytes at address 0x0800CBA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800CBC0 performed ok. + Programming of 8 bytes at address 0x0800CBC8 performed ok. + Programming of 8 bytes at address 0x0800CBD0 performed ok. + Programming of 8 bytes at address 0x0800CBD8 performed ok. + Programming of 8 bytes at address 0x0800CBE0 performed ok. + Programming of 8 bytes at address 0x0800CBE8 performed ok. + Programming of 8 bytes at address 0x0800CBF0 performed ok. + Programming of 8 bytes at address 0x0800CBF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800CC00 performed ok. + Programming of 8 bytes at address 0x0800CC08 performed ok. + Programming of 8 bytes at address 0x0800CC10 performed ok. + Programming of 8 bytes at address 0x0800CC18 performed ok. + Programming of 8 bytes at address 0x0800CC20 performed ok. + Programming of 8 bytes at address 0x0800CC28 performed ok. + Programming of 8 bytes at address 0x0800CC30 performed ok. + Programming of 8 bytes at address 0x0800CC38 performed ok. + Programming of 8 bytes at address 0x0800CC40 performed ok. + Programming of 8 bytes at address 0x0800CC48 performed ok. + Programming of 8 bytes at address 0x0800CC50 performed ok. + Programming of 8 bytes at address 0x0800CC58 performed ok. + Programming of 8 bytes at address 0x0800CC60 performed ok. + Programming of 8 bytes at address 0x0800CC68 performed ok. + Programming of 8 bytes at address 0x0800CC70 performed ok. + Programming of 8 bytes at address 0x0800CC78 performed ok. + Programming of 8 bytes at address 0x0800CC80 performed ok. + Programming of 8 bytes at address 0x0800CC88 performed ok. + Programming of 8 bytes at address 0x0800CC90 performed ok. + Programming of 8 bytes at address 0x0800CC98 performed ok. +k. +k. + Programming of 8 bytes at address 0x0800CCB0 performed ok. + Programming of 8 bytes at address 0x0800CCB8 performed ok. + Programming of 8 bytes at address 0x0800CCC0 performed ok. + Programming of 8 bytes at address 0x0800CCC8 performed ok. + Programming of 8 bytes at address 0x0800CCD0 performed ok. + Programming of 8 bytes at address 0x0800CCD8 performed ok. + Programming of 8 bytes at address 0x0800CCE0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800CD00 performed ok. + Programming of 8 bytes at address 0x0800CD08 performed ok. + Programming of 8 bytes at address 0x0800CD10 performed ok. + Programming of 8 bytes at address 0x0800CD18 performed ok. + Programming of 8 bytes at address 0x0800CD20 performed ok. + Programming of 8 bytes at address 0x0800CD28 performed ok. + Programming of 8 bytes at address 0x0800CD30 performed ok. + Programming of 8 bytes at address 0x0800CD38 performed ok. + Programming of 8 bytes at address 0x0800CD40 performed ok. + Programming of 8 bytes at address 0x0800CD48 performed ok. + Programming of 8 bytes at address 0x0800CD50 performed ok. + Programming of 8 bytes at address 0x0800CD58 performed ok. + Programming of 8 bytes at address 0x0800CD60 performed ok. + Programming of 8 bytes at address 0x0800CD68 performed ok. + Programming of 8 bytes at address 0x0800CD70 performed ok. + Programming of 8 bytes at address 0x0800CD78 performed ok. + Programming of 8 bytes at address 0x0800CD80 performed ok. + Programming of 8 bytes at address 0x0800CD88 performed ok. + Programming of 8 bytes at address 0x0800CD90 performed ok. + Programming of 8 bytes at address 0x0800CD98 performed ok. + Programming of 8 bytes at address 0x0800CDA0 performed ok. + Programming of 8 bytes at address 0x0800CDA8 performed ok. + Programming of 8 bytes at address 0x0800CDB0 performed ok. + Programming of 8 bytes at address 0x0800CDB8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800CE00 performed ok. + Programming of 8 bytes at address 0x0800CE08 performed ok. + Programming of 8 bytes at address 0x0800CE10 performed ok. + Programming of 8 bytes at address 0x0800CE18 performed ok. + Programming of 8 bytes at address 0x0800CE20 performed ok. + Programming of 8 bytes at address 0x0800CE28 performed ok. + Programming of 8 bytes at address 0x0800CE30 performed ok. + Programming of 8 bytes at address 0x0800CE38 performed ok. + Programming of 8 bytes at address 0x0800CE40 performed ok. + Programming of 8 bytes at address 0x0800CE48 performed ok. + Programming of 8 bytes at address 0x0800CE50 performed ok. + Programming of 8 bytes at address 0x0800CE58 performed ok. + Programming of 8 bytes at address 0x0800CE60 performed ok. + Programming of 8 bytes at address 0x0800CE68 performed ok. + Programming of 8 bytes at address 0x0800CE70 performed ok. + Programming of 8 bytes at address 0x0800CE78 performed ok. + Programming of 8 bytes at address 0x0800CE80 performed ok. + Programming of 8 bytes at address 0x0800CE88 performed ok. + Programming of 8 bytes at address 0x0800CE90 performed ok. + Programming of 8 bytes at address 0x0800CE98 performed ok. + Programming of 8 bytes at address 0x0800CEA0 performed ok. + Programming of 8 bytes at address 0x0800CEA8 performed ok. + Programming of 8 bytes at address 0x0800CEB0 performed ok. + Programming of 8 bytes at address 0x0800CEB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800CEF0 performed ok. + Programming of 8 bytes at address 0x0800CEF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800CF00 performed ok. + Programming of 8 bytes at address 0x0800CF08 performed ok. + Programming of 8 bytes at address 0x0800CF10 performed ok. + Programming of 8 bytes at address 0x0800CF18 performed ok. + Programming of 8 bytes at address 0x0800CF20 performed ok. + Programming of 8 bytes at address 0x0800CF28 performed ok. + Programming of 8 bytes at address 0x0800CF30 performed ok. + Programming of 8 bytes at address 0x0800CF38 performed ok. + Programming of 8 bytes at address 0x0800CF40 performed ok. + Programming of 8 bytes at address 0x0800CF48 performed ok. + Programming of 8 bytes at address 0x0800CF50 performed ok. + Programming of 8 bytes at address 0x0800CF58 performed ok. + Programming of 8 bytes at address 0x0800CF60 performed ok. + Programming of 8 bytes at address 0x0800CF68 performed ok. + Programming of 8 bytes at address 0x0800CF70 performed ok. + Programming of 8 bytes at address 0x0800CF78 performed ok. + Programming of 8 bytes at address 0x0800CF80 performed ok. + Programming of 8 bytes at address 0x0800CF88 performed ok. + Programming of 8 bytes at address 0x0800CF90 performed ok. + Programming of 8 bytes at address 0x0800CF98 performed ok. + Programming of 8 bytes at address 0x0800CFA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800CFC0 performed ok. + Programming of 8 bytes at address 0x0800CFC8 performed ok. + Programming of 8 bytes at address 0x0800CFD0 performed ok. + Programming of 8 bytes at address 0x0800CFD8 performed ok. + Programming of 8 bytes at address 0x0800CFE0 performed ok. + Programming of 8 bytes at address 0x0800CFE8 performed ok. + Programming of 8 bytes at address 0x0800CFF0 performed ok. + Programming of 8 bytes at address 0x0800CFF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800D000 performed ok. + Programming of 8 bytes at address 0x0800D008 performed ok. + Programming of 8 bytes at address 0x0800D010 performed ok. + Programming of 8 bytes at address 0x0800D018 performed ok. + Programming of 8 bytes at address 0x0800D020 performed ok. + Programming of 8 bytes at address 0x0800D028 performed ok. + Programming of 8 bytes at address 0x0800D030 performed ok. + Programming of 8 bytes at address 0x0800D038 performed ok. + Programming of 8 bytes at address 0x0800D040 performed ok. + Programming of 8 bytes at address 0x0800D048 performed ok. + Programming of 8 bytes at address 0x0800D050 performed ok. + Programming of 8 bytes at address 0x0800D058 performed ok. + Programming of 8 bytes at address 0x0800D060 performed ok. + Programming of 8 bytes at address 0x0800D068 performed ok. + Programming of 8 bytes at address 0x0800D070 performed ok. + Programming of 8 bytes at address 0x0800D078 performed ok. + Programming of 8 bytes at address 0x0800D080 performed ok. + Programming of 8 bytes at address 0x0800D088 performed ok. + Programming of 8 bytes at address 0x0800D090 performed ok. + Programming of 8 bytes at address 0x0800D098 performed ok. + Programming of 8 bytes at address 0x0800D0A0 performed ok. + Programming of 8 bytes at address 0x0800D0A8 performed ok. + Programming of 8 bytes at address 0x0800D0B0 performed ok. + Programming of 8 bytes at address 0x0800D0B8 performed ok. + Programming of 8 bytes at address 0x0800D0C0 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800D0F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800D100 performed ok. + Programming of 8 bytes at address 0x0800D108 performed ok. + Programming of 8 bytes at address 0x0800D110 performed ok. + Programming of 8 bytes at address 0x0800D118 performed ok. + Programming of 8 bytes at address 0x0800D120 performed ok. + Programming of 8 bytes at address 0x0800D128 performed ok. + Programming of 8 bytes at address 0x0800D130 performed ok. + Programming of 8 bytes at address 0x0800D138 performed ok. + Programming of 8 bytes at address 0x0800D140 performed ok. + Programming of 8 bytes at address 0x0800D148 performed ok. + Programming of 8 bytes at address 0x0800D150 performed ok. + Programming of 8 bytes at address 0x0800D158 performed ok. + Programming of 8 bytes at address 0x0800D160 performed ok. + Programming of 8 bytes at address 0x0800D168 performed ok. + Programming of 8 bytes at address 0x0800D170 performed ok. + Programming of 8 bytes at address 0x0800D178 performed ok. + Programming of 8 bytes at address 0x0800D180 performed ok. + Programming of 8 bytes at address 0x0800D188 performed ok. + Programming of 8 bytes at address 0x0800D190 performed ok. + Programming of 8 bytes at address 0x0800D198 performed ok. + Programming of 8 bytes at address 0x0800D1A0 performed ok. + Programming of 8 bytes at address 0x0800D1A8 performed ok. + Programming of 8 bytes at address 0x0800D1B0 performed ok. + Programming of 8 bytes at address 0x0800D1B8 performed ok. + Programming of 8 bytes at address 0x0800D1C0 performed ok. + Programming of 8 bytes at address 0x0800D1C8 performed ok. +k. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800D200 performed ok. + Programming of 8 bytes at address 0x0800D208 performed ok. + Programming of 8 bytes at address 0x0800D210 performed ok. + Programming of 8 bytes at address 0x0800D218 performed ok. + Programming of 8 bytes at address 0x0800D220 performed ok. + Programming of 8 bytes at address 0x0800D228 performed ok. + Programming of 8 bytes at address 0x0800D230 performed ok. + Programming of 8 bytes at address 0x0800D238 performed ok. + Programming of 8 bytes at address 0x0800D240 performed ok. + Programming of 8 bytes at address 0x0800D248 performed ok. + Programming of 8 bytes at address 0x0800D250 performed ok. + Programming of 8 bytes at address 0x0800D258 performed ok. + Programming of 8 bytes at address 0x0800D260 performed ok. + Programming of 8 bytes at address 0x0800D268 performed ok. + Programming of 8 bytes at address 0x0800D270 performed ok. + Programming of 8 bytes at address 0x0800D278 performed ok. + Programming of 8 bytes at address 0x0800D280 performed ok. + Programming of 8 bytes at address 0x0800D288 performed ok. + Programming of 8 bytes at address 0x0800D290 performed ok. +k. + Programming of 8 bytes at address 0x0800D2A0 performed ok. + Programming of 8 bytes at address 0x0800D2A8 performed ok. + Programming of 8 bytes at address 0x0800D2B0 performed ok. + Programming of 8 bytes at address 0x0800D2B8 performed ok. + Programming of 8 bytes at address 0x0800D2C0 performed ok. + Programming of 8 bytes at address 0x0800D2C8 performed ok. + Programming of 8 bytes at address 0x0800D2D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800D300 performed ok. + Programming of 8 bytes at address 0x0800D308 performed ok. + Programming of 8 bytes at address 0x0800D310 performed ok. + Programming of 8 bytes at address 0x0800D318 performed ok. + Programming of 8 bytes at address 0x0800D320 performed ok. + Programming of 8 bytes at address 0x0800D328 performed ok. + Programming of 8 bytes at address 0x0800D330 performed ok. + Programming of 8 bytes at address 0x0800D338 performed ok. + Programming of 8 bytes at address 0x0800D340 performed ok. + Programming of 8 bytes at address 0x0800D348 performed ok. + Programming of 8 bytes at address 0x0800D350 performed ok. + Programming of 8 bytes at address 0x0800D358 performed ok. + Programming of 8 bytes at address 0x0800D360 performed ok. + Programming of 8 bytes at address 0x0800D368 performed ok. + Programming of 8 bytes at address 0x0800D370 performed ok. + Programming of 8 bytes at address 0x0800D378 performed ok. + Programming of 8 bytes at address 0x0800D380 performed ok. + Programming of 8 bytes at address 0x0800D388 performed ok. + Programming of 8 bytes at address 0x0800D390 performed ok. + Programming of 8 bytes at address 0x0800D398 performed ok. + Programming of 8 bytes at address 0x0800D3A0 performed ok. + Programming of 8 bytes at address 0x0800D3A8 performed ok. + Programming of 8 bytes at address 0x0800D3B0 performed ok. + Programming of 8 bytes at address 0x0800D3B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800D3F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800D400 performed ok. + Programming of 8 bytes at address 0x0800D408 performed ok. + Programming of 8 bytes at address 0x0800D410 performed ok. + Programming of 8 bytes at address 0x0800D418 performed ok. + Programming of 8 bytes at address 0x0800D420 performed ok. + Programming of 8 bytes at address 0x0800D428 performed ok. + Programming of 8 bytes at address 0x0800D430 performed ok. + Programming of 8 bytes at address 0x0800D438 performed ok. + Programming of 8 bytes at address 0x0800D440 performed ok. + Programming of 8 bytes at address 0x0800D448 performed ok. + Programming of 8 bytes at address 0x0800D450 performed ok. + Programming of 8 bytes at address 0x0800D458 performed ok. + Programming of 8 bytes at address 0x0800D460 performed ok. + Programming of 8 bytes at address 0x0800D468 performed ok. + Programming of 8 bytes at address 0x0800D470 performed ok. + Programming of 8 bytes at address 0x0800D478 performed ok. + Programming of 8 bytes at address 0x0800D480 performed ok. + Programming of 8 bytes at address 0x0800D488 performed ok. + Programming of 8 bytes at address 0x0800D490 performed ok. + Programming of 8 bytes at address 0x0800D498 performed ok. + Programming of 8 bytes at address 0x0800D4A0 performed ok. + Programming of 8 bytes at address 0x0800D4A8 performed ok. + Programming of 8 bytes at address 0x0800D4B0 performed ok. + Programming of 8 bytes at address 0x0800D4B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800D4F0 performed ok. + Programming of 8 bytes at address 0x0800D4F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800D500 performed ok. + Programming of 8 bytes at address 0x0800D508 performed ok. + Programming of 8 bytes at address 0x0800D510 performed ok. + Programming of 8 bytes at address 0x0800D518 performed ok. + Programming of 8 bytes at address 0x0800D520 performed ok. + Programming of 8 bytes at address 0x0800D528 performed ok. + Programming of 8 bytes at address 0x0800D530 performed ok. + Programming of 8 bytes at address 0x0800D538 performed ok. + Programming of 8 bytes at address 0x0800D540 performed ok. + Programming of 8 bytes at address 0x0800D548 performed ok. + Programming of 8 bytes at address 0x0800D550 performed ok. + Programming of 8 bytes at address 0x0800D558 performed ok. + Programming of 8 bytes at address 0x0800D560 performed ok. + Programming of 8 bytes at address 0x0800D568 performed ok. + Programming of 8 bytes at address 0x0800D570 performed ok. + Programming of 8 bytes at address 0x0800D578 performed ok. + Programming of 8 bytes at address 0x0800D580 performed ok. + Programming of 8 bytes at address 0x0800D588 performed ok. + Programming of 8 bytes at address 0x0800D590 performed ok. + Programming of 8 bytes at address 0x0800D598 performed ok. + Programming of 8 bytes at address 0x0800D5A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800D5C0 performed ok. + Programming of 8 bytes at address 0x0800D5C8 performed ok. + Programming of 8 bytes at address 0x0800D5D0 performed ok. + Programming of 8 bytes at address 0x0800D5D8 performed ok. + Programming of 8 bytes at address 0x0800D5E0 performed ok. + Programming of 8 bytes at address 0x0800D5E8 performed ok. + Programming of 8 bytes at address 0x0800D5F0 performed ok. + Programming of 8 bytes at address 0x0800D5F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800D600 performed ok. + Programming of 8 bytes at address 0x0800D608 performed ok. + Programming of 8 bytes at address 0x0800D610 performed ok. + Programming of 8 bytes at address 0x0800D618 performed ok. + Programming of 8 bytes at address 0x0800D620 performed ok. + Programming of 8 bytes at address 0x0800D628 performed ok. + Programming of 8 bytes at address 0x0800D630 performed ok. + Programming of 8 bytes at address 0x0800D638 performed ok. + Programming of 8 bytes at address 0x0800D640 performed ok. + Programming of 8 bytes at address 0x0800D648 performed ok. + Programming of 8 bytes at address 0x0800D650 performed ok. + Programming of 8 bytes at address 0x0800D658 performed ok. + Programming of 8 bytes at address 0x0800D660 performed ok. + Programming of 8 bytes at address 0x0800D668 performed ok. + Programming of 8 bytes at address 0x0800D670 performed ok. + Programming of 8 bytes at address 0x0800D678 performed ok. + Programming of 8 bytes at address 0x0800D680 performed ok. + Programming of 8 bytes at address 0x0800D688 performed ok. + Programming of 8 bytes at address 0x0800D690 performed ok. + Programming of 8 bytes at address 0x0800D698 performed ok. + Programming of 8 bytes at address 0x0800D6A0 performed ok. + Programming of 8 bytes at address 0x0800D6A8 performed ok. + Programming of 8 bytes at address 0x0800D6B0 performed ok. + Programming of 8 bytes at address 0x0800D6B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800D6F0 performed ok. + Programming of 8 bytes at address 0x0800D6F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800D700 performed ok. + Programming of 8 bytes at address 0x0800D708 performed ok. + Programming of 8 bytes at address 0x0800D710 performed ok. + Programming of 8 bytes at address 0x0800D718 performed ok. + Programming of 8 bytes at address 0x0800D720 performed ok. + Programming of 8 bytes at address 0x0800D728 performed ok. + Programming of 8 bytes at address 0x0800D730 performed ok. + Programming of 8 bytes at address 0x0800D738 performed ok. + Programming of 8 bytes at address 0x0800D740 performed ok. + Programming of 8 bytes at address 0x0800D748 performed ok. + Programming of 8 bytes at address 0x0800D750 performed ok. + Programming of 8 bytes at address 0x0800D758 performed ok. + Programming of 8 bytes at address 0x0800D760 performed ok. + Programming of 8 bytes at address 0x0800D768 performed ok. + Programming of 8 bytes at address 0x0800D770 performed ok. + Programming of 8 bytes at address 0x0800D778 performed ok. + Programming of 8 bytes at address 0x0800D780 performed ok. + Programming of 8 bytes at address 0x0800D788 performed ok. + Programming of 8 bytes at address 0x0800D790 performed ok. + Programming of 8 bytes at address 0x0800D798 performed ok. +k. + Programming of 8 bytes at address 0x0800D7A8 performed ok. + Programming of 8 bytes at address 0x0800D7B0 performed ok. + Programming of 8 bytes at address 0x0800D7B8 performed ok. + Programming of 8 bytes at address 0x0800D7C0 performed ok. + Programming of 8 bytes at address 0x0800D7C8 performed ok. + Programming of 8 bytes at address 0x0800D7D0 performed ok. + Programming of 8 bytes at address 0x0800D7D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800D800 performed ok. + Programming of 8 bytes at address 0x0800D808 performed ok. + Programming of 8 bytes at address 0x0800D810 performed ok. + Programming of 8 bytes at address 0x0800D818 performed ok. + Programming of 8 bytes at address 0x0800D820 performed ok. + Programming of 8 bytes at address 0x0800D828 performed ok. + Programming of 8 bytes at address 0x0800D830 performed ok. + Programming of 8 bytes at address 0x0800D838 performed ok. + Programming of 8 bytes at address 0x0800D840 performed ok. + Programming of 8 bytes at address 0x0800D848 performed ok. + Programming of 8 bytes at address 0x0800D850 performed ok. + Programming of 8 bytes at address 0x0800D858 performed ok. + Programming of 8 bytes at address 0x0800D860 performed ok. + Programming of 8 bytes at address 0x0800D868 performed ok. + Programming of 8 bytes at address 0x0800D870 performed ok. + Programming of 8 bytes at address 0x0800D878 performed ok. + Programming of 8 bytes at address 0x0800D880 performed ok. + Programming of 8 bytes at address 0x0800D888 performed ok. + Programming of 8 bytes at address 0x0800D890 performed ok. +k. + Programming of 8 bytes at address 0x0800D8A0 performed ok. + Programming of 8 bytes at address 0x0800D8A8 performed ok. + Programming of 8 bytes at address 0x0800D8B0 performed ok. + Programming of 8 bytes at address 0x0800D8B8 performed ok. + Programming of 8 bytes at address 0x0800D8C0 performed ok. + Programming of 8 bytes at address 0x0800D8C8 performed ok. + Programming of 8 bytes at address 0x0800D8D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800D900 performed ok. + Programming of 8 bytes at address 0x0800D908 performed ok. + Programming of 8 bytes at address 0x0800D910 performed ok. + Programming of 8 bytes at address 0x0800D918 performed ok. + Programming of 8 bytes at address 0x0800D920 performed ok. + Programming of 8 bytes at address 0x0800D928 performed ok. + Programming of 8 bytes at address 0x0800D930 performed ok. + Programming of 8 bytes at address 0x0800D938 performed ok. + Programming of 8 bytes at address 0x0800D940 performed ok. + Programming of 8 bytes at address 0x0800D948 performed ok. + Programming of 8 bytes at address 0x0800D950 performed ok. + Programming of 8 bytes at address 0x0800D958 performed ok. + Programming of 8 bytes at address 0x0800D960 performed ok. + Programming of 8 bytes at address 0x0800D968 performed ok. + Programming of 8 bytes at address 0x0800D970 performed ok. + Programming of 8 bytes at address 0x0800D978 performed ok. + Programming of 8 bytes at address 0x0800D980 performed ok. + Programming of 8 bytes at address 0x0800D988 performed ok. + Programming of 8 bytes at address 0x0800D990 performed ok. + Programming of 8 bytes at address 0x0800D998 performed ok. + Programming of 8 bytes at address 0x0800D9A0 performed ok. + Programming of 8 bytes at address 0x0800D9A8 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800D9D0 performed ok. + Programming of 8 bytes at address 0x0800D9D8 performed ok. + Programming of 8 bytes at address 0x0800D9E0 performed ok. + Programming of 8 bytes at address 0x0800D9E8 performed ok. + Programming of 8 bytes at address 0x0800D9F0 performed ok. + Programming of 8 bytes at address 0x0800D9F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800DA00 performed ok. + Programming of 8 bytes at address 0x0800DA08 performed ok. + Programming of 8 bytes at address 0x0800DA10 performed ok. + Programming of 8 bytes at address 0x0800DA18 performed ok. + Programming of 8 bytes at address 0x0800DA20 performed ok. + Programming of 8 bytes at address 0x0800DA28 performed ok. + Programming of 8 bytes at address 0x0800DA30 performed ok. + Programming of 8 bytes at address 0x0800DA38 performed ok. + Programming of 8 bytes at address 0x0800DA40 performed ok. + Programming of 8 bytes at address 0x0800DA48 performed ok. + Programming of 8 bytes at address 0x0800DA50 performed ok. + Programming of 8 bytes at address 0x0800DA58 performed ok. + Programming of 8 bytes at address 0x0800DA60 performed ok. + Programming of 8 bytes at address 0x0800DA68 performed ok. + Programming of 8 bytes at address 0x0800DA70 performed ok. + Programming of 8 bytes at address 0x0800DA78 performed ok. + Programming of 8 bytes at address 0x0800DA80 performed ok. + Programming of 8 bytes at address 0x0800DA88 performed ok. + Programming of 8 bytes at address 0x0800DA90 performed ok. +k. + Programming of 8 bytes at address 0x0800DAA0 performed ok. + Programming of 8 bytes at address 0x0800DAA8 performed ok. + Programming of 8 bytes at address 0x0800DAB0 performed ok. + Programming of 8 bytes at address 0x0800DAB8 performed ok. + Programming of 8 bytes at address 0x0800DAC0 performed ok. + Programming of 8 bytes at address 0x0800DAC8 performed ok. + Programming of 8 bytes at address 0x0800DAD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800DB00 performed ok. + Programming of 8 bytes at address 0x0800DB08 performed ok. + Programming of 8 bytes at address 0x0800DB10 performed ok. + Programming of 8 bytes at address 0x0800DB18 performed ok. + Programming of 8 bytes at address 0x0800DB20 performed ok. + Programming of 8 bytes at address 0x0800DB28 performed ok. + Programming of 8 bytes at address 0x0800DB30 performed ok. + Programming of 8 bytes at address 0x0800DB38 performed ok. + Programming of 8 bytes at address 0x0800DB40 performed ok. + Programming of 8 bytes at address 0x0800DB48 performed ok. + Programming of 8 bytes at address 0x0800DB50 performed ok. + Programming of 8 bytes at address 0x0800DB58 performed ok. + Programming of 8 bytes at address 0x0800DB60 performed ok. + Programming of 8 bytes at address 0x0800DB68 performed ok. + Programming of 8 bytes at address 0x0800DB70 performed ok. + Programming of 8 bytes at address 0x0800DB78 performed ok. + Programming of 8 bytes at address 0x0800DB80 performed ok. + Programming of 8 bytes at address 0x0800DB88 performed ok. + Programming of 8 bytes at address 0x0800DB90 performed ok. + Programming of 8 bytes at address 0x0800DB98 performed ok. + Programming of 8 bytes at address 0x0800DBA0 performed ok. + Programming of 8 bytes at address 0x0800DBA8 performed ok. + Programming of 8 bytes at address 0x0800DBB0 performed ok. + Programming of 8 bytes at address 0x0800DBB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800DBF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800DC00 performed ok. + Programming of 8 bytes at address 0x0800DC08 performed ok. + Programming of 8 bytes at address 0x0800DC10 performed ok. + Programming of 8 bytes at address 0x0800DC18 performed ok. + Programming of 8 bytes at address 0x0800DC20 performed ok. + Programming of 8 bytes at address 0x0800DC28 performed ok. + Programming of 8 bytes at address 0x0800DC30 performed ok. + Programming of 8 bytes at address 0x0800DC38 performed ok. + Programming of 8 bytes at address 0x0800DC40 performed ok. + Programming of 8 bytes at address 0x0800DC48 performed ok. + Programming of 8 bytes at address 0x0800DC50 performed ok. + Programming of 8 bytes at address 0x0800DC58 performed ok. + Programming of 8 bytes at address 0x0800DC60 performed ok. + Programming of 8 bytes at address 0x0800DC68 performed ok. + Programming of 8 bytes at address 0x0800DC70 performed ok. + Programming of 8 bytes at address 0x0800DC78 performed ok. + Programming of 8 bytes at address 0x0800DC80 performed ok. + Programming of 8 bytes at address 0x0800DC88 performed ok. + Programming of 8 bytes at address 0x0800DC90 performed ok. + Programming of 8 bytes at address 0x0800DC98 performed ok. + Programming of 8 bytes at address 0x0800DCA0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800DCC8 performed ok. + Programming of 8 bytes at address 0x0800DCD0 performed ok. + Programming of 8 bytes at address 0x0800DCD8 performed ok. + Programming of 8 bytes at address 0x0800DCE0 performed ok. + Programming of 8 bytes at address 0x0800DCE8 performed ok. + Programming of 8 bytes at address 0x0800DCF0 performed ok. + Programming of 8 bytes at address 0x0800DCF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800DD00 performed ok. + Programming of 8 bytes at address 0x0800DD08 performed ok. + Programming of 8 bytes at address 0x0800DD10 performed ok. + Programming of 8 bytes at address 0x0800DD18 performed ok. + Programming of 8 bytes at address 0x0800DD20 performed ok. + Programming of 8 bytes at address 0x0800DD28 performed ok. + Programming of 8 bytes at address 0x0800DD30 performed ok. + Programming of 8 bytes at address 0x0800DD38 performed ok. + Programming of 8 bytes at address 0x0800DD40 performed ok. + Programming of 8 bytes at address 0x0800DD48 performed ok. + Programming of 8 bytes at address 0x0800DD50 performed ok. + Programming of 8 bytes at address 0x0800DD58 performed ok. + Programming of 8 bytes at address 0x0800DD60 performed ok. + Programming of 8 bytes at address 0x0800DD68 performed ok. + Programming of 8 bytes at address 0x0800DD70 performed ok. + Programming of 8 bytes at address 0x0800DD78 performed ok. + Programming of 8 bytes at address 0x0800DD80 performed ok. + Programming of 8 bytes at address 0x0800DD88 performed ok. + Programming of 8 bytes at address 0x0800DD90 performed ok. +k. + Programming of 8 bytes at address 0x0800DDA0 performed ok. + Programming of 8 bytes at address 0x0800DDA8 performed ok. + Programming of 8 bytes at address 0x0800DDB0 performed ok. + Programming of 8 bytes at address 0x0800DDB8 performed ok. + Programming of 8 bytes at address 0x0800DDC0 performed ok. + Programming of 8 bytes at address 0x0800DDC8 performed ok. + Programming of 8 bytes at address 0x0800DDD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800DE00 performed ok. + Programming of 8 bytes at address 0x0800DE08 performed ok. + Programming of 8 bytes at address 0x0800DE10 performed ok. + Programming of 8 bytes at address 0x0800DE18 performed ok. + Programming of 8 bytes at address 0x0800DE20 performed ok. + Programming of 8 bytes at address 0x0800DE28 performed ok. + Programming of 8 bytes at address 0x0800DE30 performed ok. + Programming of 8 bytes at address 0x0800DE38 performed ok. + Programming of 8 bytes at address 0x0800DE40 performed ok. + Programming of 8 bytes at address 0x0800DE48 performed ok. + Programming of 8 bytes at address 0x0800DE50 performed ok. + Programming of 8 bytes at address 0x0800DE58 performed ok. + Programming of 8 bytes at address 0x0800DE60 performed ok. + Programming of 8 bytes at address 0x0800DE68 performed ok. + Programming of 8 bytes at address 0x0800DE70 performed ok. + Programming of 8 bytes at address 0x0800DE78 performed ok. + Programming of 8 bytes at address 0x0800DE80 performed ok. + Programming of 8 bytes at address 0x0800DE88 performed ok. + Programming of 8 bytes at address 0x0800DE90 performed ok. + Programming of 8 bytes at address 0x0800DE98 performed ok. +k. +k. + Programming of 8 bytes at address 0x0800DEB0 performed ok. + Programming of 8 bytes at address 0x0800DEB8 performed ok. + Programming of 8 bytes at address 0x0800DEC0 performed ok. + Programming of 8 bytes at address 0x0800DEC8 performed ok. + Programming of 8 bytes at address 0x0800DED0 performed ok. + Programming of 8 bytes at address 0x0800DED8 performed ok. + Programming of 8 bytes at address 0x0800DEE0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800DF00 performed ok. + Programming of 8 bytes at address 0x0800DF08 performed ok. + Programming of 8 bytes at address 0x0800DF10 performed ok. + Programming of 8 bytes at address 0x0800DF18 performed ok. + Programming of 8 bytes at address 0x0800DF20 performed ok. + Programming of 8 bytes at address 0x0800DF28 performed ok. + Programming of 8 bytes at address 0x0800DF30 performed ok. + Programming of 8 bytes at address 0x0800DF38 performed ok. + Programming of 8 bytes at address 0x0800DF40 performed ok. + Programming of 8 bytes at address 0x0800DF48 performed ok. + Programming of 8 bytes at address 0x0800DF50 performed ok. + Programming of 8 bytes at address 0x0800DF58 performed ok. + Programming of 8 bytes at address 0x0800DF60 performed ok. + Programming of 8 bytes at address 0x0800DF68 performed ok. + Programming of 8 bytes at address 0x0800DF70 performed ok. + Programming of 8 bytes at address 0x0800DF78 performed ok. + Programming of 8 bytes at address 0x0800DF80 performed ok. + Programming of 8 bytes at address 0x0800DF88 performed ok. + Programming of 8 bytes at address 0x0800DF90 performed ok. + Programming of 8 bytes at address 0x0800DF98 performed ok. + Programming of 8 bytes at address 0x0800DFA0 performed ok. + Programming of 8 bytes at address 0x0800DFA8 performed ok. + Programming of 8 bytes at address 0x0800DFB0 performed ok. + Programming of 8 bytes at address 0x0800DFB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800DFF0 performed ok. + Programming of 8 bytes at address 0x0800DFF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800E000 performed ok. + Programming of 8 bytes at address 0x0800E008 performed ok. + Programming of 8 bytes at address 0x0800E010 performed ok. + Programming of 8 bytes at address 0x0800E018 performed ok. + Programming of 8 bytes at address 0x0800E020 performed ok. + Programming of 8 bytes at address 0x0800E028 performed ok. + Programming of 8 bytes at address 0x0800E030 performed ok. + Programming of 8 bytes at address 0x0800E038 performed ok. + Programming of 8 bytes at address 0x0800E040 performed ok. + Programming of 8 bytes at address 0x0800E048 performed ok. + Programming of 8 bytes at address 0x0800E050 performed ok. + Programming of 8 bytes at address 0x0800E058 performed ok. + Programming of 8 bytes at address 0x0800E060 performed ok. + Programming of 8 bytes at address 0x0800E068 performed ok. + Programming of 8 bytes at address 0x0800E070 performed ok. + Programming of 8 bytes at address 0x0800E078 performed ok. + Programming of 8 bytes at address 0x0800E080 performed ok. + Programming of 8 bytes at address 0x0800E088 performed ok. + Programming of 8 bytes at address 0x0800E090 performed ok. + Programming of 8 bytes at address 0x0800E098 performed ok. + Programming of 8 bytes at address 0x0800E0A0 performed ok. + Programming of 8 bytes at address 0x0800E0A8 performed ok. + Programming of 8 bytes at address 0x0800E0B0 performed ok. + Programming of 8 bytes at address 0x0800E0B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800E100 performed ok. + Programming of 8 bytes at address 0x0800E108 performed ok. + Programming of 8 bytes at address 0x0800E110 performed ok. + Programming of 8 bytes at address 0x0800E118 performed ok. + Programming of 8 bytes at address 0x0800E120 performed ok. + Programming of 8 bytes at address 0x0800E128 performed ok. + Programming of 8 bytes at address 0x0800E130 performed ok. + Programming of 8 bytes at address 0x0800E138 performed ok. + Programming of 8 bytes at address 0x0800E140 performed ok. + Programming of 8 bytes at address 0x0800E148 performed ok. + Programming of 8 bytes at address 0x0800E150 performed ok. + Programming of 8 bytes at address 0x0800E158 performed ok. + Programming of 8 bytes at address 0x0800E160 performed ok. + Programming of 8 bytes at address 0x0800E168 performed ok. + Programming of 8 bytes at address 0x0800E170 performed ok. + Programming of 8 bytes at address 0x0800E178 performed ok. + Programming of 8 bytes at address 0x0800E180 performed ok. + Programming of 8 bytes at address 0x0800E188 performed ok. + Programming of 8 bytes at address 0x0800E190 performed ok. + Programming of 8 bytes at address 0x0800E198 performed ok. +k. + Programming of 8 bytes at address 0x0800E1A8 performed ok. + Programming of 8 bytes at address 0x0800E1B0 performed ok. + Programming of 8 bytes at address 0x0800E1B8 performed ok. + Programming of 8 bytes at address 0x0800E1C0 performed ok. + Programming of 8 bytes at address 0x0800E1C8 performed ok. + Programming of 8 bytes at address 0x0800E1D0 performed ok. + Programming of 8 bytes at address 0x0800E1D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800E200 performed ok. + Programming of 8 bytes at address 0x0800E208 performed ok. + Programming of 8 bytes at address 0x0800E210 performed ok. + Programming of 8 bytes at address 0x0800E218 performed ok. + Programming of 8 bytes at address 0x0800E220 performed ok. + Programming of 8 bytes at address 0x0800E228 performed ok. + Programming of 8 bytes at address 0x0800E230 performed ok. + Programming of 8 bytes at address 0x0800E238 performed ok. + Programming of 8 bytes at address 0x0800E240 performed ok. + Programming of 8 bytes at address 0x0800E248 performed ok. + Programming of 8 bytes at address 0x0800E250 performed ok. + Programming of 8 bytes at address 0x0800E258 performed ok. + Programming of 8 bytes at address 0x0800E260 performed ok. + Programming of 8 bytes at address 0x0800E268 performed ok. + Programming of 8 bytes at address 0x0800E270 performed ok. + Programming of 8 bytes at address 0x0800E278 performed ok. + Programming of 8 bytes at address 0x0800E280 performed ok. + Programming of 8 bytes at address 0x0800E288 performed ok. + Programming of 8 bytes at address 0x0800E290 performed ok. + Programming of 8 bytes at address 0x0800E298 performed ok. + Programming of 8 bytes at address 0x0800E2A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800E2C0 performed ok. + Programming of 8 bytes at address 0x0800E2C8 performed ok. + Programming of 8 bytes at address 0x0800E2D0 performed ok. + Programming of 8 bytes at address 0x0800E2D8 performed ok. + Programming of 8 bytes at address 0x0800E2E0 performed ok. + Programming of 8 bytes at address 0x0800E2E8 performed ok. + Programming of 8 bytes at address 0x0800E2F0 performed ok. + Programming of 8 bytes at address 0x0800E2F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800E300 performed ok. + Programming of 8 bytes at address 0x0800E308 performed ok. + Programming of 8 bytes at address 0x0800E310 performed ok. + Programming of 8 bytes at address 0x0800E318 performed ok. + Programming of 8 bytes at address 0x0800E320 performed ok. + Programming of 8 bytes at address 0x0800E328 performed ok. + Programming of 8 bytes at address 0x0800E330 performed ok. + Programming of 8 bytes at address 0x0800E338 performed ok. + Programming of 8 bytes at address 0x0800E340 performed ok. + Programming of 8 bytes at address 0x0800E348 performed ok. + Programming of 8 bytes at address 0x0800E350 performed ok. + Programming of 8 bytes at address 0x0800E358 performed ok. + Programming of 8 bytes at address 0x0800E360 performed ok. + Programming of 8 bytes at address 0x0800E368 performed ok. + Programming of 8 bytes at address 0x0800E370 performed ok. + Programming of 8 bytes at address 0x0800E378 performed ok. + Programming of 8 bytes at address 0x0800E380 performed ok. + Programming of 8 bytes at address 0x0800E388 performed ok. + Programming of 8 bytes at address 0x0800E390 performed ok. + Programming of 8 bytes at address 0x0800E398 performed ok. + Programming of 8 bytes at address 0x0800E3A0 performed ok. + Programming of 8 bytes at address 0x0800E3A8 performed ok. + Programming of 8 bytes at address 0x0800E3B0 performed ok. + Programming of 8 bytes at address 0x0800E3B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800E400 performed ok. + Programming of 8 bytes at address 0x0800E408 performed ok. + Programming of 8 bytes at address 0x0800E410 performed ok. + Programming of 8 bytes at address 0x0800E418 performed ok. + Programming of 8 bytes at address 0x0800E420 performed ok. + Programming of 8 bytes at address 0x0800E428 performed ok. + Programming of 8 bytes at address 0x0800E430 performed ok. + Programming of 8 bytes at address 0x0800E438 performed ok. + Programming of 8 bytes at address 0x0800E440 performed ok. + Programming of 8 bytes at address 0x0800E448 performed ok. + Programming of 8 bytes at address 0x0800E450 performed ok. + Programming of 8 bytes at address 0x0800E458 performed ok. + Programming of 8 bytes at address 0x0800E460 performed ok. + Programming of 8 bytes at address 0x0800E468 performed ok. + Programming of 8 bytes at address 0x0800E470 performed ok. + Programming of 8 bytes at address 0x0800E478 performed ok. + Programming of 8 bytes at address 0x0800E480 performed ok. + Programming of 8 bytes at address 0x0800E488 performed ok. + Programming of 8 bytes at address 0x0800E490 performed ok. + Programming of 8 bytes at address 0x0800E498 performed ok. + Programming of 8 bytes at address 0x0800E4A0 performed ok. + Programming of 8 bytes at address 0x0800E4A8 performed ok. + Programming of 8 bytes at address 0x0800E4B0 performed ok. + Programming of 8 bytes at address 0x0800E4B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800E4F0 performed ok. + Programming of 8 bytes at address 0x0800E4F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800E500 performed ok. + Programming of 8 bytes at address 0x0800E508 performed ok. + Programming of 8 bytes at address 0x0800E510 performed ok. + Programming of 8 bytes at address 0x0800E518 performed ok. + Programming of 8 bytes at address 0x0800E520 performed ok. + Programming of 8 bytes at address 0x0800E528 performed ok. + Programming of 8 bytes at address 0x0800E530 performed ok. + Programming of 8 bytes at address 0x0800E538 performed ok. + Programming of 8 bytes at address 0x0800E540 performed ok. + Programming of 8 bytes at address 0x0800E548 performed ok. + Programming of 8 bytes at address 0x0800E550 performed ok. + Programming of 8 bytes at address 0x0800E558 performed ok. + Programming of 8 bytes at address 0x0800E560 performed ok. + Programming of 8 bytes at address 0x0800E568 performed ok. + Programming of 8 bytes at address 0x0800E570 performed ok. + Programming of 8 bytes at address 0x0800E578 performed ok. + Programming of 8 bytes at address 0x0800E580 performed ok. + Programming of 8 bytes at address 0x0800E588 performed ok. + Programming of 8 bytes at address 0x0800E590 performed ok. + Programming of 8 bytes at address 0x0800E598 performed ok. +k. + Programming of 8 bytes at address 0x0800E5A8 performed ok. + Programming of 8 bytes at address 0x0800E5B0 performed ok. + Programming of 8 bytes at address 0x0800E5B8 performed ok. + Programming of 8 bytes at address 0x0800E5C0 performed ok. + Programming of 8 bytes at address 0x0800E5C8 performed ok. + Programming of 8 bytes at address 0x0800E5D0 performed ok. + Programming of 8 bytes at address 0x0800E5D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800E600 performed ok. + Programming of 8 bytes at address 0x0800E608 performed ok. + Programming of 8 bytes at address 0x0800E610 performed ok. + Programming of 8 bytes at address 0x0800E618 performed ok. + Programming of 8 bytes at address 0x0800E620 performed ok. + Programming of 8 bytes at address 0x0800E628 performed ok. + Programming of 8 bytes at address 0x0800E630 performed ok. + Programming of 8 bytes at address 0x0800E638 performed ok. + Programming of 8 bytes at address 0x0800E640 performed ok. + Programming of 8 bytes at address 0x0800E648 performed ok. + Programming of 8 bytes at address 0x0800E650 performed ok. + Programming of 8 bytes at address 0x0800E658 performed ok. + Programming of 8 bytes at address 0x0800E660 performed ok. + Programming of 8 bytes at address 0x0800E668 performed ok. + Programming of 8 bytes at address 0x0800E670 performed ok. + Programming of 8 bytes at address 0x0800E678 performed ok. + Programming of 8 bytes at address 0x0800E680 performed ok. + Programming of 8 bytes at address 0x0800E688 performed ok. + Programming of 8 bytes at address 0x0800E690 performed ok. + Programming of 8 bytes at address 0x0800E698 performed ok. +k. +k. + Programming of 8 bytes at address 0x0800E6B0 performed ok. + Programming of 8 bytes at address 0x0800E6B8 performed ok. + Programming of 8 bytes at address 0x0800E6C0 performed ok. + Programming of 8 bytes at address 0x0800E6C8 performed ok. + Programming of 8 bytes at address 0x0800E6D0 performed ok. + Programming of 8 bytes at address 0x0800E6D8 performed ok. + Programming of 8 bytes at address 0x0800E6E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800E700 performed ok. + Programming of 8 bytes at address 0x0800E708 performed ok. + Programming of 8 bytes at address 0x0800E710 performed ok. + Programming of 8 bytes at address 0x0800E718 performed ok. + Programming of 8 bytes at address 0x0800E720 performed ok. + Programming of 8 bytes at address 0x0800E728 performed ok. + Programming of 8 bytes at address 0x0800E730 performed ok. + Programming of 8 bytes at address 0x0800E738 performed ok. + Programming of 8 bytes at address 0x0800E740 performed ok. + Programming of 8 bytes at address 0x0800E748 performed ok. + Programming of 8 bytes at address 0x0800E750 performed ok. + Programming of 8 bytes at address 0x0800E758 performed ok. + Programming of 8 bytes at address 0x0800E760 performed ok. + Programming of 8 bytes at address 0x0800E768 performed ok. + Programming of 8 bytes at address 0x0800E770 performed ok. + Programming of 8 bytes at address 0x0800E778 performed ok. + Programming of 8 bytes at address 0x0800E780 performed ok. + Programming of 8 bytes at address 0x0800E788 performed ok. + Programming of 8 bytes at address 0x0800E790 performed ok. + Programming of 8 bytes at address 0x0800E798 performed ok. +k. +k. + Programming of 8 bytes at address 0x0800E7B0 performed ok. + Programming of 8 bytes at address 0x0800E7B8 performed ok. + Programming of 8 bytes at address 0x0800E7C0 performed ok. + Programming of 8 bytes at address 0x0800E7C8 performed ok. + Programming of 8 bytes at address 0x0800E7D0 performed ok. + Programming of 8 bytes at address 0x0800E7D8 performed ok. + Programming of 8 bytes at address 0x0800E7E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800E800 performed ok. + Programming of 8 bytes at address 0x0800E808 performed ok. + Programming of 8 bytes at address 0x0800E810 performed ok. + Programming of 8 bytes at address 0x0800E818 performed ok. + Programming of 8 bytes at address 0x0800E820 performed ok. + Programming of 8 bytes at address 0x0800E828 performed ok. + Programming of 8 bytes at address 0x0800E830 performed ok. + Programming of 8 bytes at address 0x0800E838 performed ok. + Programming of 8 bytes at address 0x0800E840 performed ok. + Programming of 8 bytes at address 0x0800E848 performed ok. + Programming of 8 bytes at address 0x0800E850 performed ok. + Programming of 8 bytes at address 0x0800E858 performed ok. + Programming of 8 bytes at address 0x0800E860 performed ok. + Programming of 8 bytes at address 0x0800E868 performed ok. + Programming of 8 bytes at address 0x0800E870 performed ok. + Programming of 8 bytes at address 0x0800E878 performed ok. + Programming of 8 bytes at address 0x0800E880 performed ok. + Programming of 8 bytes at address 0x0800E888 performed ok. + Programming of 8 bytes at address 0x0800E890 performed ok. + Programming of 8 bytes at address 0x0800E898 performed ok. +k. + Programming of 8 bytes at address 0x0800E8A8 performed ok. + Programming of 8 bytes at address 0x0800E8B0 performed ok. + Programming of 8 bytes at address 0x0800E8B8 performed ok. + Programming of 8 bytes at address 0x0800E8C0 performed ok. + Programming of 8 bytes at address 0x0800E8C8 performed ok. + Programming of 8 bytes at address 0x0800E8D0 performed ok. + Programming of 8 bytes at address 0x0800E8D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800E900 performed ok. + Programming of 8 bytes at address 0x0800E908 performed ok. + Programming of 8 bytes at address 0x0800E910 performed ok. + Programming of 8 bytes at address 0x0800E918 performed ok. + Programming of 8 bytes at address 0x0800E920 performed ok. + Programming of 8 bytes at address 0x0800E928 performed ok. + Programming of 8 bytes at address 0x0800E930 performed ok. + Programming of 8 bytes at address 0x0800E938 performed ok. + Programming of 8 bytes at address 0x0800E940 performed ok. + Programming of 8 bytes at address 0x0800E948 performed ok. + Programming of 8 bytes at address 0x0800E950 performed ok. + Programming of 8 bytes at address 0x0800E958 performed ok. + Programming of 8 bytes at address 0x0800E960 performed ok. + Programming of 8 bytes at address 0x0800E968 performed ok. + Programming of 8 bytes at address 0x0800E970 performed ok. + Programming of 8 bytes at address 0x0800E978 performed ok. + Programming of 8 bytes at address 0x0800E980 performed ok. + Programming of 8 bytes at address 0x0800E988 performed ok. + Programming of 8 bytes at address 0x0800E990 performed ok. + Programming of 8 bytes at address 0x0800E998 performed ok. + Programming of 8 bytes at address 0x0800E9A0 performed ok. + Programming of 8 bytes at address 0x0800E9A8 performed ok. + Programming of 8 bytes at address 0x0800E9B0 performed ok. + Programming of 8 bytes at address 0x0800E9B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800EA00 performed ok. + Programming of 8 bytes at address 0x0800EA08 performed ok. + Programming of 8 bytes at address 0x0800EA10 performed ok. + Programming of 8 bytes at address 0x0800EA18 performed ok. + Programming of 8 bytes at address 0x0800EA20 performed ok. + Programming of 8 bytes at address 0x0800EA28 performed ok. + Programming of 8 bytes at address 0x0800EA30 performed ok. + Programming of 8 bytes at address 0x0800EA38 performed ok. + Programming of 8 bytes at address 0x0800EA40 performed ok. + Programming of 8 bytes at address 0x0800EA48 performed ok. + Programming of 8 bytes at address 0x0800EA50 performed ok. + Programming of 8 bytes at address 0x0800EA58 performed ok. + Programming of 8 bytes at address 0x0800EA60 performed ok. + Programming of 8 bytes at address 0x0800EA68 performed ok. + Programming of 8 bytes at address 0x0800EA70 performed ok. + Programming of 8 bytes at address 0x0800EA78 performed ok. + Programming of 8 bytes at address 0x0800EA80 performed ok. + Programming of 8 bytes at address 0x0800EA88 performed ok. + Programming of 8 bytes at address 0x0800EA90 performed ok. + Programming of 8 bytes at address 0x0800EA98 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800EAB8 performed ok. + Programming of 8 bytes at address 0x0800EAC0 performed ok. + Programming of 8 bytes at address 0x0800EAC8 performed ok. + Programming of 8 bytes at address 0x0800EAD0 performed ok. + Programming of 8 bytes at address 0x0800EAD8 performed ok. + Programming of 8 bytes at address 0x0800EAE0 performed ok. + Programming of 8 bytes at address 0x0800EAE8 performed ok. + Programming of 8 bytes at address 0x0800EAF0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800EB00 performed ok. + Programming of 8 bytes at address 0x0800EB08 performed ok. + Programming of 8 bytes at address 0x0800EB10 performed ok. + Programming of 8 bytes at address 0x0800EB18 performed ok. + Programming of 8 bytes at address 0x0800EB20 performed ok. + Programming of 8 bytes at address 0x0800EB28 performed ok. + Programming of 8 bytes at address 0x0800EB30 performed ok. + Programming of 8 bytes at address 0x0800EB38 performed ok. + Programming of 8 bytes at address 0x0800EB40 performed ok. + Programming of 8 bytes at address 0x0800EB48 performed ok. + Programming of 8 bytes at address 0x0800EB50 performed ok. + Programming of 8 bytes at address 0x0800EB58 performed ok. + Programming of 8 bytes at address 0x0800EB60 performed ok. + Programming of 8 bytes at address 0x0800EB68 performed ok. + Programming of 8 bytes at address 0x0800EB70 performed ok. + Programming of 8 bytes at address 0x0800EB78 performed ok. + Programming of 8 bytes at address 0x0800EB80 performed ok. + Programming of 8 bytes at address 0x0800EB88 performed ok. + Programming of 8 bytes at address 0x0800EB90 performed ok. + Programming of 8 bytes at address 0x0800EB98 performed ok. + Programming of 8 bytes at address 0x0800EBA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800EBC0 performed ok. + Programming of 8 bytes at address 0x0800EBC8 performed ok. + Programming of 8 bytes at address 0x0800EBD0 performed ok. + Programming of 8 bytes at address 0x0800EBD8 performed ok. + Programming of 8 bytes at address 0x0800EBE0 performed ok. + Programming of 8 bytes at address 0x0800EBE8 performed ok. + Programming of 8 bytes at address 0x0800EBF0 performed ok. + Programming of 8 bytes at address 0x0800EBF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800EC00 performed ok. + Programming of 8 bytes at address 0x0800EC08 performed ok. + Programming of 8 bytes at address 0x0800EC10 performed ok. + Programming of 8 bytes at address 0x0800EC18 performed ok. + Programming of 8 bytes at address 0x0800EC20 performed ok. + Programming of 8 bytes at address 0x0800EC28 performed ok. + Programming of 8 bytes at address 0x0800EC30 performed ok. + Programming of 8 bytes at address 0x0800EC38 performed ok. + Programming of 8 bytes at address 0x0800EC40 performed ok. + Programming of 8 bytes at address 0x0800EC48 performed ok. + Programming of 8 bytes at address 0x0800EC50 performed ok. + Programming of 8 bytes at address 0x0800EC58 performed ok. + Programming of 8 bytes at address 0x0800EC60 performed ok. + Programming of 8 bytes at address 0x0800EC68 performed ok. + Programming of 8 bytes at address 0x0800EC70 performed ok. + Programming of 8 bytes at address 0x0800EC78 performed ok. + Programming of 8 bytes at address 0x0800EC80 performed ok. + Programming of 8 bytes at address 0x0800EC88 performed ok. + Programming of 8 bytes at address 0x0800EC90 performed ok. + Programming of 8 bytes at address 0x0800EC98 performed ok. + Programming of 8 bytes at address 0x0800ECA0 performed ok. + Programming of 8 bytes at address 0x0800ECA8 performed ok. + Programming of 8 bytes at address 0x0800ECB0 performed ok. + Programming of 8 bytes at address 0x0800ECB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800ECF0 performed ok. + Programming of 8 bytes at address 0x0800ECF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800ED00 performed ok. + Programming of 8 bytes at address 0x0800ED08 performed ok. + Programming of 8 bytes at address 0x0800ED10 performed ok. + Programming of 8 bytes at address 0x0800ED18 performed ok. + Programming of 8 bytes at address 0x0800ED20 performed ok. + Programming of 8 bytes at address 0x0800ED28 performed ok. + Programming of 8 bytes at address 0x0800ED30 performed ok. + Programming of 8 bytes at address 0x0800ED38 performed ok. + Programming of 8 bytes at address 0x0800ED40 performed ok. + Programming of 8 bytes at address 0x0800ED48 performed ok. + Programming of 8 bytes at address 0x0800ED50 performed ok. + Programming of 8 bytes at address 0x0800ED58 performed ok. + Programming of 8 bytes at address 0x0800ED60 performed ok. + Programming of 8 bytes at address 0x0800ED68 performed ok. + Programming of 8 bytes at address 0x0800ED70 performed ok. + Programming of 8 bytes at address 0x0800ED78 performed ok. + Programming of 8 bytes at address 0x0800ED80 performed ok. + Programming of 8 bytes at address 0x0800ED88 performed ok. + Programming of 8 bytes at address 0x0800ED90 performed ok. + Programming of 8 bytes at address 0x0800ED98 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800EDB8 performed ok. + Programming of 8 bytes at address 0x0800EDC0 performed ok. + Programming of 8 bytes at address 0x0800EDC8 performed ok. + Programming of 8 bytes at address 0x0800EDD0 performed ok. + Programming of 8 bytes at address 0x0800EDD8 performed ok. + Programming of 8 bytes at address 0x0800EDE0 performed ok. + Programming of 8 bytes at address 0x0800EDE8 performed ok. + Programming of 8 bytes at address 0x0800EDF0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800EE00 performed ok. + Programming of 8 bytes at address 0x0800EE08 performed ok. + Programming of 8 bytes at address 0x0800EE10 performed ok. + Programming of 8 bytes at address 0x0800EE18 performed ok. + Programming of 8 bytes at address 0x0800EE20 performed ok. + Programming of 8 bytes at address 0x0800EE28 performed ok. + Programming of 8 bytes at address 0x0800EE30 performed ok. + Programming of 8 bytes at address 0x0800EE38 performed ok. + Programming of 8 bytes at address 0x0800EE40 performed ok. + Programming of 8 bytes at address 0x0800EE48 performed ok. + Programming of 8 bytes at address 0x0800EE50 performed ok. + Programming of 8 bytes at address 0x0800EE58 performed ok. + Programming of 8 bytes at address 0x0800EE60 performed ok. + Programming of 8 bytes at address 0x0800EE68 performed ok. + Programming of 8 bytes at address 0x0800EE70 performed ok. + Programming of 8 bytes at address 0x0800EE78 performed ok. + Programming of 8 bytes at address 0x0800EE80 performed ok. + Programming of 8 bytes at address 0x0800EE88 performed ok. + Programming of 8 bytes at address 0x0800EE90 performed ok. + Programming of 8 bytes at address 0x0800EE98 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800EEB8 performed ok. + Programming of 8 bytes at address 0x0800EEC0 performed ok. + Programming of 8 bytes at address 0x0800EEC8 performed ok. + Programming of 8 bytes at address 0x0800EED0 performed ok. + Programming of 8 bytes at address 0x0800EED8 performed ok. + Programming of 8 bytes at address 0x0800EEE0 performed ok. + Programming of 8 bytes at address 0x0800EEE8 performed ok. + Programming of 8 bytes at address 0x0800EEF0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800EF00 performed ok. + Programming of 8 bytes at address 0x0800EF08 performed ok. + Programming of 8 bytes at address 0x0800EF10 performed ok. + Programming of 8 bytes at address 0x0800EF18 performed ok. + Programming of 8 bytes at address 0x0800EF20 performed ok. + Programming of 8 bytes at address 0x0800EF28 performed ok. + Programming of 8 bytes at address 0x0800EF30 performed ok. + Programming of 8 bytes at address 0x0800EF38 performed ok. + Programming of 8 bytes at address 0x0800EF40 performed ok. + Programming of 8 bytes at address 0x0800EF48 performed ok. + Programming of 8 bytes at address 0x0800EF50 performed ok. + Programming of 8 bytes at address 0x0800EF58 performed ok. + Programming of 8 bytes at address 0x0800EF60 performed ok. + Programming of 8 bytes at address 0x0800EF68 performed ok. + Programming of 8 bytes at address 0x0800EF70 performed ok. + Programming of 8 bytes at address 0x0800EF78 performed ok. + Programming of 8 bytes at address 0x0800EF80 performed ok. + Programming of 8 bytes at address 0x0800EF88 performed ok. + Programming of 8 bytes at address 0x0800EF90 performed ok. +k. + Programming of 8 bytes at address 0x0800EFA0 performed ok. + Programming of 8 bytes at address 0x0800EFA8 performed ok. + Programming of 8 bytes at address 0x0800EFB0 performed ok. + Programming of 8 bytes at address 0x0800EFB8 performed ok. + Programming of 8 bytes at address 0x0800EFC0 performed ok. + Programming of 8 bytes at address 0x0800EFC8 performed ok. + Programming of 8 bytes at address 0x0800EFD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800F000 performed ok. + Programming of 8 bytes at address 0x0800F008 performed ok. + Programming of 8 bytes at address 0x0800F010 performed ok. + Programming of 8 bytes at address 0x0800F018 performed ok. + Programming of 8 bytes at address 0x0800F020 performed ok. + Programming of 8 bytes at address 0x0800F028 performed ok. + Programming of 8 bytes at address 0x0800F030 performed ok. + Programming of 8 bytes at address 0x0800F038 performed ok. + Programming of 8 bytes at address 0x0800F040 performed ok. + Programming of 8 bytes at address 0x0800F048 performed ok. + Programming of 8 bytes at address 0x0800F050 performed ok. + Programming of 8 bytes at address 0x0800F058 performed ok. + Programming of 8 bytes at address 0x0800F060 performed ok. + Programming of 8 bytes at address 0x0800F068 performed ok. + Programming of 8 bytes at address 0x0800F070 performed ok. + Programming of 8 bytes at address 0x0800F078 performed ok. + Programming of 8 bytes at address 0x0800F080 performed ok. + Programming of 8 bytes at address 0x0800F088 performed ok. + Programming of 8 bytes at address 0x0800F090 performed ok. + Programming of 8 bytes at address 0x0800F098 performed ok. + Programming of 8 bytes at address 0x0800F0A0 performed ok. + Programming of 8 bytes at address 0x0800F0A8 performed ok. + Programming of 8 bytes at address 0x0800F0B0 performed ok. + Programming of 8 bytes at address 0x0800F0B8 performed ok. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800F0E8 performed ok. + Programming of 8 bytes at address 0x0800F0F0 performed ok. + Programming of 8 bytes at address 0x0800F0F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800F100 performed ok. + Programming of 8 bytes at address 0x0800F108 performed ok. + Programming of 8 bytes at address 0x0800F110 performed ok. + Programming of 8 bytes at address 0x0800F118 performed ok. + Programming of 8 bytes at address 0x0800F120 performed ok. + Programming of 8 bytes at address 0x0800F128 performed ok. + Programming of 8 bytes at address 0x0800F130 performed ok. + Programming of 8 bytes at address 0x0800F138 performed ok. + Programming of 8 bytes at address 0x0800F140 performed ok. + Programming of 8 bytes at address 0x0800F148 performed ok. + Programming of 8 bytes at address 0x0800F150 performed ok. + Programming of 8 bytes at address 0x0800F158 performed ok. + Programming of 8 bytes at address 0x0800F160 performed ok. + Programming of 8 bytes at address 0x0800F168 performed ok. + Programming of 8 bytes at address 0x0800F170 performed ok. + Programming of 8 bytes at address 0x0800F178 performed ok. + Programming of 8 bytes at address 0x0800F180 performed ok. + Programming of 8 bytes at address 0x0800F188 performed ok. + Programming of 8 bytes at address 0x0800F190 performed ok. +k. + Programming of 8 bytes at address 0x0800F1A0 performed ok. + Programming of 8 bytes at address 0x0800F1A8 performed ok. + Programming of 8 bytes at address 0x0800F1B0 performed ok. + Programming of 8 bytes at address 0x0800F1B8 performed ok. + Programming of 8 bytes at address 0x0800F1C0 performed ok. + Programming of 8 bytes at address 0x0800F1C8 performed ok. + Programming of 8 bytes at address 0x0800F1D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800F200 performed ok. + Programming of 8 bytes at address 0x0800F208 performed ok. + Programming of 8 bytes at address 0x0800F210 performed ok. + Programming of 8 bytes at address 0x0800F218 performed ok. + Programming of 8 bytes at address 0x0800F220 performed ok. + Programming of 8 bytes at address 0x0800F228 performed ok. + Programming of 8 bytes at address 0x0800F230 performed ok. + Programming of 8 bytes at address 0x0800F238 performed ok. + Programming of 8 bytes at address 0x0800F240 performed ok. + Programming of 8 bytes at address 0x0800F248 performed ok. + Programming of 8 bytes at address 0x0800F250 performed ok. + Programming of 8 bytes at address 0x0800F258 performed ok. + Programming of 8 bytes at address 0x0800F260 performed ok. + Programming of 8 bytes at address 0x0800F268 performed ok. + Programming of 8 bytes at address 0x0800F270 performed ok. + Programming of 8 bytes at address 0x0800F278 performed ok. + Programming of 8 bytes at address 0x0800F280 performed ok. + Programming of 8 bytes at address 0x0800F288 performed ok. + Programming of 8 bytes at address 0x0800F290 performed ok. +k. + Programming of 8 bytes at address 0x0800F2A0 performed ok. + Programming of 8 bytes at address 0x0800F2A8 performed ok. + Programming of 8 bytes at address 0x0800F2B0 performed ok. + Programming of 8 bytes at address 0x0800F2B8 performed ok. + Programming of 8 bytes at address 0x0800F2C0 performed ok. + Programming of 8 bytes at address 0x0800F2C8 performed ok. + Programming of 8 bytes at address 0x0800F2D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800F300 performed ok. + Programming of 8 bytes at address 0x0800F308 performed ok. + Programming of 8 bytes at address 0x0800F310 performed ok. + Programming of 8 bytes at address 0x0800F318 performed ok. + Programming of 8 bytes at address 0x0800F320 performed ok. + Programming of 8 bytes at address 0x0800F328 performed ok. + Programming of 8 bytes at address 0x0800F330 performed ok. + Programming of 8 bytes at address 0x0800F338 performed ok. + Programming of 8 bytes at address 0x0800F340 performed ok. + Programming of 8 bytes at address 0x0800F348 performed ok. + Programming of 8 bytes at address 0x0800F350 performed ok. + Programming of 8 bytes at address 0x0800F358 performed ok. + Programming of 8 bytes at address 0x0800F360 performed ok. + Programming of 8 bytes at address 0x0800F368 performed ok. + Programming of 8 bytes at address 0x0800F370 performed ok. + Programming of 8 bytes at address 0x0800F378 performed ok. + Programming of 8 bytes at address 0x0800F380 performed ok. + Programming of 8 bytes at address 0x0800F388 performed ok. + Programming of 8 bytes at address 0x0800F390 performed ok. + Programming of 8 bytes at address 0x0800F398 performed ok. +k. +k. + Programming of 8 bytes at address 0x0800F3B0 performed ok. + Programming of 8 bytes at address 0x0800F3B8 performed ok. + Programming of 8 bytes at address 0x0800F3C0 performed ok. + Programming of 8 bytes at address 0x0800F3C8 performed ok. + Programming of 8 bytes at address 0x0800F3D0 performed ok. + Programming of 8 bytes at address 0x0800F3D8 performed ok. + Programming of 8 bytes at address 0x0800F3E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800F400 performed ok. + Programming of 8 bytes at address 0x0800F408 performed ok. + Programming of 8 bytes at address 0x0800F410 performed ok. + Programming of 8 bytes at address 0x0800F418 performed ok. + Programming of 8 bytes at address 0x0800F420 performed ok. + Programming of 8 bytes at address 0x0800F428 performed ok. + Programming of 8 bytes at address 0x0800F430 performed ok. + Programming of 8 bytes at address 0x0800F438 performed ok. + Programming of 8 bytes at address 0x0800F440 performed ok. + Programming of 8 bytes at address 0x0800F448 performed ok. + Programming of 8 bytes at address 0x0800F450 performed ok. + Programming of 8 bytes at address 0x0800F458 performed ok. + Programming of 8 bytes at address 0x0800F460 performed ok. + Programming of 8 bytes at address 0x0800F468 performed ok. + Programming of 8 bytes at address 0x0800F470 performed ok. + Programming of 8 bytes at address 0x0800F478 performed ok. + Programming of 8 bytes at address 0x0800F480 performed ok. + Programming of 8 bytes at address 0x0800F488 performed ok. + Programming of 8 bytes at address 0x0800F490 performed ok. +k. + Programming of 8 bytes at address 0x0800F4A0 performed ok. + Programming of 8 bytes at address 0x0800F4A8 performed ok. + Programming of 8 bytes at address 0x0800F4B0 performed ok. + Programming of 8 bytes at address 0x0800F4B8 performed ok. + Programming of 8 bytes at address 0x0800F4C0 performed ok. + Programming of 8 bytes at address 0x0800F4C8 performed ok. + Programming of 8 bytes at address 0x0800F4D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800F500 performed ok. + Programming of 8 bytes at address 0x0800F508 performed ok. + Programming of 8 bytes at address 0x0800F510 performed ok. + Programming of 8 bytes at address 0x0800F518 performed ok. + Programming of 8 bytes at address 0x0800F520 performed ok. + Programming of 8 bytes at address 0x0800F528 performed ok. + Programming of 8 bytes at address 0x0800F530 performed ok. + Programming of 8 bytes at address 0x0800F538 performed ok. + Programming of 8 bytes at address 0x0800F540 performed ok. + Programming of 8 bytes at address 0x0800F548 performed ok. + Programming of 8 bytes at address 0x0800F550 performed ok. + Programming of 8 bytes at address 0x0800F558 performed ok. + Programming of 8 bytes at address 0x0800F560 performed ok. + Programming of 8 bytes at address 0x0800F568 performed ok. + Programming of 8 bytes at address 0x0800F570 performed ok. + Programming of 8 bytes at address 0x0800F578 performed ok. + Programming of 8 bytes at address 0x0800F580 performed ok. + Programming of 8 bytes at address 0x0800F588 performed ok. + Programming of 8 bytes at address 0x0800F590 performed ok. + Programming of 8 bytes at address 0x0800F598 performed ok. +k. + Programming of 8 bytes at address 0x0800F5A8 performed ok. + Programming of 8 bytes at address 0x0800F5B0 performed ok. + Programming of 8 bytes at address 0x0800F5B8 performed ok. + Programming of 8 bytes at address 0x0800F5C0 performed ok. + Programming of 8 bytes at address 0x0800F5C8 performed ok. + Programming of 8 bytes at address 0x0800F5D0 performed ok. + Programming of 8 bytes at address 0x0800F5D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800F600 performed ok. + Programming of 8 bytes at address 0x0800F608 performed ok. + Programming of 8 bytes at address 0x0800F610 performed ok. + Programming of 8 bytes at address 0x0800F618 performed ok. + Programming of 8 bytes at address 0x0800F620 performed ok. + Programming of 8 bytes at address 0x0800F628 performed ok. + Programming of 8 bytes at address 0x0800F630 performed ok. + Programming of 8 bytes at address 0x0800F638 performed ok. + Programming of 8 bytes at address 0x0800F640 performed ok. + Programming of 8 bytes at address 0x0800F648 performed ok. + Programming of 8 bytes at address 0x0800F650 performed ok. + Programming of 8 bytes at address 0x0800F658 performed ok. + Programming of 8 bytes at address 0x0800F660 performed ok. + Programming of 8 bytes at address 0x0800F668 performed ok. + Programming of 8 bytes at address 0x0800F670 performed ok. + Programming of 8 bytes at address 0x0800F678 performed ok. + Programming of 8 bytes at address 0x0800F680 performed ok. + Programming of 8 bytes at address 0x0800F688 performed ok. + Programming of 8 bytes at address 0x0800F690 performed ok. + Programming of 8 bytes at address 0x0800F698 performed ok. +k. +k. + Programming of 8 bytes at address 0x0800F6B0 performed ok. + Programming of 8 bytes at address 0x0800F6B8 performed ok. + Programming of 8 bytes at address 0x0800F6C0 performed ok. + Programming of 8 bytes at address 0x0800F6C8 performed ok. + Programming of 8 bytes at address 0x0800F6D0 performed ok. + Programming of 8 bytes at address 0x0800F6D8 performed ok. + Programming of 8 bytes at address 0x0800F6E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800F700 performed ok. + Programming of 8 bytes at address 0x0800F708 performed ok. + Programming of 8 bytes at address 0x0800F710 performed ok. + Programming of 8 bytes at address 0x0800F718 performed ok. + Programming of 8 bytes at address 0x0800F720 performed ok. + Programming of 8 bytes at address 0x0800F728 performed ok. + Programming of 8 bytes at address 0x0800F730 performed ok. + Programming of 8 bytes at address 0x0800F738 performed ok. + Programming of 8 bytes at address 0x0800F740 performed ok. + Programming of 8 bytes at address 0x0800F748 performed ok. + Programming of 8 bytes at address 0x0800F750 performed ok. + Programming of 8 bytes at address 0x0800F758 performed ok. + Programming of 8 bytes at address 0x0800F760 performed ok. + Programming of 8 bytes at address 0x0800F768 performed ok. + Programming of 8 bytes at address 0x0800F770 performed ok. + Programming of 8 bytes at address 0x0800F778 performed ok. + Programming of 8 bytes at address 0x0800F780 performed ok. + Programming of 8 bytes at address 0x0800F788 performed ok. + Programming of 8 bytes at address 0x0800F790 performed ok. + Programming of 8 bytes at address 0x0800F798 performed ok. +k. + Programming of 8 bytes at address 0x0800F7A8 performed ok. + Programming of 8 bytes at address 0x0800F7B0 performed ok. + Programming of 8 bytes at address 0x0800F7B8 performed ok. + Programming of 8 bytes at address 0x0800F7C0 performed ok. + Programming of 8 bytes at address 0x0800F7C8 performed ok. + Programming of 8 bytes at address 0x0800F7D0 performed ok. + Programming of 8 bytes at address 0x0800F7D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800F800 performed ok. + Programming of 8 bytes at address 0x0800F808 performed ok. + Programming of 8 bytes at address 0x0800F810 performed ok. + Programming of 8 bytes at address 0x0800F818 performed ok. + Programming of 8 bytes at address 0x0800F820 performed ok. + Programming of 8 bytes at address 0x0800F828 performed ok. + Programming of 8 bytes at address 0x0800F830 performed ok. + Programming of 8 bytes at address 0x0800F838 performed ok. + Programming of 8 bytes at address 0x0800F840 performed ok. + Programming of 8 bytes at address 0x0800F848 performed ok. + Programming of 8 bytes at address 0x0800F850 performed ok. + Programming of 8 bytes at address 0x0800F858 performed ok. + Programming of 8 bytes at address 0x0800F860 performed ok. + Programming of 8 bytes at address 0x0800F868 performed ok. + Programming of 8 bytes at address 0x0800F870 performed ok. + Programming of 8 bytes at address 0x0800F878 performed ok. + Programming of 8 bytes at address 0x0800F880 performed ok. + Programming of 8 bytes at address 0x0800F888 performed ok. + Programming of 8 bytes at address 0x0800F890 performed ok. + Programming of 8 bytes at address 0x0800F898 performed ok. + Programming of 8 bytes at address 0x0800F8A0 performed ok. + Programming of 8 bytes at address 0x0800F8A8 performed ok. + Programming of 8 bytes at address 0x0800F8B0 performed ok. + Programming of 8 bytes at address 0x0800F8B8 performed ok. + Programming of 8 bytes at address 0x0800F8C0 performed ok. + Programming of 8 bytes at address 0x0800F8C8 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800F900 performed ok. + Programming of 8 bytes at address 0x0800F908 performed ok. + Programming of 8 bytes at address 0x0800F910 performed ok. + Programming of 8 bytes at address 0x0800F918 performed ok. + Programming of 8 bytes at address 0x0800F920 performed ok. + Programming of 8 bytes at address 0x0800F928 performed ok. + Programming of 8 bytes at address 0x0800F930 performed ok. + Programming of 8 bytes at address 0x0800F938 performed ok. + Programming of 8 bytes at address 0x0800F940 performed ok. + Programming of 8 bytes at address 0x0800F948 performed ok. + Programming of 8 bytes at address 0x0800F950 performed ok. + Programming of 8 bytes at address 0x0800F958 performed ok. + Programming of 8 bytes at address 0x0800F960 performed ok. + Programming of 8 bytes at address 0x0800F968 performed ok. + Programming of 8 bytes at address 0x0800F970 performed ok. + Programming of 8 bytes at address 0x0800F978 performed ok. + Programming of 8 bytes at address 0x0800F980 performed ok. + Programming of 8 bytes at address 0x0800F988 performed ok. + Programming of 8 bytes at address 0x0800F990 performed ok. + Programming of 8 bytes at address 0x0800F998 performed ok. + Programming of 8 bytes at address 0x0800F9A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0800F9C0 performed ok. + Programming of 8 bytes at address 0x0800F9C8 performed ok. + Programming of 8 bytes at address 0x0800F9D0 performed ok. + Programming of 8 bytes at address 0x0800F9D8 performed ok. + Programming of 8 bytes at address 0x0800F9E0 performed ok. + Programming of 8 bytes at address 0x0800F9E8 performed ok. + Programming of 8 bytes at address 0x0800F9F0 performed ok. + Programming of 8 bytes at address 0x0800F9F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800FA00 performed ok. + Programming of 8 bytes at address 0x0800FA08 performed ok. + Programming of 8 bytes at address 0x0800FA10 performed ok. + Programming of 8 bytes at address 0x0800FA18 performed ok. + Programming of 8 bytes at address 0x0800FA20 performed ok. + Programming of 8 bytes at address 0x0800FA28 performed ok. + Programming of 8 bytes at address 0x0800FA30 performed ok. + Programming of 8 bytes at address 0x0800FA38 performed ok. + Programming of 8 bytes at address 0x0800FA40 performed ok. + Programming of 8 bytes at address 0x0800FA48 performed ok. + Programming of 8 bytes at address 0x0800FA50 performed ok. + Programming of 8 bytes at address 0x0800FA58 performed ok. + Programming of 8 bytes at address 0x0800FA60 performed ok. + Programming of 8 bytes at address 0x0800FA68 performed ok. + Programming of 8 bytes at address 0x0800FA70 performed ok. + Programming of 8 bytes at address 0x0800FA78 performed ok. + Programming of 8 bytes at address 0x0800FA80 performed ok. + Programming of 8 bytes at address 0x0800FA88 performed ok. + Programming of 8 bytes at address 0x0800FA90 performed ok. + Programming of 8 bytes at address 0x0800FA98 performed ok. + Programming of 8 bytes at address 0x0800FAA0 performed ok. + Programming of 8 bytes at address 0x0800FAA8 performed ok. + Programming of 8 bytes at address 0x0800FAB0 performed ok. + Programming of 8 bytes at address 0x0800FAB8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800FB00 performed ok. + Programming of 8 bytes at address 0x0800FB08 performed ok. + Programming of 8 bytes at address 0x0800FB10 performed ok. + Programming of 8 bytes at address 0x0800FB18 performed ok. + Programming of 8 bytes at address 0x0800FB20 performed ok. + Programming of 8 bytes at address 0x0800FB28 performed ok. + Programming of 8 bytes at address 0x0800FB30 performed ok. + Programming of 8 bytes at address 0x0800FB38 performed ok. + Programming of 8 bytes at address 0x0800FB40 performed ok. + Programming of 8 bytes at address 0x0800FB48 performed ok. + Programming of 8 bytes at address 0x0800FB50 performed ok. + Programming of 8 bytes at address 0x0800FB58 performed ok. + Programming of 8 bytes at address 0x0800FB60 performed ok. + Programming of 8 bytes at address 0x0800FB68 performed ok. + Programming of 8 bytes at address 0x0800FB70 performed ok. + Programming of 8 bytes at address 0x0800FB78 performed ok. + Programming of 8 bytes at address 0x0800FB80 performed ok. + Programming of 8 bytes at address 0x0800FB88 performed ok. + Programming of 8 bytes at address 0x0800FB90 performed ok. +k. + Programming of 8 bytes at address 0x0800FBA0 performed ok. + Programming of 8 bytes at address 0x0800FBA8 performed ok. + Programming of 8 bytes at address 0x0800FBB0 performed ok. + Programming of 8 bytes at address 0x0800FBB8 performed ok. + Programming of 8 bytes at address 0x0800FBC0 performed ok. + Programming of 8 bytes at address 0x0800FBC8 performed ok. + Programming of 8 bytes at address 0x0800FBD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800FC00 performed ok. + Programming of 8 bytes at address 0x0800FC08 performed ok. + Programming of 8 bytes at address 0x0800FC10 performed ok. + Programming of 8 bytes at address 0x0800FC18 performed ok. + Programming of 8 bytes at address 0x0800FC20 performed ok. + Programming of 8 bytes at address 0x0800FC28 performed ok. + Programming of 8 bytes at address 0x0800FC30 performed ok. + Programming of 8 bytes at address 0x0800FC38 performed ok. + Programming of 8 bytes at address 0x0800FC40 performed ok. + Programming of 8 bytes at address 0x0800FC48 performed ok. + Programming of 8 bytes at address 0x0800FC50 performed ok. + Programming of 8 bytes at address 0x0800FC58 performed ok. + Programming of 8 bytes at address 0x0800FC60 performed ok. + Programming of 8 bytes at address 0x0800FC68 performed ok. + Programming of 8 bytes at address 0x0800FC70 performed ok. + Programming of 8 bytes at address 0x0800FC78 performed ok. + Programming of 8 bytes at address 0x0800FC80 performed ok. + Programming of 8 bytes at address 0x0800FC88 performed ok. + Programming of 8 bytes at address 0x0800FC90 performed ok. + Programming of 8 bytes at address 0x0800FC98 performed ok. + Programming of 8 bytes at address 0x0800FCA0 performed ok. + Programming of 8 bytes at address 0x0800FCA8 performed ok. + Programming of 8 bytes at address 0x0800FCB0 performed ok. + Programming of 8 bytes at address 0x0800FCB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800FCF0 performed ok. + Programming of 8 bytes at address 0x0800FCF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800FD00 performed ok. + Programming of 8 bytes at address 0x0800FD08 performed ok. + Programming of 8 bytes at address 0x0800FD10 performed ok. + Programming of 8 bytes at address 0x0800FD18 performed ok. + Programming of 8 bytes at address 0x0800FD20 performed ok. + Programming of 8 bytes at address 0x0800FD28 performed ok. + Programming of 8 bytes at address 0x0800FD30 performed ok. + Programming of 8 bytes at address 0x0800FD38 performed ok. + Programming of 8 bytes at address 0x0800FD40 performed ok. + Programming of 8 bytes at address 0x0800FD48 performed ok. + Programming of 8 bytes at address 0x0800FD50 performed ok. + Programming of 8 bytes at address 0x0800FD58 performed ok. + Programming of 8 bytes at address 0x0800FD60 performed ok. + Programming of 8 bytes at address 0x0800FD68 performed ok. + Programming of 8 bytes at address 0x0800FD70 performed ok. + Programming of 8 bytes at address 0x0800FD78 performed ok. + Programming of 8 bytes at address 0x0800FD80 performed ok. + Programming of 8 bytes at address 0x0800FD88 performed ok. + Programming of 8 bytes at address 0x0800FD90 performed ok. + Programming of 8 bytes at address 0x0800FD98 performed ok. + Programming of 8 bytes at address 0x0800FDA0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800FDC8 performed ok. + Programming of 8 bytes at address 0x0800FDD0 performed ok. + Programming of 8 bytes at address 0x0800FDD8 performed ok. + Programming of 8 bytes at address 0x0800FDE0 performed ok. + Programming of 8 bytes at address 0x0800FDE8 performed ok. + Programming of 8 bytes at address 0x0800FDF0 performed ok. + Programming of 8 bytes at address 0x0800FDF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800FE00 performed ok. + Programming of 8 bytes at address 0x0800FE08 performed ok. + Programming of 8 bytes at address 0x0800FE10 performed ok. + Programming of 8 bytes at address 0x0800FE18 performed ok. + Programming of 8 bytes at address 0x0800FE20 performed ok. + Programming of 8 bytes at address 0x0800FE28 performed ok. + Programming of 8 bytes at address 0x0800FE30 performed ok. + Programming of 8 bytes at address 0x0800FE38 performed ok. + Programming of 8 bytes at address 0x0800FE40 performed ok. + Programming of 8 bytes at address 0x0800FE48 performed ok. + Programming of 8 bytes at address 0x0800FE50 performed ok. + Programming of 8 bytes at address 0x0800FE58 performed ok. + Programming of 8 bytes at address 0x0800FE60 performed ok. + Programming of 8 bytes at address 0x0800FE68 performed ok. + Programming of 8 bytes at address 0x0800FE70 performed ok. + Programming of 8 bytes at address 0x0800FE78 performed ok. + Programming of 8 bytes at address 0x0800FE80 performed ok. + Programming of 8 bytes at address 0x0800FE88 performed ok. + Programming of 8 bytes at address 0x0800FE90 performed ok. + Programming of 8 bytes at address 0x0800FE98 performed ok. + Programming of 8 bytes at address 0x0800FEA0 performed ok. + Programming of 8 bytes at address 0x0800FEA8 performed ok. + Programming of 8 bytes at address 0x0800FEB0 performed ok. + Programming of 8 bytes at address 0x0800FEB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0800FEF0 performed ok. + Programming of 8 bytes at address 0x0800FEF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0800FF00 performed ok. + Programming of 8 bytes at address 0x0800FF08 performed ok. + Programming of 8 bytes at address 0x0800FF10 performed ok. + Programming of 8 bytes at address 0x0800FF18 performed ok. + Programming of 8 bytes at address 0x0800FF20 performed ok. + Programming of 8 bytes at address 0x0800FF28 performed ok. + Programming of 8 bytes at address 0x0800FF30 performed ok. + Programming of 8 bytes at address 0x0800FF38 performed ok. + Programming of 8 bytes at address 0x0800FF40 performed ok. + Programming of 8 bytes at address 0x0800FF48 performed ok. + Programming of 8 bytes at address 0x0800FF50 performed ok. + Programming of 8 bytes at address 0x0800FF58 performed ok. + Programming of 8 bytes at address 0x0800FF60 performed ok. + Programming of 8 bytes at address 0x0800FF68 performed ok. + Programming of 8 bytes at address 0x0800FF70 performed ok. + Programming of 8 bytes at address 0x0800FF78 performed ok. + Programming of 8 bytes at address 0x0800FF80 performed ok. + Programming of 8 bytes at address 0x0800FF88 performed ok. + Programming of 8 bytes at address 0x0800FF90 performed ok. +k. + Programming of 8 bytes at address 0x0800FFA0 performed ok. + Programming of 8 bytes at address 0x0800FFA8 performed ok. + Programming of 8 bytes at address 0x0800FFB0 performed ok. + Programming of 8 bytes at address 0x0800FFB8 performed ok. + Programming of 8 bytes at address 0x0800FFC0 performed ok. + Programming of 8 bytes at address 0x0800FFC8 performed ok. + Programming of 8 bytes at address 0x0800FFD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010000 performed ok. + Programming of 8 bytes at address 0x08010008 performed ok. + Programming of 8 bytes at address 0x08010010 performed ok. + Programming of 8 bytes at address 0x08010018 performed ok. + Programming of 8 bytes at address 0x08010020 performed ok. + Programming of 8 bytes at address 0x08010028 performed ok. + Programming of 8 bytes at address 0x08010030 performed ok. + Programming of 8 bytes at address 0x08010038 performed ok. + Programming of 8 bytes at address 0x08010040 performed ok. + Programming of 8 bytes at address 0x08010048 performed ok. + Programming of 8 bytes at address 0x08010050 performed ok. + Programming of 8 bytes at address 0x08010058 performed ok. + Programming of 8 bytes at address 0x08010060 performed ok. + Programming of 8 bytes at address 0x08010068 performed ok. + Programming of 8 bytes at address 0x08010070 performed ok. + Programming of 8 bytes at address 0x08010078 performed ok. + Programming of 8 bytes at address 0x08010080 performed ok. + Programming of 8 bytes at address 0x08010088 performed ok. + Programming of 8 bytes at address 0x08010090 performed ok. +k. + Programming of 8 bytes at address 0x080100A0 performed ok. + Programming of 8 bytes at address 0x080100A8 performed ok. + Programming of 8 bytes at address 0x080100B0 performed ok. + Programming of 8 bytes at address 0x080100B8 performed ok. + Programming of 8 bytes at address 0x080100C0 performed ok. + Programming of 8 bytes at address 0x080100C8 performed ok. + Programming of 8 bytes at address 0x080100D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010100 performed ok. + Programming of 8 bytes at address 0x08010108 performed ok. + Programming of 8 bytes at address 0x08010110 performed ok. + Programming of 8 bytes at address 0x08010118 performed ok. + Programming of 8 bytes at address 0x08010120 performed ok. + Programming of 8 bytes at address 0x08010128 performed ok. + Programming of 8 bytes at address 0x08010130 performed ok. + Programming of 8 bytes at address 0x08010138 performed ok. + Programming of 8 bytes at address 0x08010140 performed ok. + Programming of 8 bytes at address 0x08010148 performed ok. + Programming of 8 bytes at address 0x08010150 performed ok. + Programming of 8 bytes at address 0x08010158 performed ok. + Programming of 8 bytes at address 0x08010160 performed ok. + Programming of 8 bytes at address 0x08010168 performed ok. + Programming of 8 bytes at address 0x08010170 performed ok. + Programming of 8 bytes at address 0x08010178 performed ok. + Programming of 8 bytes at address 0x08010180 performed ok. + Programming of 8 bytes at address 0x08010188 performed ok. + Programming of 8 bytes at address 0x08010190 performed ok. + Programming of 8 bytes at address 0x08010198 performed ok. + Programming of 8 bytes at address 0x080101A0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080101C8 performed ok. + Programming of 8 bytes at address 0x080101D0 performed ok. + Programming of 8 bytes at address 0x080101D8 performed ok. + Programming of 8 bytes at address 0x080101E0 performed ok. + Programming of 8 bytes at address 0x080101E8 performed ok. + Programming of 8 bytes at address 0x080101F0 performed ok. + Programming of 8 bytes at address 0x080101F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010200 performed ok. + Programming of 8 bytes at address 0x08010208 performed ok. + Programming of 8 bytes at address 0x08010210 performed ok. + Programming of 8 bytes at address 0x08010218 performed ok. + Programming of 8 bytes at address 0x08010220 performed ok. + Programming of 8 bytes at address 0x08010228 performed ok. + Programming of 8 bytes at address 0x08010230 performed ok. + Programming of 8 bytes at address 0x08010238 performed ok. + Programming of 8 bytes at address 0x08010240 performed ok. + Programming of 8 bytes at address 0x08010248 performed ok. + Programming of 8 bytes at address 0x08010250 performed ok. + Programming of 8 bytes at address 0x08010258 performed ok. + Programming of 8 bytes at address 0x08010260 performed ok. + Programming of 8 bytes at address 0x08010268 performed ok. + Programming of 8 bytes at address 0x08010270 performed ok. + Programming of 8 bytes at address 0x08010278 performed ok. + Programming of 8 bytes at address 0x08010280 performed ok. + Programming of 8 bytes at address 0x08010288 performed ok. + Programming of 8 bytes at address 0x08010290 performed ok. + Programming of 8 bytes at address 0x08010298 performed ok. +k. + Programming of 8 bytes at address 0x080102A8 performed ok. + Programming of 8 bytes at address 0x080102B0 performed ok. + Programming of 8 bytes at address 0x080102B8 performed ok. + Programming of 8 bytes at address 0x080102C0 performed ok. + Programming of 8 bytes at address 0x080102C8 performed ok. + Programming of 8 bytes at address 0x080102D0 performed ok. + Programming of 8 bytes at address 0x080102D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010300 performed ok. + Programming of 8 bytes at address 0x08010308 performed ok. + Programming of 8 bytes at address 0x08010310 performed ok. + Programming of 8 bytes at address 0x08010318 performed ok. + Programming of 8 bytes at address 0x08010320 performed ok. + Programming of 8 bytes at address 0x08010328 performed ok. + Programming of 8 bytes at address 0x08010330 performed ok. + Programming of 8 bytes at address 0x08010338 performed ok. + Programming of 8 bytes at address 0x08010340 performed ok. + Programming of 8 bytes at address 0x08010348 performed ok. + Programming of 8 bytes at address 0x08010350 performed ok. + Programming of 8 bytes at address 0x08010358 performed ok. + Programming of 8 bytes at address 0x08010360 performed ok. + Programming of 8 bytes at address 0x08010368 performed ok. + Programming of 8 bytes at address 0x08010370 performed ok. + Programming of 8 bytes at address 0x08010378 performed ok. + Programming of 8 bytes at address 0x08010380 performed ok. + Programming of 8 bytes at address 0x08010388 performed ok. + Programming of 8 bytes at address 0x08010390 performed ok. + Programming of 8 bytes at address 0x08010398 performed ok. +k. + Programming of 8 bytes at address 0x080103A8 performed ok. + Programming of 8 bytes at address 0x080103B0 performed ok. + Programming of 8 bytes at address 0x080103B8 performed ok. + Programming of 8 bytes at address 0x080103C0 performed ok. + Programming of 8 bytes at address 0x080103C8 performed ok. + Programming of 8 bytes at address 0x080103D0 performed ok. + Programming of 8 bytes at address 0x080103D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010400 performed ok. + Programming of 8 bytes at address 0x08010408 performed ok. + Programming of 8 bytes at address 0x08010410 performed ok. + Programming of 8 bytes at address 0x08010418 performed ok. + Programming of 8 bytes at address 0x08010420 performed ok. + Programming of 8 bytes at address 0x08010428 performed ok. + Programming of 8 bytes at address 0x08010430 performed ok. + Programming of 8 bytes at address 0x08010438 performed ok. + Programming of 8 bytes at address 0x08010440 performed ok. + Programming of 8 bytes at address 0x08010448 performed ok. + Programming of 8 bytes at address 0x08010450 performed ok. + Programming of 8 bytes at address 0x08010458 performed ok. + Programming of 8 bytes at address 0x08010460 performed ok. + Programming of 8 bytes at address 0x08010468 performed ok. + Programming of 8 bytes at address 0x08010470 performed ok. + Programming of 8 bytes at address 0x08010478 performed ok. + Programming of 8 bytes at address 0x08010480 performed ok. + Programming of 8 bytes at address 0x08010488 performed ok. + Programming of 8 bytes at address 0x08010490 performed ok. + Programming of 8 bytes at address 0x08010498 performed ok. + Programming of 8 bytes at address 0x080104A0 performed ok. + Programming of 8 bytes at address 0x080104A8 performed ok. + Programming of 8 bytes at address 0x080104B0 performed ok. + Programming of 8 bytes at address 0x080104B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080104F0 performed ok. + Programming of 8 bytes at address 0x080104F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010500 performed ok. + Programming of 8 bytes at address 0x08010508 performed ok. + Programming of 8 bytes at address 0x08010510 performed ok. + Programming of 8 bytes at address 0x08010518 performed ok. + Programming of 8 bytes at address 0x08010520 performed ok. + Programming of 8 bytes at address 0x08010528 performed ok. + Programming of 8 bytes at address 0x08010530 performed ok. + Programming of 8 bytes at address 0x08010538 performed ok. + Programming of 8 bytes at address 0x08010540 performed ok. + Programming of 8 bytes at address 0x08010548 performed ok. + Programming of 8 bytes at address 0x08010550 performed ok. + Programming of 8 bytes at address 0x08010558 performed ok. + Programming of 8 bytes at address 0x08010560 performed ok. + Programming of 8 bytes at address 0x08010568 performed ok. + Programming of 8 bytes at address 0x08010570 performed ok. + Programming of 8 bytes at address 0x08010578 performed ok. + Programming of 8 bytes at address 0x08010580 performed ok. + Programming of 8 bytes at address 0x08010588 performed ok. + Programming of 8 bytes at address 0x08010590 performed ok. +k. + Programming of 8 bytes at address 0x080105A0 performed ok. + Programming of 8 bytes at address 0x080105A8 performed ok. + Programming of 8 bytes at address 0x080105B0 performed ok. + Programming of 8 bytes at address 0x080105B8 performed ok. + Programming of 8 bytes at address 0x080105C0 performed ok. + Programming of 8 bytes at address 0x080105C8 performed ok. + Programming of 8 bytes at address 0x080105D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010600 performed ok. + Programming of 8 bytes at address 0x08010608 performed ok. + Programming of 8 bytes at address 0x08010610 performed ok. + Programming of 8 bytes at address 0x08010618 performed ok. + Programming of 8 bytes at address 0x08010620 performed ok. + Programming of 8 bytes at address 0x08010628 performed ok. + Programming of 8 bytes at address 0x08010630 performed ok. + Programming of 8 bytes at address 0x08010638 performed ok. + Programming of 8 bytes at address 0x08010640 performed ok. + Programming of 8 bytes at address 0x08010648 performed ok. + Programming of 8 bytes at address 0x08010650 performed ok. + Programming of 8 bytes at address 0x08010658 performed ok. + Programming of 8 bytes at address 0x08010660 performed ok. + Programming of 8 bytes at address 0x08010668 performed ok. + Programming of 8 bytes at address 0x08010670 performed ok. + Programming of 8 bytes at address 0x08010678 performed ok. + Programming of 8 bytes at address 0x08010680 performed ok. + Programming of 8 bytes at address 0x08010688 performed ok. + Programming of 8 bytes at address 0x08010690 performed ok. + Programming of 8 bytes at address 0x08010698 performed ok. + Programming of 8 bytes at address 0x080106A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080106C0 performed ok. + Programming of 8 bytes at address 0x080106C8 performed ok. + Programming of 8 bytes at address 0x080106D0 performed ok. + Programming of 8 bytes at address 0x080106D8 performed ok. + Programming of 8 bytes at address 0x080106E0 performed ok. + Programming of 8 bytes at address 0x080106E8 performed ok. + Programming of 8 bytes at address 0x080106F0 performed ok. + Programming of 8 bytes at address 0x080106F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010700 performed ok. + Programming of 8 bytes at address 0x08010708 performed ok. + Programming of 8 bytes at address 0x08010710 performed ok. + Programming of 8 bytes at address 0x08010718 performed ok. + Programming of 8 bytes at address 0x08010720 performed ok. + Programming of 8 bytes at address 0x08010728 performed ok. + Programming of 8 bytes at address 0x08010730 performed ok. + Programming of 8 bytes at address 0x08010738 performed ok. + Programming of 8 bytes at address 0x08010740 performed ok. + Programming of 8 bytes at address 0x08010748 performed ok. + Programming of 8 bytes at address 0x08010750 performed ok. + Programming of 8 bytes at address 0x08010758 performed ok. + Programming of 8 bytes at address 0x08010760 performed ok. + Programming of 8 bytes at address 0x08010768 performed ok. + Programming of 8 bytes at address 0x08010770 performed ok. + Programming of 8 bytes at address 0x08010778 performed ok. + Programming of 8 bytes at address 0x08010780 performed ok. + Programming of 8 bytes at address 0x08010788 performed ok. + Programming of 8 bytes at address 0x08010790 performed ok. + Programming of 8 bytes at address 0x08010798 performed ok. +k. + Programming of 8 bytes at address 0x080107A8 performed ok. + Programming of 8 bytes at address 0x080107B0 performed ok. + Programming of 8 bytes at address 0x080107B8 performed ok. + Programming of 8 bytes at address 0x080107C0 performed ok. + Programming of 8 bytes at address 0x080107C8 performed ok. + Programming of 8 bytes at address 0x080107D0 performed ok. + Programming of 8 bytes at address 0x080107D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010800 performed ok. + Programming of 8 bytes at address 0x08010808 performed ok. + Programming of 8 bytes at address 0x08010810 performed ok. + Programming of 8 bytes at address 0x08010818 performed ok. + Programming of 8 bytes at address 0x08010820 performed ok. + Programming of 8 bytes at address 0x08010828 performed ok. + Programming of 8 bytes at address 0x08010830 performed ok. + Programming of 8 bytes at address 0x08010838 performed ok. + Programming of 8 bytes at address 0x08010840 performed ok. + Programming of 8 bytes at address 0x08010848 performed ok. + Programming of 8 bytes at address 0x08010850 performed ok. + Programming of 8 bytes at address 0x08010858 performed ok. + Programming of 8 bytes at address 0x08010860 performed ok. + Programming of 8 bytes at address 0x08010868 performed ok. + Programming of 8 bytes at address 0x08010870 performed ok. + Programming of 8 bytes at address 0x08010878 performed ok. + Programming of 8 bytes at address 0x08010880 performed ok. + Programming of 8 bytes at address 0x08010888 performed ok. + Programming of 8 bytes at address 0x08010890 performed ok. +k. + Programming of 8 bytes at address 0x080108A0 performed ok. + Programming of 8 bytes at address 0x080108A8 performed ok. + Programming of 8 bytes at address 0x080108B0 performed ok. + Programming of 8 bytes at address 0x080108B8 performed ok. + Programming of 8 bytes at address 0x080108C0 performed ok. + Programming of 8 bytes at address 0x080108C8 performed ok. + Programming of 8 bytes at address 0x080108D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010900 performed ok. + Programming of 8 bytes at address 0x08010908 performed ok. + Programming of 8 bytes at address 0x08010910 performed ok. + Programming of 8 bytes at address 0x08010918 performed ok. + Programming of 8 bytes at address 0x08010920 performed ok. + Programming of 8 bytes at address 0x08010928 performed ok. + Programming of 8 bytes at address 0x08010930 performed ok. + Programming of 8 bytes at address 0x08010938 performed ok. + Programming of 8 bytes at address 0x08010940 performed ok. + Programming of 8 bytes at address 0x08010948 performed ok. + Programming of 8 bytes at address 0x08010950 performed ok. + Programming of 8 bytes at address 0x08010958 performed ok. + Programming of 8 bytes at address 0x08010960 performed ok. + Programming of 8 bytes at address 0x08010968 performed ok. + Programming of 8 bytes at address 0x08010970 performed ok. + Programming of 8 bytes at address 0x08010978 performed ok. + Programming of 8 bytes at address 0x08010980 performed ok. + Programming of 8 bytes at address 0x08010988 performed ok. + Programming of 8 bytes at address 0x08010990 performed ok. + Programming of 8 bytes at address 0x08010998 performed ok. + Programming of 8 bytes at address 0x080109A0 performed ok. + Programming of 8 bytes at address 0x080109A8 performed ok. + Programming of 8 bytes at address 0x080109B0 performed ok. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080109E0 performed ok. + Programming of 8 bytes at address 0x080109E8 performed ok. + Programming of 8 bytes at address 0x080109F0 performed ok. + Programming of 8 bytes at address 0x080109F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010A00 performed ok. + Programming of 8 bytes at address 0x08010A08 performed ok. + Programming of 8 bytes at address 0x08010A10 performed ok. + Programming of 8 bytes at address 0x08010A18 performed ok. + Programming of 8 bytes at address 0x08010A20 performed ok. + Programming of 8 bytes at address 0x08010A28 performed ok. + Programming of 8 bytes at address 0x08010A30 performed ok. + Programming of 8 bytes at address 0x08010A38 performed ok. + Programming of 8 bytes at address 0x08010A40 performed ok. + Programming of 8 bytes at address 0x08010A48 performed ok. + Programming of 8 bytes at address 0x08010A50 performed ok. + Programming of 8 bytes at address 0x08010A58 performed ok. + Programming of 8 bytes at address 0x08010A60 performed ok. + Programming of 8 bytes at address 0x08010A68 performed ok. + Programming of 8 bytes at address 0x08010A70 performed ok. + Programming of 8 bytes at address 0x08010A78 performed ok. + Programming of 8 bytes at address 0x08010A80 performed ok. + Programming of 8 bytes at address 0x08010A88 performed ok. + Programming of 8 bytes at address 0x08010A90 performed ok. + Programming of 8 bytes at address 0x08010A98 performed ok. + Programming of 8 bytes at address 0x08010AA0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08010AC8 performed ok. + Programming of 8 bytes at address 0x08010AD0 performed ok. + Programming of 8 bytes at address 0x08010AD8 performed ok. + Programming of 8 bytes at address 0x08010AE0 performed ok. + Programming of 8 bytes at address 0x08010AE8 performed ok. + Programming of 8 bytes at address 0x08010AF0 performed ok. + Programming of 8 bytes at address 0x08010AF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010B00 performed ok. + Programming of 8 bytes at address 0x08010B08 performed ok. + Programming of 8 bytes at address 0x08010B10 performed ok. + Programming of 8 bytes at address 0x08010B18 performed ok. + Programming of 8 bytes at address 0x08010B20 performed ok. + Programming of 8 bytes at address 0x08010B28 performed ok. + Programming of 8 bytes at address 0x08010B30 performed ok. + Programming of 8 bytes at address 0x08010B38 performed ok. + Programming of 8 bytes at address 0x08010B40 performed ok. + Programming of 8 bytes at address 0x08010B48 performed ok. + Programming of 8 bytes at address 0x08010B50 performed ok. + Programming of 8 bytes at address 0x08010B58 performed ok. + Programming of 8 bytes at address 0x08010B60 performed ok. + Programming of 8 bytes at address 0x08010B68 performed ok. + Programming of 8 bytes at address 0x08010B70 performed ok. + Programming of 8 bytes at address 0x08010B78 performed ok. + Programming of 8 bytes at address 0x08010B80 performed ok. + Programming of 8 bytes at address 0x08010B88 performed ok. + Programming of 8 bytes at address 0x08010B90 performed ok. + Programming of 8 bytes at address 0x08010B98 performed ok. + Programming of 8 bytes at address 0x08010BA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08010BC0 performed ok. + Programming of 8 bytes at address 0x08010BC8 performed ok. + Programming of 8 bytes at address 0x08010BD0 performed ok. + Programming of 8 bytes at address 0x08010BD8 performed ok. + Programming of 8 bytes at address 0x08010BE0 performed ok. + Programming of 8 bytes at address 0x08010BE8 performed ok. + Programming of 8 bytes at address 0x08010BF0 performed ok. + Programming of 8 bytes at address 0x08010BF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010C00 performed ok. + Programming of 8 bytes at address 0x08010C08 performed ok. + Programming of 8 bytes at address 0x08010C10 performed ok. + Programming of 8 bytes at address 0x08010C18 performed ok. + Programming of 8 bytes at address 0x08010C20 performed ok. + Programming of 8 bytes at address 0x08010C28 performed ok. + Programming of 8 bytes at address 0x08010C30 performed ok. + Programming of 8 bytes at address 0x08010C38 performed ok. + Programming of 8 bytes at address 0x08010C40 performed ok. + Programming of 8 bytes at address 0x08010C48 performed ok. + Programming of 8 bytes at address 0x08010C50 performed ok. + Programming of 8 bytes at address 0x08010C58 performed ok. + Programming of 8 bytes at address 0x08010C60 performed ok. + Programming of 8 bytes at address 0x08010C68 performed ok. + Programming of 8 bytes at address 0x08010C70 performed ok. + Programming of 8 bytes at address 0x08010C78 performed ok. + Programming of 8 bytes at address 0x08010C80 performed ok. + Programming of 8 bytes at address 0x08010C88 performed ok. + Programming of 8 bytes at address 0x08010C90 performed ok. + Programming of 8 bytes at address 0x08010C98 performed ok. + Programming of 8 bytes at address 0x08010CA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08010CC0 performed ok. + Programming of 8 bytes at address 0x08010CC8 performed ok. + Programming of 8 bytes at address 0x08010CD0 performed ok. + Programming of 8 bytes at address 0x08010CD8 performed ok. + Programming of 8 bytes at address 0x08010CE0 performed ok. + Programming of 8 bytes at address 0x08010CE8 performed ok. + Programming of 8 bytes at address 0x08010CF0 performed ok. + Programming of 8 bytes at address 0x08010CF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010D00 performed ok. + Programming of 8 bytes at address 0x08010D08 performed ok. + Programming of 8 bytes at address 0x08010D10 performed ok. + Programming of 8 bytes at address 0x08010D18 performed ok. + Programming of 8 bytes at address 0x08010D20 performed ok. + Programming of 8 bytes at address 0x08010D28 performed ok. + Programming of 8 bytes at address 0x08010D30 performed ok. + Programming of 8 bytes at address 0x08010D38 performed ok. + Programming of 8 bytes at address 0x08010D40 performed ok. + Programming of 8 bytes at address 0x08010D48 performed ok. + Programming of 8 bytes at address 0x08010D50 performed ok. + Programming of 8 bytes at address 0x08010D58 performed ok. + Programming of 8 bytes at address 0x08010D60 performed ok. + Programming of 8 bytes at address 0x08010D68 performed ok. + Programming of 8 bytes at address 0x08010D70 performed ok. + Programming of 8 bytes at address 0x08010D78 performed ok. + Programming of 8 bytes at address 0x08010D80 performed ok. + Programming of 8 bytes at address 0x08010D88 performed ok. + Programming of 8 bytes at address 0x08010D90 performed ok. +k. + Programming of 8 bytes at address 0x08010DA0 performed ok. + Programming of 8 bytes at address 0x08010DA8 performed ok. + Programming of 8 bytes at address 0x08010DB0 performed ok. + Programming of 8 bytes at address 0x08010DB8 performed ok. + Programming of 8 bytes at address 0x08010DC0 performed ok. + Programming of 8 bytes at address 0x08010DC8 performed ok. + Programming of 8 bytes at address 0x08010DD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010E00 performed ok. + Programming of 8 bytes at address 0x08010E08 performed ok. + Programming of 8 bytes at address 0x08010E10 performed ok. + Programming of 8 bytes at address 0x08010E18 performed ok. + Programming of 8 bytes at address 0x08010E20 performed ok. + Programming of 8 bytes at address 0x08010E28 performed ok. + Programming of 8 bytes at address 0x08010E30 performed ok. + Programming of 8 bytes at address 0x08010E38 performed ok. + Programming of 8 bytes at address 0x08010E40 performed ok. + Programming of 8 bytes at address 0x08010E48 performed ok. + Programming of 8 bytes at address 0x08010E50 performed ok. + Programming of 8 bytes at address 0x08010E58 performed ok. + Programming of 8 bytes at address 0x08010E60 performed ok. + Programming of 8 bytes at address 0x08010E68 performed ok. + Programming of 8 bytes at address 0x08010E70 performed ok. + Programming of 8 bytes at address 0x08010E78 performed ok. + Programming of 8 bytes at address 0x08010E80 performed ok. + Programming of 8 bytes at address 0x08010E88 performed ok. + Programming of 8 bytes at address 0x08010E90 performed ok. + Programming of 8 bytes at address 0x08010E98 performed ok. + Programming of 8 bytes at address 0x08010EA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08010EC0 performed ok. + Programming of 8 bytes at address 0x08010EC8 performed ok. + Programming of 8 bytes at address 0x08010ED0 performed ok. + Programming of 8 bytes at address 0x08010ED8 performed ok. + Programming of 8 bytes at address 0x08010EE0 performed ok. + Programming of 8 bytes at address 0x08010EE8 performed ok. + Programming of 8 bytes at address 0x08010EF0 performed ok. + Programming of 8 bytes at address 0x08010EF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08010F00 performed ok. + Programming of 8 bytes at address 0x08010F08 performed ok. + Programming of 8 bytes at address 0x08010F10 performed ok. + Programming of 8 bytes at address 0x08010F18 performed ok. + Programming of 8 bytes at address 0x08010F20 performed ok. + Programming of 8 bytes at address 0x08010F28 performed ok. + Programming of 8 bytes at address 0x08010F30 performed ok. + Programming of 8 bytes at address 0x08010F38 performed ok. + Programming of 8 bytes at address 0x08010F40 performed ok. + Programming of 8 bytes at address 0x08010F48 performed ok. + Programming of 8 bytes at address 0x08010F50 performed ok. + Programming of 8 bytes at address 0x08010F58 performed ok. + Programming of 8 bytes at address 0x08010F60 performed ok. + Programming of 8 bytes at address 0x08010F68 performed ok. + Programming of 8 bytes at address 0x08010F70 performed ok. + Programming of 8 bytes at address 0x08010F78 performed ok. + Programming of 8 bytes at address 0x08010F80 performed ok. + Programming of 8 bytes at address 0x08010F88 performed ok. + Programming of 8 bytes at address 0x08010F90 performed ok. + Programming of 8 bytes at address 0x08010F98 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08010FB8 performed ok. + Programming of 8 bytes at address 0x08010FC0 performed ok. + Programming of 8 bytes at address 0x08010FC8 performed ok. + Programming of 8 bytes at address 0x08010FD0 performed ok. + Programming of 8 bytes at address 0x08010FD8 performed ok. + Programming of 8 bytes at address 0x08010FE0 performed ok. + Programming of 8 bytes at address 0x08010FE8 performed ok. + Programming of 8 bytes at address 0x08010FF0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011000 performed ok. + Programming of 8 bytes at address 0x08011008 performed ok. + Programming of 8 bytes at address 0x08011010 performed ok. + Programming of 8 bytes at address 0x08011018 performed ok. + Programming of 8 bytes at address 0x08011020 performed ok. + Programming of 8 bytes at address 0x08011028 performed ok. + Programming of 8 bytes at address 0x08011030 performed ok. + Programming of 8 bytes at address 0x08011038 performed ok. + Programming of 8 bytes at address 0x08011040 performed ok. + Programming of 8 bytes at address 0x08011048 performed ok. + Programming of 8 bytes at address 0x08011050 performed ok. + Programming of 8 bytes at address 0x08011058 performed ok. + Programming of 8 bytes at address 0x08011060 performed ok. + Programming of 8 bytes at address 0x08011068 performed ok. + Programming of 8 bytes at address 0x08011070 performed ok. + Programming of 8 bytes at address 0x08011078 performed ok. + Programming of 8 bytes at address 0x08011080 performed ok. + Programming of 8 bytes at address 0x08011088 performed ok. + Programming of 8 bytes at address 0x08011090 performed ok. +k. + Programming of 8 bytes at address 0x080110A0 performed ok. + Programming of 8 bytes at address 0x080110A8 performed ok. + Programming of 8 bytes at address 0x080110B0 performed ok. + Programming of 8 bytes at address 0x080110B8 performed ok. + Programming of 8 bytes at address 0x080110C0 performed ok. + Programming of 8 bytes at address 0x080110C8 performed ok. + Programming of 8 bytes at address 0x080110D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011100 performed ok. + Programming of 8 bytes at address 0x08011108 performed ok. + Programming of 8 bytes at address 0x08011110 performed ok. + Programming of 8 bytes at address 0x08011118 performed ok. + Programming of 8 bytes at address 0x08011120 performed ok. + Programming of 8 bytes at address 0x08011128 performed ok. + Programming of 8 bytes at address 0x08011130 performed ok. + Programming of 8 bytes at address 0x08011138 performed ok. + Programming of 8 bytes at address 0x08011140 performed ok. + Programming of 8 bytes at address 0x08011148 performed ok. + Programming of 8 bytes at address 0x08011150 performed ok. + Programming of 8 bytes at address 0x08011158 performed ok. + Programming of 8 bytes at address 0x08011160 performed ok. + Programming of 8 bytes at address 0x08011168 performed ok. + Programming of 8 bytes at address 0x08011170 performed ok. + Programming of 8 bytes at address 0x08011178 performed ok. + Programming of 8 bytes at address 0x08011180 performed ok. + Programming of 8 bytes at address 0x08011188 performed ok. + Programming of 8 bytes at address 0x08011190 performed ok. + Programming of 8 bytes at address 0x08011198 performed ok. + Programming of 8 bytes at address 0x080111A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080111C0 performed ok. + Programming of 8 bytes at address 0x080111C8 performed ok. + Programming of 8 bytes at address 0x080111D0 performed ok. + Programming of 8 bytes at address 0x080111D8 performed ok. + Programming of 8 bytes at address 0x080111E0 performed ok. + Programming of 8 bytes at address 0x080111E8 performed ok. + Programming of 8 bytes at address 0x080111F0 performed ok. + Programming of 8 bytes at address 0x080111F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011200 performed ok. + Programming of 8 bytes at address 0x08011208 performed ok. + Programming of 8 bytes at address 0x08011210 performed ok. + Programming of 8 bytes at address 0x08011218 performed ok. + Programming of 8 bytes at address 0x08011220 performed ok. + Programming of 8 bytes at address 0x08011228 performed ok. + Programming of 8 bytes at address 0x08011230 performed ok. + Programming of 8 bytes at address 0x08011238 performed ok. + Programming of 8 bytes at address 0x08011240 performed ok. + Programming of 8 bytes at address 0x08011248 performed ok. + Programming of 8 bytes at address 0x08011250 performed ok. + Programming of 8 bytes at address 0x08011258 performed ok. + Programming of 8 bytes at address 0x08011260 performed ok. + Programming of 8 bytes at address 0x08011268 performed ok. + Programming of 8 bytes at address 0x08011270 performed ok. + Programming of 8 bytes at address 0x08011278 performed ok. + Programming of 8 bytes at address 0x08011280 performed ok. + Programming of 8 bytes at address 0x08011288 performed ok. + Programming of 8 bytes at address 0x08011290 performed ok. + Programming of 8 bytes at address 0x08011298 performed ok. + Programming of 8 bytes at address 0x080112A0 performed ok. + Programming of 8 bytes at address 0x080112A8 performed ok. + Programming of 8 bytes at address 0x080112B0 performed ok. + Programming of 8 bytes at address 0x080112B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080112F0 performed ok. + Programming of 8 bytes at address 0x080112F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011300 performed ok. + Programming of 8 bytes at address 0x08011308 performed ok. + Programming of 8 bytes at address 0x08011310 performed ok. + Programming of 8 bytes at address 0x08011318 performed ok. + Programming of 8 bytes at address 0x08011320 performed ok. + Programming of 8 bytes at address 0x08011328 performed ok. + Programming of 8 bytes at address 0x08011330 performed ok. + Programming of 8 bytes at address 0x08011338 performed ok. + Programming of 8 bytes at address 0x08011340 performed ok. + Programming of 8 bytes at address 0x08011348 performed ok. + Programming of 8 bytes at address 0x08011350 performed ok. + Programming of 8 bytes at address 0x08011358 performed ok. + Programming of 8 bytes at address 0x08011360 performed ok. + Programming of 8 bytes at address 0x08011368 performed ok. + Programming of 8 bytes at address 0x08011370 performed ok. + Programming of 8 bytes at address 0x08011378 performed ok. + Programming of 8 bytes at address 0x08011380 performed ok. + Programming of 8 bytes at address 0x08011388 performed ok. + Programming of 8 bytes at address 0x08011390 performed ok. + Programming of 8 bytes at address 0x08011398 performed ok. + Programming of 8 bytes at address 0x080113A0 performed ok. + Programming of 8 bytes at address 0x080113A8 performed ok. + Programming of 8 bytes at address 0x080113B0 performed ok. + Programming of 8 bytes at address 0x080113B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080113F0 performed ok. + Programming of 8 bytes at address 0x080113F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011400 performed ok. + Programming of 8 bytes at address 0x08011408 performed ok. + Programming of 8 bytes at address 0x08011410 performed ok. + Programming of 8 bytes at address 0x08011418 performed ok. + Programming of 8 bytes at address 0x08011420 performed ok. + Programming of 8 bytes at address 0x08011428 performed ok. + Programming of 8 bytes at address 0x08011430 performed ok. + Programming of 8 bytes at address 0x08011438 performed ok. + Programming of 8 bytes at address 0x08011440 performed ok. + Programming of 8 bytes at address 0x08011448 performed ok. + Programming of 8 bytes at address 0x08011450 performed ok. + Programming of 8 bytes at address 0x08011458 performed ok. + Programming of 8 bytes at address 0x08011460 performed ok. + Programming of 8 bytes at address 0x08011468 performed ok. + Programming of 8 bytes at address 0x08011470 performed ok. + Programming of 8 bytes at address 0x08011478 performed ok. + Programming of 8 bytes at address 0x08011480 performed ok. + Programming of 8 bytes at address 0x08011488 performed ok. + Programming of 8 bytes at address 0x08011490 performed ok. + Programming of 8 bytes at address 0x08011498 performed ok. + Programming of 8 bytes at address 0x080114A0 performed ok. + Programming of 8 bytes at address 0x080114A8 performed ok. + Programming of 8 bytes at address 0x080114B0 performed ok. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080114E0 performed ok. + Programming of 8 bytes at address 0x080114E8 performed ok. + Programming of 8 bytes at address 0x080114F0 performed ok. + Programming of 8 bytes at address 0x080114F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011500 performed ok. + Programming of 8 bytes at address 0x08011508 performed ok. + Programming of 8 bytes at address 0x08011510 performed ok. + Programming of 8 bytes at address 0x08011518 performed ok. + Programming of 8 bytes at address 0x08011520 performed ok. + Programming of 8 bytes at address 0x08011528 performed ok. + Programming of 8 bytes at address 0x08011530 performed ok. + Programming of 8 bytes at address 0x08011538 performed ok. + Programming of 8 bytes at address 0x08011540 performed ok. + Programming of 8 bytes at address 0x08011548 performed ok. + Programming of 8 bytes at address 0x08011550 performed ok. + Programming of 8 bytes at address 0x08011558 performed ok. + Programming of 8 bytes at address 0x08011560 performed ok. + Programming of 8 bytes at address 0x08011568 performed ok. + Programming of 8 bytes at address 0x08011570 performed ok. + Programming of 8 bytes at address 0x08011578 performed ok. + Programming of 8 bytes at address 0x08011580 performed ok. + Programming of 8 bytes at address 0x08011588 performed ok. + Programming of 8 bytes at address 0x08011590 performed ok. + Programming of 8 bytes at address 0x08011598 performed ok. +k. +k. + Programming of 8 bytes at address 0x080115B0 performed ok. + Programming of 8 bytes at address 0x080115B8 performed ok. + Programming of 8 bytes at address 0x080115C0 performed ok. + Programming of 8 bytes at address 0x080115C8 performed ok. + Programming of 8 bytes at address 0x080115D0 performed ok. + Programming of 8 bytes at address 0x080115D8 performed ok. + Programming of 8 bytes at address 0x080115E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011600 performed ok. + Programming of 8 bytes at address 0x08011608 performed ok. + Programming of 8 bytes at address 0x08011610 performed ok. + Programming of 8 bytes at address 0x08011618 performed ok. + Programming of 8 bytes at address 0x08011620 performed ok. + Programming of 8 bytes at address 0x08011628 performed ok. + Programming of 8 bytes at address 0x08011630 performed ok. + Programming of 8 bytes at address 0x08011638 performed ok. + Programming of 8 bytes at address 0x08011640 performed ok. + Programming of 8 bytes at address 0x08011648 performed ok. + Programming of 8 bytes at address 0x08011650 performed ok. + Programming of 8 bytes at address 0x08011658 performed ok. + Programming of 8 bytes at address 0x08011660 performed ok. + Programming of 8 bytes at address 0x08011668 performed ok. + Programming of 8 bytes at address 0x08011670 performed ok. + Programming of 8 bytes at address 0x08011678 performed ok. + Programming of 8 bytes at address 0x08011680 performed ok. + Programming of 8 bytes at address 0x08011688 performed ok. + Programming of 8 bytes at address 0x08011690 performed ok. + Programming of 8 bytes at address 0x08011698 performed ok. + Programming of 8 bytes at address 0x080116A0 performed ok. + Programming of 8 bytes at address 0x080116A8 performed ok. + Programming of 8 bytes at address 0x080116B0 performed ok. + Programming of 8 bytes at address 0x080116B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080116F0 performed ok. + Programming of 8 bytes at address 0x080116F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011700 performed ok. + Programming of 8 bytes at address 0x08011708 performed ok. + Programming of 8 bytes at address 0x08011710 performed ok. + Programming of 8 bytes at address 0x08011718 performed ok. + Programming of 8 bytes at address 0x08011720 performed ok. + Programming of 8 bytes at address 0x08011728 performed ok. + Programming of 8 bytes at address 0x08011730 performed ok. + Programming of 8 bytes at address 0x08011738 performed ok. + Programming of 8 bytes at address 0x08011740 performed ok. + Programming of 8 bytes at address 0x08011748 performed ok. + Programming of 8 bytes at address 0x08011750 performed ok. + Programming of 8 bytes at address 0x08011758 performed ok. + Programming of 8 bytes at address 0x08011760 performed ok. + Programming of 8 bytes at address 0x08011768 performed ok. + Programming of 8 bytes at address 0x08011770 performed ok. + Programming of 8 bytes at address 0x08011778 performed ok. + Programming of 8 bytes at address 0x08011780 performed ok. + Programming of 8 bytes at address 0x08011788 performed ok. + Programming of 8 bytes at address 0x08011790 performed ok. + Programming of 8 bytes at address 0x08011798 performed ok. +k. + Programming of 8 bytes at address 0x080117A8 performed ok. + Programming of 8 bytes at address 0x080117B0 performed ok. + Programming of 8 bytes at address 0x080117B8 performed ok. + Programming of 8 bytes at address 0x080117C0 performed ok. + Programming of 8 bytes at address 0x080117C8 performed ok. + Programming of 8 bytes at address 0x080117D0 performed ok. + Programming of 8 bytes at address 0x080117D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011800 performed ok. + Programming of 8 bytes at address 0x08011808 performed ok. + Programming of 8 bytes at address 0x08011810 performed ok. + Programming of 8 bytes at address 0x08011818 performed ok. + Programming of 8 bytes at address 0x08011820 performed ok. + Programming of 8 bytes at address 0x08011828 performed ok. + Programming of 8 bytes at address 0x08011830 performed ok. + Programming of 8 bytes at address 0x08011838 performed ok. + Programming of 8 bytes at address 0x08011840 performed ok. + Programming of 8 bytes at address 0x08011848 performed ok. + Programming of 8 bytes at address 0x08011850 performed ok. + Programming of 8 bytes at address 0x08011858 performed ok. + Programming of 8 bytes at address 0x08011860 performed ok. + Programming of 8 bytes at address 0x08011868 performed ok. + Programming of 8 bytes at address 0x08011870 performed ok. + Programming of 8 bytes at address 0x08011878 performed ok. + Programming of 8 bytes at address 0x08011880 performed ok. + Programming of 8 bytes at address 0x08011888 performed ok. + Programming of 8 bytes at address 0x08011890 performed ok. + Programming of 8 bytes at address 0x08011898 performed ok. +k. +k. + Programming of 8 bytes at address 0x080118B0 performed ok. + Programming of 8 bytes at address 0x080118B8 performed ok. + Programming of 8 bytes at address 0x080118C0 performed ok. + Programming of 8 bytes at address 0x080118C8 performed ok. + Programming of 8 bytes at address 0x080118D0 performed ok. + Programming of 8 bytes at address 0x080118D8 performed ok. + Programming of 8 bytes at address 0x080118E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011900 performed ok. + Programming of 8 bytes at address 0x08011908 performed ok. + Programming of 8 bytes at address 0x08011910 performed ok. + Programming of 8 bytes at address 0x08011918 performed ok. + Programming of 8 bytes at address 0x08011920 performed ok. + Programming of 8 bytes at address 0x08011928 performed ok. + Programming of 8 bytes at address 0x08011930 performed ok. + Programming of 8 bytes at address 0x08011938 performed ok. + Programming of 8 bytes at address 0x08011940 performed ok. + Programming of 8 bytes at address 0x08011948 performed ok. + Programming of 8 bytes at address 0x08011950 performed ok. + Programming of 8 bytes at address 0x08011958 performed ok. + Programming of 8 bytes at address 0x08011960 performed ok. + Programming of 8 bytes at address 0x08011968 performed ok. + Programming of 8 bytes at address 0x08011970 performed ok. + Programming of 8 bytes at address 0x08011978 performed ok. + Programming of 8 bytes at address 0x08011980 performed ok. + Programming of 8 bytes at address 0x08011988 performed ok. + Programming of 8 bytes at address 0x08011990 performed ok. + Programming of 8 bytes at address 0x08011998 performed ok. +k. +k. + Programming of 8 bytes at address 0x080119B0 performed ok. + Programming of 8 bytes at address 0x080119B8 performed ok. + Programming of 8 bytes at address 0x080119C0 performed ok. + Programming of 8 bytes at address 0x080119C8 performed ok. + Programming of 8 bytes at address 0x080119D0 performed ok. + Programming of 8 bytes at address 0x080119D8 performed ok. + Programming of 8 bytes at address 0x080119E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011A00 performed ok. + Programming of 8 bytes at address 0x08011A08 performed ok. + Programming of 8 bytes at address 0x08011A10 performed ok. + Programming of 8 bytes at address 0x08011A18 performed ok. + Programming of 8 bytes at address 0x08011A20 performed ok. + Programming of 8 bytes at address 0x08011A28 performed ok. + Programming of 8 bytes at address 0x08011A30 performed ok. + Programming of 8 bytes at address 0x08011A38 performed ok. + Programming of 8 bytes at address 0x08011A40 performed ok. + Programming of 8 bytes at address 0x08011A48 performed ok. + Programming of 8 bytes at address 0x08011A50 performed ok. + Programming of 8 bytes at address 0x08011A58 performed ok. + Programming of 8 bytes at address 0x08011A60 performed ok. + Programming of 8 bytes at address 0x08011A68 performed ok. + Programming of 8 bytes at address 0x08011A70 performed ok. + Programming of 8 bytes at address 0x08011A78 performed ok. + Programming of 8 bytes at address 0x08011A80 performed ok. + Programming of 8 bytes at address 0x08011A88 performed ok. + Programming of 8 bytes at address 0x08011A90 performed ok. + Programming of 8 bytes at address 0x08011A98 performed ok. + Programming of 8 bytes at address 0x08011AA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08011AC0 performed ok. + Programming of 8 bytes at address 0x08011AC8 performed ok. + Programming of 8 bytes at address 0x08011AD0 performed ok. + Programming of 8 bytes at address 0x08011AD8 performed ok. + Programming of 8 bytes at address 0x08011AE0 performed ok. + Programming of 8 bytes at address 0x08011AE8 performed ok. + Programming of 8 bytes at address 0x08011AF0 performed ok. + Programming of 8 bytes at address 0x08011AF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011B00 performed ok. + Programming of 8 bytes at address 0x08011B08 performed ok. + Programming of 8 bytes at address 0x08011B10 performed ok. + Programming of 8 bytes at address 0x08011B18 performed ok. + Programming of 8 bytes at address 0x08011B20 performed ok. + Programming of 8 bytes at address 0x08011B28 performed ok. + Programming of 8 bytes at address 0x08011B30 performed ok. + Programming of 8 bytes at address 0x08011B38 performed ok. + Programming of 8 bytes at address 0x08011B40 performed ok. + Programming of 8 bytes at address 0x08011B48 performed ok. + Programming of 8 bytes at address 0x08011B50 performed ok. + Programming of 8 bytes at address 0x08011B58 performed ok. + Programming of 8 bytes at address 0x08011B60 performed ok. + Programming of 8 bytes at address 0x08011B68 performed ok. + Programming of 8 bytes at address 0x08011B70 performed ok. + Programming of 8 bytes at address 0x08011B78 performed ok. + Programming of 8 bytes at address 0x08011B80 performed ok. + Programming of 8 bytes at address 0x08011B88 performed ok. + Programming of 8 bytes at address 0x08011B90 performed ok. + Programming of 8 bytes at address 0x08011B98 performed ok. +k. +k. + Programming of 8 bytes at address 0x08011BB0 performed ok. + Programming of 8 bytes at address 0x08011BB8 performed ok. + Programming of 8 bytes at address 0x08011BC0 performed ok. + Programming of 8 bytes at address 0x08011BC8 performed ok. + Programming of 8 bytes at address 0x08011BD0 performed ok. + Programming of 8 bytes at address 0x08011BD8 performed ok. + Programming of 8 bytes at address 0x08011BE0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011C00 performed ok. + Programming of 8 bytes at address 0x08011C08 performed ok. + Programming of 8 bytes at address 0x08011C10 performed ok. + Programming of 8 bytes at address 0x08011C18 performed ok. + Programming of 8 bytes at address 0x08011C20 performed ok. + Programming of 8 bytes at address 0x08011C28 performed ok. + Programming of 8 bytes at address 0x08011C30 performed ok. + Programming of 8 bytes at address 0x08011C38 performed ok. + Programming of 8 bytes at address 0x08011C40 performed ok. + Programming of 8 bytes at address 0x08011C48 performed ok. + Programming of 8 bytes at address 0x08011C50 performed ok. + Programming of 8 bytes at address 0x08011C58 performed ok. + Programming of 8 bytes at address 0x08011C60 performed ok. + Programming of 8 bytes at address 0x08011C68 performed ok. + Programming of 8 bytes at address 0x08011C70 performed ok. + Programming of 8 bytes at address 0x08011C78 performed ok. + Programming of 8 bytes at address 0x08011C80 performed ok. + Programming of 8 bytes at address 0x08011C88 performed ok. + Programming of 8 bytes at address 0x08011C90 performed ok. + Programming of 8 bytes at address 0x08011C98 performed ok. + Programming of 8 bytes at address 0x08011CA0 performed ok. + Programming of 8 bytes at address 0x08011CA8 performed ok. + Programming of 8 bytes at address 0x08011CB0 performed ok. + Programming of 8 bytes at address 0x08011CB8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011D00 performed ok. + Programming of 8 bytes at address 0x08011D08 performed ok. + Programming of 8 bytes at address 0x08011D10 performed ok. + Programming of 8 bytes at address 0x08011D18 performed ok. + Programming of 8 bytes at address 0x08011D20 performed ok. + Programming of 8 bytes at address 0x08011D28 performed ok. + Programming of 8 bytes at address 0x08011D30 performed ok. + Programming of 8 bytes at address 0x08011D38 performed ok. + Programming of 8 bytes at address 0x08011D40 performed ok. + Programming of 8 bytes at address 0x08011D48 performed ok. + Programming of 8 bytes at address 0x08011D50 performed ok. + Programming of 8 bytes at address 0x08011D58 performed ok. + Programming of 8 bytes at address 0x08011D60 performed ok. + Programming of 8 bytes at address 0x08011D68 performed ok. + Programming of 8 bytes at address 0x08011D70 performed ok. + Programming of 8 bytes at address 0x08011D78 performed ok. + Programming of 8 bytes at address 0x08011D80 performed ok. + Programming of 8 bytes at address 0x08011D88 performed ok. + Programming of 8 bytes at address 0x08011D90 performed ok. + Programming of 8 bytes at address 0x08011D98 performed ok. +k. + Programming of 8 bytes at address 0x08011DA8 performed ok. + Programming of 8 bytes at address 0x08011DB0 performed ok. + Programming of 8 bytes at address 0x08011DB8 performed ok. + Programming of 8 bytes at address 0x08011DC0 performed ok. + Programming of 8 bytes at address 0x08011DC8 performed ok. + Programming of 8 bytes at address 0x08011DD0 performed ok. + Programming of 8 bytes at address 0x08011DD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011E00 performed ok. + Programming of 8 bytes at address 0x08011E08 performed ok. + Programming of 8 bytes at address 0x08011E10 performed ok. + Programming of 8 bytes at address 0x08011E18 performed ok. + Programming of 8 bytes at address 0x08011E20 performed ok. + Programming of 8 bytes at address 0x08011E28 performed ok. + Programming of 8 bytes at address 0x08011E30 performed ok. + Programming of 8 bytes at address 0x08011E38 performed ok. + Programming of 8 bytes at address 0x08011E40 performed ok. + Programming of 8 bytes at address 0x08011E48 performed ok. + Programming of 8 bytes at address 0x08011E50 performed ok. + Programming of 8 bytes at address 0x08011E58 performed ok. + Programming of 8 bytes at address 0x08011E60 performed ok. + Programming of 8 bytes at address 0x08011E68 performed ok. + Programming of 8 bytes at address 0x08011E70 performed ok. + Programming of 8 bytes at address 0x08011E78 performed ok. + Programming of 8 bytes at address 0x08011E80 performed ok. + Programming of 8 bytes at address 0x08011E88 performed ok. + Programming of 8 bytes at address 0x08011E90 performed ok. + Programming of 8 bytes at address 0x08011E98 performed ok. +k. + Programming of 8 bytes at address 0x08011EA8 performed ok. + Programming of 8 bytes at address 0x08011EB0 performed ok. + Programming of 8 bytes at address 0x08011EB8 performed ok. + Programming of 8 bytes at address 0x08011EC0 performed ok. + Programming of 8 bytes at address 0x08011EC8 performed ok. + Programming of 8 bytes at address 0x08011ED0 performed ok. + Programming of 8 bytes at address 0x08011ED8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08011F00 performed ok. + Programming of 8 bytes at address 0x08011F08 performed ok. + Programming of 8 bytes at address 0x08011F10 performed ok. + Programming of 8 bytes at address 0x08011F18 performed ok. + Programming of 8 bytes at address 0x08011F20 performed ok. + Programming of 8 bytes at address 0x08011F28 performed ok. + Programming of 8 bytes at address 0x08011F30 performed ok. + Programming of 8 bytes at address 0x08011F38 performed ok. + Programming of 8 bytes at address 0x08011F40 performed ok. + Programming of 8 bytes at address 0x08011F48 performed ok. + Programming of 8 bytes at address 0x08011F50 performed ok. + Programming of 8 bytes at address 0x08011F58 performed ok. + Programming of 8 bytes at address 0x08011F60 performed ok. + Programming of 8 bytes at address 0x08011F68 performed ok. + Programming of 8 bytes at address 0x08011F70 performed ok. + Programming of 8 bytes at address 0x08011F78 performed ok. + Programming of 8 bytes at address 0x08011F80 performed ok. + Programming of 8 bytes at address 0x08011F88 performed ok. + Programming of 8 bytes at address 0x08011F90 performed ok. + Programming of 8 bytes at address 0x08011F98 performed ok. + Programming of 8 bytes at address 0x08011FA0 performed ok. + Programming of 8 bytes at address 0x08011FA8 performed ok. + Programming of 8 bytes at address 0x08011FB0 performed ok. + Programming of 8 bytes at address 0x08011FB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08011FF0 performed ok. + Programming of 8 bytes at address 0x08011FF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012000 performed ok. + Programming of 8 bytes at address 0x08012008 performed ok. + Programming of 8 bytes at address 0x08012010 performed ok. + Programming of 8 bytes at address 0x08012018 performed ok. + Programming of 8 bytes at address 0x08012020 performed ok. + Programming of 8 bytes at address 0x08012028 performed ok. + Programming of 8 bytes at address 0x08012030 performed ok. + Programming of 8 bytes at address 0x08012038 performed ok. + Programming of 8 bytes at address 0x08012040 performed ok. + Programming of 8 bytes at address 0x08012048 performed ok. + Programming of 8 bytes at address 0x08012050 performed ok. + Programming of 8 bytes at address 0x08012058 performed ok. + Programming of 8 bytes at address 0x08012060 performed ok. + Programming of 8 bytes at address 0x08012068 performed ok. + Programming of 8 bytes at address 0x08012070 performed ok. + Programming of 8 bytes at address 0x08012078 performed ok. + Programming of 8 bytes at address 0x08012080 performed ok. + Programming of 8 bytes at address 0x08012088 performed ok. + Programming of 8 bytes at address 0x08012090 performed ok. + Programming of 8 bytes at address 0x08012098 performed ok. +k. + Programming of 8 bytes at address 0x080120A8 performed ok. + Programming of 8 bytes at address 0x080120B0 performed ok. + Programming of 8 bytes at address 0x080120B8 performed ok. + Programming of 8 bytes at address 0x080120C0 performed ok. + Programming of 8 bytes at address 0x080120C8 performed ok. + Programming of 8 bytes at address 0x080120D0 performed ok. + Programming of 8 bytes at address 0x080120D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012100 performed ok. + Programming of 8 bytes at address 0x08012108 performed ok. + Programming of 8 bytes at address 0x08012110 performed ok. + Programming of 8 bytes at address 0x08012118 performed ok. + Programming of 8 bytes at address 0x08012120 performed ok. + Programming of 8 bytes at address 0x08012128 performed ok. + Programming of 8 bytes at address 0x08012130 performed ok. + Programming of 8 bytes at address 0x08012138 performed ok. + Programming of 8 bytes at address 0x08012140 performed ok. + Programming of 8 bytes at address 0x08012148 performed ok. + Programming of 8 bytes at address 0x08012150 performed ok. + Programming of 8 bytes at address 0x08012158 performed ok. + Programming of 8 bytes at address 0x08012160 performed ok. + Programming of 8 bytes at address 0x08012168 performed ok. + Programming of 8 bytes at address 0x08012170 performed ok. + Programming of 8 bytes at address 0x08012178 performed ok. + Programming of 8 bytes at address 0x08012180 performed ok. + Programming of 8 bytes at address 0x08012188 performed ok. + Programming of 8 bytes at address 0x08012190 performed ok. + Programming of 8 bytes at address 0x08012198 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080121B8 performed ok. + Programming of 8 bytes at address 0x080121C0 performed ok. + Programming of 8 bytes at address 0x080121C8 performed ok. + Programming of 8 bytes at address 0x080121D0 performed ok. + Programming of 8 bytes at address 0x080121D8 performed ok. + Programming of 8 bytes at address 0x080121E0 performed ok. + Programming of 8 bytes at address 0x080121E8 performed ok. + Programming of 8 bytes at address 0x080121F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012200 performed ok. + Programming of 8 bytes at address 0x08012208 performed ok. + Programming of 8 bytes at address 0x08012210 performed ok. + Programming of 8 bytes at address 0x08012218 performed ok. + Programming of 8 bytes at address 0x08012220 performed ok. + Programming of 8 bytes at address 0x08012228 performed ok. + Programming of 8 bytes at address 0x08012230 performed ok. + Programming of 8 bytes at address 0x08012238 performed ok. + Programming of 8 bytes at address 0x08012240 performed ok. + Programming of 8 bytes at address 0x08012248 performed ok. + Programming of 8 bytes at address 0x08012250 performed ok. + Programming of 8 bytes at address 0x08012258 performed ok. + Programming of 8 bytes at address 0x08012260 performed ok. + Programming of 8 bytes at address 0x08012268 performed ok. + Programming of 8 bytes at address 0x08012270 performed ok. + Programming of 8 bytes at address 0x08012278 performed ok. + Programming of 8 bytes at address 0x08012280 performed ok. + Programming of 8 bytes at address 0x08012288 performed ok. + Programming of 8 bytes at address 0x08012290 performed ok. + Programming of 8 bytes at address 0x08012298 performed ok. + Programming of 8 bytes at address 0x080122A0 performed ok. + Programming of 8 bytes at address 0x080122A8 performed ok. + Programming of 8 bytes at address 0x080122B0 performed ok. + Programming of 8 bytes at address 0x080122B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012300 performed ok. + Programming of 8 bytes at address 0x08012308 performed ok. + Programming of 8 bytes at address 0x08012310 performed ok. + Programming of 8 bytes at address 0x08012318 performed ok. + Programming of 8 bytes at address 0x08012320 performed ok. + Programming of 8 bytes at address 0x08012328 performed ok. + Programming of 8 bytes at address 0x08012330 performed ok. + Programming of 8 bytes at address 0x08012338 performed ok. + Programming of 8 bytes at address 0x08012340 performed ok. + Programming of 8 bytes at address 0x08012348 performed ok. + Programming of 8 bytes at address 0x08012350 performed ok. + Programming of 8 bytes at address 0x08012358 performed ok. + Programming of 8 bytes at address 0x08012360 performed ok. + Programming of 8 bytes at address 0x08012368 performed ok. + Programming of 8 bytes at address 0x08012370 performed ok. + Programming of 8 bytes at address 0x08012378 performed ok. + Programming of 8 bytes at address 0x08012380 performed ok. + Programming of 8 bytes at address 0x08012388 performed ok. + Programming of 8 bytes at address 0x08012390 performed ok. +k. + Programming of 8 bytes at address 0x080123A0 performed ok. + Programming of 8 bytes at address 0x080123A8 performed ok. + Programming of 8 bytes at address 0x080123B0 performed ok. + Programming of 8 bytes at address 0x080123B8 performed ok. + Programming of 8 bytes at address 0x080123C0 performed ok. + Programming of 8 bytes at address 0x080123C8 performed ok. + Programming of 8 bytes at address 0x080123D0 performed ok. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012400 performed ok. + Programming of 8 bytes at address 0x08012408 performed ok. + Programming of 8 bytes at address 0x08012410 performed ok. + Programming of 8 bytes at address 0x08012418 performed ok. + Programming of 8 bytes at address 0x08012420 performed ok. + Programming of 8 bytes at address 0x08012428 performed ok. + Programming of 8 bytes at address 0x08012430 performed ok. + Programming of 8 bytes at address 0x08012438 performed ok. + Programming of 8 bytes at address 0x08012440 performed ok. + Programming of 8 bytes at address 0x08012448 performed ok. + Programming of 8 bytes at address 0x08012450 performed ok. + Programming of 8 bytes at address 0x08012458 performed ok. + Programming of 8 bytes at address 0x08012460 performed ok. + Programming of 8 bytes at address 0x08012468 performed ok. + Programming of 8 bytes at address 0x08012470 performed ok. + Programming of 8 bytes at address 0x08012478 performed ok. + Programming of 8 bytes at address 0x08012480 performed ok. + Programming of 8 bytes at address 0x08012488 performed ok. + Programming of 8 bytes at address 0x08012490 performed ok. + Programming of 8 bytes at address 0x08012498 performed ok. + Programming of 8 bytes at address 0x080124A0 performed ok. + Programming of 8 bytes at address 0x080124A8 performed ok. + Programming of 8 bytes at address 0x080124B0 performed ok. + Programming of 8 bytes at address 0x080124B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080124F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012500 performed ok. + Programming of 8 bytes at address 0x08012508 performed ok. + Programming of 8 bytes at address 0x08012510 performed ok. + Programming of 8 bytes at address 0x08012518 performed ok. + Programming of 8 bytes at address 0x08012520 performed ok. + Programming of 8 bytes at address 0x08012528 performed ok. + Programming of 8 bytes at address 0x08012530 performed ok. + Programming of 8 bytes at address 0x08012538 performed ok. + Programming of 8 bytes at address 0x08012540 performed ok. + Programming of 8 bytes at address 0x08012548 performed ok. + Programming of 8 bytes at address 0x08012550 performed ok. + Programming of 8 bytes at address 0x08012558 performed ok. + Programming of 8 bytes at address 0x08012560 performed ok. + Programming of 8 bytes at address 0x08012568 performed ok. + Programming of 8 bytes at address 0x08012570 performed ok. + Programming of 8 bytes at address 0x08012578 performed ok. + Programming of 8 bytes at address 0x08012580 performed ok. + Programming of 8 bytes at address 0x08012588 performed ok. + Programming of 8 bytes at address 0x08012590 performed ok. + Programming of 8 bytes at address 0x08012598 performed ok. + Programming of 8 bytes at address 0x080125A0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080125C8 performed ok. + Programming of 8 bytes at address 0x080125D0 performed ok. + Programming of 8 bytes at address 0x080125D8 performed ok. + Programming of 8 bytes at address 0x080125E0 performed ok. + Programming of 8 bytes at address 0x080125E8 performed ok. + Programming of 8 bytes at address 0x080125F0 performed ok. + Programming of 8 bytes at address 0x080125F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012600 performed ok. + Programming of 8 bytes at address 0x08012608 performed ok. + Programming of 8 bytes at address 0x08012610 performed ok. + Programming of 8 bytes at address 0x08012618 performed ok. + Programming of 8 bytes at address 0x08012620 performed ok. + Programming of 8 bytes at address 0x08012628 performed ok. + Programming of 8 bytes at address 0x08012630 performed ok. + Programming of 8 bytes at address 0x08012638 performed ok. + Programming of 8 bytes at address 0x08012640 performed ok. + Programming of 8 bytes at address 0x08012648 performed ok. + Programming of 8 bytes at address 0x08012650 performed ok. + Programming of 8 bytes at address 0x08012658 performed ok. + Programming of 8 bytes at address 0x08012660 performed ok. + Programming of 8 bytes at address 0x08012668 performed ok. + Programming of 8 bytes at address 0x08012670 performed ok. + Programming of 8 bytes at address 0x08012678 performed ok. + Programming of 8 bytes at address 0x08012680 performed ok. + Programming of 8 bytes at address 0x08012688 performed ok. + Programming of 8 bytes at address 0x08012690 performed ok. + Programming of 8 bytes at address 0x08012698 performed ok. +k. +k. + Programming of 8 bytes at address 0x080126B0 performed ok. + Programming of 8 bytes at address 0x080126B8 performed ok. + Programming of 8 bytes at address 0x080126C0 performed ok. + Programming of 8 bytes at address 0x080126C8 performed ok. + Programming of 8 bytes at address 0x080126D0 performed ok. + Programming of 8 bytes at address 0x080126D8 performed ok. + Programming of 8 bytes at address 0x080126E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012700 performed ok. + Programming of 8 bytes at address 0x08012708 performed ok. + Programming of 8 bytes at address 0x08012710 performed ok. + Programming of 8 bytes at address 0x08012718 performed ok. + Programming of 8 bytes at address 0x08012720 performed ok. + Programming of 8 bytes at address 0x08012728 performed ok. + Programming of 8 bytes at address 0x08012730 performed ok. + Programming of 8 bytes at address 0x08012738 performed ok. + Programming of 8 bytes at address 0x08012740 performed ok. + Programming of 8 bytes at address 0x08012748 performed ok. + Programming of 8 bytes at address 0x08012750 performed ok. + Programming of 8 bytes at address 0x08012758 performed ok. + Programming of 8 bytes at address 0x08012760 performed ok. + Programming of 8 bytes at address 0x08012768 performed ok. + Programming of 8 bytes at address 0x08012770 performed ok. + Programming of 8 bytes at address 0x08012778 performed ok. + Programming of 8 bytes at address 0x08012780 performed ok. + Programming of 8 bytes at address 0x08012788 performed ok. + Programming of 8 bytes at address 0x08012790 performed ok. + Programming of 8 bytes at address 0x08012798 performed ok. +k. + Programming of 8 bytes at address 0x080127A8 performed ok. + Programming of 8 bytes at address 0x080127B0 performed ok. + Programming of 8 bytes at address 0x080127B8 performed ok. + Programming of 8 bytes at address 0x080127C0 performed ok. + Programming of 8 bytes at address 0x080127C8 performed ok. + Programming of 8 bytes at address 0x080127D0 performed ok. + Programming of 8 bytes at address 0x080127D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012800 performed ok. + Programming of 8 bytes at address 0x08012808 performed ok. + Programming of 8 bytes at address 0x08012810 performed ok. + Programming of 8 bytes at address 0x08012818 performed ok. + Programming of 8 bytes at address 0x08012820 performed ok. + Programming of 8 bytes at address 0x08012828 performed ok. + Programming of 8 bytes at address 0x08012830 performed ok. + Programming of 8 bytes at address 0x08012838 performed ok. + Programming of 8 bytes at address 0x08012840 performed ok. + Programming of 8 bytes at address 0x08012848 performed ok. + Programming of 8 bytes at address 0x08012850 performed ok. + Programming of 8 bytes at address 0x08012858 performed ok. + Programming of 8 bytes at address 0x08012860 performed ok. + Programming of 8 bytes at address 0x08012868 performed ok. + Programming of 8 bytes at address 0x08012870 performed ok. + Programming of 8 bytes at address 0x08012878 performed ok. + Programming of 8 bytes at address 0x08012880 performed ok. + Programming of 8 bytes at address 0x08012888 performed ok. + Programming of 8 bytes at address 0x08012890 performed ok. + Programming of 8 bytes at address 0x08012898 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080128B8 performed ok. + Programming of 8 bytes at address 0x080128C0 performed ok. + Programming of 8 bytes at address 0x080128C8 performed ok. + Programming of 8 bytes at address 0x080128D0 performed ok. + Programming of 8 bytes at address 0x080128D8 performed ok. + Programming of 8 bytes at address 0x080128E0 performed ok. + Programming of 8 bytes at address 0x080128E8 performed ok. + Programming of 8 bytes at address 0x080128F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012900 performed ok. + Programming of 8 bytes at address 0x08012908 performed ok. + Programming of 8 bytes at address 0x08012910 performed ok. + Programming of 8 bytes at address 0x08012918 performed ok. + Programming of 8 bytes at address 0x08012920 performed ok. + Programming of 8 bytes at address 0x08012928 performed ok. + Programming of 8 bytes at address 0x08012930 performed ok. + Programming of 8 bytes at address 0x08012938 performed ok. + Programming of 8 bytes at address 0x08012940 performed ok. + Programming of 8 bytes at address 0x08012948 performed ok. + Programming of 8 bytes at address 0x08012950 performed ok. + Programming of 8 bytes at address 0x08012958 performed ok. + Programming of 8 bytes at address 0x08012960 performed ok. + Programming of 8 bytes at address 0x08012968 performed ok. + Programming of 8 bytes at address 0x08012970 performed ok. + Programming of 8 bytes at address 0x08012978 performed ok. + Programming of 8 bytes at address 0x08012980 performed ok. + Programming of 8 bytes at address 0x08012988 performed ok. + Programming of 8 bytes at address 0x08012990 performed ok. + Programming of 8 bytes at address 0x08012998 performed ok. + Programming of 8 bytes at address 0x080129A0 performed ok. + Programming of 8 bytes at address 0x080129A8 performed ok. + Programming of 8 bytes at address 0x080129B0 performed ok. + Programming of 8 bytes at address 0x080129B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012A00 performed ok. + Programming of 8 bytes at address 0x08012A08 performed ok. + Programming of 8 bytes at address 0x08012A10 performed ok. + Programming of 8 bytes at address 0x08012A18 performed ok. + Programming of 8 bytes at address 0x08012A20 performed ok. + Programming of 8 bytes at address 0x08012A28 performed ok. + Programming of 8 bytes at address 0x08012A30 performed ok. + Programming of 8 bytes at address 0x08012A38 performed ok. + Programming of 8 bytes at address 0x08012A40 performed ok. + Programming of 8 bytes at address 0x08012A48 performed ok. + Programming of 8 bytes at address 0x08012A50 performed ok. + Programming of 8 bytes at address 0x08012A58 performed ok. + Programming of 8 bytes at address 0x08012A60 performed ok. + Programming of 8 bytes at address 0x08012A68 performed ok. + Programming of 8 bytes at address 0x08012A70 performed ok. + Programming of 8 bytes at address 0x08012A78 performed ok. + Programming of 8 bytes at address 0x08012A80 performed ok. + Programming of 8 bytes at address 0x08012A88 performed ok. + Programming of 8 bytes at address 0x08012A90 performed ok. + Programming of 8 bytes at address 0x08012A98 performed ok. +k. + Programming of 8 bytes at address 0x08012AA8 performed ok. + Programming of 8 bytes at address 0x08012AB0 performed ok. + Programming of 8 bytes at address 0x08012AB8 performed ok. + Programming of 8 bytes at address 0x08012AC0 performed ok. + Programming of 8 bytes at address 0x08012AC8 performed ok. + Programming of 8 bytes at address 0x08012AD0 performed ok. + Programming of 8 bytes at address 0x08012AD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012B00 performed ok. + Programming of 8 bytes at address 0x08012B08 performed ok. + Programming of 8 bytes at address 0x08012B10 performed ok. + Programming of 8 bytes at address 0x08012B18 performed ok. + Programming of 8 bytes at address 0x08012B20 performed ok. + Programming of 8 bytes at address 0x08012B28 performed ok. + Programming of 8 bytes at address 0x08012B30 performed ok. + Programming of 8 bytes at address 0x08012B38 performed ok. + Programming of 8 bytes at address 0x08012B40 performed ok. + Programming of 8 bytes at address 0x08012B48 performed ok. + Programming of 8 bytes at address 0x08012B50 performed ok. + Programming of 8 bytes at address 0x08012B58 performed ok. + Programming of 8 bytes at address 0x08012B60 performed ok. + Programming of 8 bytes at address 0x08012B68 performed ok. + Programming of 8 bytes at address 0x08012B70 performed ok. + Programming of 8 bytes at address 0x08012B78 performed ok. + Programming of 8 bytes at address 0x08012B80 performed ok. + Programming of 8 bytes at address 0x08012B88 performed ok. + Programming of 8 bytes at address 0x08012B90 performed ok. + Programming of 8 bytes at address 0x08012B98 performed ok. +k. + Programming of 8 bytes at address 0x08012BA8 performed ok. + Programming of 8 bytes at address 0x08012BB0 performed ok. + Programming of 8 bytes at address 0x08012BB8 performed ok. + Programming of 8 bytes at address 0x08012BC0 performed ok. + Programming of 8 bytes at address 0x08012BC8 performed ok. + Programming of 8 bytes at address 0x08012BD0 performed ok. + Programming of 8 bytes at address 0x08012BD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012C00 performed ok. + Programming of 8 bytes at address 0x08012C08 performed ok. + Programming of 8 bytes at address 0x08012C10 performed ok. + Programming of 8 bytes at address 0x08012C18 performed ok. + Programming of 8 bytes at address 0x08012C20 performed ok. + Programming of 8 bytes at address 0x08012C28 performed ok. + Programming of 8 bytes at address 0x08012C30 performed ok. + Programming of 8 bytes at address 0x08012C38 performed ok. + Programming of 8 bytes at address 0x08012C40 performed ok. + Programming of 8 bytes at address 0x08012C48 performed ok. + Programming of 8 bytes at address 0x08012C50 performed ok. + Programming of 8 bytes at address 0x08012C58 performed ok. + Programming of 8 bytes at address 0x08012C60 performed ok. + Programming of 8 bytes at address 0x08012C68 performed ok. + Programming of 8 bytes at address 0x08012C70 performed ok. + Programming of 8 bytes at address 0x08012C78 performed ok. + Programming of 8 bytes at address 0x08012C80 performed ok. + Programming of 8 bytes at address 0x08012C88 performed ok. + Programming of 8 bytes at address 0x08012C90 performed ok. + Programming of 8 bytes at address 0x08012C98 performed ok. + Programming of 8 bytes at address 0x08012CA0 performed ok. + Programming of 8 bytes at address 0x08012CA8 performed ok. + Programming of 8 bytes at address 0x08012CB0 performed ok. + Programming of 8 bytes at address 0x08012CB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08012CF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012D00 performed ok. + Programming of 8 bytes at address 0x08012D08 performed ok. + Programming of 8 bytes at address 0x08012D10 performed ok. + Programming of 8 bytes at address 0x08012D18 performed ok. + Programming of 8 bytes at address 0x08012D20 performed ok. + Programming of 8 bytes at address 0x08012D28 performed ok. + Programming of 8 bytes at address 0x08012D30 performed ok. + Programming of 8 bytes at address 0x08012D38 performed ok. + Programming of 8 bytes at address 0x08012D40 performed ok. + Programming of 8 bytes at address 0x08012D48 performed ok. + Programming of 8 bytes at address 0x08012D50 performed ok. + Programming of 8 bytes at address 0x08012D58 performed ok. + Programming of 8 bytes at address 0x08012D60 performed ok. + Programming of 8 bytes at address 0x08012D68 performed ok. + Programming of 8 bytes at address 0x08012D70 performed ok. + Programming of 8 bytes at address 0x08012D78 performed ok. + Programming of 8 bytes at address 0x08012D80 performed ok. + Programming of 8 bytes at address 0x08012D88 performed ok. + Programming of 8 bytes at address 0x08012D90 performed ok. + Programming of 8 bytes at address 0x08012D98 performed ok. +k. + Programming of 8 bytes at address 0x08012DA8 performed ok. + Programming of 8 bytes at address 0x08012DB0 performed ok. + Programming of 8 bytes at address 0x08012DB8 performed ok. + Programming of 8 bytes at address 0x08012DC0 performed ok. + Programming of 8 bytes at address 0x08012DC8 performed ok. + Programming of 8 bytes at address 0x08012DD0 performed ok. + Programming of 8 bytes at address 0x08012DD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012E00 performed ok. + Programming of 8 bytes at address 0x08012E08 performed ok. + Programming of 8 bytes at address 0x08012E10 performed ok. + Programming of 8 bytes at address 0x08012E18 performed ok. + Programming of 8 bytes at address 0x08012E20 performed ok. + Programming of 8 bytes at address 0x08012E28 performed ok. + Programming of 8 bytes at address 0x08012E30 performed ok. + Programming of 8 bytes at address 0x08012E38 performed ok. + Programming of 8 bytes at address 0x08012E40 performed ok. + Programming of 8 bytes at address 0x08012E48 performed ok. + Programming of 8 bytes at address 0x08012E50 performed ok. + Programming of 8 bytes at address 0x08012E58 performed ok. + Programming of 8 bytes at address 0x08012E60 performed ok. + Programming of 8 bytes at address 0x08012E68 performed ok. + Programming of 8 bytes at address 0x08012E70 performed ok. + Programming of 8 bytes at address 0x08012E78 performed ok. + Programming of 8 bytes at address 0x08012E80 performed ok. + Programming of 8 bytes at address 0x08012E88 performed ok. + Programming of 8 bytes at address 0x08012E90 performed ok. +k. + Programming of 8 bytes at address 0x08012EA0 performed ok. + Programming of 8 bytes at address 0x08012EA8 performed ok. + Programming of 8 bytes at address 0x08012EB0 performed ok. + Programming of 8 bytes at address 0x08012EB8 performed ok. + Programming of 8 bytes at address 0x08012EC0 performed ok. + Programming of 8 bytes at address 0x08012EC8 performed ok. + Programming of 8 bytes at address 0x08012ED0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08012F00 performed ok. + Programming of 8 bytes at address 0x08012F08 performed ok. + Programming of 8 bytes at address 0x08012F10 performed ok. + Programming of 8 bytes at address 0x08012F18 performed ok. + Programming of 8 bytes at address 0x08012F20 performed ok. + Programming of 8 bytes at address 0x08012F28 performed ok. + Programming of 8 bytes at address 0x08012F30 performed ok. + Programming of 8 bytes at address 0x08012F38 performed ok. + Programming of 8 bytes at address 0x08012F40 performed ok. + Programming of 8 bytes at address 0x08012F48 performed ok. + Programming of 8 bytes at address 0x08012F50 performed ok. + Programming of 8 bytes at address 0x08012F58 performed ok. + Programming of 8 bytes at address 0x08012F60 performed ok. + Programming of 8 bytes at address 0x08012F68 performed ok. + Programming of 8 bytes at address 0x08012F70 performed ok. + Programming of 8 bytes at address 0x08012F78 performed ok. + Programming of 8 bytes at address 0x08012F80 performed ok. + Programming of 8 bytes at address 0x08012F88 performed ok. + Programming of 8 bytes at address 0x08012F90 performed ok. + Programming of 8 bytes at address 0x08012F98 performed ok. + Programming of 8 bytes at address 0x08012FA0 performed ok. + Programming of 8 bytes at address 0x08012FA8 performed ok. + Programming of 8 bytes at address 0x08012FB0 performed ok. + Programming of 8 bytes at address 0x08012FB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08012FF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013000 performed ok. + Programming of 8 bytes at address 0x08013008 performed ok. + Programming of 8 bytes at address 0x08013010 performed ok. + Programming of 8 bytes at address 0x08013018 performed ok. + Programming of 8 bytes at address 0x08013020 performed ok. + Programming of 8 bytes at address 0x08013028 performed ok. + Programming of 8 bytes at address 0x08013030 performed ok. + Programming of 8 bytes at address 0x08013038 performed ok. + Programming of 8 bytes at address 0x08013040 performed ok. + Programming of 8 bytes at address 0x08013048 performed ok. + Programming of 8 bytes at address 0x08013050 performed ok. + Programming of 8 bytes at address 0x08013058 performed ok. + Programming of 8 bytes at address 0x08013060 performed ok. + Programming of 8 bytes at address 0x08013068 performed ok. + Programming of 8 bytes at address 0x08013070 performed ok. + Programming of 8 bytes at address 0x08013078 performed ok. + Programming of 8 bytes at address 0x08013080 performed ok. + Programming of 8 bytes at address 0x08013088 performed ok. + Programming of 8 bytes at address 0x08013090 performed ok. + Programming of 8 bytes at address 0x08013098 performed ok. + Programming of 8 bytes at address 0x080130A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080130C0 performed ok. + Programming of 8 bytes at address 0x080130C8 performed ok. + Programming of 8 bytes at address 0x080130D0 performed ok. + Programming of 8 bytes at address 0x080130D8 performed ok. + Programming of 8 bytes at address 0x080130E0 performed ok. + Programming of 8 bytes at address 0x080130E8 performed ok. + Programming of 8 bytes at address 0x080130F0 performed ok. + Programming of 8 bytes at address 0x080130F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013100 performed ok. + Programming of 8 bytes at address 0x08013108 performed ok. + Programming of 8 bytes at address 0x08013110 performed ok. + Programming of 8 bytes at address 0x08013118 performed ok. + Programming of 8 bytes at address 0x08013120 performed ok. + Programming of 8 bytes at address 0x08013128 performed ok. + Programming of 8 bytes at address 0x08013130 performed ok. + Programming of 8 bytes at address 0x08013138 performed ok. + Programming of 8 bytes at address 0x08013140 performed ok. + Programming of 8 bytes at address 0x08013148 performed ok. + Programming of 8 bytes at address 0x08013150 performed ok. + Programming of 8 bytes at address 0x08013158 performed ok. + Programming of 8 bytes at address 0x08013160 performed ok. + Programming of 8 bytes at address 0x08013168 performed ok. + Programming of 8 bytes at address 0x08013170 performed ok. + Programming of 8 bytes at address 0x08013178 performed ok. + Programming of 8 bytes at address 0x08013180 performed ok. + Programming of 8 bytes at address 0x08013188 performed ok. + Programming of 8 bytes at address 0x08013190 performed ok. + Programming of 8 bytes at address 0x08013198 performed ok. + Programming of 8 bytes at address 0x080131A0 performed ok. + Programming of 8 bytes at address 0x080131A8 performed ok. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080131D8 performed ok. + Programming of 8 bytes at address 0x080131E0 performed ok. + Programming of 8 bytes at address 0x080131E8 performed ok. + Programming of 8 bytes at address 0x080131F0 performed ok. + Programming of 8 bytes at address 0x080131F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013200 performed ok. + Programming of 8 bytes at address 0x08013208 performed ok. + Programming of 8 bytes at address 0x08013210 performed ok. + Programming of 8 bytes at address 0x08013218 performed ok. + Programming of 8 bytes at address 0x08013220 performed ok. + Programming of 8 bytes at address 0x08013228 performed ok. + Programming of 8 bytes at address 0x08013230 performed ok. + Programming of 8 bytes at address 0x08013238 performed ok. + Programming of 8 bytes at address 0x08013240 performed ok. + Programming of 8 bytes at address 0x08013248 performed ok. + Programming of 8 bytes at address 0x08013250 performed ok. + Programming of 8 bytes at address 0x08013258 performed ok. + Programming of 8 bytes at address 0x08013260 performed ok. + Programming of 8 bytes at address 0x08013268 performed ok. + Programming of 8 bytes at address 0x08013270 performed ok. + Programming of 8 bytes at address 0x08013278 performed ok. + Programming of 8 bytes at address 0x08013280 performed ok. + Programming of 8 bytes at address 0x08013288 performed ok. + Programming of 8 bytes at address 0x08013290 performed ok. + Programming of 8 bytes at address 0x08013298 performed ok. +k. + Programming of 8 bytes at address 0x080132A8 performed ok. + Programming of 8 bytes at address 0x080132B0 performed ok. + Programming of 8 bytes at address 0x080132B8 performed ok. + Programming of 8 bytes at address 0x080132C0 performed ok. + Programming of 8 bytes at address 0x080132C8 performed ok. + Programming of 8 bytes at address 0x080132D0 performed ok. + Programming of 8 bytes at address 0x080132D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013300 performed ok. + Programming of 8 bytes at address 0x08013308 performed ok. + Programming of 8 bytes at address 0x08013310 performed ok. + Programming of 8 bytes at address 0x08013318 performed ok. + Programming of 8 bytes at address 0x08013320 performed ok. + Programming of 8 bytes at address 0x08013328 performed ok. + Programming of 8 bytes at address 0x08013330 performed ok. + Programming of 8 bytes at address 0x08013338 performed ok. + Programming of 8 bytes at address 0x08013340 performed ok. + Programming of 8 bytes at address 0x08013348 performed ok. + Programming of 8 bytes at address 0x08013350 performed ok. + Programming of 8 bytes at address 0x08013358 performed ok. + Programming of 8 bytes at address 0x08013360 performed ok. + Programming of 8 bytes at address 0x08013368 performed ok. + Programming of 8 bytes at address 0x08013370 performed ok. + Programming of 8 bytes at address 0x08013378 performed ok. + Programming of 8 bytes at address 0x08013380 performed ok. + Programming of 8 bytes at address 0x08013388 performed ok. + Programming of 8 bytes at address 0x08013390 performed ok. + Programming of 8 bytes at address 0x08013398 performed ok. + Programming of 8 bytes at address 0x080133A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080133C0 performed ok. + Programming of 8 bytes at address 0x080133C8 performed ok. + Programming of 8 bytes at address 0x080133D0 performed ok. + Programming of 8 bytes at address 0x080133D8 performed ok. + Programming of 8 bytes at address 0x080133E0 performed ok. + Programming of 8 bytes at address 0x080133E8 performed ok. + Programming of 8 bytes at address 0x080133F0 performed ok. + Programming of 8 bytes at address 0x080133F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013400 performed ok. + Programming of 8 bytes at address 0x08013408 performed ok. + Programming of 8 bytes at address 0x08013410 performed ok. + Programming of 8 bytes at address 0x08013418 performed ok. + Programming of 8 bytes at address 0x08013420 performed ok. + Programming of 8 bytes at address 0x08013428 performed ok. + Programming of 8 bytes at address 0x08013430 performed ok. + Programming of 8 bytes at address 0x08013438 performed ok. + Programming of 8 bytes at address 0x08013440 performed ok. + Programming of 8 bytes at address 0x08013448 performed ok. + Programming of 8 bytes at address 0x08013450 performed ok. + Programming of 8 bytes at address 0x08013458 performed ok. + Programming of 8 bytes at address 0x08013460 performed ok. + Programming of 8 bytes at address 0x08013468 performed ok. + Programming of 8 bytes at address 0x08013470 performed ok. + Programming of 8 bytes at address 0x08013478 performed ok. + Programming of 8 bytes at address 0x08013480 performed ok. + Programming of 8 bytes at address 0x08013488 performed ok. + Programming of 8 bytes at address 0x08013490 performed ok. +k. + Programming of 8 bytes at address 0x080134A0 performed ok. + Programming of 8 bytes at address 0x080134A8 performed ok. + Programming of 8 bytes at address 0x080134B0 performed ok. + Programming of 8 bytes at address 0x080134B8 performed ok. + Programming of 8 bytes at address 0x080134C0 performed ok. + Programming of 8 bytes at address 0x080134C8 performed ok. + Programming of 8 bytes at address 0x080134D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013500 performed ok. + Programming of 8 bytes at address 0x08013508 performed ok. + Programming of 8 bytes at address 0x08013510 performed ok. + Programming of 8 bytes at address 0x08013518 performed ok. + Programming of 8 bytes at address 0x08013520 performed ok. + Programming of 8 bytes at address 0x08013528 performed ok. + Programming of 8 bytes at address 0x08013530 performed ok. + Programming of 8 bytes at address 0x08013538 performed ok. + Programming of 8 bytes at address 0x08013540 performed ok. + Programming of 8 bytes at address 0x08013548 performed ok. + Programming of 8 bytes at address 0x08013550 performed ok. + Programming of 8 bytes at address 0x08013558 performed ok. + Programming of 8 bytes at address 0x08013560 performed ok. + Programming of 8 bytes at address 0x08013568 performed ok. + Programming of 8 bytes at address 0x08013570 performed ok. + Programming of 8 bytes at address 0x08013578 performed ok. + Programming of 8 bytes at address 0x08013580 performed ok. + Programming of 8 bytes at address 0x08013588 performed ok. + Programming of 8 bytes at address 0x08013590 performed ok. +k. + Programming of 8 bytes at address 0x080135A0 performed ok. + Programming of 8 bytes at address 0x080135A8 performed ok. + Programming of 8 bytes at address 0x080135B0 performed ok. + Programming of 8 bytes at address 0x080135B8 performed ok. + Programming of 8 bytes at address 0x080135C0 performed ok. + Programming of 8 bytes at address 0x080135C8 performed ok. + Programming of 8 bytes at address 0x080135D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013600 performed ok. + Programming of 8 bytes at address 0x08013608 performed ok. + Programming of 8 bytes at address 0x08013610 performed ok. + Programming of 8 bytes at address 0x08013618 performed ok. + Programming of 8 bytes at address 0x08013620 performed ok. + Programming of 8 bytes at address 0x08013628 performed ok. + Programming of 8 bytes at address 0x08013630 performed ok. + Programming of 8 bytes at address 0x08013638 performed ok. + Programming of 8 bytes at address 0x08013640 performed ok. + Programming of 8 bytes at address 0x08013648 performed ok. + Programming of 8 bytes at address 0x08013650 performed ok. + Programming of 8 bytes at address 0x08013658 performed ok. + Programming of 8 bytes at address 0x08013660 performed ok. + Programming of 8 bytes at address 0x08013668 performed ok. + Programming of 8 bytes at address 0x08013670 performed ok. + Programming of 8 bytes at address 0x08013678 performed ok. + Programming of 8 bytes at address 0x08013680 performed ok. + Programming of 8 bytes at address 0x08013688 performed ok. + Programming of 8 bytes at address 0x08013690 performed ok. +k. + Programming of 8 bytes at address 0x080136A0 performed ok. + Programming of 8 bytes at address 0x080136A8 performed ok. + Programming of 8 bytes at address 0x080136B0 performed ok. + Programming of 8 bytes at address 0x080136B8 performed ok. + Programming of 8 bytes at address 0x080136C0 performed ok. + Programming of 8 bytes at address 0x080136C8 performed ok. + Programming of 8 bytes at address 0x080136D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013700 performed ok. + Programming of 8 bytes at address 0x08013708 performed ok. + Programming of 8 bytes at address 0x08013710 performed ok. + Programming of 8 bytes at address 0x08013718 performed ok. + Programming of 8 bytes at address 0x08013720 performed ok. + Programming of 8 bytes at address 0x08013728 performed ok. + Programming of 8 bytes at address 0x08013730 performed ok. + Programming of 8 bytes at address 0x08013738 performed ok. + Programming of 8 bytes at address 0x08013740 performed ok. + Programming of 8 bytes at address 0x08013748 performed ok. + Programming of 8 bytes at address 0x08013750 performed ok. + Programming of 8 bytes at address 0x08013758 performed ok. + Programming of 8 bytes at address 0x08013760 performed ok. + Programming of 8 bytes at address 0x08013768 performed ok. + Programming of 8 bytes at address 0x08013770 performed ok. + Programming of 8 bytes at address 0x08013778 performed ok. + Programming of 8 bytes at address 0x08013780 performed ok. + Programming of 8 bytes at address 0x08013788 performed ok. + Programming of 8 bytes at address 0x08013790 performed ok. + Programming of 8 bytes at address 0x08013798 performed ok. + Programming of 8 bytes at address 0x080137A0 performed ok. + Programming of 8 bytes at address 0x080137A8 performed ok. + Programming of 8 bytes at address 0x080137B0 performed ok. + Programming of 8 bytes at address 0x080137B8 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080137E0 performed ok. + Programming of 8 bytes at address 0x080137E8 performed ok. + Programming of 8 bytes at address 0x080137F0 performed ok. + Programming of 8 bytes at address 0x080137F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013800 performed ok. + Programming of 8 bytes at address 0x08013808 performed ok. + Programming of 8 bytes at address 0x08013810 performed ok. + Programming of 8 bytes at address 0x08013818 performed ok. + Programming of 8 bytes at address 0x08013820 performed ok. + Programming of 8 bytes at address 0x08013828 performed ok. + Programming of 8 bytes at address 0x08013830 performed ok. + Programming of 8 bytes at address 0x08013838 performed ok. + Programming of 8 bytes at address 0x08013840 performed ok. + Programming of 8 bytes at address 0x08013848 performed ok. + Programming of 8 bytes at address 0x08013850 performed ok. + Programming of 8 bytes at address 0x08013858 performed ok. + Programming of 8 bytes at address 0x08013860 performed ok. + Programming of 8 bytes at address 0x08013868 performed ok. + Programming of 8 bytes at address 0x08013870 performed ok. + Programming of 8 bytes at address 0x08013878 performed ok. + Programming of 8 bytes at address 0x08013880 performed ok. + Programming of 8 bytes at address 0x08013888 performed ok. + Programming of 8 bytes at address 0x08013890 performed ok. +k. + Programming of 8 bytes at address 0x080138A0 performed ok. + Programming of 8 bytes at address 0x080138A8 performed ok. + Programming of 8 bytes at address 0x080138B0 performed ok. + Programming of 8 bytes at address 0x080138B8 performed ok. + Programming of 8 bytes at address 0x080138C0 performed ok. + Programming of 8 bytes at address 0x080138C8 performed ok. + Programming of 8 bytes at address 0x080138D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013900 performed ok. + Programming of 8 bytes at address 0x08013908 performed ok. + Programming of 8 bytes at address 0x08013910 performed ok. + Programming of 8 bytes at address 0x08013918 performed ok. + Programming of 8 bytes at address 0x08013920 performed ok. + Programming of 8 bytes at address 0x08013928 performed ok. + Programming of 8 bytes at address 0x08013930 performed ok. + Programming of 8 bytes at address 0x08013938 performed ok. + Programming of 8 bytes at address 0x08013940 performed ok. + Programming of 8 bytes at address 0x08013948 performed ok. + Programming of 8 bytes at address 0x08013950 performed ok. + Programming of 8 bytes at address 0x08013958 performed ok. + Programming of 8 bytes at address 0x08013960 performed ok. + Programming of 8 bytes at address 0x08013968 performed ok. + Programming of 8 bytes at address 0x08013970 performed ok. + Programming of 8 bytes at address 0x08013978 performed ok. + Programming of 8 bytes at address 0x08013980 performed ok. + Programming of 8 bytes at address 0x08013988 performed ok. + Programming of 8 bytes at address 0x08013990 performed ok. +k. + Programming of 8 bytes at address 0x080139A0 performed ok. + Programming of 8 bytes at address 0x080139A8 performed ok. + Programming of 8 bytes at address 0x080139B0 performed ok. + Programming of 8 bytes at address 0x080139B8 performed ok. + Programming of 8 bytes at address 0x080139C0 performed ok. + Programming of 8 bytes at address 0x080139C8 performed ok. + Programming of 8 bytes at address 0x080139D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013A00 performed ok. + Programming of 8 bytes at address 0x08013A08 performed ok. + Programming of 8 bytes at address 0x08013A10 performed ok. + Programming of 8 bytes at address 0x08013A18 performed ok. + Programming of 8 bytes at address 0x08013A20 performed ok. + Programming of 8 bytes at address 0x08013A28 performed ok. + Programming of 8 bytes at address 0x08013A30 performed ok. + Programming of 8 bytes at address 0x08013A38 performed ok. + Programming of 8 bytes at address 0x08013A40 performed ok. + Programming of 8 bytes at address 0x08013A48 performed ok. + Programming of 8 bytes at address 0x08013A50 performed ok. + Programming of 8 bytes at address 0x08013A58 performed ok. + Programming of 8 bytes at address 0x08013A60 performed ok. + Programming of 8 bytes at address 0x08013A68 performed ok. + Programming of 8 bytes at address 0x08013A70 performed ok. + Programming of 8 bytes at address 0x08013A78 performed ok. + Programming of 8 bytes at address 0x08013A80 performed ok. + Programming of 8 bytes at address 0x08013A88 performed ok. + Programming of 8 bytes at address 0x08013A90 performed ok. +k. + Programming of 8 bytes at address 0x08013AA0 performed ok. + Programming of 8 bytes at address 0x08013AA8 performed ok. + Programming of 8 bytes at address 0x08013AB0 performed ok. + Programming of 8 bytes at address 0x08013AB8 performed ok. + Programming of 8 bytes at address 0x08013AC0 performed ok. + Programming of 8 bytes at address 0x08013AC8 performed ok. + Programming of 8 bytes at address 0x08013AD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013B00 performed ok. + Programming of 8 bytes at address 0x08013B08 performed ok. + Programming of 8 bytes at address 0x08013B10 performed ok. + Programming of 8 bytes at address 0x08013B18 performed ok. + Programming of 8 bytes at address 0x08013B20 performed ok. + Programming of 8 bytes at address 0x08013B28 performed ok. + Programming of 8 bytes at address 0x08013B30 performed ok. + Programming of 8 bytes at address 0x08013B38 performed ok. + Programming of 8 bytes at address 0x08013B40 performed ok. + Programming of 8 bytes at address 0x08013B48 performed ok. + Programming of 8 bytes at address 0x08013B50 performed ok. + Programming of 8 bytes at address 0x08013B58 performed ok. + Programming of 8 bytes at address 0x08013B60 performed ok. + Programming of 8 bytes at address 0x08013B68 performed ok. + Programming of 8 bytes at address 0x08013B70 performed ok. + Programming of 8 bytes at address 0x08013B78 performed ok. + Programming of 8 bytes at address 0x08013B80 performed ok. + Programming of 8 bytes at address 0x08013B88 performed ok. + Programming of 8 bytes at address 0x08013B90 performed ok. + Programming of 8 bytes at address 0x08013B98 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08013BB8 performed ok. + Programming of 8 bytes at address 0x08013BC0 performed ok. + Programming of 8 bytes at address 0x08013BC8 performed ok. + Programming of 8 bytes at address 0x08013BD0 performed ok. + Programming of 8 bytes at address 0x08013BD8 performed ok. + Programming of 8 bytes at address 0x08013BE0 performed ok. + Programming of 8 bytes at address 0x08013BE8 performed ok. + Programming of 8 bytes at address 0x08013BF0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013C00 performed ok. + Programming of 8 bytes at address 0x08013C08 performed ok. + Programming of 8 bytes at address 0x08013C10 performed ok. + Programming of 8 bytes at address 0x08013C18 performed ok. + Programming of 8 bytes at address 0x08013C20 performed ok. + Programming of 8 bytes at address 0x08013C28 performed ok. + Programming of 8 bytes at address 0x08013C30 performed ok. + Programming of 8 bytes at address 0x08013C38 performed ok. + Programming of 8 bytes at address 0x08013C40 performed ok. + Programming of 8 bytes at address 0x08013C48 performed ok. + Programming of 8 bytes at address 0x08013C50 performed ok. + Programming of 8 bytes at address 0x08013C58 performed ok. + Programming of 8 bytes at address 0x08013C60 performed ok. + Programming of 8 bytes at address 0x08013C68 performed ok. + Programming of 8 bytes at address 0x08013C70 performed ok. + Programming of 8 bytes at address 0x08013C78 performed ok. + Programming of 8 bytes at address 0x08013C80 performed ok. + Programming of 8 bytes at address 0x08013C88 performed ok. + Programming of 8 bytes at address 0x08013C90 performed ok. + Programming of 8 bytes at address 0x08013C98 performed ok. + Programming of 8 bytes at address 0x08013CA0 performed ok. + Programming of 8 bytes at address 0x08013CA8 performed ok. + Programming of 8 bytes at address 0x08013CB0 performed ok. + Programming of 8 bytes at address 0x08013CB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08013CF0 performed ok. + Programming of 8 bytes at address 0x08013CF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013D00 performed ok. + Programming of 8 bytes at address 0x08013D08 performed ok. + Programming of 8 bytes at address 0x08013D10 performed ok. + Programming of 8 bytes at address 0x08013D18 performed ok. + Programming of 8 bytes at address 0x08013D20 performed ok. + Programming of 8 bytes at address 0x08013D28 performed ok. + Programming of 8 bytes at address 0x08013D30 performed ok. + Programming of 8 bytes at address 0x08013D38 performed ok. + Programming of 8 bytes at address 0x08013D40 performed ok. + Programming of 8 bytes at address 0x08013D48 performed ok. + Programming of 8 bytes at address 0x08013D50 performed ok. + Programming of 8 bytes at address 0x08013D58 performed ok. + Programming of 8 bytes at address 0x08013D60 performed ok. + Programming of 8 bytes at address 0x08013D68 performed ok. + Programming of 8 bytes at address 0x08013D70 performed ok. + Programming of 8 bytes at address 0x08013D78 performed ok. + Programming of 8 bytes at address 0x08013D80 performed ok. + Programming of 8 bytes at address 0x08013D88 performed ok. + Programming of 8 bytes at address 0x08013D90 performed ok. + Programming of 8 bytes at address 0x08013D98 performed ok. + Programming of 8 bytes at address 0x08013DA0 performed ok. + Programming of 8 bytes at address 0x08013DA8 performed ok. + Programming of 8 bytes at address 0x08013DB0 performed ok. + Programming of 8 bytes at address 0x08013DB8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013E00 performed ok. + Programming of 8 bytes at address 0x08013E08 performed ok. + Programming of 8 bytes at address 0x08013E10 performed ok. + Programming of 8 bytes at address 0x08013E18 performed ok. + Programming of 8 bytes at address 0x08013E20 performed ok. + Programming of 8 bytes at address 0x08013E28 performed ok. + Programming of 8 bytes at address 0x08013E30 performed ok. + Programming of 8 bytes at address 0x08013E38 performed ok. + Programming of 8 bytes at address 0x08013E40 performed ok. + Programming of 8 bytes at address 0x08013E48 performed ok. + Programming of 8 bytes at address 0x08013E50 performed ok. + Programming of 8 bytes at address 0x08013E58 performed ok. + Programming of 8 bytes at address 0x08013E60 performed ok. + Programming of 8 bytes at address 0x08013E68 performed ok. + Programming of 8 bytes at address 0x08013E70 performed ok. + Programming of 8 bytes at address 0x08013E78 performed ok. + Programming of 8 bytes at address 0x08013E80 performed ok. + Programming of 8 bytes at address 0x08013E88 performed ok. + Programming of 8 bytes at address 0x08013E90 performed ok. + Programming of 8 bytes at address 0x08013E98 performed ok. + Programming of 8 bytes at address 0x08013EA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08013EC0 performed ok. + Programming of 8 bytes at address 0x08013EC8 performed ok. + Programming of 8 bytes at address 0x08013ED0 performed ok. + Programming of 8 bytes at address 0x08013ED8 performed ok. + Programming of 8 bytes at address 0x08013EE0 performed ok. + Programming of 8 bytes at address 0x08013EE8 performed ok. + Programming of 8 bytes at address 0x08013EF0 performed ok. + Programming of 8 bytes at address 0x08013EF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08013F00 performed ok. + Programming of 8 bytes at address 0x08013F08 performed ok. + Programming of 8 bytes at address 0x08013F10 performed ok. + Programming of 8 bytes at address 0x08013F18 performed ok. + Programming of 8 bytes at address 0x08013F20 performed ok. + Programming of 8 bytes at address 0x08013F28 performed ok. + Programming of 8 bytes at address 0x08013F30 performed ok. + Programming of 8 bytes at address 0x08013F38 performed ok. + Programming of 8 bytes at address 0x08013F40 performed ok. + Programming of 8 bytes at address 0x08013F48 performed ok. + Programming of 8 bytes at address 0x08013F50 performed ok. + Programming of 8 bytes at address 0x08013F58 performed ok. + Programming of 8 bytes at address 0x08013F60 performed ok. + Programming of 8 bytes at address 0x08013F68 performed ok. + Programming of 8 bytes at address 0x08013F70 performed ok. + Programming of 8 bytes at address 0x08013F78 performed ok. + Programming of 8 bytes at address 0x08013F80 performed ok. + Programming of 8 bytes at address 0x08013F88 performed ok. + Programming of 8 bytes at address 0x08013F90 performed ok. + Programming of 8 bytes at address 0x08013F98 performed ok. + Programming of 8 bytes at address 0x08013FA0 performed ok. + Programming of 8 bytes at address 0x08013FA8 performed ok. + Programming of 8 bytes at address 0x08013FB0 performed ok. + Programming of 8 bytes at address 0x08013FB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08013FF0 performed ok. + Programming of 8 bytes at address 0x08013FF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014000 performed ok. + Programming of 8 bytes at address 0x08014008 performed ok. + Programming of 8 bytes at address 0x08014010 performed ok. + Programming of 8 bytes at address 0x08014018 performed ok. + Programming of 8 bytes at address 0x08014020 performed ok. + Programming of 8 bytes at address 0x08014028 performed ok. + Programming of 8 bytes at address 0x08014030 performed ok. + Programming of 8 bytes at address 0x08014038 performed ok. + Programming of 8 bytes at address 0x08014040 performed ok. + Programming of 8 bytes at address 0x08014048 performed ok. + Programming of 8 bytes at address 0x08014050 performed ok. + Programming of 8 bytes at address 0x08014058 performed ok. + Programming of 8 bytes at address 0x08014060 performed ok. + Programming of 8 bytes at address 0x08014068 performed ok. + Programming of 8 bytes at address 0x08014070 performed ok. + Programming of 8 bytes at address 0x08014078 performed ok. + Programming of 8 bytes at address 0x08014080 performed ok. + Programming of 8 bytes at address 0x08014088 performed ok. + Programming of 8 bytes at address 0x08014090 performed ok. + Programming of 8 bytes at address 0x08014098 performed ok. + Programming of 8 bytes at address 0x080140A0 performed ok. + Programming of 8 bytes at address 0x080140A8 performed ok. + Programming of 8 bytes at address 0x080140B0 performed ok. + Programming of 8 bytes at address 0x080140B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080140F0 performed ok. + Programming of 8 bytes at address 0x080140F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014100 performed ok. + Programming of 8 bytes at address 0x08014108 performed ok. + Programming of 8 bytes at address 0x08014110 performed ok. + Programming of 8 bytes at address 0x08014118 performed ok. + Programming of 8 bytes at address 0x08014120 performed ok. + Programming of 8 bytes at address 0x08014128 performed ok. + Programming of 8 bytes at address 0x08014130 performed ok. + Programming of 8 bytes at address 0x08014138 performed ok. + Programming of 8 bytes at address 0x08014140 performed ok. + Programming of 8 bytes at address 0x08014148 performed ok. + Programming of 8 bytes at address 0x08014150 performed ok. + Programming of 8 bytes at address 0x08014158 performed ok. + Programming of 8 bytes at address 0x08014160 performed ok. + Programming of 8 bytes at address 0x08014168 performed ok. + Programming of 8 bytes at address 0x08014170 performed ok. + Programming of 8 bytes at address 0x08014178 performed ok. + Programming of 8 bytes at address 0x08014180 performed ok. + Programming of 8 bytes at address 0x08014188 performed ok. + Programming of 8 bytes at address 0x08014190 performed ok. + Programming of 8 bytes at address 0x08014198 performed ok. + Programming of 8 bytes at address 0x080141A0 performed ok. + Programming of 8 bytes at address 0x080141A8 performed ok. + Programming of 8 bytes at address 0x080141B0 performed ok. + Programming of 8 bytes at address 0x080141B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080141F0 performed ok. + Programming of 8 bytes at address 0x080141F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014200 performed ok. + Programming of 8 bytes at address 0x08014208 performed ok. + Programming of 8 bytes at address 0x08014210 performed ok. + Programming of 8 bytes at address 0x08014218 performed ok. + Programming of 8 bytes at address 0x08014220 performed ok. + Programming of 8 bytes at address 0x08014228 performed ok. + Programming of 8 bytes at address 0x08014230 performed ok. + Programming of 8 bytes at address 0x08014238 performed ok. + Programming of 8 bytes at address 0x08014240 performed ok. + Programming of 8 bytes at address 0x08014248 performed ok. + Programming of 8 bytes at address 0x08014250 performed ok. + Programming of 8 bytes at address 0x08014258 performed ok. + Programming of 8 bytes at address 0x08014260 performed ok. + Programming of 8 bytes at address 0x08014268 performed ok. + Programming of 8 bytes at address 0x08014270 performed ok. + Programming of 8 bytes at address 0x08014278 performed ok. + Programming of 8 bytes at address 0x08014280 performed ok. + Programming of 8 bytes at address 0x08014288 performed ok. + Programming of 8 bytes at address 0x08014290 performed ok. + Programming of 8 bytes at address 0x08014298 performed ok. +k. + Programming of 8 bytes at address 0x080142A8 performed ok. + Programming of 8 bytes at address 0x080142B0 performed ok. + Programming of 8 bytes at address 0x080142B8 performed ok. + Programming of 8 bytes at address 0x080142C0 performed ok. + Programming of 8 bytes at address 0x080142C8 performed ok. + Programming of 8 bytes at address 0x080142D0 performed ok. + Programming of 8 bytes at address 0x080142D8 performed ok. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014300 performed ok. + Programming of 8 bytes at address 0x08014308 performed ok. + Programming of 8 bytes at address 0x08014310 performed ok. + Programming of 8 bytes at address 0x08014318 performed ok. + Programming of 8 bytes at address 0x08014320 performed ok. + Programming of 8 bytes at address 0x08014328 performed ok. + Programming of 8 bytes at address 0x08014330 performed ok. + Programming of 8 bytes at address 0x08014338 performed ok. + Programming of 8 bytes at address 0x08014340 performed ok. + Programming of 8 bytes at address 0x08014348 performed ok. + Programming of 8 bytes at address 0x08014350 performed ok. + Programming of 8 bytes at address 0x08014358 performed ok. + Programming of 8 bytes at address 0x08014360 performed ok. + Programming of 8 bytes at address 0x08014368 performed ok. + Programming of 8 bytes at address 0x08014370 performed ok. + Programming of 8 bytes at address 0x08014378 performed ok. + Programming of 8 bytes at address 0x08014380 performed ok. + Programming of 8 bytes at address 0x08014388 performed ok. + Programming of 8 bytes at address 0x08014390 performed ok. + Programming of 8 bytes at address 0x08014398 performed ok. +k. + Programming of 8 bytes at address 0x080143A8 performed ok. + Programming of 8 bytes at address 0x080143B0 performed ok. + Programming of 8 bytes at address 0x080143B8 performed ok. + Programming of 8 bytes at address 0x080143C0 performed ok. + Programming of 8 bytes at address 0x080143C8 performed ok. + Programming of 8 bytes at address 0x080143D0 performed ok. + Programming of 8 bytes at address 0x080143D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014400 performed ok. + Programming of 8 bytes at address 0x08014408 performed ok. + Programming of 8 bytes at address 0x08014410 performed ok. + Programming of 8 bytes at address 0x08014418 performed ok. + Programming of 8 bytes at address 0x08014420 performed ok. + Programming of 8 bytes at address 0x08014428 performed ok. + Programming of 8 bytes at address 0x08014430 performed ok. + Programming of 8 bytes at address 0x08014438 performed ok. + Programming of 8 bytes at address 0x08014440 performed ok. + Programming of 8 bytes at address 0x08014448 performed ok. + Programming of 8 bytes at address 0x08014450 performed ok. + Programming of 8 bytes at address 0x08014458 performed ok. + Programming of 8 bytes at address 0x08014460 performed ok. + Programming of 8 bytes at address 0x08014468 performed ok. + Programming of 8 bytes at address 0x08014470 performed ok. + Programming of 8 bytes at address 0x08014478 performed ok. + Programming of 8 bytes at address 0x08014480 performed ok. + Programming of 8 bytes at address 0x08014488 performed ok. + Programming of 8 bytes at address 0x08014490 performed ok. + Programming of 8 bytes at address 0x08014498 performed ok. +k. + Programming of 8 bytes at address 0x080144A8 performed ok. + Programming of 8 bytes at address 0x080144B0 performed ok. + Programming of 8 bytes at address 0x080144B8 performed ok. + Programming of 8 bytes at address 0x080144C0 performed ok. + Programming of 8 bytes at address 0x080144C8 performed ok. + Programming of 8 bytes at address 0x080144D0 performed ok. + Programming of 8 bytes at address 0x080144D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014500 performed ok. + Programming of 8 bytes at address 0x08014508 performed ok. + Programming of 8 bytes at address 0x08014510 performed ok. + Programming of 8 bytes at address 0x08014518 performed ok. + Programming of 8 bytes at address 0x08014520 performed ok. + Programming of 8 bytes at address 0x08014528 performed ok. + Programming of 8 bytes at address 0x08014530 performed ok. + Programming of 8 bytes at address 0x08014538 performed ok. + Programming of 8 bytes at address 0x08014540 performed ok. + Programming of 8 bytes at address 0x08014548 performed ok. + Programming of 8 bytes at address 0x08014550 performed ok. + Programming of 8 bytes at address 0x08014558 performed ok. + Programming of 8 bytes at address 0x08014560 performed ok. + Programming of 8 bytes at address 0x08014568 performed ok. + Programming of 8 bytes at address 0x08014570 performed ok. + Programming of 8 bytes at address 0x08014578 performed ok. + Programming of 8 bytes at address 0x08014580 performed ok. + Programming of 8 bytes at address 0x08014588 performed ok. + Programming of 8 bytes at address 0x08014590 performed ok. + Programming of 8 bytes at address 0x08014598 performed ok. + Programming of 8 bytes at address 0x080145A0 performed ok. + Programming of 8 bytes at address 0x080145A8 performed ok. + Programming of 8 bytes at address 0x080145B0 performed ok. + Programming of 8 bytes at address 0x080145B8 performed ok. + Programming of 8 bytes at address 0x080145C0 performed ok. + Programming of 8 bytes at address 0x080145C8 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014600 performed ok. + Programming of 8 bytes at address 0x08014608 performed ok. + Programming of 8 bytes at address 0x08014610 performed ok. + Programming of 8 bytes at address 0x08014618 performed ok. + Programming of 8 bytes at address 0x08014620 performed ok. + Programming of 8 bytes at address 0x08014628 performed ok. + Programming of 8 bytes at address 0x08014630 performed ok. + Programming of 8 bytes at address 0x08014638 performed ok. + Programming of 8 bytes at address 0x08014640 performed ok. + Programming of 8 bytes at address 0x08014648 performed ok. + Programming of 8 bytes at address 0x08014650 performed ok. + Programming of 8 bytes at address 0x08014658 performed ok. + Programming of 8 bytes at address 0x08014660 performed ok. + Programming of 8 bytes at address 0x08014668 performed ok. + Programming of 8 bytes at address 0x08014670 performed ok. + Programming of 8 bytes at address 0x08014678 performed ok. + Programming of 8 bytes at address 0x08014680 performed ok. + Programming of 8 bytes at address 0x08014688 performed ok. + Programming of 8 bytes at address 0x08014690 performed ok. + Programming of 8 bytes at address 0x08014698 performed ok. + Programming of 8 bytes at address 0x080146A0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080146C8 performed ok. + Programming of 8 bytes at address 0x080146D0 performed ok. + Programming of 8 bytes at address 0x080146D8 performed ok. + Programming of 8 bytes at address 0x080146E0 performed ok. + Programming of 8 bytes at address 0x080146E8 performed ok. + Programming of 8 bytes at address 0x080146F0 performed ok. + Programming of 8 bytes at address 0x080146F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014700 performed ok. + Programming of 8 bytes at address 0x08014708 performed ok. + Programming of 8 bytes at address 0x08014710 performed ok. + Programming of 8 bytes at address 0x08014718 performed ok. + Programming of 8 bytes at address 0x08014720 performed ok. + Programming of 8 bytes at address 0x08014728 performed ok. + Programming of 8 bytes at address 0x08014730 performed ok. + Programming of 8 bytes at address 0x08014738 performed ok. + Programming of 8 bytes at address 0x08014740 performed ok. + Programming of 8 bytes at address 0x08014748 performed ok. + Programming of 8 bytes at address 0x08014750 performed ok. + Programming of 8 bytes at address 0x08014758 performed ok. + Programming of 8 bytes at address 0x08014760 performed ok. + Programming of 8 bytes at address 0x08014768 performed ok. + Programming of 8 bytes at address 0x08014770 performed ok. + Programming of 8 bytes at address 0x08014778 performed ok. + Programming of 8 bytes at address 0x08014780 performed ok. + Programming of 8 bytes at address 0x08014788 performed ok. + Programming of 8 bytes at address 0x08014790 performed ok. + Programming of 8 bytes at address 0x08014798 performed ok. + Programming of 8 bytes at address 0x080147A0 performed ok. + Programming of 8 bytes at address 0x080147A8 performed ok. + Programming of 8 bytes at address 0x080147B0 performed ok. + Programming of 8 bytes at address 0x080147B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080147F0 performed ok. + Programming of 8 bytes at address 0x080147F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014800 performed ok. + Programming of 8 bytes at address 0x08014808 performed ok. + Programming of 8 bytes at address 0x08014810 performed ok. + Programming of 8 bytes at address 0x08014818 performed ok. + Programming of 8 bytes at address 0x08014820 performed ok. + Programming of 8 bytes at address 0x08014828 performed ok. + Programming of 8 bytes at address 0x08014830 performed ok. + Programming of 8 bytes at address 0x08014838 performed ok. + Programming of 8 bytes at address 0x08014840 performed ok. + Programming of 8 bytes at address 0x08014848 performed ok. + Programming of 8 bytes at address 0x08014850 performed ok. + Programming of 8 bytes at address 0x08014858 performed ok. + Programming of 8 bytes at address 0x08014860 performed ok. + Programming of 8 bytes at address 0x08014868 performed ok. + Programming of 8 bytes at address 0x08014870 performed ok. + Programming of 8 bytes at address 0x08014878 performed ok. + Programming of 8 bytes at address 0x08014880 performed ok. + Programming of 8 bytes at address 0x08014888 performed ok. + Programming of 8 bytes at address 0x08014890 performed ok. + Programming of 8 bytes at address 0x08014898 performed ok. + Programming of 8 bytes at address 0x080148A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080148C0 performed ok. + Programming of 8 bytes at address 0x080148C8 performed ok. + Programming of 8 bytes at address 0x080148D0 performed ok. + Programming of 8 bytes at address 0x080148D8 performed ok. + Programming of 8 bytes at address 0x080148E0 performed ok. + Programming of 8 bytes at address 0x080148E8 performed ok. + Programming of 8 bytes at address 0x080148F0 performed ok. + Programming of 8 bytes at address 0x080148F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014900 performed ok. + Programming of 8 bytes at address 0x08014908 performed ok. + Programming of 8 bytes at address 0x08014910 performed ok. + Programming of 8 bytes at address 0x08014918 performed ok. + Programming of 8 bytes at address 0x08014920 performed ok. + Programming of 8 bytes at address 0x08014928 performed ok. + Programming of 8 bytes at address 0x08014930 performed ok. + Programming of 8 bytes at address 0x08014938 performed ok. + Programming of 8 bytes at address 0x08014940 performed ok. + Programming of 8 bytes at address 0x08014948 performed ok. + Programming of 8 bytes at address 0x08014950 performed ok. + Programming of 8 bytes at address 0x08014958 performed ok. + Programming of 8 bytes at address 0x08014960 performed ok. + Programming of 8 bytes at address 0x08014968 performed ok. + Programming of 8 bytes at address 0x08014970 performed ok. + Programming of 8 bytes at address 0x08014978 performed ok. + Programming of 8 bytes at address 0x08014980 performed ok. + Programming of 8 bytes at address 0x08014988 performed ok. + Programming of 8 bytes at address 0x08014990 performed ok. +k. + Programming of 8 bytes at address 0x080149A0 performed ok. + Programming of 8 bytes at address 0x080149A8 performed ok. + Programming of 8 bytes at address 0x080149B0 performed ok. + Programming of 8 bytes at address 0x080149B8 performed ok. + Programming of 8 bytes at address 0x080149C0 performed ok. + Programming of 8 bytes at address 0x080149C8 performed ok. + Programming of 8 bytes at address 0x080149D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014A00 performed ok. + Programming of 8 bytes at address 0x08014A08 performed ok. + Programming of 8 bytes at address 0x08014A10 performed ok. + Programming of 8 bytes at address 0x08014A18 performed ok. + Programming of 8 bytes at address 0x08014A20 performed ok. + Programming of 8 bytes at address 0x08014A28 performed ok. + Programming of 8 bytes at address 0x08014A30 performed ok. + Programming of 8 bytes at address 0x08014A38 performed ok. + Programming of 8 bytes at address 0x08014A40 performed ok. + Programming of 8 bytes at address 0x08014A48 performed ok. + Programming of 8 bytes at address 0x08014A50 performed ok. + Programming of 8 bytes at address 0x08014A58 performed ok. + Programming of 8 bytes at address 0x08014A60 performed ok. + Programming of 8 bytes at address 0x08014A68 performed ok. + Programming of 8 bytes at address 0x08014A70 performed ok. + Programming of 8 bytes at address 0x08014A78 performed ok. + Programming of 8 bytes at address 0x08014A80 performed ok. + Programming of 8 bytes at address 0x08014A88 performed ok. + Programming of 8 bytes at address 0x08014A90 performed ok. + Programming of 8 bytes at address 0x08014A98 performed ok. + Programming of 8 bytes at address 0x08014AA0 performed ok. + Programming of 8 bytes at address 0x08014AA8 performed ok. + Programming of 8 bytes at address 0x08014AB0 performed ok. + Programming of 8 bytes at address 0x08014AB8 performed ok. + Programming of 8 bytes at address 0x08014AC0 performed ok. +k. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014B00 performed ok. + Programming of 8 bytes at address 0x08014B08 performed ok. + Programming of 8 bytes at address 0x08014B10 performed ok. + Programming of 8 bytes at address 0x08014B18 performed ok. + Programming of 8 bytes at address 0x08014B20 performed ok. + Programming of 8 bytes at address 0x08014B28 performed ok. + Programming of 8 bytes at address 0x08014B30 performed ok. + Programming of 8 bytes at address 0x08014B38 performed ok. + Programming of 8 bytes at address 0x08014B40 performed ok. + Programming of 8 bytes at address 0x08014B48 performed ok. + Programming of 8 bytes at address 0x08014B50 performed ok. + Programming of 8 bytes at address 0x08014B58 performed ok. + Programming of 8 bytes at address 0x08014B60 performed ok. + Programming of 8 bytes at address 0x08014B68 performed ok. + Programming of 8 bytes at address 0x08014B70 performed ok. + Programming of 8 bytes at address 0x08014B78 performed ok. + Programming of 8 bytes at address 0x08014B80 performed ok. + Programming of 8 bytes at address 0x08014B88 performed ok. + Programming of 8 bytes at address 0x08014B90 performed ok. + Programming of 8 bytes at address 0x08014B98 performed ok. + Programming of 8 bytes at address 0x08014BA0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08014BC8 performed ok. + Programming of 8 bytes at address 0x08014BD0 performed ok. + Programming of 8 bytes at address 0x08014BD8 performed ok. + Programming of 8 bytes at address 0x08014BE0 performed ok. + Programming of 8 bytes at address 0x08014BE8 performed ok. + Programming of 8 bytes at address 0x08014BF0 performed ok. + Programming of 8 bytes at address 0x08014BF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014C00 performed ok. + Programming of 8 bytes at address 0x08014C08 performed ok. + Programming of 8 bytes at address 0x08014C10 performed ok. + Programming of 8 bytes at address 0x08014C18 performed ok. + Programming of 8 bytes at address 0x08014C20 performed ok. + Programming of 8 bytes at address 0x08014C28 performed ok. + Programming of 8 bytes at address 0x08014C30 performed ok. + Programming of 8 bytes at address 0x08014C38 performed ok. + Programming of 8 bytes at address 0x08014C40 performed ok. + Programming of 8 bytes at address 0x08014C48 performed ok. + Programming of 8 bytes at address 0x08014C50 performed ok. + Programming of 8 bytes at address 0x08014C58 performed ok. + Programming of 8 bytes at address 0x08014C60 performed ok. + Programming of 8 bytes at address 0x08014C68 performed ok. + Programming of 8 bytes at address 0x08014C70 performed ok. + Programming of 8 bytes at address 0x08014C78 performed ok. + Programming of 8 bytes at address 0x08014C80 performed ok. + Programming of 8 bytes at address 0x08014C88 performed ok. + Programming of 8 bytes at address 0x08014C90 performed ok. + Programming of 8 bytes at address 0x08014C98 performed ok. + Programming of 8 bytes at address 0x08014CA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08014CC0 performed ok. + Programming of 8 bytes at address 0x08014CC8 performed ok. + Programming of 8 bytes at address 0x08014CD0 performed ok. + Programming of 8 bytes at address 0x08014CD8 performed ok. + Programming of 8 bytes at address 0x08014CE0 performed ok. + Programming of 8 bytes at address 0x08014CE8 performed ok. + Programming of 8 bytes at address 0x08014CF0 performed ok. + Programming of 8 bytes at address 0x08014CF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014D00 performed ok. + Programming of 8 bytes at address 0x08014D08 performed ok. + Programming of 8 bytes at address 0x08014D10 performed ok. + Programming of 8 bytes at address 0x08014D18 performed ok. + Programming of 8 bytes at address 0x08014D20 performed ok. + Programming of 8 bytes at address 0x08014D28 performed ok. + Programming of 8 bytes at address 0x08014D30 performed ok. + Programming of 8 bytes at address 0x08014D38 performed ok. + Programming of 8 bytes at address 0x08014D40 performed ok. + Programming of 8 bytes at address 0x08014D48 performed ok. + Programming of 8 bytes at address 0x08014D50 performed ok. + Programming of 8 bytes at address 0x08014D58 performed ok. + Programming of 8 bytes at address 0x08014D60 performed ok. + Programming of 8 bytes at address 0x08014D68 performed ok. + Programming of 8 bytes at address 0x08014D70 performed ok. + Programming of 8 bytes at address 0x08014D78 performed ok. + Programming of 8 bytes at address 0x08014D80 performed ok. + Programming of 8 bytes at address 0x08014D88 performed ok. + Programming of 8 bytes at address 0x08014D90 performed ok. + Programming of 8 bytes at address 0x08014D98 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08014DB8 performed ok. + Programming of 8 bytes at address 0x08014DC0 performed ok. + Programming of 8 bytes at address 0x08014DC8 performed ok. + Programming of 8 bytes at address 0x08014DD0 performed ok. + Programming of 8 bytes at address 0x08014DD8 performed ok. + Programming of 8 bytes at address 0x08014DE0 performed ok. + Programming of 8 bytes at address 0x08014DE8 performed ok. + Programming of 8 bytes at address 0x08014DF0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014E00 performed ok. + Programming of 8 bytes at address 0x08014E08 performed ok. + Programming of 8 bytes at address 0x08014E10 performed ok. + Programming of 8 bytes at address 0x08014E18 performed ok. + Programming of 8 bytes at address 0x08014E20 performed ok. + Programming of 8 bytes at address 0x08014E28 performed ok. + Programming of 8 bytes at address 0x08014E30 performed ok. + Programming of 8 bytes at address 0x08014E38 performed ok. + Programming of 8 bytes at address 0x08014E40 performed ok. + Programming of 8 bytes at address 0x08014E48 performed ok. + Programming of 8 bytes at address 0x08014E50 performed ok. + Programming of 8 bytes at address 0x08014E58 performed ok. + Programming of 8 bytes at address 0x08014E60 performed ok. + Programming of 8 bytes at address 0x08014E68 performed ok. + Programming of 8 bytes at address 0x08014E70 performed ok. + Programming of 8 bytes at address 0x08014E78 performed ok. + Programming of 8 bytes at address 0x08014E80 performed ok. + Programming of 8 bytes at address 0x08014E88 performed ok. + Programming of 8 bytes at address 0x08014E90 performed ok. + Programming of 8 bytes at address 0x08014E98 performed ok. +k. +k. + Programming of 8 bytes at address 0x08014EB0 performed ok. + Programming of 8 bytes at address 0x08014EB8 performed ok. + Programming of 8 bytes at address 0x08014EC0 performed ok. + Programming of 8 bytes at address 0x08014EC8 performed ok. + Programming of 8 bytes at address 0x08014ED0 performed ok. + Programming of 8 bytes at address 0x08014ED8 performed ok. + Programming of 8 bytes at address 0x08014EE0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08014F00 performed ok. + Programming of 8 bytes at address 0x08014F08 performed ok. + Programming of 8 bytes at address 0x08014F10 performed ok. + Programming of 8 bytes at address 0x08014F18 performed ok. + Programming of 8 bytes at address 0x08014F20 performed ok. + Programming of 8 bytes at address 0x08014F28 performed ok. + Programming of 8 bytes at address 0x08014F30 performed ok. + Programming of 8 bytes at address 0x08014F38 performed ok. + Programming of 8 bytes at address 0x08014F40 performed ok. + Programming of 8 bytes at address 0x08014F48 performed ok. + Programming of 8 bytes at address 0x08014F50 performed ok. + Programming of 8 bytes at address 0x08014F58 performed ok. + Programming of 8 bytes at address 0x08014F60 performed ok. + Programming of 8 bytes at address 0x08014F68 performed ok. + Programming of 8 bytes at address 0x08014F70 performed ok. + Programming of 8 bytes at address 0x08014F78 performed ok. + Programming of 8 bytes at address 0x08014F80 performed ok. + Programming of 8 bytes at address 0x08014F88 performed ok. + Programming of 8 bytes at address 0x08014F90 performed ok. + Programming of 8 bytes at address 0x08014F98 performed ok. + Programming of 8 bytes at address 0x08014FA0 performed ok. + Programming of 8 bytes at address 0x08014FA8 performed ok. + Programming of 8 bytes at address 0x08014FB0 performed ok. + Programming of 8 bytes at address 0x08014FB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08014FF0 performed ok. + Programming of 8 bytes at address 0x08014FF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015000 performed ok. + Programming of 8 bytes at address 0x08015008 performed ok. + Programming of 8 bytes at address 0x08015010 performed ok. + Programming of 8 bytes at address 0x08015018 performed ok. + Programming of 8 bytes at address 0x08015020 performed ok. + Programming of 8 bytes at address 0x08015028 performed ok. + Programming of 8 bytes at address 0x08015030 performed ok. + Programming of 8 bytes at address 0x08015038 performed ok. + Programming of 8 bytes at address 0x08015040 performed ok. + Programming of 8 bytes at address 0x08015048 performed ok. + Programming of 8 bytes at address 0x08015050 performed ok. + Programming of 8 bytes at address 0x08015058 performed ok. + Programming of 8 bytes at address 0x08015060 performed ok. + Programming of 8 bytes at address 0x08015068 performed ok. + Programming of 8 bytes at address 0x08015070 performed ok. + Programming of 8 bytes at address 0x08015078 performed ok. + Programming of 8 bytes at address 0x08015080 performed ok. + Programming of 8 bytes at address 0x08015088 performed ok. + Programming of 8 bytes at address 0x08015090 performed ok. + Programming of 8 bytes at address 0x08015098 performed ok. + Programming of 8 bytes at address 0x080150A0 performed ok. + Programming of 8 bytes at address 0x080150A8 performed ok. + Programming of 8 bytes at address 0x080150B0 performed ok. + Programming of 8 bytes at address 0x080150B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080150F0 performed ok. + Programming of 8 bytes at address 0x080150F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015100 performed ok. + Programming of 8 bytes at address 0x08015108 performed ok. + Programming of 8 bytes at address 0x08015110 performed ok. + Programming of 8 bytes at address 0x08015118 performed ok. + Programming of 8 bytes at address 0x08015120 performed ok. + Programming of 8 bytes at address 0x08015128 performed ok. + Programming of 8 bytes at address 0x08015130 performed ok. + Programming of 8 bytes at address 0x08015138 performed ok. + Programming of 8 bytes at address 0x08015140 performed ok. + Programming of 8 bytes at address 0x08015148 performed ok. + Programming of 8 bytes at address 0x08015150 performed ok. + Programming of 8 bytes at address 0x08015158 performed ok. + Programming of 8 bytes at address 0x08015160 performed ok. + Programming of 8 bytes at address 0x08015168 performed ok. + Programming of 8 bytes at address 0x08015170 performed ok. + Programming of 8 bytes at address 0x08015178 performed ok. + Programming of 8 bytes at address 0x08015180 performed ok. + Programming of 8 bytes at address 0x08015188 performed ok. + Programming of 8 bytes at address 0x08015190 performed ok. + Programming of 8 bytes at address 0x08015198 performed ok. +k. +k. + Programming of 8 bytes at address 0x080151B0 performed ok. + Programming of 8 bytes at address 0x080151B8 performed ok. + Programming of 8 bytes at address 0x080151C0 performed ok. + Programming of 8 bytes at address 0x080151C8 performed ok. + Programming of 8 bytes at address 0x080151D0 performed ok. + Programming of 8 bytes at address 0x080151D8 performed ok. + Programming of 8 bytes at address 0x080151E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015200 performed ok. + Programming of 8 bytes at address 0x08015208 performed ok. + Programming of 8 bytes at address 0x08015210 performed ok. + Programming of 8 bytes at address 0x08015218 performed ok. + Programming of 8 bytes at address 0x08015220 performed ok. + Programming of 8 bytes at address 0x08015228 performed ok. + Programming of 8 bytes at address 0x08015230 performed ok. + Programming of 8 bytes at address 0x08015238 performed ok. + Programming of 8 bytes at address 0x08015240 performed ok. + Programming of 8 bytes at address 0x08015248 performed ok. + Programming of 8 bytes at address 0x08015250 performed ok. + Programming of 8 bytes at address 0x08015258 performed ok. + Programming of 8 bytes at address 0x08015260 performed ok. + Programming of 8 bytes at address 0x08015268 performed ok. + Programming of 8 bytes at address 0x08015270 performed ok. + Programming of 8 bytes at address 0x08015278 performed ok. + Programming of 8 bytes at address 0x08015280 performed ok. + Programming of 8 bytes at address 0x08015288 performed ok. + Programming of 8 bytes at address 0x08015290 performed ok. + Programming of 8 bytes at address 0x08015298 performed ok. +k. +k. + Programming of 8 bytes at address 0x080152B0 performed ok. + Programming of 8 bytes at address 0x080152B8 performed ok. + Programming of 8 bytes at address 0x080152C0 performed ok. + Programming of 8 bytes at address 0x080152C8 performed ok. + Programming of 8 bytes at address 0x080152D0 performed ok. + Programming of 8 bytes at address 0x080152D8 performed ok. + Programming of 8 bytes at address 0x080152E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015300 performed ok. + Programming of 8 bytes at address 0x08015308 performed ok. + Programming of 8 bytes at address 0x08015310 performed ok. + Programming of 8 bytes at address 0x08015318 performed ok. + Programming of 8 bytes at address 0x08015320 performed ok. + Programming of 8 bytes at address 0x08015328 performed ok. + Programming of 8 bytes at address 0x08015330 performed ok. + Programming of 8 bytes at address 0x08015338 performed ok. + Programming of 8 bytes at address 0x08015340 performed ok. + Programming of 8 bytes at address 0x08015348 performed ok. + Programming of 8 bytes at address 0x08015350 performed ok. + Programming of 8 bytes at address 0x08015358 performed ok. + Programming of 8 bytes at address 0x08015360 performed ok. + Programming of 8 bytes at address 0x08015368 performed ok. + Programming of 8 bytes at address 0x08015370 performed ok. + Programming of 8 bytes at address 0x08015378 performed ok. + Programming of 8 bytes at address 0x08015380 performed ok. + Programming of 8 bytes at address 0x08015388 performed ok. + Programming of 8 bytes at address 0x08015390 performed ok. + Programming of 8 bytes at address 0x08015398 performed ok. + Programming of 8 bytes at address 0x080153A0 performed ok. + Programming of 8 bytes at address 0x080153A8 performed ok. + Programming of 8 bytes at address 0x080153B0 performed ok. + Programming of 8 bytes at address 0x080153B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015400 performed ok. + Programming of 8 bytes at address 0x08015408 performed ok. + Programming of 8 bytes at address 0x08015410 performed ok. + Programming of 8 bytes at address 0x08015418 performed ok. + Programming of 8 bytes at address 0x08015420 performed ok. + Programming of 8 bytes at address 0x08015428 performed ok. + Programming of 8 bytes at address 0x08015430 performed ok. + Programming of 8 bytes at address 0x08015438 performed ok. + Programming of 8 bytes at address 0x08015440 performed ok. + Programming of 8 bytes at address 0x08015448 performed ok. + Programming of 8 bytes at address 0x08015450 performed ok. + Programming of 8 bytes at address 0x08015458 performed ok. + Programming of 8 bytes at address 0x08015460 performed ok. + Programming of 8 bytes at address 0x08015468 performed ok. + Programming of 8 bytes at address 0x08015470 performed ok. + Programming of 8 bytes at address 0x08015478 performed ok. + Programming of 8 bytes at address 0x08015480 performed ok. + Programming of 8 bytes at address 0x08015488 performed ok. + Programming of 8 bytes at address 0x08015490 performed ok. + Programming of 8 bytes at address 0x08015498 performed ok. + Programming of 8 bytes at address 0x080154A0 performed ok. + Programming of 8 bytes at address 0x080154A8 performed ok. + Programming of 8 bytes at address 0x080154B0 performed ok. + Programming of 8 bytes at address 0x080154B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080154F0 performed ok. + Programming of 8 bytes at address 0x080154F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015500 performed ok. + Programming of 8 bytes at address 0x08015508 performed ok. + Programming of 8 bytes at address 0x08015510 performed ok. + Programming of 8 bytes at address 0x08015518 performed ok. + Programming of 8 bytes at address 0x08015520 performed ok. + Programming of 8 bytes at address 0x08015528 performed ok. + Programming of 8 bytes at address 0x08015530 performed ok. + Programming of 8 bytes at address 0x08015538 performed ok. + Programming of 8 bytes at address 0x08015540 performed ok. + Programming of 8 bytes at address 0x08015548 performed ok. + Programming of 8 bytes at address 0x08015550 performed ok. + Programming of 8 bytes at address 0x08015558 performed ok. + Programming of 8 bytes at address 0x08015560 performed ok. + Programming of 8 bytes at address 0x08015568 performed ok. + Programming of 8 bytes at address 0x08015570 performed ok. + Programming of 8 bytes at address 0x08015578 performed ok. + Programming of 8 bytes at address 0x08015580 performed ok. + Programming of 8 bytes at address 0x08015588 performed ok. + Programming of 8 bytes at address 0x08015590 performed ok. + Programming of 8 bytes at address 0x08015598 performed ok. + Programming of 8 bytes at address 0x080155A0 performed ok. + Programming of 8 bytes at address 0x080155A8 performed ok. + Programming of 8 bytes at address 0x080155B0 performed ok. + Programming of 8 bytes at address 0x080155B8 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080155E0 performed ok. + Programming of 8 bytes at address 0x080155E8 performed ok. + Programming of 8 bytes at address 0x080155F0 performed ok. + Programming of 8 bytes at address 0x080155F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015600 performed ok. + Programming of 8 bytes at address 0x08015608 performed ok. + Programming of 8 bytes at address 0x08015610 performed ok. + Programming of 8 bytes at address 0x08015618 performed ok. + Programming of 8 bytes at address 0x08015620 performed ok. + Programming of 8 bytes at address 0x08015628 performed ok. + Programming of 8 bytes at address 0x08015630 performed ok. + Programming of 8 bytes at address 0x08015638 performed ok. + Programming of 8 bytes at address 0x08015640 performed ok. + Programming of 8 bytes at address 0x08015648 performed ok. + Programming of 8 bytes at address 0x08015650 performed ok. + Programming of 8 bytes at address 0x08015658 performed ok. + Programming of 8 bytes at address 0x08015660 performed ok. + Programming of 8 bytes at address 0x08015668 performed ok. + Programming of 8 bytes at address 0x08015670 performed ok. + Programming of 8 bytes at address 0x08015678 performed ok. + Programming of 8 bytes at address 0x08015680 performed ok. + Programming of 8 bytes at address 0x08015688 performed ok. + Programming of 8 bytes at address 0x08015690 performed ok. + Programming of 8 bytes at address 0x08015698 performed ok. + Programming of 8 bytes at address 0x080156A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080156C0 performed ok. + Programming of 8 bytes at address 0x080156C8 performed ok. + Programming of 8 bytes at address 0x080156D0 performed ok. + Programming of 8 bytes at address 0x080156D8 performed ok. + Programming of 8 bytes at address 0x080156E0 performed ok. + Programming of 8 bytes at address 0x080156E8 performed ok. + Programming of 8 bytes at address 0x080156F0 performed ok. + Programming of 8 bytes at address 0x080156F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015700 performed ok. + Programming of 8 bytes at address 0x08015708 performed ok. + Programming of 8 bytes at address 0x08015710 performed ok. + Programming of 8 bytes at address 0x08015718 performed ok. + Programming of 8 bytes at address 0x08015720 performed ok. + Programming of 8 bytes at address 0x08015728 performed ok. + Programming of 8 bytes at address 0x08015730 performed ok. + Programming of 8 bytes at address 0x08015738 performed ok. + Programming of 8 bytes at address 0x08015740 performed ok. + Programming of 8 bytes at address 0x08015748 performed ok. + Programming of 8 bytes at address 0x08015750 performed ok. + Programming of 8 bytes at address 0x08015758 performed ok. + Programming of 8 bytes at address 0x08015760 performed ok. + Programming of 8 bytes at address 0x08015768 performed ok. + Programming of 8 bytes at address 0x08015770 performed ok. + Programming of 8 bytes at address 0x08015778 performed ok. + Programming of 8 bytes at address 0x08015780 performed ok. + Programming of 8 bytes at address 0x08015788 performed ok. + Programming of 8 bytes at address 0x08015790 performed ok. + Programming of 8 bytes at address 0x08015798 performed ok. + Programming of 8 bytes at address 0x080157A0 performed ok. + Programming of 8 bytes at address 0x080157A8 performed ok. + Programming of 8 bytes at address 0x080157B0 performed ok. + Programming of 8 bytes at address 0x080157B8 performed ok. + Programming of 8 bytes at address 0x080157C0 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080157F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015800 performed ok. + Programming of 8 bytes at address 0x08015808 performed ok. + Programming of 8 bytes at address 0x08015810 performed ok. + Programming of 8 bytes at address 0x08015818 performed ok. + Programming of 8 bytes at address 0x08015820 performed ok. + Programming of 8 bytes at address 0x08015828 performed ok. + Programming of 8 bytes at address 0x08015830 performed ok. + Programming of 8 bytes at address 0x08015838 performed ok. + Programming of 8 bytes at address 0x08015840 performed ok. + Programming of 8 bytes at address 0x08015848 performed ok. + Programming of 8 bytes at address 0x08015850 performed ok. + Programming of 8 bytes at address 0x08015858 performed ok. + Programming of 8 bytes at address 0x08015860 performed ok. + Programming of 8 bytes at address 0x08015868 performed ok. + Programming of 8 bytes at address 0x08015870 performed ok. + Programming of 8 bytes at address 0x08015878 performed ok. + Programming of 8 bytes at address 0x08015880 performed ok. + Programming of 8 bytes at address 0x08015888 performed ok. + Programming of 8 bytes at address 0x08015890 performed ok. + Programming of 8 bytes at address 0x08015898 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080158B8 performed ok. + Programming of 8 bytes at address 0x080158C0 performed ok. + Programming of 8 bytes at address 0x080158C8 performed ok. + Programming of 8 bytes at address 0x080158D0 performed ok. + Programming of 8 bytes at address 0x080158D8 performed ok. + Programming of 8 bytes at address 0x080158E0 performed ok. + Programming of 8 bytes at address 0x080158E8 performed ok. + Programming of 8 bytes at address 0x080158F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015900 performed ok. + Programming of 8 bytes at address 0x08015908 performed ok. + Programming of 8 bytes at address 0x08015910 performed ok. + Programming of 8 bytes at address 0x08015918 performed ok. + Programming of 8 bytes at address 0x08015920 performed ok. + Programming of 8 bytes at address 0x08015928 performed ok. + Programming of 8 bytes at address 0x08015930 performed ok. + Programming of 8 bytes at address 0x08015938 performed ok. + Programming of 8 bytes at address 0x08015940 performed ok. + Programming of 8 bytes at address 0x08015948 performed ok. + Programming of 8 bytes at address 0x08015950 performed ok. + Programming of 8 bytes at address 0x08015958 performed ok. + Programming of 8 bytes at address 0x08015960 performed ok. + Programming of 8 bytes at address 0x08015968 performed ok. + Programming of 8 bytes at address 0x08015970 performed ok. + Programming of 8 bytes at address 0x08015978 performed ok. + Programming of 8 bytes at address 0x08015980 performed ok. + Programming of 8 bytes at address 0x08015988 performed ok. + Programming of 8 bytes at address 0x08015990 performed ok. + Programming of 8 bytes at address 0x08015998 performed ok. + Programming of 8 bytes at address 0x080159A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080159C0 performed ok. + Programming of 8 bytes at address 0x080159C8 performed ok. + Programming of 8 bytes at address 0x080159D0 performed ok. + Programming of 8 bytes at address 0x080159D8 performed ok. + Programming of 8 bytes at address 0x080159E0 performed ok. + Programming of 8 bytes at address 0x080159E8 performed ok. + Programming of 8 bytes at address 0x080159F0 performed ok. + Programming of 8 bytes at address 0x080159F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015A00 performed ok. + Programming of 8 bytes at address 0x08015A08 performed ok. + Programming of 8 bytes at address 0x08015A10 performed ok. + Programming of 8 bytes at address 0x08015A18 performed ok. + Programming of 8 bytes at address 0x08015A20 performed ok. + Programming of 8 bytes at address 0x08015A28 performed ok. + Programming of 8 bytes at address 0x08015A30 performed ok. + Programming of 8 bytes at address 0x08015A38 performed ok. + Programming of 8 bytes at address 0x08015A40 performed ok. + Programming of 8 bytes at address 0x08015A48 performed ok. + Programming of 8 bytes at address 0x08015A50 performed ok. + Programming of 8 bytes at address 0x08015A58 performed ok. + Programming of 8 bytes at address 0x08015A60 performed ok. + Programming of 8 bytes at address 0x08015A68 performed ok. + Programming of 8 bytes at address 0x08015A70 performed ok. + Programming of 8 bytes at address 0x08015A78 performed ok. + Programming of 8 bytes at address 0x08015A80 performed ok. + Programming of 8 bytes at address 0x08015A88 performed ok. + Programming of 8 bytes at address 0x08015A90 performed ok. + Programming of 8 bytes at address 0x08015A98 performed ok. +k. +k. + Programming of 8 bytes at address 0x08015AB0 performed ok. + Programming of 8 bytes at address 0x08015AB8 performed ok. + Programming of 8 bytes at address 0x08015AC0 performed ok. + Programming of 8 bytes at address 0x08015AC8 performed ok. + Programming of 8 bytes at address 0x08015AD0 performed ok. + Programming of 8 bytes at address 0x08015AD8 performed ok. + Programming of 8 bytes at address 0x08015AE0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015B00 performed ok. + Programming of 8 bytes at address 0x08015B08 performed ok. + Programming of 8 bytes at address 0x08015B10 performed ok. + Programming of 8 bytes at address 0x08015B18 performed ok. + Programming of 8 bytes at address 0x08015B20 performed ok. + Programming of 8 bytes at address 0x08015B28 performed ok. + Programming of 8 bytes at address 0x08015B30 performed ok. + Programming of 8 bytes at address 0x08015B38 performed ok. + Programming of 8 bytes at address 0x08015B40 performed ok. + Programming of 8 bytes at address 0x08015B48 performed ok. + Programming of 8 bytes at address 0x08015B50 performed ok. + Programming of 8 bytes at address 0x08015B58 performed ok. + Programming of 8 bytes at address 0x08015B60 performed ok. + Programming of 8 bytes at address 0x08015B68 performed ok. + Programming of 8 bytes at address 0x08015B70 performed ok. + Programming of 8 bytes at address 0x08015B78 performed ok. + Programming of 8 bytes at address 0x08015B80 performed ok. + Programming of 8 bytes at address 0x08015B88 performed ok. + Programming of 8 bytes at address 0x08015B90 performed ok. + Programming of 8 bytes at address 0x08015B98 performed ok. + Programming of 8 bytes at address 0x08015BA0 performed ok. + Programming of 8 bytes at address 0x08015BA8 performed ok. + Programming of 8 bytes at address 0x08015BB0 performed ok. + Programming of 8 bytes at address 0x08015BB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08015BF0 performed ok. + Programming of 8 bytes at address 0x08015BF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015C00 performed ok. + Programming of 8 bytes at address 0x08015C08 performed ok. + Programming of 8 bytes at address 0x08015C10 performed ok. + Programming of 8 bytes at address 0x08015C18 performed ok. + Programming of 8 bytes at address 0x08015C20 performed ok. + Programming of 8 bytes at address 0x08015C28 performed ok. + Programming of 8 bytes at address 0x08015C30 performed ok. + Programming of 8 bytes at address 0x08015C38 performed ok. + Programming of 8 bytes at address 0x08015C40 performed ok. + Programming of 8 bytes at address 0x08015C48 performed ok. + Programming of 8 bytes at address 0x08015C50 performed ok. + Programming of 8 bytes at address 0x08015C58 performed ok. + Programming of 8 bytes at address 0x08015C60 performed ok. + Programming of 8 bytes at address 0x08015C68 performed ok. + Programming of 8 bytes at address 0x08015C70 performed ok. + Programming of 8 bytes at address 0x08015C78 performed ok. + Programming of 8 bytes at address 0x08015C80 performed ok. + Programming of 8 bytes at address 0x08015C88 performed ok. + Programming of 8 bytes at address 0x08015C90 performed ok. + Programming of 8 bytes at address 0x08015C98 performed ok. + Programming of 8 bytes at address 0x08015CA0 performed ok. + Programming of 8 bytes at address 0x08015CA8 performed ok. + Programming of 8 bytes at address 0x08015CB0 performed ok. + Programming of 8 bytes at address 0x08015CB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08015CF0 performed ok. + Programming of 8 bytes at address 0x08015CF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015D00 performed ok. + Programming of 8 bytes at address 0x08015D08 performed ok. + Programming of 8 bytes at address 0x08015D10 performed ok. + Programming of 8 bytes at address 0x08015D18 performed ok. + Programming of 8 bytes at address 0x08015D20 performed ok. + Programming of 8 bytes at address 0x08015D28 performed ok. + Programming of 8 bytes at address 0x08015D30 performed ok. + Programming of 8 bytes at address 0x08015D38 performed ok. + Programming of 8 bytes at address 0x08015D40 performed ok. + Programming of 8 bytes at address 0x08015D48 performed ok. + Programming of 8 bytes at address 0x08015D50 performed ok. + Programming of 8 bytes at address 0x08015D58 performed ok. + Programming of 8 bytes at address 0x08015D60 performed ok. + Programming of 8 bytes at address 0x08015D68 performed ok. + Programming of 8 bytes at address 0x08015D70 performed ok. + Programming of 8 bytes at address 0x08015D78 performed ok. + Programming of 8 bytes at address 0x08015D80 performed ok. + Programming of 8 bytes at address 0x08015D88 performed ok. + Programming of 8 bytes at address 0x08015D90 performed ok. + Programming of 8 bytes at address 0x08015D98 performed ok. + Programming of 8 bytes at address 0x08015DA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08015DC0 performed ok. + Programming of 8 bytes at address 0x08015DC8 performed ok. + Programming of 8 bytes at address 0x08015DD0 performed ok. + Programming of 8 bytes at address 0x08015DD8 performed ok. + Programming of 8 bytes at address 0x08015DE0 performed ok. + Programming of 8 bytes at address 0x08015DE8 performed ok. + Programming of 8 bytes at address 0x08015DF0 performed ok. + Programming of 8 bytes at address 0x08015DF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015E00 performed ok. + Programming of 8 bytes at address 0x08015E08 performed ok. + Programming of 8 bytes at address 0x08015E10 performed ok. + Programming of 8 bytes at address 0x08015E18 performed ok. + Programming of 8 bytes at address 0x08015E20 performed ok. + Programming of 8 bytes at address 0x08015E28 performed ok. + Programming of 8 bytes at address 0x08015E30 performed ok. + Programming of 8 bytes at address 0x08015E38 performed ok. + Programming of 8 bytes at address 0x08015E40 performed ok. + Programming of 8 bytes at address 0x08015E48 performed ok. + Programming of 8 bytes at address 0x08015E50 performed ok. + Programming of 8 bytes at address 0x08015E58 performed ok. + Programming of 8 bytes at address 0x08015E60 performed ok. + Programming of 8 bytes at address 0x08015E68 performed ok. + Programming of 8 bytes at address 0x08015E70 performed ok. + Programming of 8 bytes at address 0x08015E78 performed ok. + Programming of 8 bytes at address 0x08015E80 performed ok. + Programming of 8 bytes at address 0x08015E88 performed ok. + Programming of 8 bytes at address 0x08015E90 performed ok. + Programming of 8 bytes at address 0x08015E98 performed ok. + Programming of 8 bytes at address 0x08015EA0 performed ok. + Programming of 8 bytes at address 0x08015EA8 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08015ED0 performed ok. + Programming of 8 bytes at address 0x08015ED8 performed ok. + Programming of 8 bytes at address 0x08015EE0 performed ok. + Programming of 8 bytes at address 0x08015EE8 performed ok. + Programming of 8 bytes at address 0x08015EF0 performed ok. + Programming of 8 bytes at address 0x08015EF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08015F00 performed ok. + Programming of 8 bytes at address 0x08015F08 performed ok. + Programming of 8 bytes at address 0x08015F10 performed ok. + Programming of 8 bytes at address 0x08015F18 performed ok. + Programming of 8 bytes at address 0x08015F20 performed ok. + Programming of 8 bytes at address 0x08015F28 performed ok. + Programming of 8 bytes at address 0x08015F30 performed ok. + Programming of 8 bytes at address 0x08015F38 performed ok. + Programming of 8 bytes at address 0x08015F40 performed ok. + Programming of 8 bytes at address 0x08015F48 performed ok. + Programming of 8 bytes at address 0x08015F50 performed ok. + Programming of 8 bytes at address 0x08015F58 performed ok. + Programming of 8 bytes at address 0x08015F60 performed ok. + Programming of 8 bytes at address 0x08015F68 performed ok. + Programming of 8 bytes at address 0x08015F70 performed ok. + Programming of 8 bytes at address 0x08015F78 performed ok. + Programming of 8 bytes at address 0x08015F80 performed ok. + Programming of 8 bytes at address 0x08015F88 performed ok. + Programming of 8 bytes at address 0x08015F90 performed ok. + Programming of 8 bytes at address 0x08015F98 performed ok. +k. + Programming of 8 bytes at address 0x08015FA8 performed ok. + Programming of 8 bytes at address 0x08015FB0 performed ok. + Programming of 8 bytes at address 0x08015FB8 performed ok. + Programming of 8 bytes at address 0x08015FC0 performed ok. + Programming of 8 bytes at address 0x08015FC8 performed ok. + Programming of 8 bytes at address 0x08015FD0 performed ok. + Programming of 8 bytes at address 0x08015FD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016000 performed ok. + Programming of 8 bytes at address 0x08016008 performed ok. + Programming of 8 bytes at address 0x08016010 performed ok. + Programming of 8 bytes at address 0x08016018 performed ok. + Programming of 8 bytes at address 0x08016020 performed ok. + Programming of 8 bytes at address 0x08016028 performed ok. + Programming of 8 bytes at address 0x08016030 performed ok. + Programming of 8 bytes at address 0x08016038 performed ok. + Programming of 8 bytes at address 0x08016040 performed ok. + Programming of 8 bytes at address 0x08016048 performed ok. + Programming of 8 bytes at address 0x08016050 performed ok. + Programming of 8 bytes at address 0x08016058 performed ok. + Programming of 8 bytes at address 0x08016060 performed ok. + Programming of 8 bytes at address 0x08016068 performed ok. + Programming of 8 bytes at address 0x08016070 performed ok. + Programming of 8 bytes at address 0x08016078 performed ok. + Programming of 8 bytes at address 0x08016080 performed ok. + Programming of 8 bytes at address 0x08016088 performed ok. + Programming of 8 bytes at address 0x08016090 performed ok. +k. + Programming of 8 bytes at address 0x080160A0 performed ok. + Programming of 8 bytes at address 0x080160A8 performed ok. + Programming of 8 bytes at address 0x080160B0 performed ok. + Programming of 8 bytes at address 0x080160B8 performed ok. + Programming of 8 bytes at address 0x080160C0 performed ok. + Programming of 8 bytes at address 0x080160C8 performed ok. + Programming of 8 bytes at address 0x080160D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016100 performed ok. + Programming of 8 bytes at address 0x08016108 performed ok. + Programming of 8 bytes at address 0x08016110 performed ok. + Programming of 8 bytes at address 0x08016118 performed ok. + Programming of 8 bytes at address 0x08016120 performed ok. + Programming of 8 bytes at address 0x08016128 performed ok. + Programming of 8 bytes at address 0x08016130 performed ok. + Programming of 8 bytes at address 0x08016138 performed ok. + Programming of 8 bytes at address 0x08016140 performed ok. + Programming of 8 bytes at address 0x08016148 performed ok. + Programming of 8 bytes at address 0x08016150 performed ok. + Programming of 8 bytes at address 0x08016158 performed ok. + Programming of 8 bytes at address 0x08016160 performed ok. + Programming of 8 bytes at address 0x08016168 performed ok. + Programming of 8 bytes at address 0x08016170 performed ok. + Programming of 8 bytes at address 0x08016178 performed ok. + Programming of 8 bytes at address 0x08016180 performed ok. + Programming of 8 bytes at address 0x08016188 performed ok. + Programming of 8 bytes at address 0x08016190 performed ok. +k. + Programming of 8 bytes at address 0x080161A0 performed ok. + Programming of 8 bytes at address 0x080161A8 performed ok. + Programming of 8 bytes at address 0x080161B0 performed ok. + Programming of 8 bytes at address 0x080161B8 performed ok. + Programming of 8 bytes at address 0x080161C0 performed ok. + Programming of 8 bytes at address 0x080161C8 performed ok. + Programming of 8 bytes at address 0x080161D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016200 performed ok. + Programming of 8 bytes at address 0x08016208 performed ok. + Programming of 8 bytes at address 0x08016210 performed ok. + Programming of 8 bytes at address 0x08016218 performed ok. + Programming of 8 bytes at address 0x08016220 performed ok. + Programming of 8 bytes at address 0x08016228 performed ok. + Programming of 8 bytes at address 0x08016230 performed ok. + Programming of 8 bytes at address 0x08016238 performed ok. + Programming of 8 bytes at address 0x08016240 performed ok. + Programming of 8 bytes at address 0x08016248 performed ok. + Programming of 8 bytes at address 0x08016250 performed ok. + Programming of 8 bytes at address 0x08016258 performed ok. + Programming of 8 bytes at address 0x08016260 performed ok. + Programming of 8 bytes at address 0x08016268 performed ok. + Programming of 8 bytes at address 0x08016270 performed ok. + Programming of 8 bytes at address 0x08016278 performed ok. + Programming of 8 bytes at address 0x08016280 performed ok. + Programming of 8 bytes at address 0x08016288 performed ok. + Programming of 8 bytes at address 0x08016290 performed ok. + Programming of 8 bytes at address 0x08016298 performed ok. + Programming of 8 bytes at address 0x080162A0 performed ok. + Programming of 8 bytes at address 0x080162A8 performed ok. + Programming of 8 bytes at address 0x080162B0 performed ok. + Programming of 8 bytes at address 0x080162B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080162F0 performed ok. + Programming of 8 bytes at address 0x080162F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016300 performed ok. + Programming of 8 bytes at address 0x08016308 performed ok. + Programming of 8 bytes at address 0x08016310 performed ok. + Programming of 8 bytes at address 0x08016318 performed ok. + Programming of 8 bytes at address 0x08016320 performed ok. + Programming of 8 bytes at address 0x08016328 performed ok. + Programming of 8 bytes at address 0x08016330 performed ok. + Programming of 8 bytes at address 0x08016338 performed ok. + Programming of 8 bytes at address 0x08016340 performed ok. + Programming of 8 bytes at address 0x08016348 performed ok. + Programming of 8 bytes at address 0x08016350 performed ok. + Programming of 8 bytes at address 0x08016358 performed ok. + Programming of 8 bytes at address 0x08016360 performed ok. + Programming of 8 bytes at address 0x08016368 performed ok. + Programming of 8 bytes at address 0x08016370 performed ok. + Programming of 8 bytes at address 0x08016378 performed ok. + Programming of 8 bytes at address 0x08016380 performed ok. + Programming of 8 bytes at address 0x08016388 performed ok. + Programming of 8 bytes at address 0x08016390 performed ok. +k. + Programming of 8 bytes at address 0x080163A0 performed ok. + Programming of 8 bytes at address 0x080163A8 performed ok. + Programming of 8 bytes at address 0x080163B0 performed ok. + Programming of 8 bytes at address 0x080163B8 performed ok. + Programming of 8 bytes at address 0x080163C0 performed ok. + Programming of 8 bytes at address 0x080163C8 performed ok. + Programming of 8 bytes at address 0x080163D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016400 performed ok. + Programming of 8 bytes at address 0x08016408 performed ok. + Programming of 8 bytes at address 0x08016410 performed ok. + Programming of 8 bytes at address 0x08016418 performed ok. + Programming of 8 bytes at address 0x08016420 performed ok. + Programming of 8 bytes at address 0x08016428 performed ok. + Programming of 8 bytes at address 0x08016430 performed ok. + Programming of 8 bytes at address 0x08016438 performed ok. + Programming of 8 bytes at address 0x08016440 performed ok. + Programming of 8 bytes at address 0x08016448 performed ok. + Programming of 8 bytes at address 0x08016450 performed ok. + Programming of 8 bytes at address 0x08016458 performed ok. + Programming of 8 bytes at address 0x08016460 performed ok. + Programming of 8 bytes at address 0x08016468 performed ok. + Programming of 8 bytes at address 0x08016470 performed ok. + Programming of 8 bytes at address 0x08016478 performed ok. + Programming of 8 bytes at address 0x08016480 performed ok. + Programming of 8 bytes at address 0x08016488 performed ok. + Programming of 8 bytes at address 0x08016490 performed ok. +k. + Programming of 8 bytes at address 0x080164A0 performed ok. + Programming of 8 bytes at address 0x080164A8 performed ok. + Programming of 8 bytes at address 0x080164B0 performed ok. + Programming of 8 bytes at address 0x080164B8 performed ok. + Programming of 8 bytes at address 0x080164C0 performed ok. + Programming of 8 bytes at address 0x080164C8 performed ok. + Programming of 8 bytes at address 0x080164D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016500 performed ok. + Programming of 8 bytes at address 0x08016508 performed ok. + Programming of 8 bytes at address 0x08016510 performed ok. + Programming of 8 bytes at address 0x08016518 performed ok. + Programming of 8 bytes at address 0x08016520 performed ok. + Programming of 8 bytes at address 0x08016528 performed ok. + Programming of 8 bytes at address 0x08016530 performed ok. + Programming of 8 bytes at address 0x08016538 performed ok. + Programming of 8 bytes at address 0x08016540 performed ok. + Programming of 8 bytes at address 0x08016548 performed ok. + Programming of 8 bytes at address 0x08016550 performed ok. + Programming of 8 bytes at address 0x08016558 performed ok. + Programming of 8 bytes at address 0x08016560 performed ok. + Programming of 8 bytes at address 0x08016568 performed ok. + Programming of 8 bytes at address 0x08016570 performed ok. + Programming of 8 bytes at address 0x08016578 performed ok. + Programming of 8 bytes at address 0x08016580 performed ok. + Programming of 8 bytes at address 0x08016588 performed ok. + Programming of 8 bytes at address 0x08016590 performed ok. +k. + Programming of 8 bytes at address 0x080165A0 performed ok. + Programming of 8 bytes at address 0x080165A8 performed ok. + Programming of 8 bytes at address 0x080165B0 performed ok. + Programming of 8 bytes at address 0x080165B8 performed ok. + Programming of 8 bytes at address 0x080165C0 performed ok. + Programming of 8 bytes at address 0x080165C8 performed ok. + Programming of 8 bytes at address 0x080165D0 performed ok. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016600 performed ok. + Programming of 8 bytes at address 0x08016608 performed ok. + Programming of 8 bytes at address 0x08016610 performed ok. + Programming of 8 bytes at address 0x08016618 performed ok. + Programming of 8 bytes at address 0x08016620 performed ok. + Programming of 8 bytes at address 0x08016628 performed ok. + Programming of 8 bytes at address 0x08016630 performed ok. + Programming of 8 bytes at address 0x08016638 performed ok. + Programming of 8 bytes at address 0x08016640 performed ok. + Programming of 8 bytes at address 0x08016648 performed ok. + Programming of 8 bytes at address 0x08016650 performed ok. + Programming of 8 bytes at address 0x08016658 performed ok. + Programming of 8 bytes at address 0x08016660 performed ok. + Programming of 8 bytes at address 0x08016668 performed ok. + Programming of 8 bytes at address 0x08016670 performed ok. + Programming of 8 bytes at address 0x08016678 performed ok. + Programming of 8 bytes at address 0x08016680 performed ok. + Programming of 8 bytes at address 0x08016688 performed ok. + Programming of 8 bytes at address 0x08016690 performed ok. + Programming of 8 bytes at address 0x08016698 performed ok. + Programming of 8 bytes at address 0x080166A0 performed ok. + Programming of 8 bytes at address 0x080166A8 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080166D0 performed ok. + Programming of 8 bytes at address 0x080166D8 performed ok. + Programming of 8 bytes at address 0x080166E0 performed ok. + Programming of 8 bytes at address 0x080166E8 performed ok. + Programming of 8 bytes at address 0x080166F0 performed ok. + Programming of 8 bytes at address 0x080166F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016700 performed ok. + Programming of 8 bytes at address 0x08016708 performed ok. + Programming of 8 bytes at address 0x08016710 performed ok. + Programming of 8 bytes at address 0x08016718 performed ok. + Programming of 8 bytes at address 0x08016720 performed ok. + Programming of 8 bytes at address 0x08016728 performed ok. + Programming of 8 bytes at address 0x08016730 performed ok. + Programming of 8 bytes at address 0x08016738 performed ok. + Programming of 8 bytes at address 0x08016740 performed ok. + Programming of 8 bytes at address 0x08016748 performed ok. + Programming of 8 bytes at address 0x08016750 performed ok. + Programming of 8 bytes at address 0x08016758 performed ok. + Programming of 8 bytes at address 0x08016760 performed ok. + Programming of 8 bytes at address 0x08016768 performed ok. + Programming of 8 bytes at address 0x08016770 performed ok. + Programming of 8 bytes at address 0x08016778 performed ok. + Programming of 8 bytes at address 0x08016780 performed ok. + Programming of 8 bytes at address 0x08016788 performed ok. + Programming of 8 bytes at address 0x08016790 performed ok. + Programming of 8 bytes at address 0x08016798 performed ok. +k. + Programming of 8 bytes at address 0x080167A8 performed ok. + Programming of 8 bytes at address 0x080167B0 performed ok. + Programming of 8 bytes at address 0x080167B8 performed ok. + Programming of 8 bytes at address 0x080167C0 performed ok. + Programming of 8 bytes at address 0x080167C8 performed ok. + Programming of 8 bytes at address 0x080167D0 performed ok. + Programming of 8 bytes at address 0x080167D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016800 performed ok. + Programming of 8 bytes at address 0x08016808 performed ok. + Programming of 8 bytes at address 0x08016810 performed ok. + Programming of 8 bytes at address 0x08016818 performed ok. + Programming of 8 bytes at address 0x08016820 performed ok. + Programming of 8 bytes at address 0x08016828 performed ok. + Programming of 8 bytes at address 0x08016830 performed ok. + Programming of 8 bytes at address 0x08016838 performed ok. + Programming of 8 bytes at address 0x08016840 performed ok. + Programming of 8 bytes at address 0x08016848 performed ok. + Programming of 8 bytes at address 0x08016850 performed ok. + Programming of 8 bytes at address 0x08016858 performed ok. + Programming of 8 bytes at address 0x08016860 performed ok. + Programming of 8 bytes at address 0x08016868 performed ok. + Programming of 8 bytes at address 0x08016870 performed ok. + Programming of 8 bytes at address 0x08016878 performed ok. + Programming of 8 bytes at address 0x08016880 performed ok. + Programming of 8 bytes at address 0x08016888 performed ok. + Programming of 8 bytes at address 0x08016890 performed ok. + Programming of 8 bytes at address 0x08016898 performed ok. + Programming of 8 bytes at address 0x080168A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080168C0 performed ok. + Programming of 8 bytes at address 0x080168C8 performed ok. + Programming of 8 bytes at address 0x080168D0 performed ok. + Programming of 8 bytes at address 0x080168D8 performed ok. + Programming of 8 bytes at address 0x080168E0 performed ok. + Programming of 8 bytes at address 0x080168E8 performed ok. + Programming of 8 bytes at address 0x080168F0 performed ok. + Programming of 8 bytes at address 0x080168F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016900 performed ok. + Programming of 8 bytes at address 0x08016908 performed ok. + Programming of 8 bytes at address 0x08016910 performed ok. + Programming of 8 bytes at address 0x08016918 performed ok. + Programming of 8 bytes at address 0x08016920 performed ok. + Programming of 8 bytes at address 0x08016928 performed ok. + Programming of 8 bytes at address 0x08016930 performed ok. + Programming of 8 bytes at address 0x08016938 performed ok. + Programming of 8 bytes at address 0x08016940 performed ok. + Programming of 8 bytes at address 0x08016948 performed ok. + Programming of 8 bytes at address 0x08016950 performed ok. + Programming of 8 bytes at address 0x08016958 performed ok. + Programming of 8 bytes at address 0x08016960 performed ok. + Programming of 8 bytes at address 0x08016968 performed ok. + Programming of 8 bytes at address 0x08016970 performed ok. + Programming of 8 bytes at address 0x08016978 performed ok. + Programming of 8 bytes at address 0x08016980 performed ok. + Programming of 8 bytes at address 0x08016988 performed ok. + Programming of 8 bytes at address 0x08016990 performed ok. + Programming of 8 bytes at address 0x08016998 performed ok. + Programming of 8 bytes at address 0x080169A0 performed ok. + Programming of 8 bytes at address 0x080169A8 performed ok. + Programming of 8 bytes at address 0x080169B0 performed ok. + Programming of 8 bytes at address 0x080169B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080169F0 performed ok. + Programming of 8 bytes at address 0x080169F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016A00 performed ok. + Programming of 8 bytes at address 0x08016A08 performed ok. + Programming of 8 bytes at address 0x08016A10 performed ok. + Programming of 8 bytes at address 0x08016A18 performed ok. + Programming of 8 bytes at address 0x08016A20 performed ok. + Programming of 8 bytes at address 0x08016A28 performed ok. + Programming of 8 bytes at address 0x08016A30 performed ok. + Programming of 8 bytes at address 0x08016A38 performed ok. + Programming of 8 bytes at address 0x08016A40 performed ok. + Programming of 8 bytes at address 0x08016A48 performed ok. + Programming of 8 bytes at address 0x08016A50 performed ok. + Programming of 8 bytes at address 0x08016A58 performed ok. + Programming of 8 bytes at address 0x08016A60 performed ok. + Programming of 8 bytes at address 0x08016A68 performed ok. + Programming of 8 bytes at address 0x08016A70 performed ok. + Programming of 8 bytes at address 0x08016A78 performed ok. + Programming of 8 bytes at address 0x08016A80 performed ok. + Programming of 8 bytes at address 0x08016A88 performed ok. + Programming of 8 bytes at address 0x08016A90 performed ok. + Programming of 8 bytes at address 0x08016A98 performed ok. + Programming of 8 bytes at address 0x08016AA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08016AC0 performed ok. + Programming of 8 bytes at address 0x08016AC8 performed ok. + Programming of 8 bytes at address 0x08016AD0 performed ok. + Programming of 8 bytes at address 0x08016AD8 performed ok. + Programming of 8 bytes at address 0x08016AE0 performed ok. + Programming of 8 bytes at address 0x08016AE8 performed ok. + Programming of 8 bytes at address 0x08016AF0 performed ok. + Programming of 8 bytes at address 0x08016AF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016B00 performed ok. + Programming of 8 bytes at address 0x08016B08 performed ok. + Programming of 8 bytes at address 0x08016B10 performed ok. + Programming of 8 bytes at address 0x08016B18 performed ok. + Programming of 8 bytes at address 0x08016B20 performed ok. + Programming of 8 bytes at address 0x08016B28 performed ok. + Programming of 8 bytes at address 0x08016B30 performed ok. + Programming of 8 bytes at address 0x08016B38 performed ok. + Programming of 8 bytes at address 0x08016B40 performed ok. + Programming of 8 bytes at address 0x08016B48 performed ok. + Programming of 8 bytes at address 0x08016B50 performed ok. + Programming of 8 bytes at address 0x08016B58 performed ok. + Programming of 8 bytes at address 0x08016B60 performed ok. + Programming of 8 bytes at address 0x08016B68 performed ok. + Programming of 8 bytes at address 0x08016B70 performed ok. + Programming of 8 bytes at address 0x08016B78 performed ok. + Programming of 8 bytes at address 0x08016B80 performed ok. + Programming of 8 bytes at address 0x08016B88 performed ok. + Programming of 8 bytes at address 0x08016B90 performed ok. + Programming of 8 bytes at address 0x08016B98 performed ok. +k. + Programming of 8 bytes at address 0x08016BA8 performed ok. + Programming of 8 bytes at address 0x08016BB0 performed ok. + Programming of 8 bytes at address 0x08016BB8 performed ok. + Programming of 8 bytes at address 0x08016BC0 performed ok. + Programming of 8 bytes at address 0x08016BC8 performed ok. + Programming of 8 bytes at address 0x08016BD0 performed ok. + Programming of 8 bytes at address 0x08016BD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016C00 performed ok. + Programming of 8 bytes at address 0x08016C08 performed ok. + Programming of 8 bytes at address 0x08016C10 performed ok. + Programming of 8 bytes at address 0x08016C18 performed ok. + Programming of 8 bytes at address 0x08016C20 performed ok. + Programming of 8 bytes at address 0x08016C28 performed ok. + Programming of 8 bytes at address 0x08016C30 performed ok. + Programming of 8 bytes at address 0x08016C38 performed ok. + Programming of 8 bytes at address 0x08016C40 performed ok. + Programming of 8 bytes at address 0x08016C48 performed ok. + Programming of 8 bytes at address 0x08016C50 performed ok. + Programming of 8 bytes at address 0x08016C58 performed ok. + Programming of 8 bytes at address 0x08016C60 performed ok. + Programming of 8 bytes at address 0x08016C68 performed ok. + Programming of 8 bytes at address 0x08016C70 performed ok. + Programming of 8 bytes at address 0x08016C78 performed ok. + Programming of 8 bytes at address 0x08016C80 performed ok. + Programming of 8 bytes at address 0x08016C88 performed ok. + Programming of 8 bytes at address 0x08016C90 performed ok. +k. + Programming of 8 bytes at address 0x08016CA0 performed ok. + Programming of 8 bytes at address 0x08016CA8 performed ok. + Programming of 8 bytes at address 0x08016CB0 performed ok. + Programming of 8 bytes at address 0x08016CB8 performed ok. + Programming of 8 bytes at address 0x08016CC0 performed ok. + Programming of 8 bytes at address 0x08016CC8 performed ok. + Programming of 8 bytes at address 0x08016CD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016D00 performed ok. + Programming of 8 bytes at address 0x08016D08 performed ok. + Programming of 8 bytes at address 0x08016D10 performed ok. + Programming of 8 bytes at address 0x08016D18 performed ok. + Programming of 8 bytes at address 0x08016D20 performed ok. + Programming of 8 bytes at address 0x08016D28 performed ok. + Programming of 8 bytes at address 0x08016D30 performed ok. + Programming of 8 bytes at address 0x08016D38 performed ok. + Programming of 8 bytes at address 0x08016D40 performed ok. + Programming of 8 bytes at address 0x08016D48 performed ok. + Programming of 8 bytes at address 0x08016D50 performed ok. + Programming of 8 bytes at address 0x08016D58 performed ok. + Programming of 8 bytes at address 0x08016D60 performed ok. + Programming of 8 bytes at address 0x08016D68 performed ok. + Programming of 8 bytes at address 0x08016D70 performed ok. + Programming of 8 bytes at address 0x08016D78 performed ok. + Programming of 8 bytes at address 0x08016D80 performed ok. + Programming of 8 bytes at address 0x08016D88 performed ok. + Programming of 8 bytes at address 0x08016D90 performed ok. + Programming of 8 bytes at address 0x08016D98 performed ok. + Programming of 8 bytes at address 0x08016DA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08016DC0 performed ok. + Programming of 8 bytes at address 0x08016DC8 performed ok. + Programming of 8 bytes at address 0x08016DD0 performed ok. + Programming of 8 bytes at address 0x08016DD8 performed ok. + Programming of 8 bytes at address 0x08016DE0 performed ok. + Programming of 8 bytes at address 0x08016DE8 performed ok. + Programming of 8 bytes at address 0x08016DF0 performed ok. + Programming of 8 bytes at address 0x08016DF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016E00 performed ok. + Programming of 8 bytes at address 0x08016E08 performed ok. + Programming of 8 bytes at address 0x08016E10 performed ok. + Programming of 8 bytes at address 0x08016E18 performed ok. + Programming of 8 bytes at address 0x08016E20 performed ok. + Programming of 8 bytes at address 0x08016E28 performed ok. + Programming of 8 bytes at address 0x08016E30 performed ok. + Programming of 8 bytes at address 0x08016E38 performed ok. + Programming of 8 bytes at address 0x08016E40 performed ok. + Programming of 8 bytes at address 0x08016E48 performed ok. + Programming of 8 bytes at address 0x08016E50 performed ok. + Programming of 8 bytes at address 0x08016E58 performed ok. + Programming of 8 bytes at address 0x08016E60 performed ok. + Programming of 8 bytes at address 0x08016E68 performed ok. + Programming of 8 bytes at address 0x08016E70 performed ok. + Programming of 8 bytes at address 0x08016E78 performed ok. + Programming of 8 bytes at address 0x08016E80 performed ok. + Programming of 8 bytes at address 0x08016E88 performed ok. + Programming of 8 bytes at address 0x08016E90 performed ok. + Programming of 8 bytes at address 0x08016E98 performed ok. + Programming of 8 bytes at address 0x08016EA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08016EC0 performed ok. + Programming of 8 bytes at address 0x08016EC8 performed ok. + Programming of 8 bytes at address 0x08016ED0 performed ok. + Programming of 8 bytes at address 0x08016ED8 performed ok. + Programming of 8 bytes at address 0x08016EE0 performed ok. + Programming of 8 bytes at address 0x08016EE8 performed ok. + Programming of 8 bytes at address 0x08016EF0 performed ok. + Programming of 8 bytes at address 0x08016EF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08016F00 performed ok. + Programming of 8 bytes at address 0x08016F08 performed ok. + Programming of 8 bytes at address 0x08016F10 performed ok. + Programming of 8 bytes at address 0x08016F18 performed ok. + Programming of 8 bytes at address 0x08016F20 performed ok. + Programming of 8 bytes at address 0x08016F28 performed ok. + Programming of 8 bytes at address 0x08016F30 performed ok. + Programming of 8 bytes at address 0x08016F38 performed ok. + Programming of 8 bytes at address 0x08016F40 performed ok. + Programming of 8 bytes at address 0x08016F48 performed ok. + Programming of 8 bytes at address 0x08016F50 performed ok. + Programming of 8 bytes at address 0x08016F58 performed ok. + Programming of 8 bytes at address 0x08016F60 performed ok. + Programming of 8 bytes at address 0x08016F68 performed ok. + Programming of 8 bytes at address 0x08016F70 performed ok. + Programming of 8 bytes at address 0x08016F78 performed ok. + Programming of 8 bytes at address 0x08016F80 performed ok. + Programming of 8 bytes at address 0x08016F88 performed ok. + Programming of 8 bytes at address 0x08016F90 performed ok. + Programming of 8 bytes at address 0x08016F98 performed ok. + Programming of 8 bytes at address 0x08016FA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08016FC0 performed ok. + Programming of 8 bytes at address 0x08016FC8 performed ok. + Programming of 8 bytes at address 0x08016FD0 performed ok. + Programming of 8 bytes at address 0x08016FD8 performed ok. + Programming of 8 bytes at address 0x08016FE0 performed ok. + Programming of 8 bytes at address 0x08016FE8 performed ok. + Programming of 8 bytes at address 0x08016FF0 performed ok. + Programming of 8 bytes at address 0x08016FF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017000 performed ok. + Programming of 8 bytes at address 0x08017008 performed ok. + Programming of 8 bytes at address 0x08017010 performed ok. + Programming of 8 bytes at address 0x08017018 performed ok. + Programming of 8 bytes at address 0x08017020 performed ok. + Programming of 8 bytes at address 0x08017028 performed ok. + Programming of 8 bytes at address 0x08017030 performed ok. + Programming of 8 bytes at address 0x08017038 performed ok. + Programming of 8 bytes at address 0x08017040 performed ok. + Programming of 8 bytes at address 0x08017048 performed ok. + Programming of 8 bytes at address 0x08017050 performed ok. + Programming of 8 bytes at address 0x08017058 performed ok. + Programming of 8 bytes at address 0x08017060 performed ok. + Programming of 8 bytes at address 0x08017068 performed ok. + Programming of 8 bytes at address 0x08017070 performed ok. + Programming of 8 bytes at address 0x08017078 performed ok. + Programming of 8 bytes at address 0x08017080 performed ok. + Programming of 8 bytes at address 0x08017088 performed ok. + Programming of 8 bytes at address 0x08017090 performed ok. +k. + Programming of 8 bytes at address 0x080170A0 performed ok. + Programming of 8 bytes at address 0x080170A8 performed ok. + Programming of 8 bytes at address 0x080170B0 performed ok. + Programming of 8 bytes at address 0x080170B8 performed ok. + Programming of 8 bytes at address 0x080170C0 performed ok. + Programming of 8 bytes at address 0x080170C8 performed ok. + Programming of 8 bytes at address 0x080170D0 performed ok. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017100 performed ok. + Programming of 8 bytes at address 0x08017108 performed ok. + Programming of 8 bytes at address 0x08017110 performed ok. + Programming of 8 bytes at address 0x08017118 performed ok. + Programming of 8 bytes at address 0x08017120 performed ok. + Programming of 8 bytes at address 0x08017128 performed ok. + Programming of 8 bytes at address 0x08017130 performed ok. + Programming of 8 bytes at address 0x08017138 performed ok. + Programming of 8 bytes at address 0x08017140 performed ok. + Programming of 8 bytes at address 0x08017148 performed ok. + Programming of 8 bytes at address 0x08017150 performed ok. + Programming of 8 bytes at address 0x08017158 performed ok. + Programming of 8 bytes at address 0x08017160 performed ok. + Programming of 8 bytes at address 0x08017168 performed ok. + Programming of 8 bytes at address 0x08017170 performed ok. + Programming of 8 bytes at address 0x08017178 performed ok. + Programming of 8 bytes at address 0x08017180 performed ok. + Programming of 8 bytes at address 0x08017188 performed ok. + Programming of 8 bytes at address 0x08017190 performed ok. + Programming of 8 bytes at address 0x08017198 performed ok. + Programming of 8 bytes at address 0x080171A0 performed ok. + Programming of 8 bytes at address 0x080171A8 performed ok. + Programming of 8 bytes at address 0x080171B0 performed ok. + Programming of 8 bytes at address 0x080171B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080171F0 performed ok. + Programming of 8 bytes at address 0x080171F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017200 performed ok. + Programming of 8 bytes at address 0x08017208 performed ok. + Programming of 8 bytes at address 0x08017210 performed ok. + Programming of 8 bytes at address 0x08017218 performed ok. + Programming of 8 bytes at address 0x08017220 performed ok. + Programming of 8 bytes at address 0x08017228 performed ok. + Programming of 8 bytes at address 0x08017230 performed ok. + Programming of 8 bytes at address 0x08017238 performed ok. + Programming of 8 bytes at address 0x08017240 performed ok. + Programming of 8 bytes at address 0x08017248 performed ok. + Programming of 8 bytes at address 0x08017250 performed ok. + Programming of 8 bytes at address 0x08017258 performed ok. + Programming of 8 bytes at address 0x08017260 performed ok. + Programming of 8 bytes at address 0x08017268 performed ok. + Programming of 8 bytes at address 0x08017270 performed ok. + Programming of 8 bytes at address 0x08017278 performed ok. + Programming of 8 bytes at address 0x08017280 performed ok. + Programming of 8 bytes at address 0x08017288 performed ok. + Programming of 8 bytes at address 0x08017290 performed ok. +k. + Programming of 8 bytes at address 0x080172A0 performed ok. + Programming of 8 bytes at address 0x080172A8 performed ok. + Programming of 8 bytes at address 0x080172B0 performed ok. + Programming of 8 bytes at address 0x080172B8 performed ok. + Programming of 8 bytes at address 0x080172C0 performed ok. + Programming of 8 bytes at address 0x080172C8 performed ok. + Programming of 8 bytes at address 0x080172D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017300 performed ok. + Programming of 8 bytes at address 0x08017308 performed ok. + Programming of 8 bytes at address 0x08017310 performed ok. + Programming of 8 bytes at address 0x08017318 performed ok. + Programming of 8 bytes at address 0x08017320 performed ok. + Programming of 8 bytes at address 0x08017328 performed ok. + Programming of 8 bytes at address 0x08017330 performed ok. + Programming of 8 bytes at address 0x08017338 performed ok. + Programming of 8 bytes at address 0x08017340 performed ok. + Programming of 8 bytes at address 0x08017348 performed ok. + Programming of 8 bytes at address 0x08017350 performed ok. + Programming of 8 bytes at address 0x08017358 performed ok. + Programming of 8 bytes at address 0x08017360 performed ok. + Programming of 8 bytes at address 0x08017368 performed ok. + Programming of 8 bytes at address 0x08017370 performed ok. + Programming of 8 bytes at address 0x08017378 performed ok. + Programming of 8 bytes at address 0x08017380 performed ok. + Programming of 8 bytes at address 0x08017388 performed ok. + Programming of 8 bytes at address 0x08017390 performed ok. +k. + Programming of 8 bytes at address 0x080173A0 performed ok. + Programming of 8 bytes at address 0x080173A8 performed ok. + Programming of 8 bytes at address 0x080173B0 performed ok. + Programming of 8 bytes at address 0x080173B8 performed ok. + Programming of 8 bytes at address 0x080173C0 performed ok. + Programming of 8 bytes at address 0x080173C8 performed ok. + Programming of 8 bytes at address 0x080173D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017400 performed ok. + Programming of 8 bytes at address 0x08017408 performed ok. + Programming of 8 bytes at address 0x08017410 performed ok. + Programming of 8 bytes at address 0x08017418 performed ok. + Programming of 8 bytes at address 0x08017420 performed ok. + Programming of 8 bytes at address 0x08017428 performed ok. + Programming of 8 bytes at address 0x08017430 performed ok. + Programming of 8 bytes at address 0x08017438 performed ok. + Programming of 8 bytes at address 0x08017440 performed ok. + Programming of 8 bytes at address 0x08017448 performed ok. + Programming of 8 bytes at address 0x08017450 performed ok. + Programming of 8 bytes at address 0x08017458 performed ok. + Programming of 8 bytes at address 0x08017460 performed ok. + Programming of 8 bytes at address 0x08017468 performed ok. + Programming of 8 bytes at address 0x08017470 performed ok. + Programming of 8 bytes at address 0x08017478 performed ok. + Programming of 8 bytes at address 0x08017480 performed ok. + Programming of 8 bytes at address 0x08017488 performed ok. + Programming of 8 bytes at address 0x08017490 performed ok. + Programming of 8 bytes at address 0x08017498 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080174B8 performed ok. + Programming of 8 bytes at address 0x080174C0 performed ok. + Programming of 8 bytes at address 0x080174C8 performed ok. + Programming of 8 bytes at address 0x080174D0 performed ok. + Programming of 8 bytes at address 0x080174D8 performed ok. + Programming of 8 bytes at address 0x080174E0 performed ok. + Programming of 8 bytes at address 0x080174E8 performed ok. + Programming of 8 bytes at address 0x080174F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017500 performed ok. + Programming of 8 bytes at address 0x08017508 performed ok. + Programming of 8 bytes at address 0x08017510 performed ok. + Programming of 8 bytes at address 0x08017518 performed ok. + Programming of 8 bytes at address 0x08017520 performed ok. + Programming of 8 bytes at address 0x08017528 performed ok. + Programming of 8 bytes at address 0x08017530 performed ok. + Programming of 8 bytes at address 0x08017538 performed ok. + Programming of 8 bytes at address 0x08017540 performed ok. + Programming of 8 bytes at address 0x08017548 performed ok. + Programming of 8 bytes at address 0x08017550 performed ok. + Programming of 8 bytes at address 0x08017558 performed ok. + Programming of 8 bytes at address 0x08017560 performed ok. + Programming of 8 bytes at address 0x08017568 performed ok. + Programming of 8 bytes at address 0x08017570 performed ok. + Programming of 8 bytes at address 0x08017578 performed ok. + Programming of 8 bytes at address 0x08017580 performed ok. + Programming of 8 bytes at address 0x08017588 performed ok. + Programming of 8 bytes at address 0x08017590 performed ok. + Programming of 8 bytes at address 0x08017598 performed ok. + Programming of 8 bytes at address 0x080175A0 performed ok. + Programming of 8 bytes at address 0x080175A8 performed ok. + Programming of 8 bytes at address 0x080175B0 performed ok. + Programming of 8 bytes at address 0x080175B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017600 performed ok. + Programming of 8 bytes at address 0x08017608 performed ok. + Programming of 8 bytes at address 0x08017610 performed ok. + Programming of 8 bytes at address 0x08017618 performed ok. + Programming of 8 bytes at address 0x08017620 performed ok. + Programming of 8 bytes at address 0x08017628 performed ok. + Programming of 8 bytes at address 0x08017630 performed ok. + Programming of 8 bytes at address 0x08017638 performed ok. + Programming of 8 bytes at address 0x08017640 performed ok. + Programming of 8 bytes at address 0x08017648 performed ok. + Programming of 8 bytes at address 0x08017650 performed ok. + Programming of 8 bytes at address 0x08017658 performed ok. + Programming of 8 bytes at address 0x08017660 performed ok. + Programming of 8 bytes at address 0x08017668 performed ok. + Programming of 8 bytes at address 0x08017670 performed ok. + Programming of 8 bytes at address 0x08017678 performed ok. + Programming of 8 bytes at address 0x08017680 performed ok. + Programming of 8 bytes at address 0x08017688 performed ok. + Programming of 8 bytes at address 0x08017690 performed ok. + Programming of 8 bytes at address 0x08017698 performed ok. +k. +k. + Programming of 8 bytes at address 0x080176B0 performed ok. + Programming of 8 bytes at address 0x080176B8 performed ok. + Programming of 8 bytes at address 0x080176C0 performed ok. + Programming of 8 bytes at address 0x080176C8 performed ok. + Programming of 8 bytes at address 0x080176D0 performed ok. + Programming of 8 bytes at address 0x080176D8 performed ok. + Programming of 8 bytes at address 0x080176E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017700 performed ok. + Programming of 8 bytes at address 0x08017708 performed ok. + Programming of 8 bytes at address 0x08017710 performed ok. + Programming of 8 bytes at address 0x08017718 performed ok. + Programming of 8 bytes at address 0x08017720 performed ok. + Programming of 8 bytes at address 0x08017728 performed ok. + Programming of 8 bytes at address 0x08017730 performed ok. + Programming of 8 bytes at address 0x08017738 performed ok. + Programming of 8 bytes at address 0x08017740 performed ok. + Programming of 8 bytes at address 0x08017748 performed ok. + Programming of 8 bytes at address 0x08017750 performed ok. + Programming of 8 bytes at address 0x08017758 performed ok. + Programming of 8 bytes at address 0x08017760 performed ok. + Programming of 8 bytes at address 0x08017768 performed ok. + Programming of 8 bytes at address 0x08017770 performed ok. + Programming of 8 bytes at address 0x08017778 performed ok. + Programming of 8 bytes at address 0x08017780 performed ok. + Programming of 8 bytes at address 0x08017788 performed ok. + Programming of 8 bytes at address 0x08017790 performed ok. + Programming of 8 bytes at address 0x08017798 performed ok. + Programming of 8 bytes at address 0x080177A0 performed ok. + Programming of 8 bytes at address 0x080177A8 performed ok. + Programming of 8 bytes at address 0x080177B0 performed ok. + Programming of 8 bytes at address 0x080177B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080177F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017800 performed ok. + Programming of 8 bytes at address 0x08017808 performed ok. + Programming of 8 bytes at address 0x08017810 performed ok. + Programming of 8 bytes at address 0x08017818 performed ok. + Programming of 8 bytes at address 0x08017820 performed ok. + Programming of 8 bytes at address 0x08017828 performed ok. + Programming of 8 bytes at address 0x08017830 performed ok. + Programming of 8 bytes at address 0x08017838 performed ok. + Programming of 8 bytes at address 0x08017840 performed ok. + Programming of 8 bytes at address 0x08017848 performed ok. + Programming of 8 bytes at address 0x08017850 performed ok. + Programming of 8 bytes at address 0x08017858 performed ok. + Programming of 8 bytes at address 0x08017860 performed ok. + Programming of 8 bytes at address 0x08017868 performed ok. + Programming of 8 bytes at address 0x08017870 performed ok. + Programming of 8 bytes at address 0x08017878 performed ok. + Programming of 8 bytes at address 0x08017880 performed ok. + Programming of 8 bytes at address 0x08017888 performed ok. + Programming of 8 bytes at address 0x08017890 performed ok. + Programming of 8 bytes at address 0x08017898 performed ok. +k. + Programming of 8 bytes at address 0x080178A8 performed ok. + Programming of 8 bytes at address 0x080178B0 performed ok. + Programming of 8 bytes at address 0x080178B8 performed ok. + Programming of 8 bytes at address 0x080178C0 performed ok. + Programming of 8 bytes at address 0x080178C8 performed ok. + Programming of 8 bytes at address 0x080178D0 performed ok. + Programming of 8 bytes at address 0x080178D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017900 performed ok. + Programming of 8 bytes at address 0x08017908 performed ok. + Programming of 8 bytes at address 0x08017910 performed ok. + Programming of 8 bytes at address 0x08017918 performed ok. + Programming of 8 bytes at address 0x08017920 performed ok. + Programming of 8 bytes at address 0x08017928 performed ok. + Programming of 8 bytes at address 0x08017930 performed ok. + Programming of 8 bytes at address 0x08017938 performed ok. + Programming of 8 bytes at address 0x08017940 performed ok. + Programming of 8 bytes at address 0x08017948 performed ok. + Programming of 8 bytes at address 0x08017950 performed ok. + Programming of 8 bytes at address 0x08017958 performed ok. + Programming of 8 bytes at address 0x08017960 performed ok. + Programming of 8 bytes at address 0x08017968 performed ok. + Programming of 8 bytes at address 0x08017970 performed ok. + Programming of 8 bytes at address 0x08017978 performed ok. + Programming of 8 bytes at address 0x08017980 performed ok. + Programming of 8 bytes at address 0x08017988 performed ok. + Programming of 8 bytes at address 0x08017990 performed ok. + Programming of 8 bytes at address 0x08017998 performed ok. + Programming of 8 bytes at address 0x080179A0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080179C8 performed ok. + Programming of 8 bytes at address 0x080179D0 performed ok. + Programming of 8 bytes at address 0x080179D8 performed ok. + Programming of 8 bytes at address 0x080179E0 performed ok. + Programming of 8 bytes at address 0x080179E8 performed ok. + Programming of 8 bytes at address 0x080179F0 performed ok. + Programming of 8 bytes at address 0x080179F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017A00 performed ok. + Programming of 8 bytes at address 0x08017A08 performed ok. + Programming of 8 bytes at address 0x08017A10 performed ok. + Programming of 8 bytes at address 0x08017A18 performed ok. + Programming of 8 bytes at address 0x08017A20 performed ok. + Programming of 8 bytes at address 0x08017A28 performed ok. + Programming of 8 bytes at address 0x08017A30 performed ok. + Programming of 8 bytes at address 0x08017A38 performed ok. + Programming of 8 bytes at address 0x08017A40 performed ok. + Programming of 8 bytes at address 0x08017A48 performed ok. + Programming of 8 bytes at address 0x08017A50 performed ok. + Programming of 8 bytes at address 0x08017A58 performed ok. + Programming of 8 bytes at address 0x08017A60 performed ok. + Programming of 8 bytes at address 0x08017A68 performed ok. + Programming of 8 bytes at address 0x08017A70 performed ok. + Programming of 8 bytes at address 0x08017A78 performed ok. + Programming of 8 bytes at address 0x08017A80 performed ok. + Programming of 8 bytes at address 0x08017A88 performed ok. + Programming of 8 bytes at address 0x08017A90 performed ok. + Programming of 8 bytes at address 0x08017A98 performed ok. +k. +k. + Programming of 8 bytes at address 0x08017AB0 performed ok. + Programming of 8 bytes at address 0x08017AB8 performed ok. + Programming of 8 bytes at address 0x08017AC0 performed ok. + Programming of 8 bytes at address 0x08017AC8 performed ok. + Programming of 8 bytes at address 0x08017AD0 performed ok. + Programming of 8 bytes at address 0x08017AD8 performed ok. + Programming of 8 bytes at address 0x08017AE0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017B00 performed ok. + Programming of 8 bytes at address 0x08017B08 performed ok. + Programming of 8 bytes at address 0x08017B10 performed ok. + Programming of 8 bytes at address 0x08017B18 performed ok. + Programming of 8 bytes at address 0x08017B20 performed ok. + Programming of 8 bytes at address 0x08017B28 performed ok. + Programming of 8 bytes at address 0x08017B30 performed ok. + Programming of 8 bytes at address 0x08017B38 performed ok. + Programming of 8 bytes at address 0x08017B40 performed ok. + Programming of 8 bytes at address 0x08017B48 performed ok. + Programming of 8 bytes at address 0x08017B50 performed ok. + Programming of 8 bytes at address 0x08017B58 performed ok. + Programming of 8 bytes at address 0x08017B60 performed ok. + Programming of 8 bytes at address 0x08017B68 performed ok. + Programming of 8 bytes at address 0x08017B70 performed ok. + Programming of 8 bytes at address 0x08017B78 performed ok. + Programming of 8 bytes at address 0x08017B80 performed ok. + Programming of 8 bytes at address 0x08017B88 performed ok. + Programming of 8 bytes at address 0x08017B90 performed ok. + Programming of 8 bytes at address 0x08017B98 performed ok. + Programming of 8 bytes at address 0x08017BA0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08017BC8 performed ok. + Programming of 8 bytes at address 0x08017BD0 performed ok. + Programming of 8 bytes at address 0x08017BD8 performed ok. + Programming of 8 bytes at address 0x08017BE0 performed ok. + Programming of 8 bytes at address 0x08017BE8 performed ok. + Programming of 8 bytes at address 0x08017BF0 performed ok. + Programming of 8 bytes at address 0x08017BF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017C00 performed ok. + Programming of 8 bytes at address 0x08017C08 performed ok. + Programming of 8 bytes at address 0x08017C10 performed ok. + Programming of 8 bytes at address 0x08017C18 performed ok. + Programming of 8 bytes at address 0x08017C20 performed ok. + Programming of 8 bytes at address 0x08017C28 performed ok. + Programming of 8 bytes at address 0x08017C30 performed ok. + Programming of 8 bytes at address 0x08017C38 performed ok. + Programming of 8 bytes at address 0x08017C40 performed ok. + Programming of 8 bytes at address 0x08017C48 performed ok. + Programming of 8 bytes at address 0x08017C50 performed ok. + Programming of 8 bytes at address 0x08017C58 performed ok. + Programming of 8 bytes at address 0x08017C60 performed ok. + Programming of 8 bytes at address 0x08017C68 performed ok. + Programming of 8 bytes at address 0x08017C70 performed ok. + Programming of 8 bytes at address 0x08017C78 performed ok. + Programming of 8 bytes at address 0x08017C80 performed ok. + Programming of 8 bytes at address 0x08017C88 performed ok. + Programming of 8 bytes at address 0x08017C90 performed ok. + Programming of 8 bytes at address 0x08017C98 performed ok. + Programming of 8 bytes at address 0x08017CA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08017CC0 performed ok. + Programming of 8 bytes at address 0x08017CC8 performed ok. + Programming of 8 bytes at address 0x08017CD0 performed ok. + Programming of 8 bytes at address 0x08017CD8 performed ok. + Programming of 8 bytes at address 0x08017CE0 performed ok. + Programming of 8 bytes at address 0x08017CE8 performed ok. + Programming of 8 bytes at address 0x08017CF0 performed ok. + Programming of 8 bytes at address 0x08017CF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017D00 performed ok. + Programming of 8 bytes at address 0x08017D08 performed ok. + Programming of 8 bytes at address 0x08017D10 performed ok. + Programming of 8 bytes at address 0x08017D18 performed ok. + Programming of 8 bytes at address 0x08017D20 performed ok. + Programming of 8 bytes at address 0x08017D28 performed ok. + Programming of 8 bytes at address 0x08017D30 performed ok. + Programming of 8 bytes at address 0x08017D38 performed ok. + Programming of 8 bytes at address 0x08017D40 performed ok. + Programming of 8 bytes at address 0x08017D48 performed ok. + Programming of 8 bytes at address 0x08017D50 performed ok. + Programming of 8 bytes at address 0x08017D58 performed ok. + Programming of 8 bytes at address 0x08017D60 performed ok. + Programming of 8 bytes at address 0x08017D68 performed ok. + Programming of 8 bytes at address 0x08017D70 performed ok. + Programming of 8 bytes at address 0x08017D78 performed ok. + Programming of 8 bytes at address 0x08017D80 performed ok. + Programming of 8 bytes at address 0x08017D88 performed ok. + Programming of 8 bytes at address 0x08017D90 performed ok. + Programming of 8 bytes at address 0x08017D98 performed ok. + Programming of 8 bytes at address 0x08017DA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08017DC0 performed ok. + Programming of 8 bytes at address 0x08017DC8 performed ok. + Programming of 8 bytes at address 0x08017DD0 performed ok. + Programming of 8 bytes at address 0x08017DD8 performed ok. + Programming of 8 bytes at address 0x08017DE0 performed ok. + Programming of 8 bytes at address 0x08017DE8 performed ok. + Programming of 8 bytes at address 0x08017DF0 performed ok. + Programming of 8 bytes at address 0x08017DF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017E00 performed ok. + Programming of 8 bytes at address 0x08017E08 performed ok. + Programming of 8 bytes at address 0x08017E10 performed ok. + Programming of 8 bytes at address 0x08017E18 performed ok. + Programming of 8 bytes at address 0x08017E20 performed ok. + Programming of 8 bytes at address 0x08017E28 performed ok. + Programming of 8 bytes at address 0x08017E30 performed ok. + Programming of 8 bytes at address 0x08017E38 performed ok. + Programming of 8 bytes at address 0x08017E40 performed ok. + Programming of 8 bytes at address 0x08017E48 performed ok. + Programming of 8 bytes at address 0x08017E50 performed ok. + Programming of 8 bytes at address 0x08017E58 performed ok. + Programming of 8 bytes at address 0x08017E60 performed ok. + Programming of 8 bytes at address 0x08017E68 performed ok. + Programming of 8 bytes at address 0x08017E70 performed ok. + Programming of 8 bytes at address 0x08017E78 performed ok. + Programming of 8 bytes at address 0x08017E80 performed ok. + Programming of 8 bytes at address 0x08017E88 performed ok. + Programming of 8 bytes at address 0x08017E90 performed ok. +k. + Programming of 8 bytes at address 0x08017EA0 performed ok. + Programming of 8 bytes at address 0x08017EA8 performed ok. + Programming of 8 bytes at address 0x08017EB0 performed ok. + Programming of 8 bytes at address 0x08017EB8 performed ok. + Programming of 8 bytes at address 0x08017EC0 performed ok. + Programming of 8 bytes at address 0x08017EC8 performed ok. + Programming of 8 bytes at address 0x08017ED0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08017F00 performed ok. + Programming of 8 bytes at address 0x08017F08 performed ok. + Programming of 8 bytes at address 0x08017F10 performed ok. + Programming of 8 bytes at address 0x08017F18 performed ok. + Programming of 8 bytes at address 0x08017F20 performed ok. + Programming of 8 bytes at address 0x08017F28 performed ok. + Programming of 8 bytes at address 0x08017F30 performed ok. + Programming of 8 bytes at address 0x08017F38 performed ok. + Programming of 8 bytes at address 0x08017F40 performed ok. + Programming of 8 bytes at address 0x08017F48 performed ok. + Programming of 8 bytes at address 0x08017F50 performed ok. + Programming of 8 bytes at address 0x08017F58 performed ok. + Programming of 8 bytes at address 0x08017F60 performed ok. + Programming of 8 bytes at address 0x08017F68 performed ok. + Programming of 8 bytes at address 0x08017F70 performed ok. + Programming of 8 bytes at address 0x08017F78 performed ok. + Programming of 8 bytes at address 0x08017F80 performed ok. + Programming of 8 bytes at address 0x08017F88 performed ok. + Programming of 8 bytes at address 0x08017F90 performed ok. + Programming of 8 bytes at address 0x08017F98 performed ok. + Programming of 8 bytes at address 0x08017FA0 performed ok. + Programming of 8 bytes at address 0x08017FA8 performed ok. + Programming of 8 bytes at address 0x08017FB0 performed ok. + Programming of 8 bytes at address 0x08017FB8 performed ok. + Programming of 8 bytes at address 0x08017FC0 performed ok. +k. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018000 performed ok. + Programming of 8 bytes at address 0x08018008 performed ok. + Programming of 8 bytes at address 0x08018010 performed ok. + Programming of 8 bytes at address 0x08018018 performed ok. + Programming of 8 bytes at address 0x08018020 performed ok. + Programming of 8 bytes at address 0x08018028 performed ok. + Programming of 8 bytes at address 0x08018030 performed ok. + Programming of 8 bytes at address 0x08018038 performed ok. + Programming of 8 bytes at address 0x08018040 performed ok. + Programming of 8 bytes at address 0x08018048 performed ok. + Programming of 8 bytes at address 0x08018050 performed ok. + Programming of 8 bytes at address 0x08018058 performed ok. + Programming of 8 bytes at address 0x08018060 performed ok. + Programming of 8 bytes at address 0x08018068 performed ok. + Programming of 8 bytes at address 0x08018070 performed ok. + Programming of 8 bytes at address 0x08018078 performed ok. + Programming of 8 bytes at address 0x08018080 performed ok. + Programming of 8 bytes at address 0x08018088 performed ok. + Programming of 8 bytes at address 0x08018090 performed ok. + Programming of 8 bytes at address 0x08018098 performed ok. + Programming of 8 bytes at address 0x080180A0 performed ok. + Programming of 8 bytes at address 0x080180A8 performed ok. + Programming of 8 bytes at address 0x080180B0 performed ok. + Programming of 8 bytes at address 0x080180B8 performed ok. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080180E8 performed ok. + Programming of 8 bytes at address 0x080180F0 performed ok. + Programming of 8 bytes at address 0x080180F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018100 performed ok. + Programming of 8 bytes at address 0x08018108 performed ok. + Programming of 8 bytes at address 0x08018110 performed ok. + Programming of 8 bytes at address 0x08018118 performed ok. + Programming of 8 bytes at address 0x08018120 performed ok. + Programming of 8 bytes at address 0x08018128 performed ok. + Programming of 8 bytes at address 0x08018130 performed ok. + Programming of 8 bytes at address 0x08018138 performed ok. + Programming of 8 bytes at address 0x08018140 performed ok. + Programming of 8 bytes at address 0x08018148 performed ok. + Programming of 8 bytes at address 0x08018150 performed ok. + Programming of 8 bytes at address 0x08018158 performed ok. + Programming of 8 bytes at address 0x08018160 performed ok. + Programming of 8 bytes at address 0x08018168 performed ok. + Programming of 8 bytes at address 0x08018170 performed ok. + Programming of 8 bytes at address 0x08018178 performed ok. + Programming of 8 bytes at address 0x08018180 performed ok. + Programming of 8 bytes at address 0x08018188 performed ok. + Programming of 8 bytes at address 0x08018190 performed ok. + Programming of 8 bytes at address 0x08018198 performed ok. + Programming of 8 bytes at address 0x080181A0 performed ok. + Programming of 8 bytes at address 0x080181A8 performed ok. +k. +k. + Programming of 8 bytes at address 0x080181C0 performed ok. + Programming of 8 bytes at address 0x080181C8 performed ok. + Programming of 8 bytes at address 0x080181D0 performed ok. + Programming of 8 bytes at address 0x080181D8 performed ok. + Programming of 8 bytes at address 0x080181E0 performed ok. + Programming of 8 bytes at address 0x080181E8 performed ok. + Programming of 8 bytes at address 0x080181F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018200 performed ok. + Programming of 8 bytes at address 0x08018208 performed ok. + Programming of 8 bytes at address 0x08018210 performed ok. + Programming of 8 bytes at address 0x08018218 performed ok. + Programming of 8 bytes at address 0x08018220 performed ok. + Programming of 8 bytes at address 0x08018228 performed ok. + Programming of 8 bytes at address 0x08018230 performed ok. + Programming of 8 bytes at address 0x08018238 performed ok. + Programming of 8 bytes at address 0x08018240 performed ok. + Programming of 8 bytes at address 0x08018248 performed ok. + Programming of 8 bytes at address 0x08018250 performed ok. + Programming of 8 bytes at address 0x08018258 performed ok. + Programming of 8 bytes at address 0x08018260 performed ok. + Programming of 8 bytes at address 0x08018268 performed ok. + Programming of 8 bytes at address 0x08018270 performed ok. + Programming of 8 bytes at address 0x08018278 performed ok. + Programming of 8 bytes at address 0x08018280 performed ok. + Programming of 8 bytes at address 0x08018288 performed ok. + Programming of 8 bytes at address 0x08018290 performed ok. + Programming of 8 bytes at address 0x08018298 performed ok. + Programming of 8 bytes at address 0x080182A0 performed ok. + Programming of 8 bytes at address 0x080182A8 performed ok. + Programming of 8 bytes at address 0x080182B0 performed ok. + Programming of 8 bytes at address 0x080182B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080182F0 performed ok. + Programming of 8 bytes at address 0x080182F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018300 performed ok. + Programming of 8 bytes at address 0x08018308 performed ok. + Programming of 8 bytes at address 0x08018310 performed ok. + Programming of 8 bytes at address 0x08018318 performed ok. + Programming of 8 bytes at address 0x08018320 performed ok. + Programming of 8 bytes at address 0x08018328 performed ok. + Programming of 8 bytes at address 0x08018330 performed ok. + Programming of 8 bytes at address 0x08018338 performed ok. + Programming of 8 bytes at address 0x08018340 performed ok. + Programming of 8 bytes at address 0x08018348 performed ok. + Programming of 8 bytes at address 0x08018350 performed ok. + Programming of 8 bytes at address 0x08018358 performed ok. + Programming of 8 bytes at address 0x08018360 performed ok. + Programming of 8 bytes at address 0x08018368 performed ok. + Programming of 8 bytes at address 0x08018370 performed ok. + Programming of 8 bytes at address 0x08018378 performed ok. + Programming of 8 bytes at address 0x08018380 performed ok. + Programming of 8 bytes at address 0x08018388 performed ok. + Programming of 8 bytes at address 0x08018390 performed ok. +k. + Programming of 8 bytes at address 0x080183A0 performed ok. + Programming of 8 bytes at address 0x080183A8 performed ok. + Programming of 8 bytes at address 0x080183B0 performed ok. + Programming of 8 bytes at address 0x080183B8 performed ok. + Programming of 8 bytes at address 0x080183C0 performed ok. + Programming of 8 bytes at address 0x080183C8 performed ok. + Programming of 8 bytes at address 0x080183D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018400 performed ok. + Programming of 8 bytes at address 0x08018408 performed ok. + Programming of 8 bytes at address 0x08018410 performed ok. + Programming of 8 bytes at address 0x08018418 performed ok. + Programming of 8 bytes at address 0x08018420 performed ok. + Programming of 8 bytes at address 0x08018428 performed ok. + Programming of 8 bytes at address 0x08018430 performed ok. + Programming of 8 bytes at address 0x08018438 performed ok. + Programming of 8 bytes at address 0x08018440 performed ok. + Programming of 8 bytes at address 0x08018448 performed ok. + Programming of 8 bytes at address 0x08018450 performed ok. + Programming of 8 bytes at address 0x08018458 performed ok. + Programming of 8 bytes at address 0x08018460 performed ok. + Programming of 8 bytes at address 0x08018468 performed ok. + Programming of 8 bytes at address 0x08018470 performed ok. + Programming of 8 bytes at address 0x08018478 performed ok. + Programming of 8 bytes at address 0x08018480 performed ok. + Programming of 8 bytes at address 0x08018488 performed ok. + Programming of 8 bytes at address 0x08018490 performed ok. + Programming of 8 bytes at address 0x08018498 performed ok. + Programming of 8 bytes at address 0x080184A0 performed ok. + Programming of 8 bytes at address 0x080184A8 performed ok. + Programming of 8 bytes at address 0x080184B0 performed ok. + Programming of 8 bytes at address 0x080184B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080184F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018500 performed ok. + Programming of 8 bytes at address 0x08018508 performed ok. + Programming of 8 bytes at address 0x08018510 performed ok. + Programming of 8 bytes at address 0x08018518 performed ok. + Programming of 8 bytes at address 0x08018520 performed ok. + Programming of 8 bytes at address 0x08018528 performed ok. + Programming of 8 bytes at address 0x08018530 performed ok. + Programming of 8 bytes at address 0x08018538 performed ok. + Programming of 8 bytes at address 0x08018540 performed ok. + Programming of 8 bytes at address 0x08018548 performed ok. + Programming of 8 bytes at address 0x08018550 performed ok. + Programming of 8 bytes at address 0x08018558 performed ok. + Programming of 8 bytes at address 0x08018560 performed ok. + Programming of 8 bytes at address 0x08018568 performed ok. + Programming of 8 bytes at address 0x08018570 performed ok. + Programming of 8 bytes at address 0x08018578 performed ok. + Programming of 8 bytes at address 0x08018580 performed ok. + Programming of 8 bytes at address 0x08018588 performed ok. + Programming of 8 bytes at address 0x08018590 performed ok. + Programming of 8 bytes at address 0x08018598 performed ok. +k. + Programming of 8 bytes at address 0x080185A8 performed ok. + Programming of 8 bytes at address 0x080185B0 performed ok. + Programming of 8 bytes at address 0x080185B8 performed ok. + Programming of 8 bytes at address 0x080185C0 performed ok. + Programming of 8 bytes at address 0x080185C8 performed ok. + Programming of 8 bytes at address 0x080185D0 performed ok. + Programming of 8 bytes at address 0x080185D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018600 performed ok. + Programming of 8 bytes at address 0x08018608 performed ok. + Programming of 8 bytes at address 0x08018610 performed ok. + Programming of 8 bytes at address 0x08018618 performed ok. + Programming of 8 bytes at address 0x08018620 performed ok. + Programming of 8 bytes at address 0x08018628 performed ok. + Programming of 8 bytes at address 0x08018630 performed ok. + Programming of 8 bytes at address 0x08018638 performed ok. + Programming of 8 bytes at address 0x08018640 performed ok. + Programming of 8 bytes at address 0x08018648 performed ok. + Programming of 8 bytes at address 0x08018650 performed ok. + Programming of 8 bytes at address 0x08018658 performed ok. + Programming of 8 bytes at address 0x08018660 performed ok. + Programming of 8 bytes at address 0x08018668 performed ok. + Programming of 8 bytes at address 0x08018670 performed ok. + Programming of 8 bytes at address 0x08018678 performed ok. + Programming of 8 bytes at address 0x08018680 performed ok. + Programming of 8 bytes at address 0x08018688 performed ok. + Programming of 8 bytes at address 0x08018690 performed ok. + Programming of 8 bytes at address 0x08018698 performed ok. +k. +k. + Programming of 8 bytes at address 0x080186B0 performed ok. + Programming of 8 bytes at address 0x080186B8 performed ok. + Programming of 8 bytes at address 0x080186C0 performed ok. + Programming of 8 bytes at address 0x080186C8 performed ok. + Programming of 8 bytes at address 0x080186D0 performed ok. + Programming of 8 bytes at address 0x080186D8 performed ok. + Programming of 8 bytes at address 0x080186E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018700 performed ok. + Programming of 8 bytes at address 0x08018708 performed ok. + Programming of 8 bytes at address 0x08018710 performed ok. + Programming of 8 bytes at address 0x08018718 performed ok. + Programming of 8 bytes at address 0x08018720 performed ok. + Programming of 8 bytes at address 0x08018728 performed ok. + Programming of 8 bytes at address 0x08018730 performed ok. + Programming of 8 bytes at address 0x08018738 performed ok. + Programming of 8 bytes at address 0x08018740 performed ok. + Programming of 8 bytes at address 0x08018748 performed ok. + Programming of 8 bytes at address 0x08018750 performed ok. + Programming of 8 bytes at address 0x08018758 performed ok. + Programming of 8 bytes at address 0x08018760 performed ok. + Programming of 8 bytes at address 0x08018768 performed ok. + Programming of 8 bytes at address 0x08018770 performed ok. + Programming of 8 bytes at address 0x08018778 performed ok. + Programming of 8 bytes at address 0x08018780 performed ok. + Programming of 8 bytes at address 0x08018788 performed ok. + Programming of 8 bytes at address 0x08018790 performed ok. +k. + Programming of 8 bytes at address 0x080187A0 performed ok. + Programming of 8 bytes at address 0x080187A8 performed ok. + Programming of 8 bytes at address 0x080187B0 performed ok. + Programming of 8 bytes at address 0x080187B8 performed ok. + Programming of 8 bytes at address 0x080187C0 performed ok. + Programming of 8 bytes at address 0x080187C8 performed ok. + Programming of 8 bytes at address 0x080187D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018800 performed ok. + Programming of 8 bytes at address 0x08018808 performed ok. + Programming of 8 bytes at address 0x08018810 performed ok. + Programming of 8 bytes at address 0x08018818 performed ok. + Programming of 8 bytes at address 0x08018820 performed ok. + Programming of 8 bytes at address 0x08018828 performed ok. + Programming of 8 bytes at address 0x08018830 performed ok. + Programming of 8 bytes at address 0x08018838 performed ok. + Programming of 8 bytes at address 0x08018840 performed ok. + Programming of 8 bytes at address 0x08018848 performed ok. + Programming of 8 bytes at address 0x08018850 performed ok. + Programming of 8 bytes at address 0x08018858 performed ok. + Programming of 8 bytes at address 0x08018860 performed ok. + Programming of 8 bytes at address 0x08018868 performed ok. + Programming of 8 bytes at address 0x08018870 performed ok. + Programming of 8 bytes at address 0x08018878 performed ok. + Programming of 8 bytes at address 0x08018880 performed ok. + Programming of 8 bytes at address 0x08018888 performed ok. + Programming of 8 bytes at address 0x08018890 performed ok. + Programming of 8 bytes at address 0x08018898 performed ok. + Programming of 8 bytes at address 0x080188A0 performed ok. + Programming of 8 bytes at address 0x080188A8 performed ok. + Programming of 8 bytes at address 0x080188B0 performed ok. + Programming of 8 bytes at address 0x080188B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080188F0 performed ok. + Programming of 8 bytes at address 0x080188F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018900 performed ok. + Programming of 8 bytes at address 0x08018908 performed ok. + Programming of 8 bytes at address 0x08018910 performed ok. + Programming of 8 bytes at address 0x08018918 performed ok. + Programming of 8 bytes at address 0x08018920 performed ok. + Programming of 8 bytes at address 0x08018928 performed ok. + Programming of 8 bytes at address 0x08018930 performed ok. + Programming of 8 bytes at address 0x08018938 performed ok. + Programming of 8 bytes at address 0x08018940 performed ok. + Programming of 8 bytes at address 0x08018948 performed ok. + Programming of 8 bytes at address 0x08018950 performed ok. + Programming of 8 bytes at address 0x08018958 performed ok. + Programming of 8 bytes at address 0x08018960 performed ok. + Programming of 8 bytes at address 0x08018968 performed ok. + Programming of 8 bytes at address 0x08018970 performed ok. + Programming of 8 bytes at address 0x08018978 performed ok. + Programming of 8 bytes at address 0x08018980 performed ok. + Programming of 8 bytes at address 0x08018988 performed ok. + Programming of 8 bytes at address 0x08018990 performed ok. + Programming of 8 bytes at address 0x08018998 performed ok. + Programming of 8 bytes at address 0x080189A0 performed ok. + Programming of 8 bytes at address 0x080189A8 performed ok. + Programming of 8 bytes at address 0x080189B0 performed ok. + Programming of 8 bytes at address 0x080189B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080189F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018A00 performed ok. + Programming of 8 bytes at address 0x08018A08 performed ok. + Programming of 8 bytes at address 0x08018A10 performed ok. + Programming of 8 bytes at address 0x08018A18 performed ok. + Programming of 8 bytes at address 0x08018A20 performed ok. + Programming of 8 bytes at address 0x08018A28 performed ok. + Programming of 8 bytes at address 0x08018A30 performed ok. + Programming of 8 bytes at address 0x08018A38 performed ok. + Programming of 8 bytes at address 0x08018A40 performed ok. + Programming of 8 bytes at address 0x08018A48 performed ok. + Programming of 8 bytes at address 0x08018A50 performed ok. + Programming of 8 bytes at address 0x08018A58 performed ok. + Programming of 8 bytes at address 0x08018A60 performed ok. + Programming of 8 bytes at address 0x08018A68 performed ok. + Programming of 8 bytes at address 0x08018A70 performed ok. + Programming of 8 bytes at address 0x08018A78 performed ok. + Programming of 8 bytes at address 0x08018A80 performed ok. + Programming of 8 bytes at address 0x08018A88 performed ok. + Programming of 8 bytes at address 0x08018A90 performed ok. +k. + Programming of 8 bytes at address 0x08018AA0 performed ok. + Programming of 8 bytes at address 0x08018AA8 performed ok. + Programming of 8 bytes at address 0x08018AB0 performed ok. + Programming of 8 bytes at address 0x08018AB8 performed ok. + Programming of 8 bytes at address 0x08018AC0 performed ok. + Programming of 8 bytes at address 0x08018AC8 performed ok. + Programming of 8 bytes at address 0x08018AD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018B00 performed ok. + Programming of 8 bytes at address 0x08018B08 performed ok. + Programming of 8 bytes at address 0x08018B10 performed ok. + Programming of 8 bytes at address 0x08018B18 performed ok. + Programming of 8 bytes at address 0x08018B20 performed ok. + Programming of 8 bytes at address 0x08018B28 performed ok. + Programming of 8 bytes at address 0x08018B30 performed ok. + Programming of 8 bytes at address 0x08018B38 performed ok. + Programming of 8 bytes at address 0x08018B40 performed ok. + Programming of 8 bytes at address 0x08018B48 performed ok. + Programming of 8 bytes at address 0x08018B50 performed ok. + Programming of 8 bytes at address 0x08018B58 performed ok. + Programming of 8 bytes at address 0x08018B60 performed ok. + Programming of 8 bytes at address 0x08018B68 performed ok. + Programming of 8 bytes at address 0x08018B70 performed ok. + Programming of 8 bytes at address 0x08018B78 performed ok. + Programming of 8 bytes at address 0x08018B80 performed ok. + Programming of 8 bytes at address 0x08018B88 performed ok. + Programming of 8 bytes at address 0x08018B90 performed ok. + Programming of 8 bytes at address 0x08018B98 performed ok. +k. +k. + Programming of 8 bytes at address 0x08018BB0 performed ok. + Programming of 8 bytes at address 0x08018BB8 performed ok. + Programming of 8 bytes at address 0x08018BC0 performed ok. + Programming of 8 bytes at address 0x08018BC8 performed ok. + Programming of 8 bytes at address 0x08018BD0 performed ok. + Programming of 8 bytes at address 0x08018BD8 performed ok. + Programming of 8 bytes at address 0x08018BE0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018C00 performed ok. + Programming of 8 bytes at address 0x08018C08 performed ok. + Programming of 8 bytes at address 0x08018C10 performed ok. + Programming of 8 bytes at address 0x08018C18 performed ok. + Programming of 8 bytes at address 0x08018C20 performed ok. + Programming of 8 bytes at address 0x08018C28 performed ok. + Programming of 8 bytes at address 0x08018C30 performed ok. + Programming of 8 bytes at address 0x08018C38 performed ok. + Programming of 8 bytes at address 0x08018C40 performed ok. + Programming of 8 bytes at address 0x08018C48 performed ok. + Programming of 8 bytes at address 0x08018C50 performed ok. + Programming of 8 bytes at address 0x08018C58 performed ok. + Programming of 8 bytes at address 0x08018C60 performed ok. + Programming of 8 bytes at address 0x08018C68 performed ok. + Programming of 8 bytes at address 0x08018C70 performed ok. + Programming of 8 bytes at address 0x08018C78 performed ok. + Programming of 8 bytes at address 0x08018C80 performed ok. + Programming of 8 bytes at address 0x08018C88 performed ok. + Programming of 8 bytes at address 0x08018C90 performed ok. +k. + Programming of 8 bytes at address 0x08018CA0 performed ok. + Programming of 8 bytes at address 0x08018CA8 performed ok. + Programming of 8 bytes at address 0x08018CB0 performed ok. + Programming of 8 bytes at address 0x08018CB8 performed ok. + Programming of 8 bytes at address 0x08018CC0 performed ok. + Programming of 8 bytes at address 0x08018CC8 performed ok. + Programming of 8 bytes at address 0x08018CD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018D00 performed ok. + Programming of 8 bytes at address 0x08018D08 performed ok. + Programming of 8 bytes at address 0x08018D10 performed ok. + Programming of 8 bytes at address 0x08018D18 performed ok. + Programming of 8 bytes at address 0x08018D20 performed ok. + Programming of 8 bytes at address 0x08018D28 performed ok. + Programming of 8 bytes at address 0x08018D30 performed ok. + Programming of 8 bytes at address 0x08018D38 performed ok. + Programming of 8 bytes at address 0x08018D40 performed ok. + Programming of 8 bytes at address 0x08018D48 performed ok. + Programming of 8 bytes at address 0x08018D50 performed ok. + Programming of 8 bytes at address 0x08018D58 performed ok. + Programming of 8 bytes at address 0x08018D60 performed ok. + Programming of 8 bytes at address 0x08018D68 performed ok. + Programming of 8 bytes at address 0x08018D70 performed ok. + Programming of 8 bytes at address 0x08018D78 performed ok. + Programming of 8 bytes at address 0x08018D80 performed ok. + Programming of 8 bytes at address 0x08018D88 performed ok. + Programming of 8 bytes at address 0x08018D90 performed ok. + Programming of 8 bytes at address 0x08018D98 performed ok. + Programming of 8 bytes at address 0x08018DA0 performed ok. + Programming of 8 bytes at address 0x08018DA8 performed ok. + Programming of 8 bytes at address 0x08018DB0 performed ok. + Programming of 8 bytes at address 0x08018DB8 performed ok. +k. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x08018DF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018E00 performed ok. + Programming of 8 bytes at address 0x08018E08 performed ok. + Programming of 8 bytes at address 0x08018E10 performed ok. + Programming of 8 bytes at address 0x08018E18 performed ok. + Programming of 8 bytes at address 0x08018E20 performed ok. + Programming of 8 bytes at address 0x08018E28 performed ok. + Programming of 8 bytes at address 0x08018E30 performed ok. + Programming of 8 bytes at address 0x08018E38 performed ok. + Programming of 8 bytes at address 0x08018E40 performed ok. + Programming of 8 bytes at address 0x08018E48 performed ok. + Programming of 8 bytes at address 0x08018E50 performed ok. + Programming of 8 bytes at address 0x08018E58 performed ok. + Programming of 8 bytes at address 0x08018E60 performed ok. + Programming of 8 bytes at address 0x08018E68 performed ok. + Programming of 8 bytes at address 0x08018E70 performed ok. + Programming of 8 bytes at address 0x08018E78 performed ok. + Programming of 8 bytes at address 0x08018E80 performed ok. + Programming of 8 bytes at address 0x08018E88 performed ok. + Programming of 8 bytes at address 0x08018E90 performed ok. + Programming of 8 bytes at address 0x08018E98 performed ok. + Programming of 8 bytes at address 0x08018EA0 performed ok. + Programming of 8 bytes at address 0x08018EA8 performed ok. + Programming of 8 bytes at address 0x08018EB0 performed ok. + Programming of 8 bytes at address 0x08018EB8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08018F00 performed ok. + Programming of 8 bytes at address 0x08018F08 performed ok. + Programming of 8 bytes at address 0x08018F10 performed ok. + Programming of 8 bytes at address 0x08018F18 performed ok. + Programming of 8 bytes at address 0x08018F20 performed ok. + Programming of 8 bytes at address 0x08018F28 performed ok. + Programming of 8 bytes at address 0x08018F30 performed ok. + Programming of 8 bytes at address 0x08018F38 performed ok. + Programming of 8 bytes at address 0x08018F40 performed ok. + Programming of 8 bytes at address 0x08018F48 performed ok. + Programming of 8 bytes at address 0x08018F50 performed ok. + Programming of 8 bytes at address 0x08018F58 performed ok. + Programming of 8 bytes at address 0x08018F60 performed ok. + Programming of 8 bytes at address 0x08018F68 performed ok. + Programming of 8 bytes at address 0x08018F70 performed ok. + Programming of 8 bytes at address 0x08018F78 performed ok. + Programming of 8 bytes at address 0x08018F80 performed ok. + Programming of 8 bytes at address 0x08018F88 performed ok. + Programming of 8 bytes at address 0x08018F90 performed ok. + Programming of 8 bytes at address 0x08018F98 performed ok. +k. + Programming of 8 bytes at address 0x08018FA8 performed ok. + Programming of 8 bytes at address 0x08018FB0 performed ok. + Programming of 8 bytes at address 0x08018FB8 performed ok. + Programming of 8 bytes at address 0x08018FC0 performed ok. + Programming of 8 bytes at address 0x08018FC8 performed ok. + Programming of 8 bytes at address 0x08018FD0 performed ok. + Programming of 8 bytes at address 0x08018FD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019000 performed ok. + Programming of 8 bytes at address 0x08019008 performed ok. + Programming of 8 bytes at address 0x08019010 performed ok. + Programming of 8 bytes at address 0x08019018 performed ok. + Programming of 8 bytes at address 0x08019020 performed ok. + Programming of 8 bytes at address 0x08019028 performed ok. + Programming of 8 bytes at address 0x08019030 performed ok. + Programming of 8 bytes at address 0x08019038 performed ok. + Programming of 8 bytes at address 0x08019040 performed ok. + Programming of 8 bytes at address 0x08019048 performed ok. + Programming of 8 bytes at address 0x08019050 performed ok. + Programming of 8 bytes at address 0x08019058 performed ok. + Programming of 8 bytes at address 0x08019060 performed ok. + Programming of 8 bytes at address 0x08019068 performed ok. + Programming of 8 bytes at address 0x08019070 performed ok. + Programming of 8 bytes at address 0x08019078 performed ok. + Programming of 8 bytes at address 0x08019080 performed ok. + Programming of 8 bytes at address 0x08019088 performed ok. + Programming of 8 bytes at address 0x08019090 performed ok. + Programming of 8 bytes at address 0x08019098 performed ok. +k. + Programming of 8 bytes at address 0x080190A8 performed ok. + Programming of 8 bytes at address 0x080190B0 performed ok. + Programming of 8 bytes at address 0x080190B8 performed ok. + Programming of 8 bytes at address 0x080190C0 performed ok. + Programming of 8 bytes at address 0x080190C8 performed ok. + Programming of 8 bytes at address 0x080190D0 performed ok. + Programming of 8 bytes at address 0x080190D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019100 performed ok. + Programming of 8 bytes at address 0x08019108 performed ok. + Programming of 8 bytes at address 0x08019110 performed ok. + Programming of 8 bytes at address 0x08019118 performed ok. + Programming of 8 bytes at address 0x08019120 performed ok. + Programming of 8 bytes at address 0x08019128 performed ok. + Programming of 8 bytes at address 0x08019130 performed ok. + Programming of 8 bytes at address 0x08019138 performed ok. + Programming of 8 bytes at address 0x08019140 performed ok. + Programming of 8 bytes at address 0x08019148 performed ok. + Programming of 8 bytes at address 0x08019150 performed ok. + Programming of 8 bytes at address 0x08019158 performed ok. + Programming of 8 bytes at address 0x08019160 performed ok. + Programming of 8 bytes at address 0x08019168 performed ok. + Programming of 8 bytes at address 0x08019170 performed ok. + Programming of 8 bytes at address 0x08019178 performed ok. + Programming of 8 bytes at address 0x08019180 performed ok. + Programming of 8 bytes at address 0x08019188 performed ok. + Programming of 8 bytes at address 0x08019190 performed ok. + Programming of 8 bytes at address 0x08019198 performed ok. + Programming of 8 bytes at address 0x080191A0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080191C8 performed ok. + Programming of 8 bytes at address 0x080191D0 performed ok. + Programming of 8 bytes at address 0x080191D8 performed ok. + Programming of 8 bytes at address 0x080191E0 performed ok. + Programming of 8 bytes at address 0x080191E8 performed ok. + Programming of 8 bytes at address 0x080191F0 performed ok. + Programming of 8 bytes at address 0x080191F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019200 performed ok. + Programming of 8 bytes at address 0x08019208 performed ok. + Programming of 8 bytes at address 0x08019210 performed ok. + Programming of 8 bytes at address 0x08019218 performed ok. + Programming of 8 bytes at address 0x08019220 performed ok. + Programming of 8 bytes at address 0x08019228 performed ok. + Programming of 8 bytes at address 0x08019230 performed ok. + Programming of 8 bytes at address 0x08019238 performed ok. + Programming of 8 bytes at address 0x08019240 performed ok. + Programming of 8 bytes at address 0x08019248 performed ok. + Programming of 8 bytes at address 0x08019250 performed ok. + Programming of 8 bytes at address 0x08019258 performed ok. + Programming of 8 bytes at address 0x08019260 performed ok. + Programming of 8 bytes at address 0x08019268 performed ok. + Programming of 8 bytes at address 0x08019270 performed ok. + Programming of 8 bytes at address 0x08019278 performed ok. + Programming of 8 bytes at address 0x08019280 performed ok. + Programming of 8 bytes at address 0x08019288 performed ok. + Programming of 8 bytes at address 0x08019290 performed ok. + Programming of 8 bytes at address 0x08019298 performed ok. + Programming of 8 bytes at address 0x080192A0 performed ok. + Programming of 8 bytes at address 0x080192A8 performed ok. + Programming of 8 bytes at address 0x080192B0 performed ok. + Programming of 8 bytes at address 0x080192B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080192F0 performed ok. + Programming of 8 bytes at address 0x080192F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019300 performed ok. + Programming of 8 bytes at address 0x08019308 performed ok. + Programming of 8 bytes at address 0x08019310 performed ok. + Programming of 8 bytes at address 0x08019318 performed ok. + Programming of 8 bytes at address 0x08019320 performed ok. + Programming of 8 bytes at address 0x08019328 performed ok. + Programming of 8 bytes at address 0x08019330 performed ok. + Programming of 8 bytes at address 0x08019338 performed ok. + Programming of 8 bytes at address 0x08019340 performed ok. + Programming of 8 bytes at address 0x08019348 performed ok. + Programming of 8 bytes at address 0x08019350 performed ok. + Programming of 8 bytes at address 0x08019358 performed ok. + Programming of 8 bytes at address 0x08019360 performed ok. + Programming of 8 bytes at address 0x08019368 performed ok. + Programming of 8 bytes at address 0x08019370 performed ok. + Programming of 8 bytes at address 0x08019378 performed ok. + Programming of 8 bytes at address 0x08019380 performed ok. + Programming of 8 bytes at address 0x08019388 performed ok. + Programming of 8 bytes at address 0x08019390 performed ok. + Programming of 8 bytes at address 0x08019398 performed ok. + Programming of 8 bytes at address 0x080193A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080193C0 performed ok. + Programming of 8 bytes at address 0x080193C8 performed ok. + Programming of 8 bytes at address 0x080193D0 performed ok. + Programming of 8 bytes at address 0x080193D8 performed ok. + Programming of 8 bytes at address 0x080193E0 performed ok. + Programming of 8 bytes at address 0x080193E8 performed ok. + Programming of 8 bytes at address 0x080193F0 performed ok. + Programming of 8 bytes at address 0x080193F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019400 performed ok. + Programming of 8 bytes at address 0x08019408 performed ok. + Programming of 8 bytes at address 0x08019410 performed ok. + Programming of 8 bytes at address 0x08019418 performed ok. + Programming of 8 bytes at address 0x08019420 performed ok. + Programming of 8 bytes at address 0x08019428 performed ok. + Programming of 8 bytes at address 0x08019430 performed ok. + Programming of 8 bytes at address 0x08019438 performed ok. + Programming of 8 bytes at address 0x08019440 performed ok. + Programming of 8 bytes at address 0x08019448 performed ok. + Programming of 8 bytes at address 0x08019450 performed ok. + Programming of 8 bytes at address 0x08019458 performed ok. + Programming of 8 bytes at address 0x08019460 performed ok. + Programming of 8 bytes at address 0x08019468 performed ok. + Programming of 8 bytes at address 0x08019470 performed ok. + Programming of 8 bytes at address 0x08019478 performed ok. + Programming of 8 bytes at address 0x08019480 performed ok. + Programming of 8 bytes at address 0x08019488 performed ok. + Programming of 8 bytes at address 0x08019490 performed ok. + Programming of 8 bytes at address 0x08019498 performed ok. + Programming of 8 bytes at address 0x080194A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x080194C0 performed ok. + Programming of 8 bytes at address 0x080194C8 performed ok. + Programming of 8 bytes at address 0x080194D0 performed ok. + Programming of 8 bytes at address 0x080194D8 performed ok. + Programming of 8 bytes at address 0x080194E0 performed ok. + Programming of 8 bytes at address 0x080194E8 performed ok. + Programming of 8 bytes at address 0x080194F0 performed ok. + Programming of 8 bytes at address 0x080194F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019500 performed ok. + Programming of 8 bytes at address 0x08019508 performed ok. + Programming of 8 bytes at address 0x08019510 performed ok. + Programming of 8 bytes at address 0x08019518 performed ok. + Programming of 8 bytes at address 0x08019520 performed ok. + Programming of 8 bytes at address 0x08019528 performed ok. + Programming of 8 bytes at address 0x08019530 performed ok. + Programming of 8 bytes at address 0x08019538 performed ok. + Programming of 8 bytes at address 0x08019540 performed ok. + Programming of 8 bytes at address 0x08019548 performed ok. + Programming of 8 bytes at address 0x08019550 performed ok. + Programming of 8 bytes at address 0x08019558 performed ok. + Programming of 8 bytes at address 0x08019560 performed ok. + Programming of 8 bytes at address 0x08019568 performed ok. + Programming of 8 bytes at address 0x08019570 performed ok. + Programming of 8 bytes at address 0x08019578 performed ok. + Programming of 8 bytes at address 0x08019580 performed ok. + Programming of 8 bytes at address 0x08019588 performed ok. + Programming of 8 bytes at address 0x08019590 performed ok. + Programming of 8 bytes at address 0x08019598 performed ok. + Programming of 8 bytes at address 0x080195A0 performed ok. + Programming of 8 bytes at address 0x080195A8 performed ok. + Programming of 8 bytes at address 0x080195B0 performed ok. + Programming of 8 bytes at address 0x080195B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080195F0 performed ok. + Programming of 8 bytes at address 0x080195F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019600 performed ok. + Programming of 8 bytes at address 0x08019608 performed ok. + Programming of 8 bytes at address 0x08019610 performed ok. + Programming of 8 bytes at address 0x08019618 performed ok. + Programming of 8 bytes at address 0x08019620 performed ok. + Programming of 8 bytes at address 0x08019628 performed ok. + Programming of 8 bytes at address 0x08019630 performed ok. + Programming of 8 bytes at address 0x08019638 performed ok. + Programming of 8 bytes at address 0x08019640 performed ok. + Programming of 8 bytes at address 0x08019648 performed ok. + Programming of 8 bytes at address 0x08019650 performed ok. + Programming of 8 bytes at address 0x08019658 performed ok. + Programming of 8 bytes at address 0x08019660 performed ok. + Programming of 8 bytes at address 0x08019668 performed ok. + Programming of 8 bytes at address 0x08019670 performed ok. + Programming of 8 bytes at address 0x08019678 performed ok. + Programming of 8 bytes at address 0x08019680 performed ok. + Programming of 8 bytes at address 0x08019688 performed ok. + Programming of 8 bytes at address 0x08019690 performed ok. + Programming of 8 bytes at address 0x08019698 performed ok. +k. + Programming of 8 bytes at address 0x080196A8 performed ok. + Programming of 8 bytes at address 0x080196B0 performed ok. + Programming of 8 bytes at address 0x080196B8 performed ok. + Programming of 8 bytes at address 0x080196C0 performed ok. + Programming of 8 bytes at address 0x080196C8 performed ok. + Programming of 8 bytes at address 0x080196D0 performed ok. + Programming of 8 bytes at address 0x080196D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019700 performed ok. + Programming of 8 bytes at address 0x08019708 performed ok. + Programming of 8 bytes at address 0x08019710 performed ok. + Programming of 8 bytes at address 0x08019718 performed ok. + Programming of 8 bytes at address 0x08019720 performed ok. + Programming of 8 bytes at address 0x08019728 performed ok. + Programming of 8 bytes at address 0x08019730 performed ok. + Programming of 8 bytes at address 0x08019738 performed ok. + Programming of 8 bytes at address 0x08019740 performed ok. + Programming of 8 bytes at address 0x08019748 performed ok. + Programming of 8 bytes at address 0x08019750 performed ok. + Programming of 8 bytes at address 0x08019758 performed ok. + Programming of 8 bytes at address 0x08019760 performed ok. + Programming of 8 bytes at address 0x08019768 performed ok. + Programming of 8 bytes at address 0x08019770 performed ok. + Programming of 8 bytes at address 0x08019778 performed ok. + Programming of 8 bytes at address 0x08019780 performed ok. + Programming of 8 bytes at address 0x08019788 performed ok. + Programming of 8 bytes at address 0x08019790 performed ok. +k. + Programming of 8 bytes at address 0x080197A0 performed ok. + Programming of 8 bytes at address 0x080197A8 performed ok. + Programming of 8 bytes at address 0x080197B0 performed ok. + Programming of 8 bytes at address 0x080197B8 performed ok. + Programming of 8 bytes at address 0x080197C0 performed ok. + Programming of 8 bytes at address 0x080197C8 performed ok. + Programming of 8 bytes at address 0x080197D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019800 performed ok. + Programming of 8 bytes at address 0x08019808 performed ok. + Programming of 8 bytes at address 0x08019810 performed ok. + Programming of 8 bytes at address 0x08019818 performed ok. + Programming of 8 bytes at address 0x08019820 performed ok. + Programming of 8 bytes at address 0x08019828 performed ok. + Programming of 8 bytes at address 0x08019830 performed ok. + Programming of 8 bytes at address 0x08019838 performed ok. + Programming of 8 bytes at address 0x08019840 performed ok. + Programming of 8 bytes at address 0x08019848 performed ok. + Programming of 8 bytes at address 0x08019850 performed ok. + Programming of 8 bytes at address 0x08019858 performed ok. + Programming of 8 bytes at address 0x08019860 performed ok. + Programming of 8 bytes at address 0x08019868 performed ok. + Programming of 8 bytes at address 0x08019870 performed ok. + Programming of 8 bytes at address 0x08019878 performed ok. + Programming of 8 bytes at address 0x08019880 performed ok. + Programming of 8 bytes at address 0x08019888 performed ok. + Programming of 8 bytes at address 0x08019890 performed ok. + Programming of 8 bytes at address 0x08019898 performed ok. + Programming of 8 bytes at address 0x080198A0 performed ok. + Programming of 8 bytes at address 0x080198A8 performed ok. + Programming of 8 bytes at address 0x080198B0 performed ok. + Programming of 8 bytes at address 0x080198B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x080198F0 performed ok. + Programming of 8 bytes at address 0x080198F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019900 performed ok. + Programming of 8 bytes at address 0x08019908 performed ok. + Programming of 8 bytes at address 0x08019910 performed ok. + Programming of 8 bytes at address 0x08019918 performed ok. + Programming of 8 bytes at address 0x08019920 performed ok. + Programming of 8 bytes at address 0x08019928 performed ok. + Programming of 8 bytes at address 0x08019930 performed ok. + Programming of 8 bytes at address 0x08019938 performed ok. + Programming of 8 bytes at address 0x08019940 performed ok. + Programming of 8 bytes at address 0x08019948 performed ok. + Programming of 8 bytes at address 0x08019950 performed ok. + Programming of 8 bytes at address 0x08019958 performed ok. + Programming of 8 bytes at address 0x08019960 performed ok. + Programming of 8 bytes at address 0x08019968 performed ok. + Programming of 8 bytes at address 0x08019970 performed ok. + Programming of 8 bytes at address 0x08019978 performed ok. + Programming of 8 bytes at address 0x08019980 performed ok. + Programming of 8 bytes at address 0x08019988 performed ok. + Programming of 8 bytes at address 0x08019990 performed ok. + Programming of 8 bytes at address 0x08019998 performed ok. +k. + Programming of 8 bytes at address 0x080199A8 performed ok. + Programming of 8 bytes at address 0x080199B0 performed ok. + Programming of 8 bytes at address 0x080199B8 performed ok. + Programming of 8 bytes at address 0x080199C0 performed ok. + Programming of 8 bytes at address 0x080199C8 performed ok. + Programming of 8 bytes at address 0x080199D0 performed ok. + Programming of 8 bytes at address 0x080199D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019A00 performed ok. + Programming of 8 bytes at address 0x08019A08 performed ok. + Programming of 8 bytes at address 0x08019A10 performed ok. + Programming of 8 bytes at address 0x08019A18 performed ok. + Programming of 8 bytes at address 0x08019A20 performed ok. + Programming of 8 bytes at address 0x08019A28 performed ok. + Programming of 8 bytes at address 0x08019A30 performed ok. + Programming of 8 bytes at address 0x08019A38 performed ok. + Programming of 8 bytes at address 0x08019A40 performed ok. + Programming of 8 bytes at address 0x08019A48 performed ok. + Programming of 8 bytes at address 0x08019A50 performed ok. + Programming of 8 bytes at address 0x08019A58 performed ok. + Programming of 8 bytes at address 0x08019A60 performed ok. + Programming of 8 bytes at address 0x08019A68 performed ok. + Programming of 8 bytes at address 0x08019A70 performed ok. + Programming of 8 bytes at address 0x08019A78 performed ok. + Programming of 8 bytes at address 0x08019A80 performed ok. + Programming of 8 bytes at address 0x08019A88 performed ok. + Programming of 8 bytes at address 0x08019A90 performed ok. + Programming of 8 bytes at address 0x08019A98 performed ok. + Programming of 8 bytes at address 0x08019AA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08019AC0 performed ok. + Programming of 8 bytes at address 0x08019AC8 performed ok. + Programming of 8 bytes at address 0x08019AD0 performed ok. + Programming of 8 bytes at address 0x08019AD8 performed ok. + Programming of 8 bytes at address 0x08019AE0 performed ok. + Programming of 8 bytes at address 0x08019AE8 performed ok. + Programming of 8 bytes at address 0x08019AF0 performed ok. + Programming of 8 bytes at address 0x08019AF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019B00 performed ok. + Programming of 8 bytes at address 0x08019B08 performed ok. + Programming of 8 bytes at address 0x08019B10 performed ok. + Programming of 8 bytes at address 0x08019B18 performed ok. + Programming of 8 bytes at address 0x08019B20 performed ok. + Programming of 8 bytes at address 0x08019B28 performed ok. + Programming of 8 bytes at address 0x08019B30 performed ok. + Programming of 8 bytes at address 0x08019B38 performed ok. + Programming of 8 bytes at address 0x08019B40 performed ok. + Programming of 8 bytes at address 0x08019B48 performed ok. + Programming of 8 bytes at address 0x08019B50 performed ok. + Programming of 8 bytes at address 0x08019B58 performed ok. + Programming of 8 bytes at address 0x08019B60 performed ok. + Programming of 8 bytes at address 0x08019B68 performed ok. + Programming of 8 bytes at address 0x08019B70 performed ok. + Programming of 8 bytes at address 0x08019B78 performed ok. + Programming of 8 bytes at address 0x08019B80 performed ok. + Programming of 8 bytes at address 0x08019B88 performed ok. + Programming of 8 bytes at address 0x08019B90 performed ok. + Programming of 8 bytes at address 0x08019B98 performed ok. +k. +k. + Programming of 8 bytes at address 0x08019BB0 performed ok. + Programming of 8 bytes at address 0x08019BB8 performed ok. + Programming of 8 bytes at address 0x08019BC0 performed ok. + Programming of 8 bytes at address 0x08019BC8 performed ok. + Programming of 8 bytes at address 0x08019BD0 performed ok. + Programming of 8 bytes at address 0x08019BD8 performed ok. + Programming of 8 bytes at address 0x08019BE0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019C00 performed ok. + Programming of 8 bytes at address 0x08019C08 performed ok. + Programming of 8 bytes at address 0x08019C10 performed ok. + Programming of 8 bytes at address 0x08019C18 performed ok. + Programming of 8 bytes at address 0x08019C20 performed ok. + Programming of 8 bytes at address 0x08019C28 performed ok. + Programming of 8 bytes at address 0x08019C30 performed ok. + Programming of 8 bytes at address 0x08019C38 performed ok. + Programming of 8 bytes at address 0x08019C40 performed ok. + Programming of 8 bytes at address 0x08019C48 performed ok. + Programming of 8 bytes at address 0x08019C50 performed ok. + Programming of 8 bytes at address 0x08019C58 performed ok. + Programming of 8 bytes at address 0x08019C60 performed ok. + Programming of 8 bytes at address 0x08019C68 performed ok. + Programming of 8 bytes at address 0x08019C70 performed ok. + Programming of 8 bytes at address 0x08019C78 performed ok. + Programming of 8 bytes at address 0x08019C80 performed ok. + Programming of 8 bytes at address 0x08019C88 performed ok. + Programming of 8 bytes at address 0x08019C90 performed ok. +k. + Programming of 8 bytes at address 0x08019CA0 performed ok. + Programming of 8 bytes at address 0x08019CA8 performed ok. + Programming of 8 bytes at address 0x08019CB0 performed ok. + Programming of 8 bytes at address 0x08019CB8 performed ok. + Programming of 8 bytes at address 0x08019CC0 performed ok. + Programming of 8 bytes at address 0x08019CC8 performed ok. + Programming of 8 bytes at address 0x08019CD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019D00 performed ok. + Programming of 8 bytes at address 0x08019D08 performed ok. + Programming of 8 bytes at address 0x08019D10 performed ok. + Programming of 8 bytes at address 0x08019D18 performed ok. + Programming of 8 bytes at address 0x08019D20 performed ok. + Programming of 8 bytes at address 0x08019D28 performed ok. + Programming of 8 bytes at address 0x08019D30 performed ok. + Programming of 8 bytes at address 0x08019D38 performed ok. + Programming of 8 bytes at address 0x08019D40 performed ok. + Programming of 8 bytes at address 0x08019D48 performed ok. + Programming of 8 bytes at address 0x08019D50 performed ok. + Programming of 8 bytes at address 0x08019D58 performed ok. + Programming of 8 bytes at address 0x08019D60 performed ok. + Programming of 8 bytes at address 0x08019D68 performed ok. + Programming of 8 bytes at address 0x08019D70 performed ok. + Programming of 8 bytes at address 0x08019D78 performed ok. + Programming of 8 bytes at address 0x08019D80 performed ok. + Programming of 8 bytes at address 0x08019D88 performed ok. + Programming of 8 bytes at address 0x08019D90 performed ok. + Programming of 8 bytes at address 0x08019D98 performed ok. +k. + Programming of 8 bytes at address 0x08019DA8 performed ok. + Programming of 8 bytes at address 0x08019DB0 performed ok. + Programming of 8 bytes at address 0x08019DB8 performed ok. + Programming of 8 bytes at address 0x08019DC0 performed ok. + Programming of 8 bytes at address 0x08019DC8 performed ok. + Programming of 8 bytes at address 0x08019DD0 performed ok. + Programming of 8 bytes at address 0x08019DD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019E00 performed ok. + Programming of 8 bytes at address 0x08019E08 performed ok. + Programming of 8 bytes at address 0x08019E10 performed ok. + Programming of 8 bytes at address 0x08019E18 performed ok. + Programming of 8 bytes at address 0x08019E20 performed ok. + Programming of 8 bytes at address 0x08019E28 performed ok. + Programming of 8 bytes at address 0x08019E30 performed ok. + Programming of 8 bytes at address 0x08019E38 performed ok. + Programming of 8 bytes at address 0x08019E40 performed ok. + Programming of 8 bytes at address 0x08019E48 performed ok. + Programming of 8 bytes at address 0x08019E50 performed ok. + Programming of 8 bytes at address 0x08019E58 performed ok. + Programming of 8 bytes at address 0x08019E60 performed ok. + Programming of 8 bytes at address 0x08019E68 performed ok. + Programming of 8 bytes at address 0x08019E70 performed ok. + Programming of 8 bytes at address 0x08019E78 performed ok. + Programming of 8 bytes at address 0x08019E80 performed ok. + Programming of 8 bytes at address 0x08019E88 performed ok. + Programming of 8 bytes at address 0x08019E90 performed ok. + Programming of 8 bytes at address 0x08019E98 performed ok. + Programming of 8 bytes at address 0x08019EA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x08019EC0 performed ok. + Programming of 8 bytes at address 0x08019EC8 performed ok. + Programming of 8 bytes at address 0x08019ED0 performed ok. + Programming of 8 bytes at address 0x08019ED8 performed ok. + Programming of 8 bytes at address 0x08019EE0 performed ok. + Programming of 8 bytes at address 0x08019EE8 performed ok. + Programming of 8 bytes at address 0x08019EF0 performed ok. + Programming of 8 bytes at address 0x08019EF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x08019F00 performed ok. + Programming of 8 bytes at address 0x08019F08 performed ok. + Programming of 8 bytes at address 0x08019F10 performed ok. + Programming of 8 bytes at address 0x08019F18 performed ok. + Programming of 8 bytes at address 0x08019F20 performed ok. + Programming of 8 bytes at address 0x08019F28 performed ok. + Programming of 8 bytes at address 0x08019F30 performed ok. + Programming of 8 bytes at address 0x08019F38 performed ok. + Programming of 8 bytes at address 0x08019F40 performed ok. + Programming of 8 bytes at address 0x08019F48 performed ok. + Programming of 8 bytes at address 0x08019F50 performed ok. + Programming of 8 bytes at address 0x08019F58 performed ok. + Programming of 8 bytes at address 0x08019F60 performed ok. + Programming of 8 bytes at address 0x08019F68 performed ok. + Programming of 8 bytes at address 0x08019F70 performed ok. + Programming of 8 bytes at address 0x08019F78 performed ok. + Programming of 8 bytes at address 0x08019F80 performed ok. + Programming of 8 bytes at address 0x08019F88 performed ok. + Programming of 8 bytes at address 0x08019F90 performed ok. + Programming of 8 bytes at address 0x08019F98 performed ok. +k. + Programming of 8 bytes at address 0x08019FA8 performed ok. + Programming of 8 bytes at address 0x08019FB0 performed ok. + Programming of 8 bytes at address 0x08019FB8 performed ok. + Programming of 8 bytes at address 0x08019FC0 performed ok. + Programming of 8 bytes at address 0x08019FC8 performed ok. + Programming of 8 bytes at address 0x08019FD0 performed ok. + Programming of 8 bytes at address 0x08019FD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801A000 performed ok. + Programming of 8 bytes at address 0x0801A008 performed ok. + Programming of 8 bytes at address 0x0801A010 performed ok. + Programming of 8 bytes at address 0x0801A018 performed ok. + Programming of 8 bytes at address 0x0801A020 performed ok. + Programming of 8 bytes at address 0x0801A028 performed ok. + Programming of 8 bytes at address 0x0801A030 performed ok. + Programming of 8 bytes at address 0x0801A038 performed ok. + Programming of 8 bytes at address 0x0801A040 performed ok. + Programming of 8 bytes at address 0x0801A048 performed ok. + Programming of 8 bytes at address 0x0801A050 performed ok. + Programming of 8 bytes at address 0x0801A058 performed ok. + Programming of 8 bytes at address 0x0801A060 performed ok. + Programming of 8 bytes at address 0x0801A068 performed ok. + Programming of 8 bytes at address 0x0801A070 performed ok. + Programming of 8 bytes at address 0x0801A078 performed ok. + Programming of 8 bytes at address 0x0801A080 performed ok. + Programming of 8 bytes at address 0x0801A088 performed ok. + Programming of 8 bytes at address 0x0801A090 performed ok. + Programming of 8 bytes at address 0x0801A098 performed ok. +k. + Programming of 8 bytes at address 0x0801A0A8 performed ok. + Programming of 8 bytes at address 0x0801A0B0 performed ok. + Programming of 8 bytes at address 0x0801A0B8 performed ok. + Programming of 8 bytes at address 0x0801A0C0 performed ok. + Programming of 8 bytes at address 0x0801A0C8 performed ok. + Programming of 8 bytes at address 0x0801A0D0 performed ok. + Programming of 8 bytes at address 0x0801A0D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801A100 performed ok. + Programming of 8 bytes at address 0x0801A108 performed ok. + Programming of 8 bytes at address 0x0801A110 performed ok. + Programming of 8 bytes at address 0x0801A118 performed ok. + Programming of 8 bytes at address 0x0801A120 performed ok. + Programming of 8 bytes at address 0x0801A128 performed ok. + Programming of 8 bytes at address 0x0801A130 performed ok. + Programming of 8 bytes at address 0x0801A138 performed ok. + Programming of 8 bytes at address 0x0801A140 performed ok. + Programming of 8 bytes at address 0x0801A148 performed ok. + Programming of 8 bytes at address 0x0801A150 performed ok. + Programming of 8 bytes at address 0x0801A158 performed ok. + Programming of 8 bytes at address 0x0801A160 performed ok. + Programming of 8 bytes at address 0x0801A168 performed ok. + Programming of 8 bytes at address 0x0801A170 performed ok. + Programming of 8 bytes at address 0x0801A178 performed ok. + Programming of 8 bytes at address 0x0801A180 performed ok. + Programming of 8 bytes at address 0x0801A188 performed ok. + Programming of 8 bytes at address 0x0801A190 performed ok. + Programming of 8 bytes at address 0x0801A198 performed ok. +k. + Programming of 8 bytes at address 0x0801A1A8 performed ok. + Programming of 8 bytes at address 0x0801A1B0 performed ok. + Programming of 8 bytes at address 0x0801A1B8 performed ok. + Programming of 8 bytes at address 0x0801A1C0 performed ok. + Programming of 8 bytes at address 0x0801A1C8 performed ok. + Programming of 8 bytes at address 0x0801A1D0 performed ok. + Programming of 8 bytes at address 0x0801A1D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801A200 performed ok. + Programming of 8 bytes at address 0x0801A208 performed ok. + Programming of 8 bytes at address 0x0801A210 performed ok. + Programming of 8 bytes at address 0x0801A218 performed ok. + Programming of 8 bytes at address 0x0801A220 performed ok. + Programming of 8 bytes at address 0x0801A228 performed ok. + Programming of 8 bytes at address 0x0801A230 performed ok. + Programming of 8 bytes at address 0x0801A238 performed ok. + Programming of 8 bytes at address 0x0801A240 performed ok. + Programming of 8 bytes at address 0x0801A248 performed ok. + Programming of 8 bytes at address 0x0801A250 performed ok. + Programming of 8 bytes at address 0x0801A258 performed ok. + Programming of 8 bytes at address 0x0801A260 performed ok. + Programming of 8 bytes at address 0x0801A268 performed ok. + Programming of 8 bytes at address 0x0801A270 performed ok. + Programming of 8 bytes at address 0x0801A278 performed ok. + Programming of 8 bytes at address 0x0801A280 performed ok. + Programming of 8 bytes at address 0x0801A288 performed ok. + Programming of 8 bytes at address 0x0801A290 performed ok. + Programming of 8 bytes at address 0x0801A298 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801A2B8 performed ok. + Programming of 8 bytes at address 0x0801A2C0 performed ok. + Programming of 8 bytes at address 0x0801A2C8 performed ok. + Programming of 8 bytes at address 0x0801A2D0 performed ok. + Programming of 8 bytes at address 0x0801A2D8 performed ok. + Programming of 8 bytes at address 0x0801A2E0 performed ok. + Programming of 8 bytes at address 0x0801A2E8 performed ok. + Programming of 8 bytes at address 0x0801A2F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801A300 performed ok. + Programming of 8 bytes at address 0x0801A308 performed ok. + Programming of 8 bytes at address 0x0801A310 performed ok. + Programming of 8 bytes at address 0x0801A318 performed ok. + Programming of 8 bytes at address 0x0801A320 performed ok. + Programming of 8 bytes at address 0x0801A328 performed ok. + Programming of 8 bytes at address 0x0801A330 performed ok. + Programming of 8 bytes at address 0x0801A338 performed ok. + Programming of 8 bytes at address 0x0801A340 performed ok. + Programming of 8 bytes at address 0x0801A348 performed ok. + Programming of 8 bytes at address 0x0801A350 performed ok. + Programming of 8 bytes at address 0x0801A358 performed ok. + Programming of 8 bytes at address 0x0801A360 performed ok. + Programming of 8 bytes at address 0x0801A368 performed ok. + Programming of 8 bytes at address 0x0801A370 performed ok. + Programming of 8 bytes at address 0x0801A378 performed ok. + Programming of 8 bytes at address 0x0801A380 performed ok. + Programming of 8 bytes at address 0x0801A388 performed ok. + Programming of 8 bytes at address 0x0801A390 performed ok. +k. + Programming of 8 bytes at address 0x0801A3A0 performed ok. + Programming of 8 bytes at address 0x0801A3A8 performed ok. + Programming of 8 bytes at address 0x0801A3B0 performed ok. + Programming of 8 bytes at address 0x0801A3B8 performed ok. + Programming of 8 bytes at address 0x0801A3C0 performed ok. + Programming of 8 bytes at address 0x0801A3C8 performed ok. + Programming of 8 bytes at address 0x0801A3D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801A400 performed ok. + Programming of 8 bytes at address 0x0801A408 performed ok. + Programming of 8 bytes at address 0x0801A410 performed ok. + Programming of 8 bytes at address 0x0801A418 performed ok. + Programming of 8 bytes at address 0x0801A420 performed ok. + Programming of 8 bytes at address 0x0801A428 performed ok. + Programming of 8 bytes at address 0x0801A430 performed ok. + Programming of 8 bytes at address 0x0801A438 performed ok. + Programming of 8 bytes at address 0x0801A440 performed ok. + Programming of 8 bytes at address 0x0801A448 performed ok. + Programming of 8 bytes at address 0x0801A450 performed ok. + Programming of 8 bytes at address 0x0801A458 performed ok. + Programming of 8 bytes at address 0x0801A460 performed ok. + Programming of 8 bytes at address 0x0801A468 performed ok. + Programming of 8 bytes at address 0x0801A470 performed ok. + Programming of 8 bytes at address 0x0801A478 performed ok. + Programming of 8 bytes at address 0x0801A480 performed ok. + Programming of 8 bytes at address 0x0801A488 performed ok. + Programming of 8 bytes at address 0x0801A490 performed ok. + Programming of 8 bytes at address 0x0801A498 performed ok. + Programming of 8 bytes at address 0x0801A4A0 performed ok. + Programming of 8 bytes at address 0x0801A4A8 performed ok. + Programming of 8 bytes at address 0x0801A4B0 performed ok. + Programming of 8 bytes at address 0x0801A4B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801A500 performed ok. + Programming of 8 bytes at address 0x0801A508 performed ok. + Programming of 8 bytes at address 0x0801A510 performed ok. + Programming of 8 bytes at address 0x0801A518 performed ok. + Programming of 8 bytes at address 0x0801A520 performed ok. + Programming of 8 bytes at address 0x0801A528 performed ok. + Programming of 8 bytes at address 0x0801A530 performed ok. + Programming of 8 bytes at address 0x0801A538 performed ok. + Programming of 8 bytes at address 0x0801A540 performed ok. + Programming of 8 bytes at address 0x0801A548 performed ok. + Programming of 8 bytes at address 0x0801A550 performed ok. + Programming of 8 bytes at address 0x0801A558 performed ok. + Programming of 8 bytes at address 0x0801A560 performed ok. + Programming of 8 bytes at address 0x0801A568 performed ok. + Programming of 8 bytes at address 0x0801A570 performed ok. + Programming of 8 bytes at address 0x0801A578 performed ok. + Programming of 8 bytes at address 0x0801A580 performed ok. + Programming of 8 bytes at address 0x0801A588 performed ok. + Programming of 8 bytes at address 0x0801A590 performed ok. + Programming of 8 bytes at address 0x0801A598 performed ok. + Programming of 8 bytes at address 0x0801A5A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801A5C0 performed ok. + Programming of 8 bytes at address 0x0801A5C8 performed ok. + Programming of 8 bytes at address 0x0801A5D0 performed ok. + Programming of 8 bytes at address 0x0801A5D8 performed ok. + Programming of 8 bytes at address 0x0801A5E0 performed ok. + Programming of 8 bytes at address 0x0801A5E8 performed ok. + Programming of 8 bytes at address 0x0801A5F0 performed ok. + Programming of 8 bytes at address 0x0801A5F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801A600 performed ok. + Programming of 8 bytes at address 0x0801A608 performed ok. + Programming of 8 bytes at address 0x0801A610 performed ok. + Programming of 8 bytes at address 0x0801A618 performed ok. + Programming of 8 bytes at address 0x0801A620 performed ok. + Programming of 8 bytes at address 0x0801A628 performed ok. + Programming of 8 bytes at address 0x0801A630 performed ok. + Programming of 8 bytes at address 0x0801A638 performed ok. + Programming of 8 bytes at address 0x0801A640 performed ok. + Programming of 8 bytes at address 0x0801A648 performed ok. + Programming of 8 bytes at address 0x0801A650 performed ok. + Programming of 8 bytes at address 0x0801A658 performed ok. + Programming of 8 bytes at address 0x0801A660 performed ok. + Programming of 8 bytes at address 0x0801A668 performed ok. + Programming of 8 bytes at address 0x0801A670 performed ok. + Programming of 8 bytes at address 0x0801A678 performed ok. + Programming of 8 bytes at address 0x0801A680 performed ok. + Programming of 8 bytes at address 0x0801A688 performed ok. + Programming of 8 bytes at address 0x0801A690 performed ok. + Programming of 8 bytes at address 0x0801A698 performed ok. +k. + Programming of 8 bytes at address 0x0801A6A8 performed ok. + Programming of 8 bytes at address 0x0801A6B0 performed ok. + Programming of 8 bytes at address 0x0801A6B8 performed ok. + Programming of 8 bytes at address 0x0801A6C0 performed ok. + Programming of 8 bytes at address 0x0801A6C8 performed ok. + Programming of 8 bytes at address 0x0801A6D0 performed ok. + Programming of 8 bytes at address 0x0801A6D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801A700 performed ok. + Programming of 8 bytes at address 0x0801A708 performed ok. + Programming of 8 bytes at address 0x0801A710 performed ok. + Programming of 8 bytes at address 0x0801A718 performed ok. + Programming of 8 bytes at address 0x0801A720 performed ok. + Programming of 8 bytes at address 0x0801A728 performed ok. + Programming of 8 bytes at address 0x0801A730 performed ok. + Programming of 8 bytes at address 0x0801A738 performed ok. + Programming of 8 bytes at address 0x0801A740 performed ok. + Programming of 8 bytes at address 0x0801A748 performed ok. + Programming of 8 bytes at address 0x0801A750 performed ok. + Programming of 8 bytes at address 0x0801A758 performed ok. + Programming of 8 bytes at address 0x0801A760 performed ok. + Programming of 8 bytes at address 0x0801A768 performed ok. + Programming of 8 bytes at address 0x0801A770 performed ok. + Programming of 8 bytes at address 0x0801A778 performed ok. + Programming of 8 bytes at address 0x0801A780 performed ok. + Programming of 8 bytes at address 0x0801A788 performed ok. + Programming of 8 bytes at address 0x0801A790 performed ok. + Programming of 8 bytes at address 0x0801A798 performed ok. + Programming of 8 bytes at address 0x0801A7A0 performed ok. + Programming of 8 bytes at address 0x0801A7A8 performed ok. + Programming of 8 bytes at address 0x0801A7B0 performed ok. + Programming of 8 bytes at address 0x0801A7B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801A7F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801A800 performed ok. + Programming of 8 bytes at address 0x0801A808 performed ok. + Programming of 8 bytes at address 0x0801A810 performed ok. + Programming of 8 bytes at address 0x0801A818 performed ok. + Programming of 8 bytes at address 0x0801A820 performed ok. + Programming of 8 bytes at address 0x0801A828 performed ok. + Programming of 8 bytes at address 0x0801A830 performed ok. + Programming of 8 bytes at address 0x0801A838 performed ok. + Programming of 8 bytes at address 0x0801A840 performed ok. + Programming of 8 bytes at address 0x0801A848 performed ok. + Programming of 8 bytes at address 0x0801A850 performed ok. + Programming of 8 bytes at address 0x0801A858 performed ok. + Programming of 8 bytes at address 0x0801A860 performed ok. + Programming of 8 bytes at address 0x0801A868 performed ok. + Programming of 8 bytes at address 0x0801A870 performed ok. + Programming of 8 bytes at address 0x0801A878 performed ok. + Programming of 8 bytes at address 0x0801A880 performed ok. + Programming of 8 bytes at address 0x0801A888 performed ok. + Programming of 8 bytes at address 0x0801A890 performed ok. + Programming of 8 bytes at address 0x0801A898 performed ok. + Programming of 8 bytes at address 0x0801A8A0 performed ok. + Programming of 8 bytes at address 0x0801A8A8 performed ok. + Programming of 8 bytes at address 0x0801A8B0 performed ok. + Programming of 8 bytes at address 0x0801A8B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801A8F0 performed ok. + Programming of 8 bytes at address 0x0801A8F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801A900 performed ok. + Programming of 8 bytes at address 0x0801A908 performed ok. + Programming of 8 bytes at address 0x0801A910 performed ok. + Programming of 8 bytes at address 0x0801A918 performed ok. + Programming of 8 bytes at address 0x0801A920 performed ok. + Programming of 8 bytes at address 0x0801A928 performed ok. + Programming of 8 bytes at address 0x0801A930 performed ok. + Programming of 8 bytes at address 0x0801A938 performed ok. + Programming of 8 bytes at address 0x0801A940 performed ok. + Programming of 8 bytes at address 0x0801A948 performed ok. + Programming of 8 bytes at address 0x0801A950 performed ok. + Programming of 8 bytes at address 0x0801A958 performed ok. + Programming of 8 bytes at address 0x0801A960 performed ok. + Programming of 8 bytes at address 0x0801A968 performed ok. + Programming of 8 bytes at address 0x0801A970 performed ok. + Programming of 8 bytes at address 0x0801A978 performed ok. + Programming of 8 bytes at address 0x0801A980 performed ok. + Programming of 8 bytes at address 0x0801A988 performed ok. + Programming of 8 bytes at address 0x0801A990 performed ok. + Programming of 8 bytes at address 0x0801A998 performed ok. +k. +k. + Programming of 8 bytes at address 0x0801A9B0 performed ok. + Programming of 8 bytes at address 0x0801A9B8 performed ok. + Programming of 8 bytes at address 0x0801A9C0 performed ok. + Programming of 8 bytes at address 0x0801A9C8 performed ok. + Programming of 8 bytes at address 0x0801A9D0 performed ok. + Programming of 8 bytes at address 0x0801A9D8 performed ok. + Programming of 8 bytes at address 0x0801A9E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801AA00 performed ok. + Programming of 8 bytes at address 0x0801AA08 performed ok. + Programming of 8 bytes at address 0x0801AA10 performed ok. + Programming of 8 bytes at address 0x0801AA18 performed ok. + Programming of 8 bytes at address 0x0801AA20 performed ok. + Programming of 8 bytes at address 0x0801AA28 performed ok. + Programming of 8 bytes at address 0x0801AA30 performed ok. + Programming of 8 bytes at address 0x0801AA38 performed ok. + Programming of 8 bytes at address 0x0801AA40 performed ok. + Programming of 8 bytes at address 0x0801AA48 performed ok. + Programming of 8 bytes at address 0x0801AA50 performed ok. + Programming of 8 bytes at address 0x0801AA58 performed ok. + Programming of 8 bytes at address 0x0801AA60 performed ok. + Programming of 8 bytes at address 0x0801AA68 performed ok. + Programming of 8 bytes at address 0x0801AA70 performed ok. + Programming of 8 bytes at address 0x0801AA78 performed ok. + Programming of 8 bytes at address 0x0801AA80 performed ok. + Programming of 8 bytes at address 0x0801AA88 performed ok. + Programming of 8 bytes at address 0x0801AA90 performed ok. + Programming of 8 bytes at address 0x0801AA98 performed ok. + Programming of 8 bytes at address 0x0801AAA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801AAC0 performed ok. + Programming of 8 bytes at address 0x0801AAC8 performed ok. + Programming of 8 bytes at address 0x0801AAD0 performed ok. + Programming of 8 bytes at address 0x0801AAD8 performed ok. + Programming of 8 bytes at address 0x0801AAE0 performed ok. + Programming of 8 bytes at address 0x0801AAE8 performed ok. + Programming of 8 bytes at address 0x0801AAF0 performed ok. + Programming of 8 bytes at address 0x0801AAF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801AB00 performed ok. + Programming of 8 bytes at address 0x0801AB08 performed ok. + Programming of 8 bytes at address 0x0801AB10 performed ok. + Programming of 8 bytes at address 0x0801AB18 performed ok. + Programming of 8 bytes at address 0x0801AB20 performed ok. + Programming of 8 bytes at address 0x0801AB28 performed ok. + Programming of 8 bytes at address 0x0801AB30 performed ok. + Programming of 8 bytes at address 0x0801AB38 performed ok. + Programming of 8 bytes at address 0x0801AB40 performed ok. + Programming of 8 bytes at address 0x0801AB48 performed ok. + Programming of 8 bytes at address 0x0801AB50 performed ok. + Programming of 8 bytes at address 0x0801AB58 performed ok. + Programming of 8 bytes at address 0x0801AB60 performed ok. + Programming of 8 bytes at address 0x0801AB68 performed ok. + Programming of 8 bytes at address 0x0801AB70 performed ok. + Programming of 8 bytes at address 0x0801AB78 performed ok. + Programming of 8 bytes at address 0x0801AB80 performed ok. + Programming of 8 bytes at address 0x0801AB88 performed ok. + Programming of 8 bytes at address 0x0801AB90 performed ok. + Programming of 8 bytes at address 0x0801AB98 performed ok. + Programming of 8 bytes at address 0x0801ABA0 performed ok. + Programming of 8 bytes at address 0x0801ABA8 performed ok. + Programming of 8 bytes at address 0x0801ABB0 performed ok. + Programming of 8 bytes at address 0x0801ABB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801ABF0 performed ok. + Programming of 8 bytes at address 0x0801ABF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801AC00 performed ok. + Programming of 8 bytes at address 0x0801AC08 performed ok. + Programming of 8 bytes at address 0x0801AC10 performed ok. + Programming of 8 bytes at address 0x0801AC18 performed ok. + Programming of 8 bytes at address 0x0801AC20 performed ok. + Programming of 8 bytes at address 0x0801AC28 performed ok. + Programming of 8 bytes at address 0x0801AC30 performed ok. + Programming of 8 bytes at address 0x0801AC38 performed ok. + Programming of 8 bytes at address 0x0801AC40 performed ok. + Programming of 8 bytes at address 0x0801AC48 performed ok. + Programming of 8 bytes at address 0x0801AC50 performed ok. + Programming of 8 bytes at address 0x0801AC58 performed ok. + Programming of 8 bytes at address 0x0801AC60 performed ok. + Programming of 8 bytes at address 0x0801AC68 performed ok. + Programming of 8 bytes at address 0x0801AC70 performed ok. + Programming of 8 bytes at address 0x0801AC78 performed ok. + Programming of 8 bytes at address 0x0801AC80 performed ok. + Programming of 8 bytes at address 0x0801AC88 performed ok. + Programming of 8 bytes at address 0x0801AC90 performed ok. + Programming of 8 bytes at address 0x0801AC98 performed ok. +k. +k. + Programming of 8 bytes at address 0x0801ACB0 performed ok. + Programming of 8 bytes at address 0x0801ACB8 performed ok. + Programming of 8 bytes at address 0x0801ACC0 performed ok. + Programming of 8 bytes at address 0x0801ACC8 performed ok. + Programming of 8 bytes at address 0x0801ACD0 performed ok. + Programming of 8 bytes at address 0x0801ACD8 performed ok. + Programming of 8 bytes at address 0x0801ACE0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801AD00 performed ok. + Programming of 8 bytes at address 0x0801AD08 performed ok. + Programming of 8 bytes at address 0x0801AD10 performed ok. + Programming of 8 bytes at address 0x0801AD18 performed ok. + Programming of 8 bytes at address 0x0801AD20 performed ok. + Programming of 8 bytes at address 0x0801AD28 performed ok. + Programming of 8 bytes at address 0x0801AD30 performed ok. + Programming of 8 bytes at address 0x0801AD38 performed ok. + Programming of 8 bytes at address 0x0801AD40 performed ok. + Programming of 8 bytes at address 0x0801AD48 performed ok. + Programming of 8 bytes at address 0x0801AD50 performed ok. + Programming of 8 bytes at address 0x0801AD58 performed ok. + Programming of 8 bytes at address 0x0801AD60 performed ok. + Programming of 8 bytes at address 0x0801AD68 performed ok. + Programming of 8 bytes at address 0x0801AD70 performed ok. + Programming of 8 bytes at address 0x0801AD78 performed ok. + Programming of 8 bytes at address 0x0801AD80 performed ok. + Programming of 8 bytes at address 0x0801AD88 performed ok. + Programming of 8 bytes at address 0x0801AD90 performed ok. + Programming of 8 bytes at address 0x0801AD98 performed ok. +k. + Programming of 8 bytes at address 0x0801ADA8 performed ok. + Programming of 8 bytes at address 0x0801ADB0 performed ok. + Programming of 8 bytes at address 0x0801ADB8 performed ok. + Programming of 8 bytes at address 0x0801ADC0 performed ok. + Programming of 8 bytes at address 0x0801ADC8 performed ok. + Programming of 8 bytes at address 0x0801ADD0 performed ok. + Programming of 8 bytes at address 0x0801ADD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801AE00 performed ok. + Programming of 8 bytes at address 0x0801AE08 performed ok. + Programming of 8 bytes at address 0x0801AE10 performed ok. + Programming of 8 bytes at address 0x0801AE18 performed ok. + Programming of 8 bytes at address 0x0801AE20 performed ok. + Programming of 8 bytes at address 0x0801AE28 performed ok. + Programming of 8 bytes at address 0x0801AE30 performed ok. + Programming of 8 bytes at address 0x0801AE38 performed ok. + Programming of 8 bytes at address 0x0801AE40 performed ok. + Programming of 8 bytes at address 0x0801AE48 performed ok. + Programming of 8 bytes at address 0x0801AE50 performed ok. + Programming of 8 bytes at address 0x0801AE58 performed ok. + Programming of 8 bytes at address 0x0801AE60 performed ok. + Programming of 8 bytes at address 0x0801AE68 performed ok. + Programming of 8 bytes at address 0x0801AE70 performed ok. + Programming of 8 bytes at address 0x0801AE78 performed ok. + Programming of 8 bytes at address 0x0801AE80 performed ok. + Programming of 8 bytes at address 0x0801AE88 performed ok. + Programming of 8 bytes at address 0x0801AE90 performed ok. + Programming of 8 bytes at address 0x0801AE98 performed ok. +k. +k. + Programming of 8 bytes at address 0x0801AEB0 performed ok. + Programming of 8 bytes at address 0x0801AEB8 performed ok. + Programming of 8 bytes at address 0x0801AEC0 performed ok. + Programming of 8 bytes at address 0x0801AEC8 performed ok. + Programming of 8 bytes at address 0x0801AED0 performed ok. + Programming of 8 bytes at address 0x0801AED8 performed ok. + Programming of 8 bytes at address 0x0801AEE0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801AF00 performed ok. + Programming of 8 bytes at address 0x0801AF08 performed ok. + Programming of 8 bytes at address 0x0801AF10 performed ok. + Programming of 8 bytes at address 0x0801AF18 performed ok. + Programming of 8 bytes at address 0x0801AF20 performed ok. + Programming of 8 bytes at address 0x0801AF28 performed ok. + Programming of 8 bytes at address 0x0801AF30 performed ok. + Programming of 8 bytes at address 0x0801AF38 performed ok. + Programming of 8 bytes at address 0x0801AF40 performed ok. + Programming of 8 bytes at address 0x0801AF48 performed ok. + Programming of 8 bytes at address 0x0801AF50 performed ok. + Programming of 8 bytes at address 0x0801AF58 performed ok. + Programming of 8 bytes at address 0x0801AF60 performed ok. + Programming of 8 bytes at address 0x0801AF68 performed ok. + Programming of 8 bytes at address 0x0801AF70 performed ok. + Programming of 8 bytes at address 0x0801AF78 performed ok. + Programming of 8 bytes at address 0x0801AF80 performed ok. + Programming of 8 bytes at address 0x0801AF88 performed ok. + Programming of 8 bytes at address 0x0801AF90 performed ok. + Programming of 8 bytes at address 0x0801AF98 performed ok. + Programming of 8 bytes at address 0x0801AFA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801AFC0 performed ok. + Programming of 8 bytes at address 0x0801AFC8 performed ok. + Programming of 8 bytes at address 0x0801AFD0 performed ok. + Programming of 8 bytes at address 0x0801AFD8 performed ok. + Programming of 8 bytes at address 0x0801AFE0 performed ok. + Programming of 8 bytes at address 0x0801AFE8 performed ok. + Programming of 8 bytes at address 0x0801AFF0 performed ok. + Programming of 8 bytes at address 0x0801AFF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801B000 performed ok. + Programming of 8 bytes at address 0x0801B008 performed ok. + Programming of 8 bytes at address 0x0801B010 performed ok. + Programming of 8 bytes at address 0x0801B018 performed ok. + Programming of 8 bytes at address 0x0801B020 performed ok. + Programming of 8 bytes at address 0x0801B028 performed ok. + Programming of 8 bytes at address 0x0801B030 performed ok. + Programming of 8 bytes at address 0x0801B038 performed ok. + Programming of 8 bytes at address 0x0801B040 performed ok. + Programming of 8 bytes at address 0x0801B048 performed ok. + Programming of 8 bytes at address 0x0801B050 performed ok. + Programming of 8 bytes at address 0x0801B058 performed ok. + Programming of 8 bytes at address 0x0801B060 performed ok. + Programming of 8 bytes at address 0x0801B068 performed ok. + Programming of 8 bytes at address 0x0801B070 performed ok. + Programming of 8 bytes at address 0x0801B078 performed ok. + Programming of 8 bytes at address 0x0801B080 performed ok. + Programming of 8 bytes at address 0x0801B088 performed ok. + Programming of 8 bytes at address 0x0801B090 performed ok. + Programming of 8 bytes at address 0x0801B098 performed ok. + Programming of 8 bytes at address 0x0801B0A0 performed ok. + Programming of 8 bytes at address 0x0801B0A8 performed ok. + Programming of 8 bytes at address 0x0801B0B0 performed ok. + Programming of 8 bytes at address 0x0801B0B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801B0F0 performed ok. + Programming of 8 bytes at address 0x0801B0F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801B100 performed ok. + Programming of 8 bytes at address 0x0801B108 performed ok. + Programming of 8 bytes at address 0x0801B110 performed ok. + Programming of 8 bytes at address 0x0801B118 performed ok. + Programming of 8 bytes at address 0x0801B120 performed ok. + Programming of 8 bytes at address 0x0801B128 performed ok. + Programming of 8 bytes at address 0x0801B130 performed ok. + Programming of 8 bytes at address 0x0801B138 performed ok. + Programming of 8 bytes at address 0x0801B140 performed ok. + Programming of 8 bytes at address 0x0801B148 performed ok. + Programming of 8 bytes at address 0x0801B150 performed ok. + Programming of 8 bytes at address 0x0801B158 performed ok. + Programming of 8 bytes at address 0x0801B160 performed ok. + Programming of 8 bytes at address 0x0801B168 performed ok. + Programming of 8 bytes at address 0x0801B170 performed ok. + Programming of 8 bytes at address 0x0801B178 performed ok. + Programming of 8 bytes at address 0x0801B180 performed ok. + Programming of 8 bytes at address 0x0801B188 performed ok. + Programming of 8 bytes at address 0x0801B190 performed ok. + Programming of 8 bytes at address 0x0801B198 performed ok. + Programming of 8 bytes at address 0x0801B1A0 performed ok. + Programming of 8 bytes at address 0x0801B1A8 performed ok. + Programming of 8 bytes at address 0x0801B1B0 performed ok. + Programming of 8 bytes at address 0x0801B1B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801B200 performed ok. + Programming of 8 bytes at address 0x0801B208 performed ok. + Programming of 8 bytes at address 0x0801B210 performed ok. + Programming of 8 bytes at address 0x0801B218 performed ok. + Programming of 8 bytes at address 0x0801B220 performed ok. + Programming of 8 bytes at address 0x0801B228 performed ok. + Programming of 8 bytes at address 0x0801B230 performed ok. + Programming of 8 bytes at address 0x0801B238 performed ok. + Programming of 8 bytes at address 0x0801B240 performed ok. + Programming of 8 bytes at address 0x0801B248 performed ok. + Programming of 8 bytes at address 0x0801B250 performed ok. + Programming of 8 bytes at address 0x0801B258 performed ok. + Programming of 8 bytes at address 0x0801B260 performed ok. + Programming of 8 bytes at address 0x0801B268 performed ok. + Programming of 8 bytes at address 0x0801B270 performed ok. + Programming of 8 bytes at address 0x0801B278 performed ok. + Programming of 8 bytes at address 0x0801B280 performed ok. + Programming of 8 bytes at address 0x0801B288 performed ok. + Programming of 8 bytes at address 0x0801B290 performed ok. + Programming of 8 bytes at address 0x0801B298 performed ok. + Programming of 8 bytes at address 0x0801B2A0 performed ok. + Programming of 8 bytes at address 0x0801B2A8 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801B2C8 performed ok. + Programming of 8 bytes at address 0x0801B2D0 performed ok. + Programming of 8 bytes at address 0x0801B2D8 performed ok. + Programming of 8 bytes at address 0x0801B2E0 performed ok. + Programming of 8 bytes at address 0x0801B2E8 performed ok. + Programming of 8 bytes at address 0x0801B2F0 performed ok. + Programming of 8 bytes at address 0x0801B2F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801B300 performed ok. + Programming of 8 bytes at address 0x0801B308 performed ok. + Programming of 8 bytes at address 0x0801B310 performed ok. + Programming of 8 bytes at address 0x0801B318 performed ok. + Programming of 8 bytes at address 0x0801B320 performed ok. + Programming of 8 bytes at address 0x0801B328 performed ok. + Programming of 8 bytes at address 0x0801B330 performed ok. + Programming of 8 bytes at address 0x0801B338 performed ok. + Programming of 8 bytes at address 0x0801B340 performed ok. + Programming of 8 bytes at address 0x0801B348 performed ok. + Programming of 8 bytes at address 0x0801B350 performed ok. + Programming of 8 bytes at address 0x0801B358 performed ok. + Programming of 8 bytes at address 0x0801B360 performed ok. + Programming of 8 bytes at address 0x0801B368 performed ok. + Programming of 8 bytes at address 0x0801B370 performed ok. + Programming of 8 bytes at address 0x0801B378 performed ok. + Programming of 8 bytes at address 0x0801B380 performed ok. + Programming of 8 bytes at address 0x0801B388 performed ok. + Programming of 8 bytes at address 0x0801B390 performed ok. +k. + Programming of 8 bytes at address 0x0801B3A0 performed ok. + Programming of 8 bytes at address 0x0801B3A8 performed ok. + Programming of 8 bytes at address 0x0801B3B0 performed ok. + Programming of 8 bytes at address 0x0801B3B8 performed ok. + Programming of 8 bytes at address 0x0801B3C0 performed ok. + Programming of 8 bytes at address 0x0801B3C8 performed ok. + Programming of 8 bytes at address 0x0801B3D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801B400 performed ok. + Programming of 8 bytes at address 0x0801B408 performed ok. + Programming of 8 bytes at address 0x0801B410 performed ok. + Programming of 8 bytes at address 0x0801B418 performed ok. + Programming of 8 bytes at address 0x0801B420 performed ok. + Programming of 8 bytes at address 0x0801B428 performed ok. + Programming of 8 bytes at address 0x0801B430 performed ok. + Programming of 8 bytes at address 0x0801B438 performed ok. + Programming of 8 bytes at address 0x0801B440 performed ok. + Programming of 8 bytes at address 0x0801B448 performed ok. + Programming of 8 bytes at address 0x0801B450 performed ok. + Programming of 8 bytes at address 0x0801B458 performed ok. + Programming of 8 bytes at address 0x0801B460 performed ok. + Programming of 8 bytes at address 0x0801B468 performed ok. + Programming of 8 bytes at address 0x0801B470 performed ok. + Programming of 8 bytes at address 0x0801B478 performed ok. + Programming of 8 bytes at address 0x0801B480 performed ok. + Programming of 8 bytes at address 0x0801B488 performed ok. + Programming of 8 bytes at address 0x0801B490 performed ok. + Programming of 8 bytes at address 0x0801B498 performed ok. +k. + Programming of 8 bytes at address 0x0801B4A8 performed ok. + Programming of 8 bytes at address 0x0801B4B0 performed ok. + Programming of 8 bytes at address 0x0801B4B8 performed ok. + Programming of 8 bytes at address 0x0801B4C0 performed ok. + Programming of 8 bytes at address 0x0801B4C8 performed ok. + Programming of 8 bytes at address 0x0801B4D0 performed ok. + Programming of 8 bytes at address 0x0801B4D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801B500 performed ok. + Programming of 8 bytes at address 0x0801B508 performed ok. + Programming of 8 bytes at address 0x0801B510 performed ok. + Programming of 8 bytes at address 0x0801B518 performed ok. + Programming of 8 bytes at address 0x0801B520 performed ok. + Programming of 8 bytes at address 0x0801B528 performed ok. + Programming of 8 bytes at address 0x0801B530 performed ok. + Programming of 8 bytes at address 0x0801B538 performed ok. + Programming of 8 bytes at address 0x0801B540 performed ok. + Programming of 8 bytes at address 0x0801B548 performed ok. + Programming of 8 bytes at address 0x0801B550 performed ok. + Programming of 8 bytes at address 0x0801B558 performed ok. + Programming of 8 bytes at address 0x0801B560 performed ok. + Programming of 8 bytes at address 0x0801B568 performed ok. + Programming of 8 bytes at address 0x0801B570 performed ok. + Programming of 8 bytes at address 0x0801B578 performed ok. + Programming of 8 bytes at address 0x0801B580 performed ok. + Programming of 8 bytes at address 0x0801B588 performed ok. + Programming of 8 bytes at address 0x0801B590 performed ok. + Programming of 8 bytes at address 0x0801B598 performed ok. + Programming of 8 bytes at address 0x0801B5A0 performed ok. + Programming of 8 bytes at address 0x0801B5A8 performed ok. + Programming of 8 bytes at address 0x0801B5B0 performed ok. + Programming of 8 bytes at address 0x0801B5B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801B5F0 performed ok. + Programming of 8 bytes at address 0x0801B5F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801B600 performed ok. + Programming of 8 bytes at address 0x0801B608 performed ok. + Programming of 8 bytes at address 0x0801B610 performed ok. + Programming of 8 bytes at address 0x0801B618 performed ok. + Programming of 8 bytes at address 0x0801B620 performed ok. + Programming of 8 bytes at address 0x0801B628 performed ok. + Programming of 8 bytes at address 0x0801B630 performed ok. + Programming of 8 bytes at address 0x0801B638 performed ok. + Programming of 8 bytes at address 0x0801B640 performed ok. + Programming of 8 bytes at address 0x0801B648 performed ok. + Programming of 8 bytes at address 0x0801B650 performed ok. + Programming of 8 bytes at address 0x0801B658 performed ok. + Programming of 8 bytes at address 0x0801B660 performed ok. + Programming of 8 bytes at address 0x0801B668 performed ok. + Programming of 8 bytes at address 0x0801B670 performed ok. + Programming of 8 bytes at address 0x0801B678 performed ok. + Programming of 8 bytes at address 0x0801B680 performed ok. + Programming of 8 bytes at address 0x0801B688 performed ok. + Programming of 8 bytes at address 0x0801B690 performed ok. + Programming of 8 bytes at address 0x0801B698 performed ok. + Programming of 8 bytes at address 0x0801B6A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801B6C0 performed ok. + Programming of 8 bytes at address 0x0801B6C8 performed ok. + Programming of 8 bytes at address 0x0801B6D0 performed ok. + Programming of 8 bytes at address 0x0801B6D8 performed ok. + Programming of 8 bytes at address 0x0801B6E0 performed ok. + Programming of 8 bytes at address 0x0801B6E8 performed ok. + Programming of 8 bytes at address 0x0801B6F0 performed ok. + Programming of 8 bytes at address 0x0801B6F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801B700 performed ok. + Programming of 8 bytes at address 0x0801B708 performed ok. + Programming of 8 bytes at address 0x0801B710 performed ok. + Programming of 8 bytes at address 0x0801B718 performed ok. + Programming of 8 bytes at address 0x0801B720 performed ok. + Programming of 8 bytes at address 0x0801B728 performed ok. + Programming of 8 bytes at address 0x0801B730 performed ok. + Programming of 8 bytes at address 0x0801B738 performed ok. + Programming of 8 bytes at address 0x0801B740 performed ok. + Programming of 8 bytes at address 0x0801B748 performed ok. + Programming of 8 bytes at address 0x0801B750 performed ok. + Programming of 8 bytes at address 0x0801B758 performed ok. + Programming of 8 bytes at address 0x0801B760 performed ok. + Programming of 8 bytes at address 0x0801B768 performed ok. + Programming of 8 bytes at address 0x0801B770 performed ok. + Programming of 8 bytes at address 0x0801B778 performed ok. + Programming of 8 bytes at address 0x0801B780 performed ok. + Programming of 8 bytes at address 0x0801B788 performed ok. + Programming of 8 bytes at address 0x0801B790 performed ok. + Programming of 8 bytes at address 0x0801B798 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801B7B8 performed ok. + Programming of 8 bytes at address 0x0801B7C0 performed ok. + Programming of 8 bytes at address 0x0801B7C8 performed ok. + Programming of 8 bytes at address 0x0801B7D0 performed ok. + Programming of 8 bytes at address 0x0801B7D8 performed ok. + Programming of 8 bytes at address 0x0801B7E0 performed ok. + Programming of 8 bytes at address 0x0801B7E8 performed ok. + Programming of 8 bytes at address 0x0801B7F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801B800 performed ok. + Programming of 8 bytes at address 0x0801B808 performed ok. + Programming of 8 bytes at address 0x0801B810 performed ok. + Programming of 8 bytes at address 0x0801B818 performed ok. + Programming of 8 bytes at address 0x0801B820 performed ok. + Programming of 8 bytes at address 0x0801B828 performed ok. + Programming of 8 bytes at address 0x0801B830 performed ok. + Programming of 8 bytes at address 0x0801B838 performed ok. + Programming of 8 bytes at address 0x0801B840 performed ok. + Programming of 8 bytes at address 0x0801B848 performed ok. + Programming of 8 bytes at address 0x0801B850 performed ok. + Programming of 8 bytes at address 0x0801B858 performed ok. + Programming of 8 bytes at address 0x0801B860 performed ok. + Programming of 8 bytes at address 0x0801B868 performed ok. + Programming of 8 bytes at address 0x0801B870 performed ok. + Programming of 8 bytes at address 0x0801B878 performed ok. + Programming of 8 bytes at address 0x0801B880 performed ok. + Programming of 8 bytes at address 0x0801B888 performed ok. + Programming of 8 bytes at address 0x0801B890 performed ok. + Programming of 8 bytes at address 0x0801B898 performed ok. +k. + Programming of 8 bytes at address 0x0801B8A8 performed ok. + Programming of 8 bytes at address 0x0801B8B0 performed ok. + Programming of 8 bytes at address 0x0801B8B8 performed ok. + Programming of 8 bytes at address 0x0801B8C0 performed ok. + Programming of 8 bytes at address 0x0801B8C8 performed ok. + Programming of 8 bytes at address 0x0801B8D0 performed ok. + Programming of 8 bytes at address 0x0801B8D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801B900 performed ok. + Programming of 8 bytes at address 0x0801B908 performed ok. + Programming of 8 bytes at address 0x0801B910 performed ok. + Programming of 8 bytes at address 0x0801B918 performed ok. + Programming of 8 bytes at address 0x0801B920 performed ok. + Programming of 8 bytes at address 0x0801B928 performed ok. + Programming of 8 bytes at address 0x0801B930 performed ok. + Programming of 8 bytes at address 0x0801B938 performed ok. + Programming of 8 bytes at address 0x0801B940 performed ok. + Programming of 8 bytes at address 0x0801B948 performed ok. + Programming of 8 bytes at address 0x0801B950 performed ok. + Programming of 8 bytes at address 0x0801B958 performed ok. + Programming of 8 bytes at address 0x0801B960 performed ok. + Programming of 8 bytes at address 0x0801B968 performed ok. + Programming of 8 bytes at address 0x0801B970 performed ok. + Programming of 8 bytes at address 0x0801B978 performed ok. + Programming of 8 bytes at address 0x0801B980 performed ok. + Programming of 8 bytes at address 0x0801B988 performed ok. + Programming of 8 bytes at address 0x0801B990 performed ok. + Programming of 8 bytes at address 0x0801B998 performed ok. + Programming of 8 bytes at address 0x0801B9A0 performed ok. + Programming of 8 bytes at address 0x0801B9A8 performed ok. + Programming of 8 bytes at address 0x0801B9B0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801B9D0 performed ok. + Programming of 8 bytes at address 0x0801B9D8 performed ok. + Programming of 8 bytes at address 0x0801B9E0 performed ok. + Programming of 8 bytes at address 0x0801B9E8 performed ok. + Programming of 8 bytes at address 0x0801B9F0 performed ok. + Programming of 8 bytes at address 0x0801B9F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801BA00 performed ok. + Programming of 8 bytes at address 0x0801BA08 performed ok. + Programming of 8 bytes at address 0x0801BA10 performed ok. + Programming of 8 bytes at address 0x0801BA18 performed ok. + Programming of 8 bytes at address 0x0801BA20 performed ok. + Programming of 8 bytes at address 0x0801BA28 performed ok. + Programming of 8 bytes at address 0x0801BA30 performed ok. + Programming of 8 bytes at address 0x0801BA38 performed ok. + Programming of 8 bytes at address 0x0801BA40 performed ok. + Programming of 8 bytes at address 0x0801BA48 performed ok. + Programming of 8 bytes at address 0x0801BA50 performed ok. + Programming of 8 bytes at address 0x0801BA58 performed ok. + Programming of 8 bytes at address 0x0801BA60 performed ok. + Programming of 8 bytes at address 0x0801BA68 performed ok. + Programming of 8 bytes at address 0x0801BA70 performed ok. + Programming of 8 bytes at address 0x0801BA78 performed ok. + Programming of 8 bytes at address 0x0801BA80 performed ok. + Programming of 8 bytes at address 0x0801BA88 performed ok. + Programming of 8 bytes at address 0x0801BA90 performed ok. + Programming of 8 bytes at address 0x0801BA98 performed ok. + Programming of 8 bytes at address 0x0801BAA0 performed ok. + Programming of 8 bytes at address 0x0801BAA8 performed ok. + Programming of 8 bytes at address 0x0801BAB0 performed ok. + Programming of 8 bytes at address 0x0801BAB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801BAF0 performed ok. + Programming of 8 bytes at address 0x0801BAF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801BB00 performed ok. + Programming of 8 bytes at address 0x0801BB08 performed ok. + Programming of 8 bytes at address 0x0801BB10 performed ok. + Programming of 8 bytes at address 0x0801BB18 performed ok. + Programming of 8 bytes at address 0x0801BB20 performed ok. + Programming of 8 bytes at address 0x0801BB28 performed ok. + Programming of 8 bytes at address 0x0801BB30 performed ok. + Programming of 8 bytes at address 0x0801BB38 performed ok. + Programming of 8 bytes at address 0x0801BB40 performed ok. + Programming of 8 bytes at address 0x0801BB48 performed ok. + Programming of 8 bytes at address 0x0801BB50 performed ok. + Programming of 8 bytes at address 0x0801BB58 performed ok. + Programming of 8 bytes at address 0x0801BB60 performed ok. + Programming of 8 bytes at address 0x0801BB68 performed ok. + Programming of 8 bytes at address 0x0801BB70 performed ok. + Programming of 8 bytes at address 0x0801BB78 performed ok. + Programming of 8 bytes at address 0x0801BB80 performed ok. + Programming of 8 bytes at address 0x0801BB88 performed ok. + Programming of 8 bytes at address 0x0801BB90 performed ok. + Programming of 8 bytes at address 0x0801BB98 performed ok. + Programming of 8 bytes at address 0x0801BBA0 performed ok. + Programming of 8 bytes at address 0x0801BBA8 performed ok. + Programming of 8 bytes at address 0x0801BBB0 performed ok. + Programming of 8 bytes at address 0x0801BBB8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801BC00 performed ok. + Programming of 8 bytes at address 0x0801BC08 performed ok. + Programming of 8 bytes at address 0x0801BC10 performed ok. + Programming of 8 bytes at address 0x0801BC18 performed ok. + Programming of 8 bytes at address 0x0801BC20 performed ok. + Programming of 8 bytes at address 0x0801BC28 performed ok. + Programming of 8 bytes at address 0x0801BC30 performed ok. + Programming of 8 bytes at address 0x0801BC38 performed ok. + Programming of 8 bytes at address 0x0801BC40 performed ok. + Programming of 8 bytes at address 0x0801BC48 performed ok. + Programming of 8 bytes at address 0x0801BC50 performed ok. + Programming of 8 bytes at address 0x0801BC58 performed ok. + Programming of 8 bytes at address 0x0801BC60 performed ok. + Programming of 8 bytes at address 0x0801BC68 performed ok. + Programming of 8 bytes at address 0x0801BC70 performed ok. + Programming of 8 bytes at address 0x0801BC78 performed ok. + Programming of 8 bytes at address 0x0801BC80 performed ok. + Programming of 8 bytes at address 0x0801BC88 performed ok. + Programming of 8 bytes at address 0x0801BC90 performed ok. + Programming of 8 bytes at address 0x0801BC98 performed ok. + Programming of 8 bytes at address 0x0801BCA0 performed ok. + Programming of 8 bytes at address 0x0801BCA8 performed ok. + Programming of 8 bytes at address 0x0801BCB0 performed ok. + Programming of 8 bytes at address 0x0801BCB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801BCF0 performed ok. + Programming of 8 bytes at address 0x0801BCF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801BD00 performed ok. + Programming of 8 bytes at address 0x0801BD08 performed ok. + Programming of 8 bytes at address 0x0801BD10 performed ok. + Programming of 8 bytes at address 0x0801BD18 performed ok. + Programming of 8 bytes at address 0x0801BD20 performed ok. + Programming of 8 bytes at address 0x0801BD28 performed ok. + Programming of 8 bytes at address 0x0801BD30 performed ok. + Programming of 8 bytes at address 0x0801BD38 performed ok. + Programming of 8 bytes at address 0x0801BD40 performed ok. + Programming of 8 bytes at address 0x0801BD48 performed ok. + Programming of 8 bytes at address 0x0801BD50 performed ok. + Programming of 8 bytes at address 0x0801BD58 performed ok. + Programming of 8 bytes at address 0x0801BD60 performed ok. + Programming of 8 bytes at address 0x0801BD68 performed ok. + Programming of 8 bytes at address 0x0801BD70 performed ok. + Programming of 8 bytes at address 0x0801BD78 performed ok. + Programming of 8 bytes at address 0x0801BD80 performed ok. + Programming of 8 bytes at address 0x0801BD88 performed ok. + Programming of 8 bytes at address 0x0801BD90 performed ok. + Programming of 8 bytes at address 0x0801BD98 performed ok. +k. +k. + Programming of 8 bytes at address 0x0801BDB0 performed ok. + Programming of 8 bytes at address 0x0801BDB8 performed ok. + Programming of 8 bytes at address 0x0801BDC0 performed ok. + Programming of 8 bytes at address 0x0801BDC8 performed ok. + Programming of 8 bytes at address 0x0801BDD0 performed ok. + Programming of 8 bytes at address 0x0801BDD8 performed ok. + Programming of 8 bytes at address 0x0801BDE0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801BE00 performed ok. + Programming of 8 bytes at address 0x0801BE08 performed ok. + Programming of 8 bytes at address 0x0801BE10 performed ok. + Programming of 8 bytes at address 0x0801BE18 performed ok. + Programming of 8 bytes at address 0x0801BE20 performed ok. + Programming of 8 bytes at address 0x0801BE28 performed ok. + Programming of 8 bytes at address 0x0801BE30 performed ok. + Programming of 8 bytes at address 0x0801BE38 performed ok. + Programming of 8 bytes at address 0x0801BE40 performed ok. + Programming of 8 bytes at address 0x0801BE48 performed ok. + Programming of 8 bytes at address 0x0801BE50 performed ok. + Programming of 8 bytes at address 0x0801BE58 performed ok. + Programming of 8 bytes at address 0x0801BE60 performed ok. + Programming of 8 bytes at address 0x0801BE68 performed ok. + Programming of 8 bytes at address 0x0801BE70 performed ok. + Programming of 8 bytes at address 0x0801BE78 performed ok. + Programming of 8 bytes at address 0x0801BE80 performed ok. + Programming of 8 bytes at address 0x0801BE88 performed ok. + Programming of 8 bytes at address 0x0801BE90 performed ok. + Programming of 8 bytes at address 0x0801BE98 performed ok. + Programming of 8 bytes at address 0x0801BEA0 performed ok. + Programming of 8 bytes at address 0x0801BEA8 performed ok. + Programming of 8 bytes at address 0x0801BEB0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801BED8 performed ok. + Programming of 8 bytes at address 0x0801BEE0 performed ok. + Programming of 8 bytes at address 0x0801BEE8 performed ok. + Programming of 8 bytes at address 0x0801BEF0 performed ok. + Programming of 8 bytes at address 0x0801BEF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801BF00 performed ok. + Programming of 8 bytes at address 0x0801BF08 performed ok. + Programming of 8 bytes at address 0x0801BF10 performed ok. + Programming of 8 bytes at address 0x0801BF18 performed ok. + Programming of 8 bytes at address 0x0801BF20 performed ok. + Programming of 8 bytes at address 0x0801BF28 performed ok. + Programming of 8 bytes at address 0x0801BF30 performed ok. + Programming of 8 bytes at address 0x0801BF38 performed ok. + Programming of 8 bytes at address 0x0801BF40 performed ok. + Programming of 8 bytes at address 0x0801BF48 performed ok. + Programming of 8 bytes at address 0x0801BF50 performed ok. + Programming of 8 bytes at address 0x0801BF58 performed ok. + Programming of 8 bytes at address 0x0801BF60 performed ok. + Programming of 8 bytes at address 0x0801BF68 performed ok. + Programming of 8 bytes at address 0x0801BF70 performed ok. + Programming of 8 bytes at address 0x0801BF78 performed ok. + Programming of 8 bytes at address 0x0801BF80 performed ok. + Programming of 8 bytes at address 0x0801BF88 performed ok. + Programming of 8 bytes at address 0x0801BF90 performed ok. + Programming of 8 bytes at address 0x0801BF98 performed ok. + Programming of 8 bytes at address 0x0801BFA0 performed ok. + Programming of 8 bytes at address 0x0801BFA8 performed ok. + Programming of 8 bytes at address 0x0801BFB0 performed ok. + Programming of 8 bytes at address 0x0801BFB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801BFF0 performed ok. + Programming of 8 bytes at address 0x0801BFF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801C000 performed ok. + Programming of 8 bytes at address 0x0801C008 performed ok. + Programming of 8 bytes at address 0x0801C010 performed ok. + Programming of 8 bytes at address 0x0801C018 performed ok. + Programming of 8 bytes at address 0x0801C020 performed ok. + Programming of 8 bytes at address 0x0801C028 performed ok. + Programming of 8 bytes at address 0x0801C030 performed ok. + Programming of 8 bytes at address 0x0801C038 performed ok. + Programming of 8 bytes at address 0x0801C040 performed ok. + Programming of 8 bytes at address 0x0801C048 performed ok. + Programming of 8 bytes at address 0x0801C050 performed ok. + Programming of 8 bytes at address 0x0801C058 performed ok. + Programming of 8 bytes at address 0x0801C060 performed ok. + Programming of 8 bytes at address 0x0801C068 performed ok. + Programming of 8 bytes at address 0x0801C070 performed ok. + Programming of 8 bytes at address 0x0801C078 performed ok. + Programming of 8 bytes at address 0x0801C080 performed ok. + Programming of 8 bytes at address 0x0801C088 performed ok. + Programming of 8 bytes at address 0x0801C090 performed ok. + Programming of 8 bytes at address 0x0801C098 performed ok. + Programming of 8 bytes at address 0x0801C0A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801C0C0 performed ok. + Programming of 8 bytes at address 0x0801C0C8 performed ok. + Programming of 8 bytes at address 0x0801C0D0 performed ok. + Programming of 8 bytes at address 0x0801C0D8 performed ok. + Programming of 8 bytes at address 0x0801C0E0 performed ok. + Programming of 8 bytes at address 0x0801C0E8 performed ok. + Programming of 8 bytes at address 0x0801C0F0 performed ok. + Programming of 8 bytes at address 0x0801C0F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801C100 performed ok. + Programming of 8 bytes at address 0x0801C108 performed ok. + Programming of 8 bytes at address 0x0801C110 performed ok. + Programming of 8 bytes at address 0x0801C118 performed ok. + Programming of 8 bytes at address 0x0801C120 performed ok. + Programming of 8 bytes at address 0x0801C128 performed ok. + Programming of 8 bytes at address 0x0801C130 performed ok. + Programming of 8 bytes at address 0x0801C138 performed ok. + Programming of 8 bytes at address 0x0801C140 performed ok. + Programming of 8 bytes at address 0x0801C148 performed ok. + Programming of 8 bytes at address 0x0801C150 performed ok. + Programming of 8 bytes at address 0x0801C158 performed ok. + Programming of 8 bytes at address 0x0801C160 performed ok. + Programming of 8 bytes at address 0x0801C168 performed ok. + Programming of 8 bytes at address 0x0801C170 performed ok. + Programming of 8 bytes at address 0x0801C178 performed ok. + Programming of 8 bytes at address 0x0801C180 performed ok. + Programming of 8 bytes at address 0x0801C188 performed ok. + Programming of 8 bytes at address 0x0801C190 performed ok. + Programming of 8 bytes at address 0x0801C198 performed ok. + Programming of 8 bytes at address 0x0801C1A0 performed ok. + Programming of 8 bytes at address 0x0801C1A8 performed ok. + Programming of 8 bytes at address 0x0801C1B0 performed ok. + Programming of 8 bytes at address 0x0801C1B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801C1F0 performed ok. + Programming of 8 bytes at address 0x0801C1F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801C200 performed ok. + Programming of 8 bytes at address 0x0801C208 performed ok. + Programming of 8 bytes at address 0x0801C210 performed ok. + Programming of 8 bytes at address 0x0801C218 performed ok. + Programming of 8 bytes at address 0x0801C220 performed ok. + Programming of 8 bytes at address 0x0801C228 performed ok. + Programming of 8 bytes at address 0x0801C230 performed ok. + Programming of 8 bytes at address 0x0801C238 performed ok. + Programming of 8 bytes at address 0x0801C240 performed ok. + Programming of 8 bytes at address 0x0801C248 performed ok. + Programming of 8 bytes at address 0x0801C250 performed ok. + Programming of 8 bytes at address 0x0801C258 performed ok. + Programming of 8 bytes at address 0x0801C260 performed ok. + Programming of 8 bytes at address 0x0801C268 performed ok. + Programming of 8 bytes at address 0x0801C270 performed ok. + Programming of 8 bytes at address 0x0801C278 performed ok. + Programming of 8 bytes at address 0x0801C280 performed ok. + Programming of 8 bytes at address 0x0801C288 performed ok. + Programming of 8 bytes at address 0x0801C290 performed ok. + Programming of 8 bytes at address 0x0801C298 performed ok. +k. + Programming of 8 bytes at address 0x0801C2A8 performed ok. + Programming of 8 bytes at address 0x0801C2B0 performed ok. + Programming of 8 bytes at address 0x0801C2B8 performed ok. + Programming of 8 bytes at address 0x0801C2C0 performed ok. + Programming of 8 bytes at address 0x0801C2C8 performed ok. + Programming of 8 bytes at address 0x0801C2D0 performed ok. + Programming of 8 bytes at address 0x0801C2D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801C300 performed ok. + Programming of 8 bytes at address 0x0801C308 performed ok. + Programming of 8 bytes at address 0x0801C310 performed ok. + Programming of 8 bytes at address 0x0801C318 performed ok. + Programming of 8 bytes at address 0x0801C320 performed ok. + Programming of 8 bytes at address 0x0801C328 performed ok. + Programming of 8 bytes at address 0x0801C330 performed ok. + Programming of 8 bytes at address 0x0801C338 performed ok. + Programming of 8 bytes at address 0x0801C340 performed ok. + Programming of 8 bytes at address 0x0801C348 performed ok. + Programming of 8 bytes at address 0x0801C350 performed ok. + Programming of 8 bytes at address 0x0801C358 performed ok. + Programming of 8 bytes at address 0x0801C360 performed ok. + Programming of 8 bytes at address 0x0801C368 performed ok. + Programming of 8 bytes at address 0x0801C370 performed ok. + Programming of 8 bytes at address 0x0801C378 performed ok. + Programming of 8 bytes at address 0x0801C380 performed ok. + Programming of 8 bytes at address 0x0801C388 performed ok. + Programming of 8 bytes at address 0x0801C390 performed ok. + Programming of 8 bytes at address 0x0801C398 performed ok. +k. + Programming of 8 bytes at address 0x0801C3A8 performed ok. + Programming of 8 bytes at address 0x0801C3B0 performed ok. + Programming of 8 bytes at address 0x0801C3B8 performed ok. + Programming of 8 bytes at address 0x0801C3C0 performed ok. + Programming of 8 bytes at address 0x0801C3C8 performed ok. + Programming of 8 bytes at address 0x0801C3D0 performed ok. + Programming of 8 bytes at address 0x0801C3D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801C400 performed ok. + Programming of 8 bytes at address 0x0801C408 performed ok. + Programming of 8 bytes at address 0x0801C410 performed ok. + Programming of 8 bytes at address 0x0801C418 performed ok. + Programming of 8 bytes at address 0x0801C420 performed ok. + Programming of 8 bytes at address 0x0801C428 performed ok. + Programming of 8 bytes at address 0x0801C430 performed ok. + Programming of 8 bytes at address 0x0801C438 performed ok. + Programming of 8 bytes at address 0x0801C440 performed ok. + Programming of 8 bytes at address 0x0801C448 performed ok. + Programming of 8 bytes at address 0x0801C450 performed ok. + Programming of 8 bytes at address 0x0801C458 performed ok. + Programming of 8 bytes at address 0x0801C460 performed ok. + Programming of 8 bytes at address 0x0801C468 performed ok. + Programming of 8 bytes at address 0x0801C470 performed ok. + Programming of 8 bytes at address 0x0801C478 performed ok. + Programming of 8 bytes at address 0x0801C480 performed ok. + Programming of 8 bytes at address 0x0801C488 performed ok. + Programming of 8 bytes at address 0x0801C490 performed ok. + Programming of 8 bytes at address 0x0801C498 performed ok. + Programming of 8 bytes at address 0x0801C4A0 performed ok. + Programming of 8 bytes at address 0x0801C4A8 performed ok. + Programming of 8 bytes at address 0x0801C4B0 performed ok. + Programming of 8 bytes at address 0x0801C4B8 performed ok. + Programming of 8 bytes at address 0x0801C4C0 performed ok. +k. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801C500 performed ok. + Programming of 8 bytes at address 0x0801C508 performed ok. + Programming of 8 bytes at address 0x0801C510 performed ok. + Programming of 8 bytes at address 0x0801C518 performed ok. + Programming of 8 bytes at address 0x0801C520 performed ok. + Programming of 8 bytes at address 0x0801C528 performed ok. + Programming of 8 bytes at address 0x0801C530 performed ok. + Programming of 8 bytes at address 0x0801C538 performed ok. + Programming of 8 bytes at address 0x0801C540 performed ok. + Programming of 8 bytes at address 0x0801C548 performed ok. + Programming of 8 bytes at address 0x0801C550 performed ok. + Programming of 8 bytes at address 0x0801C558 performed ok. + Programming of 8 bytes at address 0x0801C560 performed ok. + Programming of 8 bytes at address 0x0801C568 performed ok. + Programming of 8 bytes at address 0x0801C570 performed ok. + Programming of 8 bytes at address 0x0801C578 performed ok. + Programming of 8 bytes at address 0x0801C580 performed ok. + Programming of 8 bytes at address 0x0801C588 performed ok. + Programming of 8 bytes at address 0x0801C590 performed ok. + Programming of 8 bytes at address 0x0801C598 performed ok. + Programming of 8 bytes at address 0x0801C5A0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801C5C8 performed ok. + Programming of 8 bytes at address 0x0801C5D0 performed ok. + Programming of 8 bytes at address 0x0801C5D8 performed ok. + Programming of 8 bytes at address 0x0801C5E0 performed ok. + Programming of 8 bytes at address 0x0801C5E8 performed ok. + Programming of 8 bytes at address 0x0801C5F0 performed ok. + Programming of 8 bytes at address 0x0801C5F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801C600 performed ok. + Programming of 8 bytes at address 0x0801C608 performed ok. + Programming of 8 bytes at address 0x0801C610 performed ok. + Programming of 8 bytes at address 0x0801C618 performed ok. + Programming of 8 bytes at address 0x0801C620 performed ok. + Programming of 8 bytes at address 0x0801C628 performed ok. + Programming of 8 bytes at address 0x0801C630 performed ok. + Programming of 8 bytes at address 0x0801C638 performed ok. + Programming of 8 bytes at address 0x0801C640 performed ok. + Programming of 8 bytes at address 0x0801C648 performed ok. + Programming of 8 bytes at address 0x0801C650 performed ok. + Programming of 8 bytes at address 0x0801C658 performed ok. + Programming of 8 bytes at address 0x0801C660 performed ok. + Programming of 8 bytes at address 0x0801C668 performed ok. + Programming of 8 bytes at address 0x0801C670 performed ok. + Programming of 8 bytes at address 0x0801C678 performed ok. + Programming of 8 bytes at address 0x0801C680 performed ok. + Programming of 8 bytes at address 0x0801C688 performed ok. + Programming of 8 bytes at address 0x0801C690 performed ok. + Programming of 8 bytes at address 0x0801C698 performed ok. +k. + Programming of 8 bytes at address 0x0801C6A8 performed ok. + Programming of 8 bytes at address 0x0801C6B0 performed ok. + Programming of 8 bytes at address 0x0801C6B8 performed ok. + Programming of 8 bytes at address 0x0801C6C0 performed ok. + Programming of 8 bytes at address 0x0801C6C8 performed ok. + Programming of 8 bytes at address 0x0801C6D0 performed ok. + Programming of 8 bytes at address 0x0801C6D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801C700 performed ok. + Programming of 8 bytes at address 0x0801C708 performed ok. + Programming of 8 bytes at address 0x0801C710 performed ok. + Programming of 8 bytes at address 0x0801C718 performed ok. + Programming of 8 bytes at address 0x0801C720 performed ok. + Programming of 8 bytes at address 0x0801C728 performed ok. + Programming of 8 bytes at address 0x0801C730 performed ok. + Programming of 8 bytes at address 0x0801C738 performed ok. + Programming of 8 bytes at address 0x0801C740 performed ok. + Programming of 8 bytes at address 0x0801C748 performed ok. + Programming of 8 bytes at address 0x0801C750 performed ok. + Programming of 8 bytes at address 0x0801C758 performed ok. + Programming of 8 bytes at address 0x0801C760 performed ok. + Programming of 8 bytes at address 0x0801C768 performed ok. + Programming of 8 bytes at address 0x0801C770 performed ok. + Programming of 8 bytes at address 0x0801C778 performed ok. + Programming of 8 bytes at address 0x0801C780 performed ok. + Programming of 8 bytes at address 0x0801C788 performed ok. + Programming of 8 bytes at address 0x0801C790 performed ok. + Programming of 8 bytes at address 0x0801C798 performed ok. + Programming of 8 bytes at address 0x0801C7A0 performed ok. + Programming of 8 bytes at address 0x0801C7A8 performed ok. + Programming of 8 bytes at address 0x0801C7B0 performed ok. + Programming of 8 bytes at address 0x0801C7B8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801C800 performed ok. + Programming of 8 bytes at address 0x0801C808 performed ok. + Programming of 8 bytes at address 0x0801C810 performed ok. + Programming of 8 bytes at address 0x0801C818 performed ok. + Programming of 8 bytes at address 0x0801C820 performed ok. + Programming of 8 bytes at address 0x0801C828 performed ok. + Programming of 8 bytes at address 0x0801C830 performed ok. + Programming of 8 bytes at address 0x0801C838 performed ok. + Programming of 8 bytes at address 0x0801C840 performed ok. + Programming of 8 bytes at address 0x0801C848 performed ok. + Programming of 8 bytes at address 0x0801C850 performed ok. + Programming of 8 bytes at address 0x0801C858 performed ok. + Programming of 8 bytes at address 0x0801C860 performed ok. + Programming of 8 bytes at address 0x0801C868 performed ok. + Programming of 8 bytes at address 0x0801C870 performed ok. + Programming of 8 bytes at address 0x0801C878 performed ok. + Programming of 8 bytes at address 0x0801C880 performed ok. + Programming of 8 bytes at address 0x0801C888 performed ok. + Programming of 8 bytes at address 0x0801C890 performed ok. + Programming of 8 bytes at address 0x0801C898 performed ok. + Programming of 8 bytes at address 0x0801C8A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801C8C0 performed ok. + Programming of 8 bytes at address 0x0801C8C8 performed ok. + Programming of 8 bytes at address 0x0801C8D0 performed ok. + Programming of 8 bytes at address 0x0801C8D8 performed ok. + Programming of 8 bytes at address 0x0801C8E0 performed ok. + Programming of 8 bytes at address 0x0801C8E8 performed ok. + Programming of 8 bytes at address 0x0801C8F0 performed ok. + Programming of 8 bytes at address 0x0801C8F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801C900 performed ok. + Programming of 8 bytes at address 0x0801C908 performed ok. + Programming of 8 bytes at address 0x0801C910 performed ok. + Programming of 8 bytes at address 0x0801C918 performed ok. + Programming of 8 bytes at address 0x0801C920 performed ok. + Programming of 8 bytes at address 0x0801C928 performed ok. + Programming of 8 bytes at address 0x0801C930 performed ok. + Programming of 8 bytes at address 0x0801C938 performed ok. + Programming of 8 bytes at address 0x0801C940 performed ok. + Programming of 8 bytes at address 0x0801C948 performed ok. + Programming of 8 bytes at address 0x0801C950 performed ok. + Programming of 8 bytes at address 0x0801C958 performed ok. + Programming of 8 bytes at address 0x0801C960 performed ok. + Programming of 8 bytes at address 0x0801C968 performed ok. + Programming of 8 bytes at address 0x0801C970 performed ok. + Programming of 8 bytes at address 0x0801C978 performed ok. + Programming of 8 bytes at address 0x0801C980 performed ok. + Programming of 8 bytes at address 0x0801C988 performed ok. + Programming of 8 bytes at address 0x0801C990 performed ok. + Programming of 8 bytes at address 0x0801C998 performed ok. + Programming of 8 bytes at address 0x0801C9A0 performed ok. + Programming of 8 bytes at address 0x0801C9A8 performed ok. + Programming of 8 bytes at address 0x0801C9B0 performed ok. + Programming of 8 bytes at address 0x0801C9B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801C9F0 performed ok. + Programming of 8 bytes at address 0x0801C9F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801CA00 performed ok. + Programming of 8 bytes at address 0x0801CA08 performed ok. + Programming of 8 bytes at address 0x0801CA10 performed ok. + Programming of 8 bytes at address 0x0801CA18 performed ok. + Programming of 8 bytes at address 0x0801CA20 performed ok. + Programming of 8 bytes at address 0x0801CA28 performed ok. + Programming of 8 bytes at address 0x0801CA30 performed ok. + Programming of 8 bytes at address 0x0801CA38 performed ok. + Programming of 8 bytes at address 0x0801CA40 performed ok. + Programming of 8 bytes at address 0x0801CA48 performed ok. + Programming of 8 bytes at address 0x0801CA50 performed ok. + Programming of 8 bytes at address 0x0801CA58 performed ok. + Programming of 8 bytes at address 0x0801CA60 performed ok. + Programming of 8 bytes at address 0x0801CA68 performed ok. + Programming of 8 bytes at address 0x0801CA70 performed ok. + Programming of 8 bytes at address 0x0801CA78 performed ok. + Programming of 8 bytes at address 0x0801CA80 performed ok. + Programming of 8 bytes at address 0x0801CA88 performed ok. + Programming of 8 bytes at address 0x0801CA90 performed ok. + Programming of 8 bytes at address 0x0801CA98 performed ok. + Programming of 8 bytes at address 0x0801CAA0 performed ok. + Programming of 8 bytes at address 0x0801CAA8 performed ok. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801CAD8 performed ok. + Programming of 8 bytes at address 0x0801CAE0 performed ok. + Programming of 8 bytes at address 0x0801CAE8 performed ok. + Programming of 8 bytes at address 0x0801CAF0 performed ok. + Programming of 8 bytes at address 0x0801CAF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801CB00 performed ok. + Programming of 8 bytes at address 0x0801CB08 performed ok. + Programming of 8 bytes at address 0x0801CB10 performed ok. + Programming of 8 bytes at address 0x0801CB18 performed ok. + Programming of 8 bytes at address 0x0801CB20 performed ok. + Programming of 8 bytes at address 0x0801CB28 performed ok. + Programming of 8 bytes at address 0x0801CB30 performed ok. + Programming of 8 bytes at address 0x0801CB38 performed ok. + Programming of 8 bytes at address 0x0801CB40 performed ok. + Programming of 8 bytes at address 0x0801CB48 performed ok. + Programming of 8 bytes at address 0x0801CB50 performed ok. + Programming of 8 bytes at address 0x0801CB58 performed ok. + Programming of 8 bytes at address 0x0801CB60 performed ok. + Programming of 8 bytes at address 0x0801CB68 performed ok. + Programming of 8 bytes at address 0x0801CB70 performed ok. + Programming of 8 bytes at address 0x0801CB78 performed ok. + Programming of 8 bytes at address 0x0801CB80 performed ok. + Programming of 8 bytes at address 0x0801CB88 performed ok. + Programming of 8 bytes at address 0x0801CB90 performed ok. + Programming of 8 bytes at address 0x0801CB98 performed ok. +k. + Programming of 8 bytes at address 0x0801CBA8 performed ok. + Programming of 8 bytes at address 0x0801CBB0 performed ok. + Programming of 8 bytes at address 0x0801CBB8 performed ok. + Programming of 8 bytes at address 0x0801CBC0 performed ok. + Programming of 8 bytes at address 0x0801CBC8 performed ok. + Programming of 8 bytes at address 0x0801CBD0 performed ok. + Programming of 8 bytes at address 0x0801CBD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801CC00 performed ok. + Programming of 8 bytes at address 0x0801CC08 performed ok. + Programming of 8 bytes at address 0x0801CC10 performed ok. + Programming of 8 bytes at address 0x0801CC18 performed ok. + Programming of 8 bytes at address 0x0801CC20 performed ok. + Programming of 8 bytes at address 0x0801CC28 performed ok. + Programming of 8 bytes at address 0x0801CC30 performed ok. + Programming of 8 bytes at address 0x0801CC38 performed ok. + Programming of 8 bytes at address 0x0801CC40 performed ok. + Programming of 8 bytes at address 0x0801CC48 performed ok. + Programming of 8 bytes at address 0x0801CC50 performed ok. + Programming of 8 bytes at address 0x0801CC58 performed ok. + Programming of 8 bytes at address 0x0801CC60 performed ok. + Programming of 8 bytes at address 0x0801CC68 performed ok. + Programming of 8 bytes at address 0x0801CC70 performed ok. + Programming of 8 bytes at address 0x0801CC78 performed ok. + Programming of 8 bytes at address 0x0801CC80 performed ok. + Programming of 8 bytes at address 0x0801CC88 performed ok. + Programming of 8 bytes at address 0x0801CC90 performed ok. + Programming of 8 bytes at address 0x0801CC98 performed ok. + Programming of 8 bytes at address 0x0801CCA0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801CCC8 performed ok. + Programming of 8 bytes at address 0x0801CCD0 performed ok. + Programming of 8 bytes at address 0x0801CCD8 performed ok. + Programming of 8 bytes at address 0x0801CCE0 performed ok. + Programming of 8 bytes at address 0x0801CCE8 performed ok. + Programming of 8 bytes at address 0x0801CCF0 performed ok. + Programming of 8 bytes at address 0x0801CCF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801CD00 performed ok. + Programming of 8 bytes at address 0x0801CD08 performed ok. + Programming of 8 bytes at address 0x0801CD10 performed ok. + Programming of 8 bytes at address 0x0801CD18 performed ok. + Programming of 8 bytes at address 0x0801CD20 performed ok. + Programming of 8 bytes at address 0x0801CD28 performed ok. + Programming of 8 bytes at address 0x0801CD30 performed ok. + Programming of 8 bytes at address 0x0801CD38 performed ok. + Programming of 8 bytes at address 0x0801CD40 performed ok. + Programming of 8 bytes at address 0x0801CD48 performed ok. + Programming of 8 bytes at address 0x0801CD50 performed ok. + Programming of 8 bytes at address 0x0801CD58 performed ok. + Programming of 8 bytes at address 0x0801CD60 performed ok. + Programming of 8 bytes at address 0x0801CD68 performed ok. + Programming of 8 bytes at address 0x0801CD70 performed ok. + Programming of 8 bytes at address 0x0801CD78 performed ok. + Programming of 8 bytes at address 0x0801CD80 performed ok. + Programming of 8 bytes at address 0x0801CD88 performed ok. + Programming of 8 bytes at address 0x0801CD90 performed ok. + Programming of 8 bytes at address 0x0801CD98 performed ok. + Programming of 8 bytes at address 0x0801CDA0 performed ok. + Programming of 8 bytes at address 0x0801CDA8 performed ok. + Programming of 8 bytes at address 0x0801CDB0 performed ok. + Programming of 8 bytes at address 0x0801CDB8 performed ok. + Programming of 8 bytes at address 0x0801CDC0 performed ok. +k. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801CE00 performed ok. + Programming of 8 bytes at address 0x0801CE08 performed ok. + Programming of 8 bytes at address 0x0801CE10 performed ok. + Programming of 8 bytes at address 0x0801CE18 performed ok. + Programming of 8 bytes at address 0x0801CE20 performed ok. + Programming of 8 bytes at address 0x0801CE28 performed ok. + Programming of 8 bytes at address 0x0801CE30 performed ok. + Programming of 8 bytes at address 0x0801CE38 performed ok. + Programming of 8 bytes at address 0x0801CE40 performed ok. + Programming of 8 bytes at address 0x0801CE48 performed ok. + Programming of 8 bytes at address 0x0801CE50 performed ok. + Programming of 8 bytes at address 0x0801CE58 performed ok. + Programming of 8 bytes at address 0x0801CE60 performed ok. + Programming of 8 bytes at address 0x0801CE68 performed ok. + Programming of 8 bytes at address 0x0801CE70 performed ok. + Programming of 8 bytes at address 0x0801CE78 performed ok. + Programming of 8 bytes at address 0x0801CE80 performed ok. + Programming of 8 bytes at address 0x0801CE88 performed ok. + Programming of 8 bytes at address 0x0801CE90 performed ok. + Programming of 8 bytes at address 0x0801CE98 performed ok. + Programming of 8 bytes at address 0x0801CEA0 performed ok. + Programming of 8 bytes at address 0x0801CEA8 performed ok. + Programming of 8 bytes at address 0x0801CEB0 performed ok. + Programming of 8 bytes at address 0x0801CEB8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801CF00 performed ok. + Programming of 8 bytes at address 0x0801CF08 performed ok. + Programming of 8 bytes at address 0x0801CF10 performed ok. + Programming of 8 bytes at address 0x0801CF18 performed ok. + Programming of 8 bytes at address 0x0801CF20 performed ok. + Programming of 8 bytes at address 0x0801CF28 performed ok. + Programming of 8 bytes at address 0x0801CF30 performed ok. + Programming of 8 bytes at address 0x0801CF38 performed ok. + Programming of 8 bytes at address 0x0801CF40 performed ok. + Programming of 8 bytes at address 0x0801CF48 performed ok. + Programming of 8 bytes at address 0x0801CF50 performed ok. + Programming of 8 bytes at address 0x0801CF58 performed ok. + Programming of 8 bytes at address 0x0801CF60 performed ok. + Programming of 8 bytes at address 0x0801CF68 performed ok. + Programming of 8 bytes at address 0x0801CF70 performed ok. + Programming of 8 bytes at address 0x0801CF78 performed ok. + Programming of 8 bytes at address 0x0801CF80 performed ok. + Programming of 8 bytes at address 0x0801CF88 performed ok. + Programming of 8 bytes at address 0x0801CF90 performed ok. + Programming of 8 bytes at address 0x0801CF98 performed ok. +k. + Programming of 8 bytes at address 0x0801CFA8 performed ok. + Programming of 8 bytes at address 0x0801CFB0 performed ok. + Programming of 8 bytes at address 0x0801CFB8 performed ok. + Programming of 8 bytes at address 0x0801CFC0 performed ok. + Programming of 8 bytes at address 0x0801CFC8 performed ok. + Programming of 8 bytes at address 0x0801CFD0 performed ok. + Programming of 8 bytes at address 0x0801CFD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801D000 performed ok. + Programming of 8 bytes at address 0x0801D008 performed ok. + Programming of 8 bytes at address 0x0801D010 performed ok. + Programming of 8 bytes at address 0x0801D018 performed ok. + Programming of 8 bytes at address 0x0801D020 performed ok. + Programming of 8 bytes at address 0x0801D028 performed ok. + Programming of 8 bytes at address 0x0801D030 performed ok. + Programming of 8 bytes at address 0x0801D038 performed ok. + Programming of 8 bytes at address 0x0801D040 performed ok. + Programming of 8 bytes at address 0x0801D048 performed ok. + Programming of 8 bytes at address 0x0801D050 performed ok. + Programming of 8 bytes at address 0x0801D058 performed ok. + Programming of 8 bytes at address 0x0801D060 performed ok. + Programming of 8 bytes at address 0x0801D068 performed ok. + Programming of 8 bytes at address 0x0801D070 performed ok. + Programming of 8 bytes at address 0x0801D078 performed ok. + Programming of 8 bytes at address 0x0801D080 performed ok. + Programming of 8 bytes at address 0x0801D088 performed ok. + Programming of 8 bytes at address 0x0801D090 performed ok. +k. + Programming of 8 bytes at address 0x0801D0A0 performed ok. + Programming of 8 bytes at address 0x0801D0A8 performed ok. + Programming of 8 bytes at address 0x0801D0B0 performed ok. + Programming of 8 bytes at address 0x0801D0B8 performed ok. + Programming of 8 bytes at address 0x0801D0C0 performed ok. + Programming of 8 bytes at address 0x0801D0C8 performed ok. + Programming of 8 bytes at address 0x0801D0D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801D100 performed ok. + Programming of 8 bytes at address 0x0801D108 performed ok. + Programming of 8 bytes at address 0x0801D110 performed ok. + Programming of 8 bytes at address 0x0801D118 performed ok. + Programming of 8 bytes at address 0x0801D120 performed ok. + Programming of 8 bytes at address 0x0801D128 performed ok. + Programming of 8 bytes at address 0x0801D130 performed ok. + Programming of 8 bytes at address 0x0801D138 performed ok. + Programming of 8 bytes at address 0x0801D140 performed ok. + Programming of 8 bytes at address 0x0801D148 performed ok. + Programming of 8 bytes at address 0x0801D150 performed ok. + Programming of 8 bytes at address 0x0801D158 performed ok. + Programming of 8 bytes at address 0x0801D160 performed ok. + Programming of 8 bytes at address 0x0801D168 performed ok. + Programming of 8 bytes at address 0x0801D170 performed ok. + Programming of 8 bytes at address 0x0801D178 performed ok. + Programming of 8 bytes at address 0x0801D180 performed ok. + Programming of 8 bytes at address 0x0801D188 performed ok. + Programming of 8 bytes at address 0x0801D190 performed ok. + Programming of 8 bytes at address 0x0801D198 performed ok. + Programming of 8 bytes at address 0x0801D1A0 performed ok. + Programming of 8 bytes at address 0x0801D1A8 performed ok. + Programming of 8 bytes at address 0x0801D1B0 performed ok. + Programming of 8 bytes at address 0x0801D1B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801D1F0 performed ok. + Programming of 8 bytes at address 0x0801D1F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801D200 performed ok. + Programming of 8 bytes at address 0x0801D208 performed ok. + Programming of 8 bytes at address 0x0801D210 performed ok. + Programming of 8 bytes at address 0x0801D218 performed ok. + Programming of 8 bytes at address 0x0801D220 performed ok. + Programming of 8 bytes at address 0x0801D228 performed ok. + Programming of 8 bytes at address 0x0801D230 performed ok. + Programming of 8 bytes at address 0x0801D238 performed ok. + Programming of 8 bytes at address 0x0801D240 performed ok. + Programming of 8 bytes at address 0x0801D248 performed ok. + Programming of 8 bytes at address 0x0801D250 performed ok. + Programming of 8 bytes at address 0x0801D258 performed ok. + Programming of 8 bytes at address 0x0801D260 performed ok. + Programming of 8 bytes at address 0x0801D268 performed ok. + Programming of 8 bytes at address 0x0801D270 performed ok. + Programming of 8 bytes at address 0x0801D278 performed ok. + Programming of 8 bytes at address 0x0801D280 performed ok. + Programming of 8 bytes at address 0x0801D288 performed ok. + Programming of 8 bytes at address 0x0801D290 performed ok. + Programming of 8 bytes at address 0x0801D298 performed ok. + Programming of 8 bytes at address 0x0801D2A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801D2C0 performed ok. + Programming of 8 bytes at address 0x0801D2C8 performed ok. + Programming of 8 bytes at address 0x0801D2D0 performed ok. + Programming of 8 bytes at address 0x0801D2D8 performed ok. + Programming of 8 bytes at address 0x0801D2E0 performed ok. + Programming of 8 bytes at address 0x0801D2E8 performed ok. + Programming of 8 bytes at address 0x0801D2F0 performed ok. + Programming of 8 bytes at address 0x0801D2F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801D300 performed ok. + Programming of 8 bytes at address 0x0801D308 performed ok. + Programming of 8 bytes at address 0x0801D310 performed ok. + Programming of 8 bytes at address 0x0801D318 performed ok. + Programming of 8 bytes at address 0x0801D320 performed ok. + Programming of 8 bytes at address 0x0801D328 performed ok. + Programming of 8 bytes at address 0x0801D330 performed ok. + Programming of 8 bytes at address 0x0801D338 performed ok. + Programming of 8 bytes at address 0x0801D340 performed ok. + Programming of 8 bytes at address 0x0801D348 performed ok. + Programming of 8 bytes at address 0x0801D350 performed ok. + Programming of 8 bytes at address 0x0801D358 performed ok. + Programming of 8 bytes at address 0x0801D360 performed ok. + Programming of 8 bytes at address 0x0801D368 performed ok. + Programming of 8 bytes at address 0x0801D370 performed ok. + Programming of 8 bytes at address 0x0801D378 performed ok. + Programming of 8 bytes at address 0x0801D380 performed ok. + Programming of 8 bytes at address 0x0801D388 performed ok. + Programming of 8 bytes at address 0x0801D390 performed ok. + Programming of 8 bytes at address 0x0801D398 performed ok. + Programming of 8 bytes at address 0x0801D3A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801D3C0 performed ok. + Programming of 8 bytes at address 0x0801D3C8 performed ok. + Programming of 8 bytes at address 0x0801D3D0 performed ok. + Programming of 8 bytes at address 0x0801D3D8 performed ok. + Programming of 8 bytes at address 0x0801D3E0 performed ok. + Programming of 8 bytes at address 0x0801D3E8 performed ok. + Programming of 8 bytes at address 0x0801D3F0 performed ok. + Programming of 8 bytes at address 0x0801D3F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801D400 performed ok. + Programming of 8 bytes at address 0x0801D408 performed ok. + Programming of 8 bytes at address 0x0801D410 performed ok. + Programming of 8 bytes at address 0x0801D418 performed ok. + Programming of 8 bytes at address 0x0801D420 performed ok. + Programming of 8 bytes at address 0x0801D428 performed ok. + Programming of 8 bytes at address 0x0801D430 performed ok. + Programming of 8 bytes at address 0x0801D438 performed ok. + Programming of 8 bytes at address 0x0801D440 performed ok. + Programming of 8 bytes at address 0x0801D448 performed ok. + Programming of 8 bytes at address 0x0801D450 performed ok. + Programming of 8 bytes at address 0x0801D458 performed ok. + Programming of 8 bytes at address 0x0801D460 performed ok. + Programming of 8 bytes at address 0x0801D468 performed ok. + Programming of 8 bytes at address 0x0801D470 performed ok. + Programming of 8 bytes at address 0x0801D478 performed ok. + Programming of 8 bytes at address 0x0801D480 performed ok. + Programming of 8 bytes at address 0x0801D488 performed ok. + Programming of 8 bytes at address 0x0801D490 performed ok. + Programming of 8 bytes at address 0x0801D498 performed ok. +k. + Programming of 8 bytes at address 0x0801D4A8 performed ok. + Programming of 8 bytes at address 0x0801D4B0 performed ok. + Programming of 8 bytes at address 0x0801D4B8 performed ok. + Programming of 8 bytes at address 0x0801D4C0 performed ok. + Programming of 8 bytes at address 0x0801D4C8 performed ok. + Programming of 8 bytes at address 0x0801D4D0 performed ok. + Programming of 8 bytes at address 0x0801D4D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801D500 performed ok. + Programming of 8 bytes at address 0x0801D508 performed ok. + Programming of 8 bytes at address 0x0801D510 performed ok. + Programming of 8 bytes at address 0x0801D518 performed ok. + Programming of 8 bytes at address 0x0801D520 performed ok. + Programming of 8 bytes at address 0x0801D528 performed ok. + Programming of 8 bytes at address 0x0801D530 performed ok. + Programming of 8 bytes at address 0x0801D538 performed ok. + Programming of 8 bytes at address 0x0801D540 performed ok. + Programming of 8 bytes at address 0x0801D548 performed ok. + Programming of 8 bytes at address 0x0801D550 performed ok. + Programming of 8 bytes at address 0x0801D558 performed ok. + Programming of 8 bytes at address 0x0801D560 performed ok. + Programming of 8 bytes at address 0x0801D568 performed ok. + Programming of 8 bytes at address 0x0801D570 performed ok. + Programming of 8 bytes at address 0x0801D578 performed ok. + Programming of 8 bytes at address 0x0801D580 performed ok. + Programming of 8 bytes at address 0x0801D588 performed ok. + Programming of 8 bytes at address 0x0801D590 performed ok. + Programming of 8 bytes at address 0x0801D598 performed ok. + Programming of 8 bytes at address 0x0801D5A0 performed ok. + Programming of 8 bytes at address 0x0801D5A8 performed ok. + Programming of 8 bytes at address 0x0801D5B0 performed ok. + Programming of 8 bytes at address 0x0801D5B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801D5F0 performed ok. + Programming of 8 bytes at address 0x0801D5F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801D600 performed ok. + Programming of 8 bytes at address 0x0801D608 performed ok. + Programming of 8 bytes at address 0x0801D610 performed ok. + Programming of 8 bytes at address 0x0801D618 performed ok. + Programming of 8 bytes at address 0x0801D620 performed ok. + Programming of 8 bytes at address 0x0801D628 performed ok. + Programming of 8 bytes at address 0x0801D630 performed ok. + Programming of 8 bytes at address 0x0801D638 performed ok. + Programming of 8 bytes at address 0x0801D640 performed ok. + Programming of 8 bytes at address 0x0801D648 performed ok. + Programming of 8 bytes at address 0x0801D650 performed ok. + Programming of 8 bytes at address 0x0801D658 performed ok. + Programming of 8 bytes at address 0x0801D660 performed ok. + Programming of 8 bytes at address 0x0801D668 performed ok. + Programming of 8 bytes at address 0x0801D670 performed ok. + Programming of 8 bytes at address 0x0801D678 performed ok. + Programming of 8 bytes at address 0x0801D680 performed ok. + Programming of 8 bytes at address 0x0801D688 performed ok. + Programming of 8 bytes at address 0x0801D690 performed ok. + Programming of 8 bytes at address 0x0801D698 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801D6B8 performed ok. + Programming of 8 bytes at address 0x0801D6C0 performed ok. + Programming of 8 bytes at address 0x0801D6C8 performed ok. + Programming of 8 bytes at address 0x0801D6D0 performed ok. + Programming of 8 bytes at address 0x0801D6D8 performed ok. + Programming of 8 bytes at address 0x0801D6E0 performed ok. + Programming of 8 bytes at address 0x0801D6E8 performed ok. + Programming of 8 bytes at address 0x0801D6F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801D700 performed ok. + Programming of 8 bytes at address 0x0801D708 performed ok. + Programming of 8 bytes at address 0x0801D710 performed ok. + Programming of 8 bytes at address 0x0801D718 performed ok. + Programming of 8 bytes at address 0x0801D720 performed ok. + Programming of 8 bytes at address 0x0801D728 performed ok. + Programming of 8 bytes at address 0x0801D730 performed ok. + Programming of 8 bytes at address 0x0801D738 performed ok. + Programming of 8 bytes at address 0x0801D740 performed ok. + Programming of 8 bytes at address 0x0801D748 performed ok. + Programming of 8 bytes at address 0x0801D750 performed ok. + Programming of 8 bytes at address 0x0801D758 performed ok. + Programming of 8 bytes at address 0x0801D760 performed ok. + Programming of 8 bytes at address 0x0801D768 performed ok. + Programming of 8 bytes at address 0x0801D770 performed ok. + Programming of 8 bytes at address 0x0801D778 performed ok. + Programming of 8 bytes at address 0x0801D780 performed ok. + Programming of 8 bytes at address 0x0801D788 performed ok. + Programming of 8 bytes at address 0x0801D790 performed ok. + Programming of 8 bytes at address 0x0801D798 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801D7B8 performed ok. + Programming of 8 bytes at address 0x0801D7C0 performed ok. + Programming of 8 bytes at address 0x0801D7C8 performed ok. + Programming of 8 bytes at address 0x0801D7D0 performed ok. + Programming of 8 bytes at address 0x0801D7D8 performed ok. + Programming of 8 bytes at address 0x0801D7E0 performed ok. + Programming of 8 bytes at address 0x0801D7E8 performed ok. + Programming of 8 bytes at address 0x0801D7F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801D800 performed ok. + Programming of 8 bytes at address 0x0801D808 performed ok. + Programming of 8 bytes at address 0x0801D810 performed ok. + Programming of 8 bytes at address 0x0801D818 performed ok. + Programming of 8 bytes at address 0x0801D820 performed ok. + Programming of 8 bytes at address 0x0801D828 performed ok. + Programming of 8 bytes at address 0x0801D830 performed ok. + Programming of 8 bytes at address 0x0801D838 performed ok. + Programming of 8 bytes at address 0x0801D840 performed ok. + Programming of 8 bytes at address 0x0801D848 performed ok. + Programming of 8 bytes at address 0x0801D850 performed ok. + Programming of 8 bytes at address 0x0801D858 performed ok. + Programming of 8 bytes at address 0x0801D860 performed ok. + Programming of 8 bytes at address 0x0801D868 performed ok. + Programming of 8 bytes at address 0x0801D870 performed ok. + Programming of 8 bytes at address 0x0801D878 performed ok. + Programming of 8 bytes at address 0x0801D880 performed ok. + Programming of 8 bytes at address 0x0801D888 performed ok. + Programming of 8 bytes at address 0x0801D890 performed ok. + Programming of 8 bytes at address 0x0801D898 performed ok. + Programming of 8 bytes at address 0x0801D8A0 performed ok. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801D8C8 performed ok. + Programming of 8 bytes at address 0x0801D8D0 performed ok. + Programming of 8 bytes at address 0x0801D8D8 performed ok. + Programming of 8 bytes at address 0x0801D8E0 performed ok. + Programming of 8 bytes at address 0x0801D8E8 performed ok. + Programming of 8 bytes at address 0x0801D8F0 performed ok. + Programming of 8 bytes at address 0x0801D8F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801D900 performed ok. + Programming of 8 bytes at address 0x0801D908 performed ok. + Programming of 8 bytes at address 0x0801D910 performed ok. + Programming of 8 bytes at address 0x0801D918 performed ok. + Programming of 8 bytes at address 0x0801D920 performed ok. + Programming of 8 bytes at address 0x0801D928 performed ok. + Programming of 8 bytes at address 0x0801D930 performed ok. + Programming of 8 bytes at address 0x0801D938 performed ok. + Programming of 8 bytes at address 0x0801D940 performed ok. + Programming of 8 bytes at address 0x0801D948 performed ok. + Programming of 8 bytes at address 0x0801D950 performed ok. + Programming of 8 bytes at address 0x0801D958 performed ok. + Programming of 8 bytes at address 0x0801D960 performed ok. + Programming of 8 bytes at address 0x0801D968 performed ok. + Programming of 8 bytes at address 0x0801D970 performed ok. + Programming of 8 bytes at address 0x0801D978 performed ok. + Programming of 8 bytes at address 0x0801D980 performed ok. + Programming of 8 bytes at address 0x0801D988 performed ok. + Programming of 8 bytes at address 0x0801D990 performed ok. + Programming of 8 bytes at address 0x0801D998 performed ok. + Programming of 8 bytes at address 0x0801D9A0 performed ok. + Programming of 8 bytes at address 0x0801D9A8 performed ok. +k. + Programming of 8 bytes at address 0x0801D9B8 performed ok. + Programming of 8 bytes at address 0x0801D9C0 performed ok. + Programming of 8 bytes at address 0x0801D9C8 performed ok. + Programming of 8 bytes at address 0x0801D9D0 performed ok. + Programming of 8 bytes at address 0x0801D9D8 performed ok. + Programming of 8 bytes at address 0x0801D9E0 performed ok. + Programming of 8 bytes at address 0x0801D9E8 performed ok. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801DA00 performed ok. + Programming of 8 bytes at address 0x0801DA08 performed ok. + Programming of 8 bytes at address 0x0801DA10 performed ok. + Programming of 8 bytes at address 0x0801DA18 performed ok. + Programming of 8 bytes at address 0x0801DA20 performed ok. + Programming of 8 bytes at address 0x0801DA28 performed ok. + Programming of 8 bytes at address 0x0801DA30 performed ok. + Programming of 8 bytes at address 0x0801DA38 performed ok. + Programming of 8 bytes at address 0x0801DA40 performed ok. + Programming of 8 bytes at address 0x0801DA48 performed ok. + Programming of 8 bytes at address 0x0801DA50 performed ok. + Programming of 8 bytes at address 0x0801DA58 performed ok. + Programming of 8 bytes at address 0x0801DA60 performed ok. + Programming of 8 bytes at address 0x0801DA68 performed ok. + Programming of 8 bytes at address 0x0801DA70 performed ok. + Programming of 8 bytes at address 0x0801DA78 performed ok. + Programming of 8 bytes at address 0x0801DA80 performed ok. + Programming of 8 bytes at address 0x0801DA88 performed ok. + Programming of 8 bytes at address 0x0801DA90 performed ok. + Programming of 8 bytes at address 0x0801DA98 performed ok. + Programming of 8 bytes at address 0x0801DAA0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801DAC0 performed ok. + Programming of 8 bytes at address 0x0801DAC8 performed ok. + Programming of 8 bytes at address 0x0801DAD0 performed ok. + Programming of 8 bytes at address 0x0801DAD8 performed ok. + Programming of 8 bytes at address 0x0801DAE0 performed ok. + Programming of 8 bytes at address 0x0801DAE8 performed ok. + Programming of 8 bytes at address 0x0801DAF0 performed ok. + Programming of 8 bytes at address 0x0801DAF8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801DB00 performed ok. + Programming of 8 bytes at address 0x0801DB08 performed ok. + Programming of 8 bytes at address 0x0801DB10 performed ok. + Programming of 8 bytes at address 0x0801DB18 performed ok. + Programming of 8 bytes at address 0x0801DB20 performed ok. + Programming of 8 bytes at address 0x0801DB28 performed ok. + Programming of 8 bytes at address 0x0801DB30 performed ok. + Programming of 8 bytes at address 0x0801DB38 performed ok. + Programming of 8 bytes at address 0x0801DB40 performed ok. + Programming of 8 bytes at address 0x0801DB48 performed ok. + Programming of 8 bytes at address 0x0801DB50 performed ok. + Programming of 8 bytes at address 0x0801DB58 performed ok. + Programming of 8 bytes at address 0x0801DB60 performed ok. + Programming of 8 bytes at address 0x0801DB68 performed ok. + Programming of 8 bytes at address 0x0801DB70 performed ok. + Programming of 8 bytes at address 0x0801DB78 performed ok. + Programming of 8 bytes at address 0x0801DB80 performed ok. + Programming of 8 bytes at address 0x0801DB88 performed ok. + Programming of 8 bytes at address 0x0801DB90 performed ok. + Programming of 8 bytes at address 0x0801DB98 performed ok. + Programming of 8 bytes at address 0x0801DBA0 performed ok. + Programming of 8 bytes at address 0x0801DBA8 performed ok. + Programming of 8 bytes at address 0x0801DBB0 performed ok. + Programming of 8 bytes at address 0x0801DBB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801DBF0 performed ok. + Programming of 8 bytes at address 0x0801DBF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801DC00 performed ok. + Programming of 8 bytes at address 0x0801DC08 performed ok. + Programming of 8 bytes at address 0x0801DC10 performed ok. + Programming of 8 bytes at address 0x0801DC18 performed ok. + Programming of 8 bytes at address 0x0801DC20 performed ok. + Programming of 8 bytes at address 0x0801DC28 performed ok. + Programming of 8 bytes at address 0x0801DC30 performed ok. + Programming of 8 bytes at address 0x0801DC38 performed ok. + Programming of 8 bytes at address 0x0801DC40 performed ok. + Programming of 8 bytes at address 0x0801DC48 performed ok. + Programming of 8 bytes at address 0x0801DC50 performed ok. + Programming of 8 bytes at address 0x0801DC58 performed ok. + Programming of 8 bytes at address 0x0801DC60 performed ok. + Programming of 8 bytes at address 0x0801DC68 performed ok. + Programming of 8 bytes at address 0x0801DC70 performed ok. + Programming of 8 bytes at address 0x0801DC78 performed ok. + Programming of 8 bytes at address 0x0801DC80 performed ok. + Programming of 8 bytes at address 0x0801DC88 performed ok. + Programming of 8 bytes at address 0x0801DC90 performed ok. +k. + Programming of 8 bytes at address 0x0801DCA0 performed ok. + Programming of 8 bytes at address 0x0801DCA8 performed ok. + Programming of 8 bytes at address 0x0801DCB0 performed ok. + Programming of 8 bytes at address 0x0801DCB8 performed ok. + Programming of 8 bytes at address 0x0801DCC0 performed ok. + Programming of 8 bytes at address 0x0801DCC8 performed ok. + Programming of 8 bytes at address 0x0801DCD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801DD00 performed ok. + Programming of 8 bytes at address 0x0801DD08 performed ok. + Programming of 8 bytes at address 0x0801DD10 performed ok. + Programming of 8 bytes at address 0x0801DD18 performed ok. + Programming of 8 bytes at address 0x0801DD20 performed ok. + Programming of 8 bytes at address 0x0801DD28 performed ok. + Programming of 8 bytes at address 0x0801DD30 performed ok. + Programming of 8 bytes at address 0x0801DD38 performed ok. + Programming of 8 bytes at address 0x0801DD40 performed ok. + Programming of 8 bytes at address 0x0801DD48 performed ok. + Programming of 8 bytes at address 0x0801DD50 performed ok. + Programming of 8 bytes at address 0x0801DD58 performed ok. + Programming of 8 bytes at address 0x0801DD60 performed ok. + Programming of 8 bytes at address 0x0801DD68 performed ok. + Programming of 8 bytes at address 0x0801DD70 performed ok. + Programming of 8 bytes at address 0x0801DD78 performed ok. + Programming of 8 bytes at address 0x0801DD80 performed ok. + Programming of 8 bytes at address 0x0801DD88 performed ok. + Programming of 8 bytes at address 0x0801DD90 performed ok. + Programming of 8 bytes at address 0x0801DD98 performed ok. +k. + Programming of 8 bytes at address 0x0801DDA8 performed ok. + Programming of 8 bytes at address 0x0801DDB0 performed ok. + Programming of 8 bytes at address 0x0801DDB8 performed ok. + Programming of 8 bytes at address 0x0801DDC0 performed ok. + Programming of 8 bytes at address 0x0801DDC8 performed ok. + Programming of 8 bytes at address 0x0801DDD0 performed ok. + Programming of 8 bytes at address 0x0801DDD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801DE00 performed ok. + Programming of 8 bytes at address 0x0801DE08 performed ok. + Programming of 8 bytes at address 0x0801DE10 performed ok. + Programming of 8 bytes at address 0x0801DE18 performed ok. + Programming of 8 bytes at address 0x0801DE20 performed ok. + Programming of 8 bytes at address 0x0801DE28 performed ok. + Programming of 8 bytes at address 0x0801DE30 performed ok. + Programming of 8 bytes at address 0x0801DE38 performed ok. + Programming of 8 bytes at address 0x0801DE40 performed ok. + Programming of 8 bytes at address 0x0801DE48 performed ok. + Programming of 8 bytes at address 0x0801DE50 performed ok. + Programming of 8 bytes at address 0x0801DE58 performed ok. + Programming of 8 bytes at address 0x0801DE60 performed ok. + Programming of 8 bytes at address 0x0801DE68 performed ok. + Programming of 8 bytes at address 0x0801DE70 performed ok. + Programming of 8 bytes at address 0x0801DE78 performed ok. + Programming of 8 bytes at address 0x0801DE80 performed ok. + Programming of 8 bytes at address 0x0801DE88 performed ok. + Programming of 8 bytes at address 0x0801DE90 performed ok. + Programming of 8 bytes at address 0x0801DE98 performed ok. + Programming of 8 bytes at address 0x0801DEA0 performed ok. + Programming of 8 bytes at address 0x0801DEA8 performed ok. + Programming of 8 bytes at address 0x0801DEB0 performed ok. + Programming of 8 bytes at address 0x0801DEB8 performed ok. +k. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801DF00 performed ok. + Programming of 8 bytes at address 0x0801DF08 performed ok. + Programming of 8 bytes at address 0x0801DF10 performed ok. + Programming of 8 bytes at address 0x0801DF18 performed ok. + Programming of 8 bytes at address 0x0801DF20 performed ok. + Programming of 8 bytes at address 0x0801DF28 performed ok. + Programming of 8 bytes at address 0x0801DF30 performed ok. + Programming of 8 bytes at address 0x0801DF38 performed ok. + Programming of 8 bytes at address 0x0801DF40 performed ok. + Programming of 8 bytes at address 0x0801DF48 performed ok. + Programming of 8 bytes at address 0x0801DF50 performed ok. + Programming of 8 bytes at address 0x0801DF58 performed ok. + Programming of 8 bytes at address 0x0801DF60 performed ok. + Programming of 8 bytes at address 0x0801DF68 performed ok. + Programming of 8 bytes at address 0x0801DF70 performed ok. + Programming of 8 bytes at address 0x0801DF78 performed ok. + Programming of 8 bytes at address 0x0801DF80 performed ok. + Programming of 8 bytes at address 0x0801DF88 performed ok. + Programming of 8 bytes at address 0x0801DF90 performed ok. + Programming of 8 bytes at address 0x0801DF98 performed ok. +k. + Programming of 8 bytes at address 0x0801DFA8 performed ok. + Programming of 8 bytes at address 0x0801DFB0 performed ok. + Programming of 8 bytes at address 0x0801DFB8 performed ok. + Programming of 8 bytes at address 0x0801DFC0 performed ok. + Programming of 8 bytes at address 0x0801DFC8 performed ok. + Programming of 8 bytes at address 0x0801DFD0 performed ok. + Programming of 8 bytes at address 0x0801DFD8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801E000 performed ok. + Programming of 8 bytes at address 0x0801E008 performed ok. + Programming of 8 bytes at address 0x0801E010 performed ok. + Programming of 8 bytes at address 0x0801E018 performed ok. + Programming of 8 bytes at address 0x0801E020 performed ok. + Programming of 8 bytes at address 0x0801E028 performed ok. + Programming of 8 bytes at address 0x0801E030 performed ok. + Programming of 8 bytes at address 0x0801E038 performed ok. + Programming of 8 bytes at address 0x0801E040 performed ok. + Programming of 8 bytes at address 0x0801E048 performed ok. + Programming of 8 bytes at address 0x0801E050 performed ok. + Programming of 8 bytes at address 0x0801E058 performed ok. + Programming of 8 bytes at address 0x0801E060 performed ok. + Programming of 8 bytes at address 0x0801E068 performed ok. + Programming of 8 bytes at address 0x0801E070 performed ok. + Programming of 8 bytes at address 0x0801E078 performed ok. + Programming of 8 bytes at address 0x0801E080 performed ok. + Programming of 8 bytes at address 0x0801E088 performed ok. + Programming of 8 bytes at address 0x0801E090 performed ok. + Programming of 8 bytes at address 0x0801E098 performed ok. + Programming of 8 bytes at address 0x0801E0A0 performed ok. + Programming of 8 bytes at address 0x0801E0A8 performed ok. + Programming of 8 bytes at address 0x0801E0B0 performed ok. + Programming of 8 bytes at address 0x0801E0B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801E0F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801E100 performed ok. + Programming of 8 bytes at address 0x0801E108 performed ok. + Programming of 8 bytes at address 0x0801E110 performed ok. + Programming of 8 bytes at address 0x0801E118 performed ok. + Programming of 8 bytes at address 0x0801E120 performed ok. + Programming of 8 bytes at address 0x0801E128 performed ok. + Programming of 8 bytes at address 0x0801E130 performed ok. + Programming of 8 bytes at address 0x0801E138 performed ok. + Programming of 8 bytes at address 0x0801E140 performed ok. + Programming of 8 bytes at address 0x0801E148 performed ok. + Programming of 8 bytes at address 0x0801E150 performed ok. + Programming of 8 bytes at address 0x0801E158 performed ok. + Programming of 8 bytes at address 0x0801E160 performed ok. + Programming of 8 bytes at address 0x0801E168 performed ok. + Programming of 8 bytes at address 0x0801E170 performed ok. + Programming of 8 bytes at address 0x0801E178 performed ok. + Programming of 8 bytes at address 0x0801E180 performed ok. + Programming of 8 bytes at address 0x0801E188 performed ok. + Programming of 8 bytes at address 0x0801E190 performed ok. + Programming of 8 bytes at address 0x0801E198 performed ok. +k. + Programming of 8 bytes at address 0x0801E1A8 performed ok. + Programming of 8 bytes at address 0x0801E1B0 performed ok. + Programming of 8 bytes at address 0x0801E1B8 performed ok. + Programming of 8 bytes at address 0x0801E1C0 performed ok. + Programming of 8 bytes at address 0x0801E1C8 performed ok. + Programming of 8 bytes at address 0x0801E1D0 performed ok. + Programming of 8 bytes at address 0x0801E1D8 performed ok. +k. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801E200 performed ok. + Programming of 8 bytes at address 0x0801E208 performed ok. + Programming of 8 bytes at address 0x0801E210 performed ok. + Programming of 8 bytes at address 0x0801E218 performed ok. + Programming of 8 bytes at address 0x0801E220 performed ok. + Programming of 8 bytes at address 0x0801E228 performed ok. + Programming of 8 bytes at address 0x0801E230 performed ok. + Programming of 8 bytes at address 0x0801E238 performed ok. + Programming of 8 bytes at address 0x0801E240 performed ok. + Programming of 8 bytes at address 0x0801E248 performed ok. + Programming of 8 bytes at address 0x0801E250 performed ok. + Programming of 8 bytes at address 0x0801E258 performed ok. + Programming of 8 bytes at address 0x0801E260 performed ok. + Programming of 8 bytes at address 0x0801E268 performed ok. + Programming of 8 bytes at address 0x0801E270 performed ok. + Programming of 8 bytes at address 0x0801E278 performed ok. + Programming of 8 bytes at address 0x0801E280 performed ok. + Programming of 8 bytes at address 0x0801E288 performed ok. + Programming of 8 bytes at address 0x0801E290 performed ok. + Programming of 8 bytes at address 0x0801E298 performed ok. +k. +k. + Programming of 8 bytes at address 0x0801E2B0 performed ok. + Programming of 8 bytes at address 0x0801E2B8 performed ok. + Programming of 8 bytes at address 0x0801E2C0 performed ok. + Programming of 8 bytes at address 0x0801E2C8 performed ok. + Programming of 8 bytes at address 0x0801E2D0 performed ok. + Programming of 8 bytes at address 0x0801E2D8 performed ok. + Programming of 8 bytes at address 0x0801E2E0 performed ok. +k. +k. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801E300 performed ok. + Programming of 8 bytes at address 0x0801E308 performed ok. + Programming of 8 bytes at address 0x0801E310 performed ok. + Programming of 8 bytes at address 0x0801E318 performed ok. + Programming of 8 bytes at address 0x0801E320 performed ok. + Programming of 8 bytes at address 0x0801E328 performed ok. + Programming of 8 bytes at address 0x0801E330 performed ok. + Programming of 8 bytes at address 0x0801E338 performed ok. + Programming of 8 bytes at address 0x0801E340 performed ok. + Programming of 8 bytes at address 0x0801E348 performed ok. + Programming of 8 bytes at address 0x0801E350 performed ok. + Programming of 8 bytes at address 0x0801E358 performed ok. + Programming of 8 bytes at address 0x0801E360 performed ok. + Programming of 8 bytes at address 0x0801E368 performed ok. + Programming of 8 bytes at address 0x0801E370 performed ok. + Programming of 8 bytes at address 0x0801E378 performed ok. + Programming of 8 bytes at address 0x0801E380 performed ok. + Programming of 8 bytes at address 0x0801E388 performed ok. + Programming of 8 bytes at address 0x0801E390 performed ok. + Programming of 8 bytes at address 0x0801E398 performed ok. + Programming of 8 bytes at address 0x0801E3A0 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801E3C0 performed ok. + Programming of 8 bytes at address 0x0801E3C8 performed ok. + Programming of 8 bytes at address 0x0801E3D0 performed ok. + Programming of 8 bytes at address 0x0801E3D8 performed ok. + Programming of 8 bytes at address 0x0801E3E0 performed ok. + Programming of 8 bytes at address 0x0801E3E8 performed ok. + Programming of 8 bytes at address 0x0801E3F0 performed ok. + Programming of 8 bytes at address 0x0801E3F8 performed ok. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801E400 performed ok. + Programming of 8 bytes at address 0x0801E408 performed ok. + Programming of 8 bytes at address 0x0801E410 performed ok. + Programming of 8 bytes at address 0x0801E418 performed ok. + Programming of 8 bytes at address 0x0801E420 performed ok. + Programming of 8 bytes at address 0x0801E428 performed ok. + Programming of 8 bytes at address 0x0801E430 performed ok. + Programming of 8 bytes at address 0x0801E438 performed ok. + Programming of 8 bytes at address 0x0801E440 performed ok. + Programming of 8 bytes at address 0x0801E448 performed ok. + Programming of 8 bytes at address 0x0801E450 performed ok. + Programming of 8 bytes at address 0x0801E458 performed ok. + Programming of 8 bytes at address 0x0801E460 performed ok. + Programming of 8 bytes at address 0x0801E468 performed ok. + Programming of 8 bytes at address 0x0801E470 performed ok. + Programming of 8 bytes at address 0x0801E478 performed ok. + Programming of 8 bytes at address 0x0801E480 performed ok. + Programming of 8 bytes at address 0x0801E488 performed ok. + Programming of 8 bytes at address 0x0801E490 performed ok. + Programming of 8 bytes at address 0x0801E498 performed ok. + Programming of 8 bytes at address 0x0801E4A0 performed ok. + Programming of 8 bytes at address 0x0801E4A8 performed ok. + Programming of 8 bytes at address 0x0801E4B0 performed ok. + Programming of 8 bytes at address 0x0801E4B8 performed ok. + Programming of 8 bytes at address 0x0801E4C0 performed ok. +k. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801E500 performed ok. + Programming of 8 bytes at address 0x0801E508 performed ok. + Programming of 8 bytes at address 0x0801E510 performed ok. + Programming of 8 bytes at address 0x0801E518 performed ok. + Programming of 8 bytes at address 0x0801E520 performed ok. + Programming of 8 bytes at address 0x0801E528 performed ok. + Programming of 8 bytes at address 0x0801E530 performed ok. + Programming of 8 bytes at address 0x0801E538 performed ok. + Programming of 8 bytes at address 0x0801E540 performed ok. + Programming of 8 bytes at address 0x0801E548 performed ok. + Programming of 8 bytes at address 0x0801E550 performed ok. + Programming of 8 bytes at address 0x0801E558 performed ok. + Programming of 8 bytes at address 0x0801E560 performed ok. + Programming of 8 bytes at address 0x0801E568 performed ok. + Programming of 8 bytes at address 0x0801E570 performed ok. + Programming of 8 bytes at address 0x0801E578 performed ok. + Programming of 8 bytes at address 0x0801E580 performed ok. + Programming of 8 bytes at address 0x0801E588 performed ok. + Programming of 8 bytes at address 0x0801E590 performed ok. + Programming of 8 bytes at address 0x0801E598 performed ok. + Programming of 8 bytes at address 0x0801E5A0 performed ok. + Programming of 8 bytes at address 0x0801E5A8 performed ok. + Programming of 8 bytes at address 0x0801E5B0 performed ok. + Programming of 8 bytes at address 0x0801E5B8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801E5F0 performed ok. + Programming of 8 bytes at address 0x0801E5F8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801E600 performed ok. + Programming of 8 bytes at address 0x0801E608 performed ok. + Programming of 8 bytes at address 0x0801E610 performed ok. + Programming of 8 bytes at address 0x0801E618 performed ok. + Programming of 8 bytes at address 0x0801E620 performed ok. + Programming of 8 bytes at address 0x0801E628 performed ok. + Programming of 8 bytes at address 0x0801E630 performed ok. + Programming of 8 bytes at address 0x0801E638 performed ok. + Programming of 8 bytes at address 0x0801E640 performed ok. + Programming of 8 bytes at address 0x0801E648 performed ok. + Programming of 8 bytes at address 0x0801E650 performed ok. + Programming of 8 bytes at address 0x0801E658 performed ok. + Programming of 8 bytes at address 0x0801E660 performed ok. + Programming of 8 bytes at address 0x0801E668 performed ok. + Programming of 8 bytes at address 0x0801E670 performed ok. + Programming of 8 bytes at address 0x0801E678 performed ok. + Programming of 8 bytes at address 0x0801E680 performed ok. + Programming of 8 bytes at address 0x0801E688 performed ok. + Programming of 8 bytes at address 0x0801E690 performed ok. + Programming of 8 bytes at address 0x0801E698 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801E6B8 performed ok. + Programming of 8 bytes at address 0x0801E6C0 performed ok. + Programming of 8 bytes at address 0x0801E6C8 performed ok. + Programming of 8 bytes at address 0x0801E6D0 performed ok. + Programming of 8 bytes at address 0x0801E6D8 performed ok. + Programming of 8 bytes at address 0x0801E6E0 performed ok. + Programming of 8 bytes at address 0x0801E6E8 performed ok. + Programming of 8 bytes at address 0x0801E6F0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801E700 performed ok. + Programming of 8 bytes at address 0x0801E708 performed ok. + Programming of 8 bytes at address 0x0801E710 performed ok. + Programming of 8 bytes at address 0x0801E718 performed ok. + Programming of 8 bytes at address 0x0801E720 performed ok. + Programming of 8 bytes at address 0x0801E728 performed ok. + Programming of 8 bytes at address 0x0801E730 performed ok. + Programming of 8 bytes at address 0x0801E738 performed ok. + Programming of 8 bytes at address 0x0801E740 performed ok. + Programming of 8 bytes at address 0x0801E748 performed ok. + Programming of 8 bytes at address 0x0801E750 performed ok. + Programming of 8 bytes at address 0x0801E758 performed ok. + Programming of 8 bytes at address 0x0801E760 performed ok. + Programming of 8 bytes at address 0x0801E768 performed ok. + Programming of 8 bytes at address 0x0801E770 performed ok. + Programming of 8 bytes at address 0x0801E778 performed ok. + Programming of 8 bytes at address 0x0801E780 performed ok. + Programming of 8 bytes at address 0x0801E788 performed ok. + Programming of 8 bytes at address 0x0801E790 performed ok. +k. + Programming of 8 bytes at address 0x0801E7A0 performed ok. + Programming of 8 bytes at address 0x0801E7A8 performed ok. + Programming of 8 bytes at address 0x0801E7B0 performed ok. + Programming of 8 bytes at address 0x0801E7B8 performed ok. + Programming of 8 bytes at address 0x0801E7C0 performed ok. + Programming of 8 bytes at address 0x0801E7C8 performed ok. + Programming of 8 bytes at address 0x0801E7D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801E800 performed ok. + Programming of 8 bytes at address 0x0801E808 performed ok. + Programming of 8 bytes at address 0x0801E810 performed ok. + Programming of 8 bytes at address 0x0801E818 performed ok. + Programming of 8 bytes at address 0x0801E820 performed ok. + Programming of 8 bytes at address 0x0801E828 performed ok. + Programming of 8 bytes at address 0x0801E830 performed ok. + Programming of 8 bytes at address 0x0801E838 performed ok. + Programming of 8 bytes at address 0x0801E840 performed ok. + Programming of 8 bytes at address 0x0801E848 performed ok. + Programming of 8 bytes at address 0x0801E850 performed ok. + Programming of 8 bytes at address 0x0801E858 performed ok. + Programming of 8 bytes at address 0x0801E860 performed ok. + Programming of 8 bytes at address 0x0801E868 performed ok. + Programming of 8 bytes at address 0x0801E870 performed ok. + Programming of 8 bytes at address 0x0801E878 performed ok. + Programming of 8 bytes at address 0x0801E880 performed ok. + Programming of 8 bytes at address 0x0801E888 performed ok. +k. + Programming of 8 bytes at address 0x0801E898 performed ok. + Programming of 8 bytes at address 0x0801E8A0 performed ok. + Programming of 8 bytes at address 0x0801E8A8 performed ok. + Programming of 8 bytes at address 0x0801E8B0 performed ok. + Programming of 8 bytes at address 0x0801E8B8 performed ok. + Programming of 8 bytes at address 0x0801E8C0 performed ok. + Programming of 8 bytes at address 0x0801E8C8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801E900 performed ok. + Programming of 8 bytes at address 0x0801E908 performed ok. + Programming of 8 bytes at address 0x0801E910 performed ok. + Programming of 8 bytes at address 0x0801E918 performed ok. + Programming of 8 bytes at address 0x0801E920 performed ok. + Programming of 8 bytes at address 0x0801E928 performed ok. + Programming of 8 bytes at address 0x0801E930 performed ok. + Programming of 8 bytes at address 0x0801E938 performed ok. + Programming of 8 bytes at address 0x0801E940 performed ok. + Programming of 8 bytes at address 0x0801E948 performed ok. + Programming of 8 bytes at address 0x0801E950 performed ok. + Programming of 8 bytes at address 0x0801E958 performed ok. + Programming of 8 bytes at address 0x0801E960 performed ok. + Programming of 8 bytes at address 0x0801E968 performed ok. + Programming of 8 bytes at address 0x0801E970 performed ok. + Programming of 8 bytes at address 0x0801E978 performed ok. + Programming of 8 bytes at address 0x0801E980 performed ok. + Programming of 8 bytes at address 0x0801E988 performed ok. + Programming of 8 bytes at address 0x0801E990 performed ok. +k. + Programming of 8 bytes at address 0x0801E9A0 performed ok. + Programming of 8 bytes at address 0x0801E9A8 performed ok. + Programming of 8 bytes at address 0x0801E9B0 performed ok. + Programming of 8 bytes at address 0x0801E9B8 performed ok. + Programming of 8 bytes at address 0x0801E9C0 performed ok. + Programming of 8 bytes at address 0x0801E9C8 performed ok. + Programming of 8 bytes at address 0x0801E9D0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801EA00 performed ok. + Programming of 8 bytes at address 0x0801EA08 performed ok. + Programming of 8 bytes at address 0x0801EA10 performed ok. + Programming of 8 bytes at address 0x0801EA18 performed ok. + Programming of 8 bytes at address 0x0801EA20 performed ok. + Programming of 8 bytes at address 0x0801EA28 performed ok. + Programming of 8 bytes at address 0x0801EA30 performed ok. + Programming of 8 bytes at address 0x0801EA38 performed ok. + Programming of 8 bytes at address 0x0801EA40 performed ok. + Programming of 8 bytes at address 0x0801EA48 performed ok. + Programming of 8 bytes at address 0x0801EA50 performed ok. + Programming of 8 bytes at address 0x0801EA58 performed ok. + Programming of 8 bytes at address 0x0801EA60 performed ok. + Programming of 8 bytes at address 0x0801EA68 performed ok. + Programming of 8 bytes at address 0x0801EA70 performed ok. + Programming of 8 bytes at address 0x0801EA78 performed ok. + Programming of 8 bytes at address 0x0801EA80 performed ok. + Programming of 8 bytes at address 0x0801EA88 performed ok. + Programming of 8 bytes at address 0x0801EA90 performed ok. + Programming of 8 bytes at address 0x0801EA98 performed ok. + Programming of 8 bytes at address 0x0801EAA0 performed ok. + Programming of 8 bytes at address 0x0801EAA8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801EAE0 performed ok. + Programming of 8 bytes at address 0x0801EAE8 performed ok. + Programming of 8 bytes at address 0x0801EAF0 performed ok. + Programming of 8 bytes at address 0x0801EAF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801EB00 performed ok. + Programming of 8 bytes at address 0x0801EB08 performed ok. + Programming of 8 bytes at address 0x0801EB10 performed ok. + Programming of 8 bytes at address 0x0801EB18 performed ok. + Programming of 8 bytes at address 0x0801EB20 performed ok. + Programming of 8 bytes at address 0x0801EB28 performed ok. + Programming of 8 bytes at address 0x0801EB30 performed ok. + Programming of 8 bytes at address 0x0801EB38 performed ok. + Programming of 8 bytes at address 0x0801EB40 performed ok. + Programming of 8 bytes at address 0x0801EB48 performed ok. + Programming of 8 bytes at address 0x0801EB50 performed ok. + Programming of 8 bytes at address 0x0801EB58 performed ok. + Programming of 8 bytes at address 0x0801EB60 performed ok. + Programming of 8 bytes at address 0x0801EB68 performed ok. + Programming of 8 bytes at address 0x0801EB70 performed ok. + Programming of 8 bytes at address 0x0801EB78 performed ok. + Programming of 8 bytes at address 0x0801EB80 performed ok. + Programming of 8 bytes at address 0x0801EB88 performed ok. + Programming of 8 bytes at address 0x0801EB90 performed ok. + Programming of 8 bytes at address 0x0801EB98 performed ok. +k. +k. +k. + Programming of 8 bytes at address 0x0801EBB8 performed ok. + Programming of 8 bytes at address 0x0801EBC0 performed ok. + Programming of 8 bytes at address 0x0801EBC8 performed ok. + Programming of 8 bytes at address 0x0801EBD0 performed ok. + Programming of 8 bytes at address 0x0801EBD8 performed ok. + Programming of 8 bytes at address 0x0801EBE0 performed ok. + Programming of 8 bytes at address 0x0801EBE8 performed ok. + Programming of 8 bytes at address 0x0801EBF0 performed ok. +k. +79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801EC00 performed ok. + Programming of 8 bytes at address 0x0801EC08 performed ok. + Programming of 8 bytes at address 0x0801EC10 performed ok. + Programming of 8 bytes at address 0x0801EC18 performed ok. + Programming of 8 bytes at address 0x0801EC20 performed ok. + Programming of 8 bytes at address 0x0801EC28 performed ok. + Programming of 8 bytes at address 0x0801EC30 performed ok. + Programming of 8 bytes at address 0x0801EC38 performed ok. + Programming of 8 bytes at address 0x0801EC40 performed ok. + Programming of 8 bytes at address 0x0801EC48 performed ok. + Programming of 8 bytes at address 0x0801EC50 performed ok. + Programming of 8 bytes at address 0x0801EC58 performed ok. + Programming of 8 bytes at address 0x0801EC60 performed ok. + Programming of 8 bytes at address 0x0801EC68 performed ok. + Programming of 8 bytes at address 0x0801EC70 performed ok. + Programming of 8 bytes at address 0x0801EC78 performed ok. + Programming of 8 bytes at address 0x0801EC80 performed ok. + Programming of 8 bytes at address 0x0801EC88 performed ok. + Programming of 8 bytes at address 0x0801EC90 performed ok. +k. + Programming of 8 bytes at address 0x0801ECA0 performed ok. + Programming of 8 bytes at address 0x0801ECA8 performed ok. + Programming of 8 bytes at address 0x0801ECB0 performed ok. + Programming of 8 bytes at address 0x0801ECB8 performed ok. + Programming of 8 bytes at address 0x0801ECC0 performed ok. + Programming of 8 bytes at address 0x0801ECC8 performed ok. + Programming of 8 bytes at address 0x0801ECD0 performed ok. +k. +k. +k. +k. +k. +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801ED00 performed ok. + Programming of 8 bytes at address 0x0801ED08 performed ok. + Programming of 8 bytes at address 0x0801ED10 performed ok. + Programming of 8 bytes at address 0x0801ED18 performed ok. + Programming of 8 bytes at address 0x0801ED20 performed ok. + Programming of 8 bytes at address 0x0801ED28 performed ok. + Programming of 8 bytes at address 0x0801ED30 performed ok. + Programming of 8 bytes at address 0x0801ED38 performed ok. + Programming of 8 bytes at address 0x0801ED40 performed ok. + Programming of 8 bytes at address 0x0801ED48 performed ok. + Programming of 8 bytes at address 0x0801ED50 performed ok. + Programming of 8 bytes at address 0x0801ED58 performed ok. + Programming of 8 bytes at address 0x0801ED60 performed ok. + Programming of 8 bytes at address 0x0801ED68 performed ok. + Programming of 8 bytes at address 0x0801ED70 performed ok. + Programming of 8 bytes at address 0x0801ED78 performed ok. + Programming of 8 bytes at address 0x0801ED80 performed ok. + Programming of 8 bytes at address 0x0801ED88 performed ok. + Programming of 8 bytes at address 0x0801ED90 performed ok. + Programming of 8 bytes at address 0x0801ED98 performed ok. + Programming of 8 bytes at address 0x0801EDA0 performed ok. + Programming of 8 bytes at address 0x0801EDA8 performed ok. + Programming of 8 bytes at address 0x0801EDB0 performed ok. + Programming of 8 bytes at address 0x0801EDB8 performed ok. +k. +k. +k. +k. +k. +k. + Programming of 8 bytes at address 0x0801EDF0 performed ok. + Programming of 8 bytes at address 0x0801EDF8 performed ok. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801EE00 performed ok. + Programming of 8 bytes at address 0x0801EE08 performed ok. + Programming of 8 bytes at address 0x0801EE10 performed ok. + Programming of 8 bytes at address 0x0801EE18 performed ok. + Programming of 8 bytes at address 0x0801EE20 performed ok. + Programming of 8 bytes at address 0x0801EE28 performed ok. + Programming of 8 bytes at address 0x0801EE30 performed ok. + Programming of 8 bytes at address 0x0801EE38 performed ok. + Programming of 8 bytes at address 0x0801EE40 performed ok. + Programming of 8 bytes at address 0x0801EE48 performed ok. + Programming of 8 bytes at address 0x0801EE50 performed ok. + Programming of 8 bytes at address 0x0801EE58 performed ok. + Programming of 8 bytes at address 0x0801EE60 performed ok. + Programming of 8 bytes at address 0x0801EE68 performed ok. + Programming of 8 bytes at address 0x0801EE70 performed ok. + Programming of 8 bytes at address 0x0801EE78 performed ok. + Programming of 8 bytes at address 0x0801EE80 performed ok. + Programming of 8 bytes at address 0x0801EE88 performed ok. + Programming of 8 bytes at address 0x0801EE90 performed ok. + Programming of 8 bytes at address 0x0801EE98 performed ok. + Programming of 8 bytes at address 0x0801EEA0 performed ok. + Programming of 8 bytes at address 0x0801EEA8 performed ok. + Programming of 8 bytes at address 0x0801EEB0 performed ok. + Programming of 8 bytes at address 0x0801EEB8 performed ok. +k. +k. +k. +k. +k. +k. + Sending 1 bytes: 79 +Got WRITE MEMORY command. + Sending 1 bytes: 79 + Sending 1 bytes: 79 + Decrypting 256 bytes... Starting programming of 256 bytes. + Programming of 8 bytes at address 0x0801EF00 performed ok. + Programming of 8 bytes at address 0x0801EF08 performed ok. + Programming of 8 bytes at address 0x0801EF10 performed ok. + Programming of 8 bytes at address 0x0801EF18 performed ok. + Programming of 8 bytes at address 0x0801EF20 performed ok. + Programming of 8 bytes at address 0x0801EF28 performed ok. + Programming of 8 bytes at address 0x0801EF30 performed ok. + Programming of 8 bytes at address 0x0801EF38 performed ok. + Programming of 8 bytes at address 0x0801EF40 performed ok. + Programming of 8 bytes at address 0x0801EF48 performed ok. + Programming of 8 bytes at address 0x0801EF50 performed ok. + Programming of 8 bytes at address 0x0801EF58 performed ok. + Programming of 8 bytes at address 0x0801EF60 performed ok. + Programming of 8 bytes at address 0x0801EF68 performed ok. + Programming of 8 bytes at address 0x0801EF70 performed ok. + Programming of 8 bytes at address 0x0801EF78 performed ok. + Programming of 8 bytes at address 0x0801EF80 performed ok. + Programming of 8 bytes at address 0x0801EF88 performed ok. + Programming of 8 bytes at address 0x0801EF90 performed ok. +k. + Programming of 8 bytes at address 0x0801EFA0 performed ok. + Programming of 8 bytes at address 0x0801EFA8 performed ok. + Programming of 8 bytes at address 0x0801EFB0 performed ok. + Programming of 8 bytes at address 0x0801EFB8 performed ok. + Programming of 8 bytes at address 0x0801EFC0 performed ok. + Programming of 8 bytes at address 0x0801EFC8 performed ok. + Programming of 8 bytes at address 0x0801EFD0 performed ok. +k. +k. +k. +k. +k. + +Waiting 10s for communication initialization... + +Timeout of 10s! +Starting calculating FW CRC + + Address: 0x08003000 + Address: 0x08003004 + Address: 0x08003008 + Address: 0x0800300C + Address: 0x08003010 + Address: 0x08003014 + Address: 0x08003018 + Address: 0x0800301C + Address: 0x08003020 + Address: 0x08003024 + Address: 0x08003028 + Address: 0x0800302C + Address: 0x08003030 + Address: 0x08003034 + Address: 0x08003038 + Address: 0x0800303C + Address: 0x08003040 + Address: 0x08003044 + Address: 0x08003048 + Address: 0x0800304C + Address: 0x08003050 + Address: 0x08003054 + Address: 0x08003058 + Address: 0x0800305C + Address: 0x08003060 + Address: 0x08003064 + Address: 0x08003068 + Address: 0x0800306C + Address: 0x08003070 + Address: 0x08003074 + Address: 0x08003078 + Address: 0x0800307C + Address: 0x08003080 + Address: 0x08003084 + Address: 0x08003088 + Address: 0x0800308C + Address: 0x08003090 + Address: 0x08003094 + Address: 0x08003098 + Address: 0x0800309C + Address: 0x080030A0 + Address: 0x080030A4 + Address: 0x080030A8 + Address: 0x080030AC + Address: 0x080030B0 + Address: 0x080030B4 + Address: 0x080030B8 + Address: 0x080030BC + Address: 0x080030C0 + Address: 0x080030C4 + Address: 0x080030C8 + Address: 0x080030CC + Address: 0x080030D0 + Address: 0x080030D4 + Address: 0x080030D8 + Address: 0x080030DC + Address: 0x080030E0 + Address: 0x080030F0 + Address: 0x080030F4 + Address: 0x080030F8 + Address: 0x080030FC + Address: 0x08003100 + Address: 0x08003104 + Address: 0x08003108 + Address: 0x0800310C + Address: 0x08003110 + Address: 0x08003114 + Address: 0x08003118 + Address: 0x0800311C + Address: 0x08003120 + Address: 0x08003124 + Address: 0x08003128 + Address: 0x0800312C + Address: 0x08003130 + Address: 0x08003134 + Address: 0x08003150 + Address: 0x08003154 + Address: 0x08003158 + Address: 0x0800315C + Address: 0x08003160 + Address: 0x08003164 + Address: 0x08003168 + Address: 0x0800316C + Address: 0x08003170 + Address: 0x08003174 + Address: 0x08003178 + Address: 0x0800317C + Address: 0x08003180 + Address: 0x08003184 + Address: 0x08003188 + Address: 0x0800318C + Address: 0x08003190 + Address: 0x08003194 + Address: 0x08003198 + Address: 0x0800319C + Address: 0x080031AC + Address: 0x080031B0 + Address: 0x080031B4 + Address: 0x080031B8 + Address: 0x080031BC + Address: 0x080031C0 + Address: 0x080031C4 + Address: 0x080031C8 + Address: 0x080031CC + Address: 0x080031D0 + Address: 0x080031D4 + Address: 0x080031D8 + Address: 0x080031DC + Address: 0x080031E0 + Address: 0x080031E4 + Address: 0x080031E8 + Address: 0x080031EC + Address: 0x080031F0 + Address: 0x0800320C + Address: 0x08003210 + Address: 0x08003214 + Address: 0x08003218 + Address: 0x0800321C + Address: 0x08003220 + Address: 0x08003224 + Address: 0x08003228 + Address: 0x0800322C + Address: 0x08003230 + Address: 0x08003234 + Address: 0x08003238 + Address: 0x0800323C + Address: 0x08003240 + Address: 0x08003244 + Address: 0x08003248 + Address: 0x0800324C + Address: 0x08003250 + Address: 0x08003254 + Address: 0x08003258 + Address: 0x08003260 + Address: 0x08003264 + Address: 0x08003268 + Address: 0x0800326C + Address: 0x08003270 + Address: 0x08003274 + Address: 0x08003278 + Address: 0x0800327C + Address: 0x08003280 + Address: 0x08003284 + Address: 0x08003288 + Address: 0x0800328C + Address: 0x08003290 + Address: 0x08003294 + Address: 0x08003298 + Address: 0x0800329C + Address: 0x080032A0 + Address: 0x080032C8 + Address: 0x080032CC + Address: 0x080032D0 + Address: 0x080032D4 + Address: 0x080032D8 + Address: 0x080032DC + Address: 0x080032E0 + Address: 0x080032E4 + Address: 0x080032E8 + Address: 0x080032EC + Address: 0x080032F0 + Address: 0x080032F4 + Address: 0x080032F8 + Address: 0x080032FC + Address: 0x08003300 + Address: 0x08003304 + Address: 0x08003308 + Address: 0x0800330C + Address: 0x08003310 + Address: 0x08003314 + Address: 0x08003318 + Address: 0x08003324 + Address: 0x08003328 + Address: 0x0800332C + Address: 0x08003330 + Address: 0x08003334 + Address: 0x08003338 + Address: 0x0800333C + Address: 0x08003340 + Address: 0x08003344 + Address: 0x08003348 + Address: 0x0800334C + Address: 0x08003350 + Address: 0x08003354 + Address: 0x08003358 + Address: 0x0800335C + Address: 0x08003360 + Address: 0x08003364 + Address: 0x08003368 + Address: 0x08003388 + Address: 0x0800338C + Address: 0x08003390 + Address: 0x08003394 + Address: 0x08003398 + Address: 0x0800339C + Address: 0x080033A0 + Address: 0x080033A4 + Address: 0x080033A8 + Address: 0x080033AC + Address: 0x080033B0 + Address: 0x080033B4 + Address: 0x080033B8 + Address: 0x080033BC + Address: 0x080033C0 + Address: 0x080033C4 + Address: 0x080033C8 + Address: 0x080033CC + Address: 0x080033D0 + Address: 0x080033D4 + Address: 0x080033E0 + Address: 0x080033E4 + Address: 0x080033E8 + Address: 0x080033EC + Address: 0x080033F0 + Address: 0x080033F4 + Address: 0x080033F8 + Address: 0x080033FC + Address: 0x08003400 + Address: 0x08003404 + Address: 0x08003408 + Address: 0x0800340C + Address: 0x08003410 + Address: 0x08003414 + Address: 0x08003418 + Address: 0x0800341C + Address: 0x08003420 + Address: 0x08003424 + Address: 0x0800343C + Address: 0x08003440 + Address: 0x08003444 + Address: 0x08003448 + Address: 0x0800344C + Address: 0x08003450 + Address: 0x08003454 + Address: 0x08003458 + Address: 0x0800345C + Address: 0x08003460 + Address: 0x08003464 + Address: 0x08003468 + Address: 0x0800346C + Address: 0x08003470 + Address: 0x08003474 + Address: 0x08003478 + Address: 0x0800347C + Address: 0x08003480 + Address: 0x08003484 + Address: 0x0800349C + Address: 0x080034A0 + Address: 0x080034A4 + Address: 0x080034A8 + Address: 0x080034AC + Address: 0x080034B0 + Address: 0x080034B4 + Address: 0x080034B8 + Address: 0x080034BC + Address: 0x080034C0 + Address: 0x080034C4 + Address: 0x080034C8 + Address: 0x080034CC + Address: 0x080034D0 + Address: 0x080034D4 + Address: 0x080034D8 + Address: 0x080034DC + Address: 0x080034E0 + Address: 0x080034E4 + Address: 0x080034FC + Address: 0x08003500 + Address: 0x08003504 + Address: 0x08003508 + Address: 0x0800350C + Address: 0x08003510 + Address: 0x08003514 + Address: 0x08003518 + Address: 0x0800351C + Address: 0x08003520 + Address: 0x08003524 + Address: 0x08003528 + Address: 0x0800352C + Address: 0x08003530 + Address: 0x08003534 + Address: 0x08003538 + Address: 0x0800353C + Address: 0x08003540 + Address: 0x08003544 + Address: 0x08003558 + Address: 0x0800355C + Address: 0x08003560 + Address: 0x08003564 + Address: 0x08003568 + Address: 0x0800356C + Address: 0x08003570 + Address: 0x08003574 + Address: 0x08003578 + Address: 0x0800357C + Address: 0x08003580 + Address: 0x08003584 + Address: 0x08003588 + Address: 0x0800358C + Address: 0x08003590 + Address: 0x08003594 + Address: 0x08003598 + Address: 0x0800359C + Address: 0x080035A0 + Address: 0x080035B0 + Address: 0x080035B4 + Address: 0x080035B8 + Address: 0x080035BC + Address: 0x080035C0 + Address: 0x080035C4 + Address: 0x080035C8 + Address: 0x080035CC + Address: 0x080035D0 + Address: 0x080035D4 + Address: 0x080035D8 + Address: 0x080035DC + Address: 0x080035E0 + Address: 0x080035E4 + Address: 0x080035E8 + Address: 0x080035EC + Address: 0x080035F0 + Address: 0x080035F4 + Address: 0x08003614 + Address: 0x08003618 + Address: 0x0800361C + Address: 0x08003620 + Address: 0x08003624 + Address: 0x08003628 + Address: 0x0800362C + Address: 0x08003630 + Address: 0x08003634 + Address: 0x08003638 + Address: 0x0800363C + Address: 0x08003640 + Address: 0x08003644 + Address: 0x08003648 + Address: 0x0800364C + Address: 0x08003650 + Address: 0x08003654 + Address: 0x08003658 + Address: 0x0800365C + Address: 0x08003660 + Address: 0x08003670 + Address: 0x08003674 + Address: 0x08003678 + Address: 0x0800367C + Address: 0x08003680 + Address: 0x08003684 + Address: 0x08003688 + Address: 0x0800368C + Address: 0x08003690 + Address: 0x08003694 + Address: 0x08003698 + Address: 0x0800369C + Address: 0x080036A0 + Address: 0x080036A4 + Address: 0x080036A8 + Address: 0x080036AC + Address: 0x080036B0 + Address: 0x080036B4 + Address: 0x080036CC + Address: 0x080036D0 + Address: 0x080036D4 + Address: 0x080036D8 + Address: 0x080036DC + Address: 0x080036E0 + Address: 0x080036E4 + Address: 0x080036E8 + Address: 0x080036EC + Address: 0x080036F0 + Address: 0x080036F4 + Address: 0x080036F8 + Address: 0x080036FC + Address: 0x08003700 + Address: 0x08003704 + Address: 0x08003708 + Address: 0x0800370C + Address: 0x08003710 + Address: 0x08003714 + Address: 0x08003724 + Address: 0x08003728 + Address: 0x0800372C + Address: 0x08003730 + Address: 0x08003734 + Address: 0x08003738 + Address: 0x0800373C + Address: 0x08003740 + Address: 0x08003744 + Address: 0x08003748 + Address: 0x0800374C + Address: 0x08003750 + Address: 0x08003754 + Address: 0x08003758 + Address: 0x0800375C + Address: 0x08003760 + Address: 0x08003764 + Address: 0x08003768 + Address: 0x08003788 + Address: 0x0800378C + Address: 0x08003790 + Address: 0x08003794 + Address: 0x08003798 + Address: 0x0800379C + Address: 0x080037A0 + Address: 0x080037A4 + Address: 0x080037A8 + Address: 0x080037AC + Address: 0x080037B0 + Address: 0x080037B4 + Address: 0x080037B8 + Address: 0x080037BC + Address: 0x080037C0 + Address: 0x080037C4 + Address: 0x080037C8 + Address: 0x080037CC + Address: 0x080037D0 + Address: 0x080037D4 + Address: 0x080037E4 + Address: 0x080037E8 + Address: 0x080037EC + Address: 0x080037F0 + Address: 0x080037F4 + Address: 0x080037F8 + Address: 0x080037FC + Address: 0x08003800 + Address: 0x08003804 + Address: 0x08003808 + Address: 0x0800380C + Address: 0x08003810 + Address: 0x08003814 + Address: 0x08003818 + Address: 0x0800381C + Address: 0x08003820 + Address: 0x08003824 + Address: 0x08003828 + Address: 0x08003848 + Address: 0x0800384C + Address: 0x08003850 + Address: 0x08003854 + Address: 0x08003858 + Address: 0x0800385C + Address: 0x08003860 + Address: 0x08003864 + Address: 0x08003868 + Address: 0x0800386C + Address: 0x08003870 + Address: 0x08003874 + Address: 0x08003878 + Address: 0x0800387C + Address: 0x08003880 + Address: 0x08003884 + Address: 0x08003888 + Address: 0x0800388C + Address: 0x08003890 + Address: 0x08003894 + Address: 0x08003898 + Address: 0x0800389C + Address: 0x080038A0 + Address: 0x080038A4 + Address: 0x080038A8 + Address: 0x080038AC + Address: 0x080038B0 + Address: 0x080038B4 + Address: 0x080038B8 + Address: 0x080038BC + Address: 0x080038C0 + Address: 0x080038C4 + Address: 0x080038C8 + Address: 0x080038CC + Address: 0x080038D0 + Address: 0x080038D4 + Address: 0x080038D8 + Address: 0x08003900 + Address: 0x08003904 + Address: 0x08003908 + Address: 0x0800390C + Address: 0x08003910 + Address: 0x08003914 + Address: 0x08003918 + Address: 0x0800391C + Address: 0x08003920 + Address: 0x08003924 + Address: 0x08003928 + Address: 0x0800392C + Address: 0x08003930 + Address: 0x08003934 + Address: 0x08003938 + Address: 0x0800393C + Address: 0x08003940 + Address: 0x08003944 + Address: 0x08003948 + Address: 0x0800394C + Address: 0x08003950 + Address: 0x08003958 + Address: 0x0800395C + Address: 0x08003960 + Address: 0x08003964 + Address: 0x08003968 + Address: 0x0800396C + Address: 0x08003970 + Address: 0x08003974 + Address: 0x08003978 + Address: 0x0800397C + Address: 0x08003980 + Address: 0x08003984 + Address: 0x08003988 + Address: 0x0800398C + Address: 0x08003990 + Address: 0x08003994 + Address: 0x08003998 + Address: 0x080039C0 + Address: 0x080039C4 + Address: 0x080039C8 + Address: 0x080039CC + Address: 0x080039D0 + Address: 0x080039D4 + Address: 0x080039D8 + Address: 0x080039DC + Address: 0x080039E0 + Address: 0x080039E4 + Address: 0x080039E8 + Address: 0x080039EC + Address: 0x080039F0 + Address: 0x080039F4 + Address: 0x080039F8 + Address: 0x080039FC + Address: 0x08003A00 + Address: 0x08003A04 + Address: 0x08003A08 + Address: 0x08003A0C + Address: 0x08003A10 + Address: 0x08003A14 + Address: 0x08003A18 + Address: 0x08003A1C + Address: 0x08003A20 + Address: 0x08003A24 + Address: 0x08003A28 + Address: 0x08003A2C + Address: 0x08003A30 + Address: 0x08003A34 + Address: 0x08003A38 + Address: 0x08003A3C + Address: 0x08003A40 + Address: 0x08003A44 + Address: 0x08003A48 + Address: 0x08003A4C + Address: 0x08003A50 + Address: 0x08003A78 + Address: 0x08003A7C + Address: 0x08003A80 + Address: 0x08003A84 + Address: 0x08003A88 + Address: 0x08003A8C + Address: 0x08003A90 + Address: 0x08003A94 + Address: 0x08003A98 + Address: 0x08003A9C + Address: 0x08003AA0 + Address: 0x08003AA4 + Address: 0x08003AA8 + Address: 0x08003AAC + Address: 0x08003AB0 + Address: 0x08003AB4 + Address: 0x08003AB8 + Address: 0x08003ABC + Address: 0x08003AC0 + Address: 0x08003AC4 + Address: 0x08003AC8 + Address: 0x08003ACC + Address: 0x08003AD0 + Address: 0x08003AD4 + Address: 0x08003AD8 + Address: 0x08003ADC + Address: 0x08003AE0 + Address: 0x08003AE4 + Address: 0x08003AE8 + Address: 0x08003AEC + Address: 0x08003AF0 + Address: 0x08003AF4 + Address: 0x08003AF8 + Address: 0x08003AFC + Address: 0x08003B00 + Address: 0x08003B04 + Address: 0x08003B08 + Address: 0x08003B0C + Address: 0x08003B34 + Address: 0x08003B38 + Address: 0x08003B3C + Address: 0x08003B40 + Address: 0x08003B44 + Address: 0x08003B48 + Address: 0x08003B4C + Address: 0x08003B50 + Address: 0x08003B54 + Address: 0x08003B58 + Address: 0x08003B5C + Address: 0x08003B60 + Address: 0x08003B64 + Address: 0x08003B68 + Address: 0x08003B6C + Address: 0x08003B70 + Address: 0x08003B74 + Address: 0x08003B78 + Address: 0x08003B7C + Address: 0x08003B80 + Address: 0x08003B84 + Address: 0x08003B88 + Address: 0x08003B8C + Address: 0x08003B90 + Address: 0x08003B94 + Address: 0x08003B98 + Address: 0x08003B9C + Address: 0x08003BA0 + Address: 0x08003BA4 + Address: 0x08003BA8 + Address: 0x08003BAC + Address: 0x08003BB0 + Address: 0x08003BB4 + Address: 0x08003BB8 + Address: 0x08003BBC + Address: 0x08003BC0 + Address: 0x08003BC4 + Address: 0x08003BEC + Address: 0x08003BF0 + Address: 0x08003BF4 + Address: 0x08003BF8 + Address: 0x08003BFC + Address: 0x08003C00 + Address: 0x08003C04 + Address: 0x08003C08 + Address: 0x08003C0C + Address: 0x08003C10 + Address: 0x08003C14 + Address: 0x08003C18 + Address: 0x08003C1C + Address: 0x08003C20 + Address: 0x08003C24 + Address: 0x08003C28 + Address: 0x08003C2C + Address: 0x08003C30 + Address: 0x08003C34 + Address: 0x08003C38 + Address: 0x08003C3C + Address: 0x08003C44 + Address: 0x08003C48 + Address: 0x08003C4C + Address: 0x08003C50 + Address: 0x08003C54 + Address: 0x08003C58 + Address: 0x08003C5C + Address: 0x08003C60 + Address: 0x08003C64 + Address: 0x08003C68 + Address: 0x08003C6C + Address: 0x08003C70 + Address: 0x08003C74 + Address: 0x08003C78 + Address: 0x08003C7C + Address: 0x08003C80 + Address: 0x08003C84 + Address: 0x08003CA4 + Address: 0x08003CA8 + Address: 0x08003CAC + Address: 0x08003CB0 + Address: 0x08003CB4 + Address: 0x08003CB8 + Address: 0x08003CBC + Address: 0x08003CC0 + Address: 0x08003CC4 + Address: 0x08003CC8 + Address: 0x08003CCC + Address: 0x08003CD0 + Address: 0x08003CD4 + Address: 0x08003CD8 + Address: 0x08003CDC + Address: 0x08003CE0 + Address: 0x08003CE4 + Address: 0x08003CE8 + Address: 0x08003CEC + Address: 0x08003CF0 + Address: 0x08003CF4 + Address: 0x08003CF8 + Address: 0x08003CFC + Address: 0x08003D00 + Address: 0x08003D04 + Address: 0x08003D08 + Address: 0x08003D0C + Address: 0x08003D10 + Address: 0x08003D14 + Address: 0x08003D18 + Address: 0x08003D1C + Address: 0x08003D20 + Address: 0x08003D24 + Address: 0x08003D28 + Address: 0x08003D2C + Address: 0x08003D30 + Address: 0x08003D34 + Address: 0x08003D60 + Address: 0x08003D64 + Address: 0x08003D68 + Address: 0x08003D6C + Address: 0x08003D70 + Address: 0x08003D74 + Address: 0x08003D78 + Address: 0x08003D7C + Address: 0x08003D80 + Address: 0x08003D84 + Address: 0x08003D88 + Address: 0x08003D8C + Address: 0x08003D90 + Address: 0x08003D94 + Address: 0x08003D98 + Address: 0x08003D9C + Address: 0x08003DA0 + Address: 0x08003DA4 + Address: 0x08003DA8 + Address: 0x08003DAC + Address: 0x08003DB0 + Address: 0x08003DB4 + Address: 0x08003DB8 + Address: 0x08003DBC + Address: 0x08003DC0 + Address: 0x08003DC4 + Address: 0x08003DC8 + Address: 0x08003DCC + Address: 0x08003DD0 + Address: 0x08003DD4 + Address: 0x08003DD8 + Address: 0x08003DDC + Address: 0x08003DE0 + Address: 0x08003DE4 + Address: 0x08003DE8 + Address: 0x08003DEC + Address: 0x08003DF0 + Address: 0x08003DF4 + Address: 0x08003E1C + Address: 0x08003E20 + Address: 0x08003E24 + Address: 0x08003E28 + Address: 0x08003E2C + Address: 0x08003E30 + Address: 0x08003E34 + Address: 0x08003E38 + Address: 0x08003E3C + Address: 0x08003E40 + Address: 0x08003E44 + Address: 0x08003E48 + Address: 0x08003E4C + Address: 0x08003E50 + Address: 0x08003E54 + Address: 0x08003E58 + Address: 0x08003E5C + Address: 0x08003E60 + Address: 0x08003E64 + Address: 0x08003E68 + Address: 0x08003E6C + Address: 0x08003E70 + Address: 0x08003E74 + Address: 0x08003E78 + Address: 0x08003E7C + Address: 0x08003E80 + Address: 0x08003E84 + Address: 0x08003E88 + Address: 0x08003E8C + Address: 0x08003E90 + Address: 0x08003E94 + Address: 0x08003E98 + Address: 0x08003E9C + Address: 0x08003EA0 + Address: 0x08003EA4 + Address: 0x08003EA8 + Address: 0x08003EAC + Address: 0x08003EC4 + Address: 0x08003EC8 + Address: 0x08003ECC + Address: 0x08003ED0 + Address: 0x08003ED4 + Address: 0x08003ED8 + Address: 0x08003EDC + Address: 0x08003EE0 + Address: 0x08003EE4 + Address: 0x08003EE8 + Address: 0x08003EEC + Address: 0x08003EF0 + Address: 0x08003EF4 + Address: 0x08003EF8 + Address: 0x08003EFC + Address: 0x08003F00 + Address: 0x08003F04 + Address: 0x08003F08 + Address: 0x08003F0C + Address: 0x08003F24 + Address: 0x08003F28 + Address: 0x08003F2C + Address: 0x08003F30 + Address: 0x08003F34 + Address: 0x08003F38 + Address: 0x08003F3C + Address: 0x08003F40 + Address: 0x08003F44 + Address: 0x08003F48 + Address: 0x08003F4C + Address: 0x08003F50 + Address: 0x08003F54 + Address: 0x08003F58 + Address: 0x08003F5C + Address: 0x08003F60 + Address: 0x08003F64 + Address: 0x08003F68 + Address: 0x08003F6C + Address: 0x08003F84 + Address: 0x08003F88 + Address: 0x08003F8C + Address: 0x08003F90 + Address: 0x08003F94 + Address: 0x08003F98 + Address: 0x08003F9C + Address: 0x08003FA0 + Address: 0x08003FA4 + Address: 0x08003FA8 + Address: 0x08003FAC + Address: 0x08003FB0 + Address: 0x08003FB4 + Address: 0x08003FB8 + Address: 0x08003FBC + Address: 0x08003FC0 + Address: 0x08003FC4 + Address: 0x08003FC8 + Address: 0x08003FCC + Address: 0x08003FE0 + Address: 0x08003FE4 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0x080040C4 + Address: 0x080040C8 + Address: 0x080040CC + Address: 0x080040D0 + Address: 0x080040D4 + Address: 0x080040D8 + Address: 0x080040DC + Address: 0x080040E0 + Address: 0x080040E4 + Address: 0x080040E8 + Address: 0x080040F4 + Address: 0x080040F8 + Address: 0x080040FC + Address: 0x08004100 + Address: 0x08004104 + Address: 0x08004108 + Address: 0x0800410C + Address: 0x08004110 + Address: 0x08004114 + Address: 0x08004118 + Address: 0x0800411C + Address: 0x08004120 + Address: 0x08004124 + Address: 0x08004128 + Address: 0x0800412C + Address: 0x08004130 + Address: 0x08004134 + Address: 0x08004138 + Address: 0x08004154 + Address: 0x08004158 + Address: 0x0800415C + Address: 0x08004160 + Address: 0x08004164 + Address: 0x08004168 + Address: 0x0800416C + Address: 0x08004170 + Address: 0x08004174 + Address: 0x08004178 + Address: 0x0800417C + Address: 0x08004180 + Address: 0x08004184 + Address: 0x08004188 + Address: 0x0800418C + Address: 0x08004190 + Address: 0x08004194 + Address: 0x08004198 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0x0800427C + Address: 0x08004280 + Address: 0x08004284 + Address: 0x08004288 + Address: 0x0800428C + Address: 0x08004290 + Address: 0x08004294 + Address: 0x08004298 + Address: 0x0800429C + Address: 0x080042A0 + Address: 0x080042A4 + Address: 0x080042A8 + Address: 0x080042CC + Address: 0x080042D0 + Address: 0x080042D4 + Address: 0x080042D8 + Address: 0x080042DC + Address: 0x080042E0 + Address: 0x080042E4 + Address: 0x080042E8 + Address: 0x080042EC + Address: 0x080042F0 + Address: 0x080042F4 + Address: 0x080042F8 + Address: 0x080042FC + Address: 0x08004300 + Address: 0x08004304 + Address: 0x08004308 + Address: 0x0800430C + Address: 0x08004310 + Address: 0x08004314 + Address: 0x08004318 + Address: 0x0800431C + Address: 0x08004320 + Address: 0x08004324 + Address: 0x08004328 + Address: 0x0800432C + Address: 0x08004330 + Address: 0x08004334 + Address: 0x08004338 + Address: 0x0800433C + Address: 0x08004340 + Address: 0x08004344 + Address: 0x08004348 + Address: 0x0800434C + Address: 0x08004350 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0x08004450 + Address: 0x08004454 + Address: 0x08004458 + Address: 0x0800445C + Address: 0x08004460 + Address: 0x08004464 + Address: 0x08004468 + Address: 0x0800446C + Address: 0x08004470 + Address: 0x08004474 + Address: 0x08004478 + Address: 0x0800447C + Address: 0x08004480 + Address: 0x08004484 + Address: 0x08004488 + Address: 0x0800448C + Address: 0x08004490 + Address: 0x08004494 + Address: 0x08004498 + Address: 0x0800449C + Address: 0x080044A0 + Address: 0x080044A4 + Address: 0x080044A8 + Address: 0x080044AC + Address: 0x080044B0 + Address: 0x080044B4 + Address: 0x080044B8 + Address: 0x080044BC + Address: 0x080044C0 + Address: 0x080044C4 + Address: 0x080044C8 + Address: 0x080044CC + Address: 0x080044D0 + Address: 0x080044F8 + Address: 0x080044FC + Address: 0x08004500 + Address: 0x08004504 + Address: 0x08004508 + Address: 0x0800450C + Address: 0x08004510 + Address: 0x08004514 + Address: 0x08004518 + Address: 0x0800451C + Address: 0x08004520 + Address: 0x08004524 + Address: 0x08004528 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0x08004604 + Address: 0x08004608 + Address: 0x0800460C + Address: 0x08004610 + Address: 0x08004614 + Address: 0x08004618 + Address: 0x0800461C + Address: 0x08004620 + Address: 0x08004624 + Address: 0x08004628 + Address: 0x0800462C + Address: 0x08004630 + Address: 0x08004634 + Address: 0x08004638 + Address: 0x0800463C + Address: 0x08004640 + Address: 0x08004644 + Address: 0x08004670 + Address: 0x08004674 + Address: 0x08004678 + Address: 0x0800467C + Address: 0x08004680 + Address: 0x08004684 + Address: 0x08004688 + Address: 0x0800468C + Address: 0x08004690 + Address: 0x08004694 + Address: 0x08004698 + Address: 0x0800469C + Address: 0x080046A0 + Address: 0x080046A4 + Address: 0x080046A8 + Address: 0x080046AC + Address: 0x080046B0 + Address: 0x080046B4 + Address: 0x080046B8 + Address: 0x080046BC + Address: 0x080046C0 + Address: 0x080046C4 + Address: 0x080046C8 + Address: 0x080046CC + Address: 0x080046D0 + Address: 0x080046D4 + Address: 0x080046D8 + Address: 0x080046DC + Address: 0x080046E0 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0x080047B4 + Address: 0x080047E0 + Address: 0x080047E4 + Address: 0x080047E8 + Address: 0x080047EC + Address: 0x080047F0 + Address: 0x080047F4 + Address: 0x080047F8 + Address: 0x080047FC + Address: 0x08004800 + Address: 0x08004804 + Address: 0x08004808 + Address: 0x0800480C + Address: 0x08004810 + Address: 0x08004814 + Address: 0x08004818 + Address: 0x0800481C + Address: 0x08004820 + Address: 0x08004824 + Address: 0x08004828 + Address: 0x0800482C + Address: 0x08004830 + Address: 0x08004838 + Address: 0x0800483C + Address: 0x08004840 + Address: 0x08004844 + Address: 0x08004848 + Address: 0x0800484C + Address: 0x08004850 + Address: 0x08004854 + Address: 0x08004858 + Address: 0x0800485C + Address: 0x08004860 + Address: 0x08004864 + Address: 0x08004868 + Address: 0x0800486C + Address: 0x08004870 + Address: 0x08004874 + Address: 0x08004878 + Address: 0x08004898 + Address: 0x0800489C + Address: 0x080048A0 + Address: 0x080048A4 + Address: 0x080048A8 + Address: 0x080048AC + Address: 0x080048B0 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0x0800498C + Address: 0x08004990 + Address: 0x08004994 + Address: 0x08004998 + Address: 0x0800499C + Address: 0x080049A0 + Address: 0x080049AC + Address: 0x080049B0 + Address: 0x080049B4 + Address: 0x080049B8 + Address: 0x080049BC + Address: 0x080049C0 + Address: 0x080049C4 + Address: 0x080049C8 + Address: 0x080049CC + Address: 0x080049D0 + Address: 0x080049D4 + Address: 0x080049D8 + Address: 0x080049DC + Address: 0x080049E0 + Address: 0x080049E4 + Address: 0x080049E8 + Address: 0x080049EC + Address: 0x08004A0C + Address: 0x08004A10 + Address: 0x08004A14 + Address: 0x08004A18 + Address: 0x08004A1C + Address: 0x08004A20 + Address: 0x08004A24 + Address: 0x08004A28 + Address: 0x08004A2C + Address: 0x08004A30 + Address: 0x08004A34 + Address: 0x08004A38 + Address: 0x08004A3C + Address: 0x08004A40 + Address: 0x08004A44 + Address: 0x08004A48 + Address: 0x08004A4C + Address: 0x08004A50 + Address: 0x08004A54 + Address: 0x08004A58 + Address: 0x08004A60 + Address: 0x08004A64 + Address: 0x08004A68 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0x08004B48 + Address: 0x08004B4C + Address: 0x08004B50 + Address: 0x08004B54 + Address: 0x08004B58 + Address: 0x08004B5C + Address: 0x08004B60 + Address: 0x08004B80 + Address: 0x08004B84 + Address: 0x08004B88 + Address: 0x08004B8C + Address: 0x08004B90 + Address: 0x08004B94 + Address: 0x08004B98 + Address: 0x08004B9C + Address: 0x08004BA0 + Address: 0x08004BA4 + Address: 0x08004BA8 + Address: 0x08004BAC + Address: 0x08004BB0 + Address: 0x08004BB4 + Address: 0x08004BB8 + Address: 0x08004BBC + Address: 0x08004BC0 + Address: 0x08004BC4 + Address: 0x08004BC8 + Address: 0x08004BCC + Address: 0x08004BD4 + Address: 0x08004BD8 + Address: 0x08004BDC + Address: 0x08004BE0 + Address: 0x08004BE4 + Address: 0x08004BE8 + Address: 0x08004BEC + Address: 0x08004BF0 + Address: 0x08004BF4 + Address: 0x08004BF8 + Address: 0x08004BFC + Address: 0x08004C00 + Address: 0x08004C04 + Address: 0x08004C08 + Address: 0x08004C0C + Address: 0x08004C10 + Address: 0x08004C14 + Address: 0x08004C3C + Address: 0x08004C40 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0x08004D14 + Address: 0x08004D18 + Address: 0x08004D1C + Address: 0x08004D20 + Address: 0x08004D24 + Address: 0x08004D28 + Address: 0x08004D2C + Address: 0x08004D30 + Address: 0x08004D34 + Address: 0x08004D38 + Address: 0x08004D3C + Address: 0x08004D44 + Address: 0x08004D48 + Address: 0x08004D4C + Address: 0x08004D50 + Address: 0x08004D54 + Address: 0x08004D58 + Address: 0x08004D5C + Address: 0x08004D60 + Address: 0x08004D64 + Address: 0x08004D68 + Address: 0x08004D6C + Address: 0x08004D70 + Address: 0x08004D74 + Address: 0x08004D78 + Address: 0x08004D7C + Address: 0x08004D80 + Address: 0x08004D84 + Address: 0x08004DB0 + Address: 0x08004DB4 + Address: 0x08004DB8 + Address: 0x08004DBC + Address: 0x08004DC0 + Address: 0x08004DC4 + Address: 0x08004DC8 + Address: 0x08004DCC + Address: 0x08004DD0 + Address: 0x08004DD4 + Address: 0x08004DD8 + Address: 0x08004DDC + Address: 0x08004DE0 + Address: 0x08004DE4 + Address: 0x08004DE8 + Address: 0x08004DEC + Address: 0x08004DF0 + Address: 0x08004DF4 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0x08004ED0 + Address: 0x08004ED4 + Address: 0x08004ED8 + Address: 0x08004EDC + Address: 0x08004EE0 + Address: 0x08004EE4 + Address: 0x08004EE8 + Address: 0x08004EEC + Address: 0x08004EF0 + Address: 0x08004EF4 + Address: 0x08004EF8 + Address: 0x08004EFC + Address: 0x08004F1C + Address: 0x08004F20 + Address: 0x08004F24 + Address: 0x08004F28 + Address: 0x08004F2C + Address: 0x08004F30 + Address: 0x08004F34 + Address: 0x08004F38 + Address: 0x08004F3C + Address: 0x08004F40 + Address: 0x08004F44 + Address: 0x08004F48 + Address: 0x08004F4C + Address: 0x08004F50 + Address: 0x08004F54 + Address: 0x08004F58 + Address: 0x08004F5C + Address: 0x08004F60 + Address: 0x08004F64 + Address: 0x08004F68 + Address: 0x08004F74 + Address: 0x08004F78 + Address: 0x08004F7C + Address: 0x08004F80 + Address: 0x08004F84 + Address: 0x08004F88 + Address: 0x08004F8C + Address: 0x08004F90 + Address: 0x08004F94 + Address: 0x08004F98 + Address: 0x08004F9C + Address: 0x08004FA0 + Address: 0x08004FA4 + Address: 0x08004FA8 + Address: 0x08004FAC + Address: 0x08004FB0 + Address: 0x08004FB4 + Address: 0x08004FB8 + Address: 0x08004FDC + Address: 0x08004FE0 + Address: 0x08004FE4 + Address: 0x08004FE8 + Address: 0x08004FEC + Address: 0x08004FF0 + Address: 0x08004FF4 + Address: 0x08004FF8 + Address: 0x08004FFC + Address: 0x08005000 + Address: 0x08005004 + Address: 0x08005008 + Address: 0x0800500C + Address: 0x08005010 + Address: 0x08005014 + Address: 0x08005018 + Address: 0x0800501C + Address: 0x08005020 + Address: 0x08005024 + Address: 0x08005028 + Address: 0x08005030 + Address: 0x08005034 + Address: 0x08005038 + Address: 0x0800503C + Address: 0x08005040 + Address: 0x08005044 + Address: 0x08005048 + Address: 0x0800504C + Address: 0x08005050 + Address: 0x08005054 + Address: 0x08005058 + Address: 0x0800505C + Address: 0x08005060 + Address: 0x08005064 + Address: 0x08005068 + Address: 0x0800506C + Address: 0x08005070 + Address: 0x08005090 + Address: 0x08005094 + Address: 0x08005098 + Address: 0x0800509C + Address: 0x080050A0 + Address: 0x080050A4 + Address: 0x080050A8 + Address: 0x080050AC + Address: 0x080050B0 + Address: 0x080050B4 + Address: 0x080050B8 + Address: 0x080050BC + Address: 0x080050C0 + Address: 0x080050C4 + Address: 0x080050C8 + Address: 0x080050CC + Address: 0x080050D0 + Address: 0x080050D4 + Address: 0x080050D8 + Address: 0x080050DC + Address: 0x080050EC + Address: 0x080050F0 + Address: 0x080050F4 + Address: 0x080050F8 + Address: 0x080050FC + Address: 0x08005100 + Address: 0x08005104 + Address: 0x08005108 + Address: 0x0800510C + Address: 0x08005110 + Address: 0x08005114 + Address: 0x08005118 + Address: 0x0800511C + Address: 0x08005120 + Address: 0x08005124 + Address: 0x08005128 + Address: 0x0800512C + Address: 0x08005130 + Address: 0x08005150 + Address: 0x08005154 + Address: 0x08005158 + Address: 0x0800515C + Address: 0x08005160 + Address: 0x08005164 + Address: 0x08005168 + Address: 0x0800516C + Address: 0x08005170 + Address: 0x08005174 + Address: 0x08005178 + Address: 0x0800517C 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0x08005268 + Address: 0x0800526C + Address: 0x08005270 + Address: 0x08005274 + Address: 0x08005278 + Address: 0x0800527C + Address: 0x08005280 + Address: 0x08005284 + Address: 0x08005288 + Address: 0x0800528C + Address: 0x08005290 + Address: 0x08005294 + Address: 0x08005298 + Address: 0x0800529C + Address: 0x080052A0 + Address: 0x080052A4 + Address: 0x080052A8 + Address: 0x080052AC + Address: 0x080052B0 + Address: 0x080052C8 + Address: 0x080052CC + Address: 0x080052D0 + Address: 0x080052D4 + Address: 0x080052D8 + Address: 0x080052DC + Address: 0x080052E0 + Address: 0x080052E4 + Address: 0x080052E8 + Address: 0x080052EC + Address: 0x080052F0 + Address: 0x080052F4 + Address: 0x080052F8 + Address: 0x080052FC + Address: 0x08005300 + Address: 0x08005304 + Address: 0x08005308 + Address: 0x0800530C + Address: 0x08005310 + Address: 0x08005320 + Address: 0x08005324 + Address: 0x08005328 + Address: 0x0800532C + Address: 0x08005330 + Address: 0x08005334 + Address: 0x08005338 + Address: 0x0800533C + Address: 0x08005340 + Address: 0x08005344 + Address: 0x08005348 + Address: 0x0800534C + Address: 0x08005350 + Address: 0x08005354 + Address: 0x08005358 + Address: 0x0800535C + Address: 0x08005360 + Address: 0x08005364 + Address: 0x0800537C + Address: 0x08005380 + Address: 0x08005384 + Address: 0x08005388 + Address: 0x0800538C + Address: 0x08005390 + Address: 0x08005394 + Address: 0x08005398 + Address: 0x0800539C + Address: 0x080053A0 + Address: 0x080053A4 + Address: 0x080053A8 + Address: 0x080053AC + Address: 0x080053B0 + Address: 0x080053B4 + Address: 0x080053B8 + Address: 0x080053BC + Address: 0x080053C0 + Address: 0x080053C4 + Address: 0x080053DC + Address: 0x080053E0 + Address: 0x080053E4 + Address: 0x080053E8 + Address: 0x080053EC + Address: 0x080053F0 + Address: 0x080053F4 + Address: 0x080053F8 + Address: 0x080053FC + Address: 0x08005400 + Address: 0x08005404 + Address: 0x08005408 + Address: 0x0800540C + Address: 0x08005410 + Address: 0x08005414 + Address: 0x08005418 + Address: 0x0800541C + Address: 0x08005420 + Address: 0x08005424 + Address: 0x08005438 + Address: 0x0800543C + Address: 0x08005440 + Address: 0x08005444 + Address: 0x08005448 + Address: 0x0800544C + Address: 0x08005450 + Address: 0x08005454 + Address: 0x08005458 + Address: 0x0800545C + Address: 0x08005460 + Address: 0x08005464 + Address: 0x08005468 + Address: 0x0800546C + Address: 0x08005470 + Address: 0x08005474 + Address: 0x08005478 + Address: 0x0800547C + Address: 0x08005480 + Address: 0x08005498 + Address: 0x0800549C + Address: 0x080054A0 + Address: 0x080054A4 + Address: 0x080054A8 + Address: 0x080054AC + Address: 0x080054B0 + Address: 0x080054B4 + Address: 0x080054B8 + Address: 0x080054BC + Address: 0x080054C0 + Address: 0x080054C4 + Address: 0x080054C8 + Address: 0x080054CC + Address: 0x080054D0 + Address: 0x080054D4 + Address: 0x080054D8 + Address: 0x080054DC + Address: 0x080054E0 + Address: 0x080054EC + Address: 0x080054F0 + Address: 0x080054F4 + Address: 0x080054F8 + Address: 0x080054FC + Address: 0x08005500 + Address: 0x08005504 + Address: 0x08005508 + Address: 0x0800550C + Address: 0x08005510 + Address: 0x08005514 + Address: 0x08005518 + Address: 0x0800551C + Address: 0x08005520 + Address: 0x08005524 + Address: 0x08005528 + Address: 0x0800552C + Address: 0x08005530 + Address: 0x08005550 + Address: 0x08005554 + Address: 0x08005558 + Address: 0x0800555C + Address: 0x08005560 + Address: 0x08005564 + Address: 0x08005568 + Address: 0x0800556C + Address: 0x08005570 + Address: 0x08005574 + Address: 0x08005578 + Address: 0x0800557C + Address: 0x08005580 + Address: 0x08005584 + Address: 0x08005588 + Address: 0x0800558C + Address: 0x08005590 + Address: 0x08005594 + Address: 0x08005598 + Address: 0x0800559C + Address: 0x080055A8 + Address: 0x080055AC + Address: 0x080055B0 + Address: 0x080055B4 + Address: 0x080055B8 + Address: 0x080055BC + Address: 0x080055C0 + Address: 0x080055C4 + Address: 0x080055C8 + Address: 0x080055CC + Address: 0x080055D0 + Address: 0x080055D4 + Address: 0x080055D8 + Address: 0x080055DC + Address: 0x080055E0 + Address: 0x080055E4 + Address: 0x080055E8 + Address: 0x080055EC + Address: 0x0800560C + Address: 0x08005610 + Address: 0x08005614 + Address: 0x08005618 + Address: 0x0800561C + Address: 0x08005620 + Address: 0x08005624 + Address: 0x08005628 + Address: 0x0800562C + Address: 0x08005630 + Address: 0x08005634 + Address: 0x08005638 + Address: 0x0800563C + Address: 0x08005640 + Address: 0x08005644 + Address: 0x08005648 + Address: 0x0800564C + Address: 0x08005650 + Address: 0x08005654 + Address: 0x08005658 + Address: 0x0800565C + Address: 0x08005660 + Address: 0x08005664 + Address: 0x08005668 + Address: 0x0800566C + Address: 0x08005670 + Address: 0x08005674 + Address: 0x08005678 + Address: 0x0800567C + Address: 0x08005680 + Address: 0x08005684 + Address: 0x08005688 + Address: 0x0800568C + Address: 0x08005690 + Address: 0x08005694 + Address: 0x08005698 + Address: 0x0800569C + Address: 0x080056C8 + Address: 0x080056CC + Address: 0x080056D0 + Address: 0x080056D4 + Address: 0x080056D8 + Address: 0x080056DC + Address: 0x080056E0 + Address: 0x080056E4 + Address: 0x080056E8 + Address: 0x080056EC + Address: 0x080056F0 + Address: 0x080056F4 + Address: 0x080056F8 + Address: 0x080056FC + Address: 0x08005700 + Address: 0x08005704 + Address: 0x08005708 + Address: 0x0800570C + Address: 0x08005710 + Address: 0x08005714 + Address: 0x08005718 + Address: 0x0800571C + Address: 0x08005720 + Address: 0x08005724 + Address: 0x08005728 + Address: 0x0800572C + Address: 0x08005730 + Address: 0x08005734 + Address: 0x08005738 + Address: 0x0800573C + Address: 0x08005740 + Address: 0x08005744 + Address: 0x08005748 + Address: 0x0800574C + Address: 0x08005750 + Address: 0x08005754 + Address: 0x08005758 + Address: 0x0800575C + Address: 0x08005784 + Address: 0x08005788 + Address: 0x0800578C + Address: 0x08005790 + Address: 0x08005794 + Address: 0x08005798 + Address: 0x0800579C + Address: 0x080057A0 + Address: 0x080057A4 + Address: 0x080057A8 + Address: 0x080057AC + Address: 0x080057B0 + Address: 0x080057B4 + Address: 0x080057B8 + Address: 0x080057BC + Address: 0x080057C0 + Address: 0x080057C4 + Address: 0x080057C8 + Address: 0x080057CC + Address: 0x080057D0 + Address: 0x080057D4 + Address: 0x080057D8 + Address: 0x080057DC + Address: 0x080057E0 + Address: 0x080057E4 + Address: 0x080057E8 + Address: 0x080057EC + Address: 0x080057F0 + Address: 0x080057F4 + Address: 0x080057F8 + Address: 0x080057FC + Address: 0x08005800 + Address: 0x08005804 + Address: 0x08005808 + Address: 0x0800580C + Address: 0x08005810 + Address: 0x08005814 + Address: 0x0800583C + Address: 0x08005840 + Address: 0x08005844 + Address: 0x08005848 + Address: 0x0800584C + Address: 0x08005850 + Address: 0x08005854 + Address: 0x08005858 + Address: 0x0800585C + Address: 0x08005860 + Address: 0x08005864 + Address: 0x08005868 + Address: 0x0800586C + Address: 0x08005870 + Address: 0x08005874 + Address: 0x08005878 + Address: 0x0800587C + Address: 0x08005880 + Address: 0x08005884 + Address: 0x08005888 + Address: 0x0800588C + Address: 0x08005894 + Address: 0x08005898 + Address: 0x0800589C + Address: 0x080058A0 + Address: 0x080058A4 + Address: 0x080058A8 + Address: 0x080058AC + Address: 0x080058B0 + Address: 0x080058B4 + Address: 0x080058B8 + Address: 0x080058BC + Address: 0x080058C0 + Address: 0x080058C4 + Address: 0x080058C8 + Address: 0x080058CC + Address: 0x080058D0 + Address: 0x080058D4 + Address: 0x080058F4 + Address: 0x080058F8 + Address: 0x080058FC + Address: 0x08005900 + Address: 0x08005904 + Address: 0x08005908 + Address: 0x0800590C + Address: 0x08005910 + Address: 0x08005914 + Address: 0x08005918 + Address: 0x0800591C + Address: 0x08005920 + Address: 0x08005924 + Address: 0x08005928 + Address: 0x0800592C + Address: 0x08005930 + Address: 0x08005934 + Address: 0x08005938 + Address: 0x0800593C + Address: 0x08005940 + Address: 0x08005944 + Address: 0x08005948 + Address: 0x0800594C + Address: 0x08005950 + Address: 0x08005954 + Address: 0x08005958 + Address: 0x0800595C + Address: 0x08005960 + Address: 0x08005964 + Address: 0x08005968 + Address: 0x0800596C + Address: 0x08005970 + Address: 0x08005974 + Address: 0x08005978 + Address: 0x0800597C + Address: 0x08005980 + Address: 0x08005984 + Address: 0x080059AC + Address: 0x080059B0 + Address: 0x080059B4 + Address: 0x080059B8 + Address: 0x080059BC + Address: 0x080059C0 + Address: 0x080059C4 + Address: 0x080059C8 + Address: 0x080059CC + Address: 0x080059D0 + Address: 0x080059D4 + Address: 0x080059D8 + Address: 0x080059DC + Address: 0x080059E0 + Address: 0x080059E4 + Address: 0x080059E8 + Address: 0x080059EC + Address: 0x080059F0 + Address: 0x080059F4 + Address: 0x080059F8 + Address: 0x080059FC + Address: 0x08005A08 + Address: 0x08005A0C + Address: 0x08005A10 + Address: 0x08005A14 + Address: 0x08005A18 + Address: 0x08005A1C + Address: 0x08005A20 + Address: 0x08005A24 + Address: 0x08005A28 + Address: 0x08005A2C + Address: 0x08005A30 + Address: 0x08005A34 + Address: 0x08005A38 + Address: 0x08005A3C + Address: 0x08005A40 + Address: 0x08005A44 + Address: 0x08005A48 + Address: 0x08005A68 + Address: 0x08005A6C + Address: 0x08005A70 + Address: 0x08005A74 + Address: 0x08005A78 + Address: 0x08005A7C + Address: 0x08005A80 + Address: 0x08005A84 + Address: 0x08005A88 + Address: 0x08005A8C + Address: 0x08005A90 + Address: 0x08005A94 + Address: 0x08005A98 + Address: 0x08005A9C + Address: 0x08005AA0 + Address: 0x08005AA4 + Address: 0x08005AA8 + Address: 0x08005AAC + Address: 0x08005AB0 + Address: 0x08005AB4 + Address: 0x08005ABC + Address: 0x08005AC0 + Address: 0x08005AC4 + Address: 0x08005AC8 + Address: 0x08005ACC + Address: 0x08005AD0 + Address: 0x08005AD4 + Address: 0x08005AD8 + Address: 0x08005ADC + Address: 0x08005AE0 + Address: 0x08005AE4 + Address: 0x08005AE8 + Address: 0x08005AEC + Address: 0x08005AF0 + Address: 0x08005AF4 + Address: 0x08005AF8 + Address: 0x08005AFC + Address: 0x08005B20 + Address: 0x08005B24 + Address: 0x08005B28 + Address: 0x08005B2C + Address: 0x08005B30 + Address: 0x08005B34 + Address: 0x08005B38 + Address: 0x08005B3C + Address: 0x08005B40 + Address: 0x08005B44 + Address: 0x08005B48 + Address: 0x08005B4C + Address: 0x08005B50 + Address: 0x08005B54 + Address: 0x08005B58 + Address: 0x08005B5C + Address: 0x08005B60 + Address: 0x08005B64 + Address: 0x08005B68 + Address: 0x08005B6C + Address: 0x08005B70 + Address: 0x08005B7C + Address: 0x08005B80 + Address: 0x08005B84 + Address: 0x08005B88 + Address: 0x08005B8C + Address: 0x08005B90 + Address: 0x08005B94 + Address: 0x08005B98 + Address: 0x08005B9C + Address: 0x08005BA0 + Address: 0x08005BA4 + Address: 0x08005BA8 + Address: 0x08005BAC + Address: 0x08005BB0 + Address: 0x08005BB4 + Address: 0x08005BB8 + Address: 0x08005BBC + Address: 0x08005BDC + Address: 0x08005BE0 + Address: 0x08005BE4 + Address: 0x08005BE8 + Address: 0x08005BEC + Address: 0x08005BF0 + Address: 0x08005BF4 + Address: 0x08005BF8 + Address: 0x08005BFC + Address: 0x08005C00 + Address: 0x08005C04 + Address: 0x08005C08 + Address: 0x08005C0C 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0x08005CF0 + Address: 0x08005CF4 + Address: 0x08005CF8 + Address: 0x08005CFC + Address: 0x08005D00 + Address: 0x08005D04 + Address: 0x08005D08 + Address: 0x08005D0C + Address: 0x08005D10 + Address: 0x08005D14 + Address: 0x08005D18 + Address: 0x08005D1C + Address: 0x08005D20 + Address: 0x08005D24 + Address: 0x08005D28 + Address: 0x08005D2C + Address: 0x08005D30 + Address: 0x08005D50 + Address: 0x08005D54 + Address: 0x08005D58 + Address: 0x08005D5C + Address: 0x08005D60 + Address: 0x08005D64 + Address: 0x08005D68 + Address: 0x08005D6C + Address: 0x08005D70 + Address: 0x08005D74 + Address: 0x08005D78 + Address: 0x08005D7C + Address: 0x08005D80 + Address: 0x08005D84 + Address: 0x08005D88 + Address: 0x08005D8C + Address: 0x08005D90 + Address: 0x08005D94 + Address: 0x08005D98 + Address: 0x08005D9C + Address: 0x08005DA4 + Address: 0x08005DA8 + Address: 0x08005DAC + Address: 0x08005DB0 + Address: 0x08005DB4 + Address: 0x08005DB8 + Address: 0x08005DBC + Address: 0x08005DC0 + Address: 0x08005DC4 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0x08005EA4 + Address: 0x08005EC4 + Address: 0x08005EC8 + Address: 0x08005ECC + Address: 0x08005ED0 + Address: 0x08005ED4 + Address: 0x08005ED8 + Address: 0x08005EDC + Address: 0x08005EE0 + Address: 0x08005EE4 + Address: 0x08005EE8 + Address: 0x08005EEC + Address: 0x08005EF0 + Address: 0x08005EF4 + Address: 0x08005EF8 + Address: 0x08005EFC + Address: 0x08005F00 + Address: 0x08005F04 + Address: 0x08005F08 + Address: 0x08005F0C + Address: 0x08005F10 + Address: 0x08005F14 + Address: 0x08005F18 + Address: 0x08005F1C + Address: 0x08005F20 + Address: 0x08005F24 + Address: 0x08005F28 + Address: 0x08005F2C + Address: 0x08005F30 + Address: 0x08005F34 + Address: 0x08005F38 + Address: 0x08005F3C + Address: 0x08005F40 + Address: 0x08005F44 + Address: 0x08005F48 + Address: 0x08005F4C + Address: 0x08005F50 + Address: 0x08005F54 + Address: 0x08005F80 + Address: 0x08005F84 + Address: 0x08005F88 + Address: 0x08005F8C + Address: 0x08005F90 + Address: 0x08005F94 + Address: 0x08005F98 + Address: 0x08005F9C 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0x08006078 + Address: 0x0800607C + Address: 0x08006080 + Address: 0x08006084 + Address: 0x08006088 + Address: 0x0800608C + Address: 0x08006090 + Address: 0x08006094 + Address: 0x08006098 + Address: 0x0800609C + Address: 0x080060A0 + Address: 0x080060A4 + Address: 0x080060A8 + Address: 0x080060AC + Address: 0x080060B0 + Address: 0x080060B4 + Address: 0x080060B8 + Address: 0x080060BC + Address: 0x080060C0 + Address: 0x080060C4 + Address: 0x080060C8 + Address: 0x080060CC + Address: 0x080060EC + Address: 0x080060F0 + Address: 0x080060F4 + Address: 0x080060F8 + Address: 0x080060FC + Address: 0x08006100 + Address: 0x08006104 + Address: 0x08006108 + Address: 0x0800610C + Address: 0x08006110 + Address: 0x08006114 + Address: 0x08006118 + Address: 0x0800611C + Address: 0x08006120 + Address: 0x08006124 + Address: 0x08006128 + Address: 0x0800612C + Address: 0x08006130 + Address: 0x08006134 + Address: 0x08006138 + Address: 0x08006144 + Address: 0x08006148 + Address: 0x0800614C + Address: 0x08006150 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0x08006228 + Address: 0x0800622C + Address: 0x08006230 + Address: 0x08006234 + Address: 0x08006238 + Address: 0x0800623C + Address: 0x08006260 + Address: 0x08006264 + Address: 0x08006268 + Address: 0x0800626C + Address: 0x08006270 + Address: 0x08006274 + Address: 0x08006278 + Address: 0x0800627C + Address: 0x08006280 + Address: 0x08006284 + Address: 0x08006288 + Address: 0x0800628C + Address: 0x08006290 + Address: 0x08006294 + Address: 0x08006298 + Address: 0x0800629C + Address: 0x080062A0 + Address: 0x080062A4 + Address: 0x080062A8 + Address: 0x080062AC + Address: 0x080062BC + Address: 0x080062C0 + Address: 0x080062C4 + Address: 0x080062C8 + Address: 0x080062CC + Address: 0x080062D0 + Address: 0x080062D4 + Address: 0x080062D8 + Address: 0x080062DC + Address: 0x080062E0 + Address: 0x080062E4 + Address: 0x080062E8 + Address: 0x080062EC + Address: 0x080062F0 + Address: 0x080062F4 + Address: 0x080062F8 + Address: 0x080062FC + Address: 0x08006300 + Address: 0x08006318 + Address: 0x0800631C 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0x080063FC + Address: 0x08006400 + Address: 0x08006404 + Address: 0x08006408 + Address: 0x0800640C + Address: 0x08006410 + Address: 0x08006414 + Address: 0x08006418 + Address: 0x0800641C + Address: 0x08006420 + Address: 0x0800642C + Address: 0x08006430 + Address: 0x08006434 + Address: 0x08006438 + Address: 0x0800643C + Address: 0x08006440 + Address: 0x08006444 + Address: 0x08006448 + Address: 0x0800644C + Address: 0x08006450 + Address: 0x08006454 + Address: 0x08006458 + Address: 0x0800645C + Address: 0x08006460 + Address: 0x08006464 + Address: 0x08006468 + Address: 0x0800646C + Address: 0x08006470 + Address: 0x0800648C + Address: 0x08006490 + Address: 0x08006494 + Address: 0x08006498 + Address: 0x0800649C + Address: 0x080064A0 + Address: 0x080064A4 + Address: 0x080064A8 + Address: 0x080064AC + Address: 0x080064B0 + Address: 0x080064B4 + Address: 0x080064B8 + Address: 0x080064BC + Address: 0x080064C0 + Address: 0x080064C4 + Address: 0x080064C8 + Address: 0x080064CC + Address: 0x080064D0 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0x080065B4 + Address: 0x080065B8 + Address: 0x080065BC + Address: 0x080065C0 + Address: 0x080065C4 + Address: 0x080065C8 + Address: 0x080065CC + Address: 0x080065D0 + Address: 0x080065D4 + Address: 0x080065D8 + Address: 0x080065DC + Address: 0x080065E0 + Address: 0x08006600 + Address: 0x08006604 + Address: 0x08006608 + Address: 0x0800660C + Address: 0x08006610 + Address: 0x08006614 + Address: 0x08006618 + Address: 0x0800661C + Address: 0x08006620 + Address: 0x08006624 + Address: 0x08006628 + Address: 0x0800662C + Address: 0x08006630 + Address: 0x08006634 + Address: 0x08006638 + Address: 0x0800663C + Address: 0x08006640 + Address: 0x08006644 + Address: 0x08006648 + Address: 0x0800664C + Address: 0x08006654 + Address: 0x08006658 + Address: 0x0800665C + Address: 0x08006660 + Address: 0x08006664 + Address: 0x08006668 + Address: 0x0800666C + Address: 0x08006670 + Address: 0x08006674 + Address: 0x08006678 + Address: 0x0800667C + Address: 0x08006680 + Address: 0x08006684 + Address: 0x08006688 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0x08006788 + Address: 0x0800678C + Address: 0x08006790 + Address: 0x08006794 + Address: 0x08006798 + Address: 0x0800679C + Address: 0x080067A0 + Address: 0x080067A4 + Address: 0x080067A8 + Address: 0x080067AC + Address: 0x080067B0 + Address: 0x080067B4 + Address: 0x080067B8 + Address: 0x080067BC + Address: 0x080067C0 + Address: 0x080067C4 + Address: 0x080067C8 + Address: 0x080067CC + Address: 0x080067D0 + Address: 0x080067D4 + Address: 0x080067D8 + Address: 0x080067DC + Address: 0x080067E0 + Address: 0x080067E4 + Address: 0x080067E8 + Address: 0x080067EC + Address: 0x080067F0 + Address: 0x080067F4 + Address: 0x080067F8 + Address: 0x080067FC + Address: 0x08006800 + Address: 0x08006804 + Address: 0x08006808 + Address: 0x08006830 + Address: 0x08006834 + Address: 0x08006838 + Address: 0x0800683C + Address: 0x08006840 + Address: 0x08006844 + Address: 0x08006848 + Address: 0x0800684C + Address: 0x08006850 + Address: 0x08006854 + Address: 0x08006858 + Address: 0x0800685C + Address: 0x08006860 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0x0800693C + Address: 0x08006940 + Address: 0x08006944 + Address: 0x08006948 + Address: 0x0800694C + Address: 0x08006950 + Address: 0x08006954 + Address: 0x08006958 + Address: 0x0800695C + Address: 0x08006960 + Address: 0x08006964 + Address: 0x08006968 + Address: 0x0800696C + Address: 0x08006970 + Address: 0x08006974 + Address: 0x08006978 + Address: 0x0800697C + Address: 0x080069A4 + Address: 0x080069A8 + Address: 0x080069AC + Address: 0x080069B0 + Address: 0x080069B4 + Address: 0x080069B8 + Address: 0x080069BC + Address: 0x080069C0 + Address: 0x080069C4 + Address: 0x080069C8 + Address: 0x080069CC + Address: 0x080069D0 + Address: 0x080069D4 + Address: 0x080069D8 + Address: 0x080069DC + Address: 0x080069E0 + Address: 0x080069E4 + Address: 0x080069E8 + Address: 0x080069EC + Address: 0x080069F0 + Address: 0x080069F4 + Address: 0x080069FC + Address: 0x08006A00 + Address: 0x08006A04 + Address: 0x08006A08 + Address: 0x08006A0C + Address: 0x08006A10 + Address: 0x08006A14 + Address: 0x08006A18 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0x08006AEC + Address: 0x08006B18 + Address: 0x08006B1C + Address: 0x08006B20 + Address: 0x08006B24 + Address: 0x08006B28 + Address: 0x08006B2C + Address: 0x08006B30 + Address: 0x08006B34 + Address: 0x08006B38 + Address: 0x08006B3C + Address: 0x08006B40 + Address: 0x08006B44 + Address: 0x08006B48 + Address: 0x08006B4C + Address: 0x08006B50 + Address: 0x08006B54 + Address: 0x08006B58 + Address: 0x08006B5C + Address: 0x08006B60 + Address: 0x08006B64 + Address: 0x08006B68 + Address: 0x08006B6C + Address: 0x08006B70 + Address: 0x08006B74 + Address: 0x08006B78 + Address: 0x08006B7C + Address: 0x08006B80 + Address: 0x08006B84 + Address: 0x08006B88 + Address: 0x08006B8C + Address: 0x08006B90 + Address: 0x08006B94 + Address: 0x08006B98 + Address: 0x08006B9C + Address: 0x08006BA0 + Address: 0x08006BA4 + Address: 0x08006BA8 + Address: 0x08006BAC + Address: 0x08006BD4 + Address: 0x08006BD8 + Address: 0x08006BDC + Address: 0x08006BE0 + Address: 0x08006BE4 + Address: 0x08006BE8 + Address: 0x08006BEC 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0x08006CC0 + Address: 0x08006CC4 + Address: 0x08006CC8 + Address: 0x08006CCC + Address: 0x08006CD0 + Address: 0x08006CDC + Address: 0x08006CE0 + Address: 0x08006CE4 + Address: 0x08006CE8 + Address: 0x08006CEC + Address: 0x08006CF0 + Address: 0x08006CF4 + Address: 0x08006CF8 + Address: 0x08006CFC + Address: 0x08006D00 + Address: 0x08006D04 + Address: 0x08006D08 + Address: 0x08006D0C + Address: 0x08006D10 + Address: 0x08006D14 + Address: 0x08006D18 + Address: 0x08006D1C + Address: 0x08006D20 + Address: 0x08006D3C + Address: 0x08006D40 + Address: 0x08006D44 + Address: 0x08006D48 + Address: 0x08006D4C + Address: 0x08006D50 + Address: 0x08006D54 + Address: 0x08006D58 + Address: 0x08006D5C + Address: 0x08006D60 + Address: 0x08006D64 + Address: 0x08006D68 + Address: 0x08006D6C + Address: 0x08006D70 + Address: 0x08006D74 + Address: 0x08006D78 + Address: 0x08006D7C + Address: 0x08006D80 + Address: 0x08006D84 + Address: 0x08006D90 + Address: 0x08006D94 + Address: 0x08006D98 + Address: 0x08006D9C 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0x08006E80 + Address: 0x08006E84 + Address: 0x08006E88 + Address: 0x08006E8C + Address: 0x08006E90 + Address: 0x08006E94 + Address: 0x08006E98 + Address: 0x08006EB0 + Address: 0x08006EB4 + Address: 0x08006EB8 + Address: 0x08006EBC + Address: 0x08006EC0 + Address: 0x08006EC4 + Address: 0x08006EC8 + Address: 0x08006ECC + Address: 0x08006ED0 + Address: 0x08006ED4 + Address: 0x08006ED8 + Address: 0x08006EDC + Address: 0x08006EE0 + Address: 0x08006EE4 + Address: 0x08006EE8 + Address: 0x08006EEC + Address: 0x08006EF0 + Address: 0x08006EF4 + Address: 0x08006EF8 + Address: 0x08006F04 + Address: 0x08006F08 + Address: 0x08006F0C + Address: 0x08006F10 + Address: 0x08006F14 + Address: 0x08006F18 + Address: 0x08006F1C + Address: 0x08006F20 + Address: 0x08006F24 + Address: 0x08006F28 + Address: 0x08006F2C + Address: 0x08006F30 + Address: 0x08006F34 + Address: 0x08006F38 + Address: 0x08006F3C + Address: 0x08006F40 + Address: 0x08006F44 + Address: 0x08006F48 + Address: 0x08006F6C + Address: 0x08006F70 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0x08007048 + Address: 0x0800704C + Address: 0x08007050 + Address: 0x08007054 + Address: 0x08007058 + Address: 0x0800705C + Address: 0x08007060 + Address: 0x08007064 + Address: 0x08007068 + Address: 0x0800706C + Address: 0x08007070 + Address: 0x08007074 + Address: 0x08007078 + Address: 0x0800707C + Address: 0x08007080 + Address: 0x08007084 + Address: 0x08007088 + Address: 0x0800708C + Address: 0x08007090 + Address: 0x08007094 + Address: 0x08007098 + Address: 0x0800709C + Address: 0x080070A0 + Address: 0x080070A4 + Address: 0x080070A8 + Address: 0x080070AC + Address: 0x080070B0 + Address: 0x080070B4 + Address: 0x080070E0 + Address: 0x080070E4 + Address: 0x080070E8 + Address: 0x080070EC + Address: 0x080070F0 + Address: 0x080070F4 + Address: 0x080070F8 + Address: 0x080070FC + Address: 0x08007100 + Address: 0x08007104 + Address: 0x08007108 + Address: 0x0800710C + Address: 0x08007110 + Address: 0x08007114 + Address: 0x08007118 + Address: 0x0800711C + Address: 0x08007120 + Address: 0x08007124 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0x08007200 + Address: 0x08007204 + Address: 0x08007208 + Address: 0x0800720C + Address: 0x08007210 + Address: 0x08007214 + Address: 0x08007218 + Address: 0x0800721C + Address: 0x08007220 + Address: 0x08007224 + Address: 0x08007228 + Address: 0x0800722C + Address: 0x08007254 + Address: 0x08007258 + Address: 0x0800725C + Address: 0x08007260 + Address: 0x08007264 + Address: 0x08007268 + Address: 0x0800726C + Address: 0x08007270 + Address: 0x08007274 + Address: 0x08007278 + Address: 0x0800727C + Address: 0x08007280 + Address: 0x08007284 + Address: 0x08007288 + Address: 0x0800728C + Address: 0x08007290 + Address: 0x08007294 + Address: 0x08007298 + Address: 0x0800729C + Address: 0x080072A0 + Address: 0x080072A4 + Address: 0x080072AC + Address: 0x080072B0 + Address: 0x080072B4 + Address: 0x080072B8 + Address: 0x080072BC + Address: 0x080072C0 + Address: 0x080072C4 + Address: 0x080072C8 + Address: 0x080072CC + Address: 0x080072D0 + Address: 0x080072D4 + Address: 0x080072D8 + Address: 0x080072DC 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0x080073E0 + Address: 0x080073E4 + Address: 0x080073E8 + Address: 0x080073EC + Address: 0x080073F0 + Address: 0x080073F4 + Address: 0x080073F8 + Address: 0x080073FC + Address: 0x08007400 + Address: 0x08007404 + Address: 0x08007408 + Address: 0x0800740C + Address: 0x08007410 + Address: 0x08007414 + Address: 0x08007418 + Address: 0x0800741C + Address: 0x08007420 + Address: 0x08007424 + Address: 0x08007428 + Address: 0x0800742C + Address: 0x08007430 + Address: 0x08007434 + Address: 0x08007438 + Address: 0x0800743C + Address: 0x08007440 + Address: 0x08007444 + Address: 0x08007448 + Address: 0x0800744C + Address: 0x08007450 + Address: 0x08007454 + Address: 0x08007458 + Address: 0x0800745C + Address: 0x08007460 + Address: 0x08007464 + Address: 0x08007484 + Address: 0x08007488 + Address: 0x0800748C + Address: 0x08007490 + Address: 0x08007494 + Address: 0x08007498 + Address: 0x0800749C + Address: 0x080074A0 + Address: 0x080074A4 + Address: 0x080074A8 + Address: 0x080074AC + Address: 0x080074B0 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0x08007590 + Address: 0x08007598 + Address: 0x0800759C + Address: 0x080075A0 + Address: 0x080075A4 + Address: 0x080075A8 + Address: 0x080075AC + Address: 0x080075B0 + Address: 0x080075B4 + Address: 0x080075B8 + Address: 0x080075BC + Address: 0x080075C0 + Address: 0x080075C4 + Address: 0x080075C8 + Address: 0x080075CC + Address: 0x080075D0 + Address: 0x080075D4 + Address: 0x080075D8 + Address: 0x080075F8 + Address: 0x080075FC + Address: 0x08007600 + Address: 0x08007604 + Address: 0x08007608 + Address: 0x0800760C + Address: 0x08007610 + Address: 0x08007614 + Address: 0x08007618 + Address: 0x0800761C + Address: 0x08007620 + Address: 0x08007624 + Address: 0x08007628 + Address: 0x0800762C + Address: 0x08007630 + Address: 0x08007634 + Address: 0x08007638 + Address: 0x0800763C + Address: 0x08007640 + Address: 0x08007644 + Address: 0x08007648 + Address: 0x0800764C + Address: 0x08007650 + Address: 0x08007654 + Address: 0x08007658 + Address: 0x0800765C + Address: 0x08007660 + Address: 0x08007664 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0x08007744 + Address: 0x08007748 + Address: 0x08007770 + Address: 0x08007774 + Address: 0x08007778 + Address: 0x0800777C + Address: 0x08007780 + Address: 0x08007784 + Address: 0x08007788 + Address: 0x0800778C + Address: 0x08007790 + Address: 0x08007794 + Address: 0x08007798 + Address: 0x0800779C + Address: 0x080077A0 + Address: 0x080077A4 + Address: 0x080077A8 + Address: 0x080077AC + Address: 0x080077B0 + Address: 0x080077B4 + Address: 0x080077B8 + Address: 0x080077BC + Address: 0x080077C0 + Address: 0x080077C4 + Address: 0x080077C8 + Address: 0x080077CC + Address: 0x080077D0 + Address: 0x080077D4 + Address: 0x080077D8 + Address: 0x080077DC + Address: 0x080077E0 + Address: 0x080077E4 + Address: 0x080077E8 + Address: 0x080077EC + Address: 0x080077F0 + Address: 0x080077F4 + Address: 0x080077F8 + Address: 0x080077FC + Address: 0x08007800 + Address: 0x08007820 + Address: 0x08007824 + Address: 0x08007828 + Address: 0x0800782C + Address: 0x08007830 + Address: 0x08007834 + Address: 0x08007838 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0x08007910 + Address: 0x08007914 + Address: 0x08007918 + Address: 0x0800791C + Address: 0x08007920 + Address: 0x0800792C + Address: 0x08007930 + Address: 0x08007934 + Address: 0x08007938 + Address: 0x0800793C + Address: 0x08007940 + Address: 0x08007944 + Address: 0x08007948 + Address: 0x0800794C + Address: 0x08007950 + Address: 0x08007954 + Address: 0x08007958 + Address: 0x0800795C + Address: 0x08007960 + Address: 0x08007964 + Address: 0x08007968 + Address: 0x0800796C + Address: 0x08007970 + Address: 0x08007994 + Address: 0x08007998 + Address: 0x0800799C + Address: 0x080079A0 + Address: 0x080079A4 + Address: 0x080079A8 + Address: 0x080079AC + Address: 0x080079B0 + Address: 0x080079B4 + Address: 0x080079B8 + Address: 0x080079BC + Address: 0x080079C0 + Address: 0x080079C4 + Address: 0x080079C8 + Address: 0x080079CC + Address: 0x080079D0 + Address: 0x080079D4 + Address: 0x080079D8 + Address: 0x080079DC + Address: 0x080079E0 + Address: 0x080079EC + Address: 0x080079F0 + Address: 0x080079F4 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0x08007ACC + Address: 0x08007AD0 + Address: 0x08007AD4 + Address: 0x08007AD8 + Address: 0x08007ADC + Address: 0x08007AE0 + Address: 0x08007AE4 + Address: 0x08007B0C + Address: 0x08007B10 + Address: 0x08007B14 + Address: 0x08007B18 + Address: 0x08007B1C + Address: 0x08007B20 + Address: 0x08007B24 + Address: 0x08007B28 + Address: 0x08007B2C + Address: 0x08007B30 + Address: 0x08007B34 + Address: 0x08007B38 + Address: 0x08007B3C + Address: 0x08007B40 + Address: 0x08007B44 + Address: 0x08007B48 + Address: 0x08007B4C + Address: 0x08007B50 + Address: 0x08007B54 + Address: 0x08007B58 + Address: 0x08007B5C + Address: 0x08007B64 + Address: 0x08007B68 + Address: 0x08007B6C + Address: 0x08007B70 + Address: 0x08007B74 + Address: 0x08007B78 + Address: 0x08007B7C + Address: 0x08007B80 + Address: 0x08007B84 + Address: 0x08007B88 + Address: 0x08007B8C + Address: 0x08007B90 + Address: 0x08007B94 + Address: 0x08007B98 + Address: 0x08007B9C + Address: 0x08007BA0 + Address: 0x08007BA4 + Address: 0x08007BC0 + Address: 0x08007BC4 + Address: 0x08007BC8 + Address: 0x08007BCC + Address: 0x08007BD0 + Address: 0x08007BD4 + Address: 0x08007BD8 + Address: 0x08007BDC + Address: 0x08007BE0 + Address: 0x08007BE4 + Address: 0x08007BE8 + Address: 0x08007BEC + Address: 0x08007BF0 + Address: 0x08007BF4 + Address: 0x08007BF8 + Address: 0x08007BFC + Address: 0x08007C00 + Address: 0x08007C04 + Address: 0x08007C08 + Address: 0x08007C0C + Address: 0x08007C14 + Address: 0x08007C18 + Address: 0x08007C1C + Address: 0x08007C20 + Address: 0x08007C24 + Address: 0x08007C28 + Address: 0x08007C2C + Address: 0x08007C30 + Address: 0x08007C34 + Address: 0x08007C38 + Address: 0x08007C3C + Address: 0x08007C40 + Address: 0x08007C44 + Address: 0x08007C48 + Address: 0x08007C4C + Address: 0x08007C50 + Address: 0x08007C54 + Address: 0x08007C7C + Address: 0x08007C80 + Address: 0x08007C84 + Address: 0x08007C88 + Address: 0x08007C8C + Address: 0x08007C90 + Address: 0x08007C94 + Address: 0x08007C98 + Address: 0x08007C9C + Address: 0x08007CA0 + Address: 0x08007CA4 + Address: 0x08007CA8 + Address: 0x08007CAC + Address: 0x08007CB0 + Address: 0x08007CB4 + Address: 0x08007CB8 + Address: 0x08007CBC + Address: 0x08007CC0 + Address: 0x08007CC4 + Address: 0x08007CC8 + Address: 0x08007CCC + Address: 0x08007CD4 + Address: 0x08007CD8 + Address: 0x08007CDC + Address: 0x08007CE0 + Address: 0x08007CE4 + Address: 0x08007CE8 + Address: 0x08007CEC + Address: 0x08007CF0 + Address: 0x08007CF4 + Address: 0x08007CF8 + Address: 0x08007CFC + Address: 0x08007D00 + Address: 0x08007D04 + Address: 0x08007D08 + Address: 0x08007D0C + Address: 0x08007D10 + Address: 0x08007D14 + Address: 0x08007D38 + Address: 0x08007D3C + Address: 0x08007D40 + Address: 0x08007D44 + Address: 0x08007D48 + Address: 0x08007D4C + Address: 0x08007D50 + Address: 0x08007D54 + Address: 0x08007D58 + Address: 0x08007D5C + Address: 0x08007D60 + Address: 0x08007D64 + Address: 0x08007D68 + Address: 0x08007D6C + Address: 0x08007D70 + Address: 0x08007D74 + Address: 0x08007D78 + Address: 0x08007D7C + Address: 0x08007D80 + Address: 0x08007D84 + Address: 0x08007D88 + Address: 0x08007D8C + Address: 0x08007D90 + Address: 0x08007D94 + Address: 0x08007D98 + Address: 0x08007D9C + Address: 0x08007DA0 + Address: 0x08007DA4 + Address: 0x08007DA8 + Address: 0x08007DAC + Address: 0x08007DB0 + Address: 0x08007DB4 + Address: 0x08007DB8 + Address: 0x08007DBC + Address: 0x08007DC0 + Address: 0x08007DC4 + Address: 0x08007DC8 + Address: 0x08007DEC + Address: 0x08007DF0 + Address: 0x08007DF4 + Address: 0x08007DF8 + Address: 0x08007DFC + Address: 0x08007E00 + Address: 0x08007E04 + Address: 0x08007E08 + Address: 0x08007E0C + Address: 0x08007E10 + Address: 0x08007E14 + Address: 0x08007E18 + Address: 0x08007E1C + Address: 0x08007E20 + Address: 0x08007E24 + Address: 0x08007E28 + Address: 0x08007E2C + Address: 0x08007E30 + Address: 0x08007E34 + Address: 0x08007E38 + Address: 0x08007E3C + Address: 0x08007E44 + Address: 0x08007E48 + Address: 0x08007E4C + Address: 0x08007E50 + Address: 0x08007E54 + Address: 0x08007E58 + Address: 0x08007E5C + Address: 0x08007E60 + Address: 0x08007E64 + Address: 0x08007E68 + Address: 0x08007E6C + Address: 0x08007E70 + Address: 0x08007E74 + Address: 0x08007E78 + Address: 0x08007E7C + Address: 0x08007E80 + Address: 0x08007E84 + Address: 0x08007EA8 + Address: 0x08007EAC + Address: 0x08007EB0 + Address: 0x08007EB4 + Address: 0x08007EB8 + Address: 0x08007EBC + Address: 0x08007EC0 + Address: 0x08007EC4 + Address: 0x08007EC8 + Address: 0x08007ECC + Address: 0x08007ED0 + Address: 0x08007ED4 + Address: 0x08007ED8 + Address: 0x08007EDC + Address: 0x08007EE0 + Address: 0x08007EE4 + Address: 0x08007EE8 + Address: 0x08007EEC + Address: 0x08007EF0 + Address: 0x08007EF4 + Address: 0x08007EF8 + Address: 0x08007EFC + Address: 0x08007F00 + Address: 0x08007F04 + Address: 0x08007F08 + Address: 0x08007F0C + Address: 0x08007F10 + Address: 0x08007F14 + Address: 0x08007F18 + Address: 0x08007F1C + Address: 0x08007F20 + Address: 0x08007F24 + Address: 0x08007F28 + Address: 0x08007F2C + Address: 0x08007F30 + Address: 0x08007F34 + Address: 0x08007F38 + Address: 0x08007F68 + Address: 0x08007F6C + Address: 0x08007F70 + Address: 0x08007F74 + Address: 0x08007F78 + Address: 0x08007F7C + Address: 0x08007F80 + Address: 0x08007F84 + Address: 0x08007F88 + Address: 0x08007F8C + Address: 0x08007F90 + Address: 0x08007F94 + Address: 0x08007F98 + Address: 0x08007F9C + Address: 0x08007FA0 + Address: 0x08007FA4 + Address: 0x08007FA8 + Address: 0x08007FAC + Address: 0x08007FB0 + Address: 0x08007FB4 + Address: 0x08007FB8 + Address: 0x08007FBC + Address: 0x08007FC0 + Address: 0x08007FC4 + Address: 0x08007FC8 + Address: 0x08007FCC + Address: 0x08007FD0 + Address: 0x08007FD4 + Address: 0x08007FD8 + Address: 0x08007FDC + Address: 0x08007FE0 + Address: 0x08007FE4 + Address: 0x08007FE8 + Address: 0x08007FEC + Address: 0x08007FF0 + Address: 0x08007FF4 + Address: 0x08007FF8 + Address: 0x08007FFC + Address: 0x0800801C + Address: 0x08008020 + Address: 0x08008024 + Address: 0x08008028 + Address: 0x0800802C + Address: 0x08008030 + Address: 0x08008034 + Address: 0x08008038 + Address: 0x0800803C + Address: 0x08008040 + Address: 0x08008044 + Address: 0x08008048 + Address: 0x0800804C + Address: 0x08008050 + Address: 0x08008054 + Address: 0x08008058 + Address: 0x0800805C + Address: 0x08008060 + Address: 0x08008064 + Address: 0x08008068 + Address: 0x08008070 + Address: 0x08008074 + Address: 0x08008078 + Address: 0x0800807C + Address: 0x08008080 + Address: 0x08008084 + Address: 0x08008088 + Address: 0x0800808C + Address: 0x08008090 + Address: 0x08008094 + Address: 0x08008098 + Address: 0x0800809C + Address: 0x080080A0 + Address: 0x080080A4 + Address: 0x080080A8 + Address: 0x080080AC + Address: 0x080080B0 + Address: 0x080080D8 + Address: 0x080080DC + Address: 0x080080E0 + Address: 0x080080E4 + Address: 0x080080E8 + Address: 0x080080EC + Address: 0x080080F0 + Address: 0x080080F4 + Address: 0x080080F8 + Address: 0x080080FC + Address: 0x08008100 + Address: 0x08008104 + Address: 0x08008108 + Address: 0x0800810C + Address: 0x08008110 + Address: 0x08008114 + Address: 0x08008118 + Address: 0x0800811C + Address: 0x08008120 + Address: 0x08008124 + Address: 0x08008128 + Address: 0x08008130 + Address: 0x08008134 + Address: 0x08008138 + Address: 0x0800813C + Address: 0x08008140 + Address: 0x08008144 + Address: 0x08008148 + Address: 0x0800814C + Address: 0x08008150 + Address: 0x08008154 + Address: 0x08008158 + Address: 0x0800815C + Address: 0x08008160 + Address: 0x08008164 + Address: 0x08008168 + Address: 0x0800816C + Address: 0x08008170 + Address: 0x08008198 + Address: 0x0800819C + Address: 0x080081A0 + Address: 0x080081A4 + Address: 0x080081A8 + Address: 0x080081AC + Address: 0x080081B0 + Address: 0x080081B4 + Address: 0x080081B8 + Address: 0x080081BC + Address: 0x080081C0 + Address: 0x080081C4 + Address: 0x080081C8 + Address: 0x080081CC + Address: 0x080081D0 + Address: 0x080081D4 + Address: 0x080081D8 + Address: 0x080081DC + Address: 0x080081E0 + Address: 0x080081E4 + Address: 0x080081E8 + Address: 0x080081EC + Address: 0x080081F0 + Address: 0x080081F4 + Address: 0x080081F8 + Address: 0x080081FC + Address: 0x08008200 + Address: 0x08008204 + Address: 0x08008208 + Address: 0x0800820C + Address: 0x08008210 + Address: 0x08008214 + Address: 0x08008218 + Address: 0x0800821C + Address: 0x08008220 + Address: 0x08008224 + Address: 0x08008228 + Address: 0x0800824C + Address: 0x08008250 + Address: 0x08008254 + Address: 0x08008258 + Address: 0x0800825C + Address: 0x08008260 + Address: 0x08008264 + Address: 0x08008268 + Address: 0x0800826C + Address: 0x08008270 + Address: 0x08008274 + Address: 0x08008278 + Address: 0x0800827C + Address: 0x08008280 + Address: 0x08008284 + Address: 0x08008288 + Address: 0x0800828C + Address: 0x08008290 + Address: 0x08008294 + Address: 0x08008298 + Address: 0x080082A8 + Address: 0x080082AC + Address: 0x080082B0 + Address: 0x080082B4 + Address: 0x080082B8 + Address: 0x080082BC + Address: 0x080082C0 + Address: 0x080082C4 + Address: 0x080082C8 + Address: 0x080082CC + Address: 0x080082D0 + Address: 0x080082D4 + Address: 0x080082D8 + Address: 0x080082DC + Address: 0x080082E0 + Address: 0x080082E4 + Address: 0x080082E8 + Address: 0x080082EC + Address: 0x08008304 + Address: 0x08008308 + Address: 0x0800830C + Address: 0x08008310 + Address: 0x08008314 + Address: 0x08008318 + Address: 0x0800831C + Address: 0x08008320 + Address: 0x08008324 + Address: 0x08008328 + Address: 0x0800832C + Address: 0x08008330 + Address: 0x08008334 + Address: 0x08008338 + Address: 0x0800833C + Address: 0x08008340 + Address: 0x08008344 + Address: 0x08008348 + Address: 0x0800834C + Address: 0x0800835C + Address: 0x08008360 + Address: 0x08008364 + Address: 0x08008368 + Address: 0x0800836C + Address: 0x08008370 + Address: 0x08008374 + Address: 0x08008378 + Address: 0x0800837C + Address: 0x08008380 + Address: 0x08008384 + Address: 0x08008388 + Address: 0x0800838C + Address: 0x08008390 + Address: 0x08008394 + Address: 0x08008398 + Address: 0x0800839C + Address: 0x080083A0 + Address: 0x080083BC + Address: 0x080083C0 + Address: 0x080083C4 + Address: 0x080083C8 + Address: 0x080083CC + Address: 0x080083D0 + Address: 0x080083D4 + Address: 0x080083D8 + Address: 0x080083DC + Address: 0x080083E0 + Address: 0x080083E4 + Address: 0x080083E8 + Address: 0x080083EC + Address: 0x080083F0 + Address: 0x080083F4 + Address: 0x080083F8 + Address: 0x080083FC + Address: 0x08008400 + Address: 0x08008404 + Address: 0x08008408 + Address: 0x08008418 + Address: 0x0800841C + Address: 0x08008420 + Address: 0x08008424 + Address: 0x08008428 + Address: 0x0800842C + Address: 0x08008430 + Address: 0x08008434 + Address: 0x08008438 + Address: 0x0800843C + Address: 0x08008440 + Address: 0x08008444 + Address: 0x08008448 + Address: 0x0800844C + Address: 0x08008450 + Address: 0x08008454 + Address: 0x08008458 + Address: 0x0800845C + Address: 0x0800847C + Address: 0x08008480 + Address: 0x08008484 + Address: 0x08008488 + Address: 0x0800848C + Address: 0x08008490 + Address: 0x08008494 + Address: 0x08008498 + Address: 0x0800849C + Address: 0x080084A0 + Address: 0x080084A4 + Address: 0x080084A8 + Address: 0x080084AC + Address: 0x080084B0 + Address: 0x080084B4 + Address: 0x080084B8 + Address: 0x080084BC + Address: 0x080084C0 + Address: 0x080084C4 + Address: 0x080084C8 + Address: 0x080084D4 + Address: 0x080084D8 + Address: 0x080084DC + Address: 0x080084E0 + Address: 0x080084E4 + Address: 0x080084E8 + Address: 0x080084EC + Address: 0x080084F0 + Address: 0x080084F4 + Address: 0x080084F8 + Address: 0x080084FC + Address: 0x08008500 + Address: 0x08008504 + Address: 0x08008508 + Address: 0x0800850C + Address: 0x08008510 + Address: 0x08008514 + Address: 0x08008518 + Address: 0x08008530 + Address: 0x08008534 + Address: 0x08008538 + Address: 0x0800853C + Address: 0x08008540 + Address: 0x08008544 + Address: 0x08008548 + Address: 0x0800854C + Address: 0x08008550 + Address: 0x08008554 + Address: 0x08008558 + Address: 0x0800855C + Address: 0x08008560 + Address: 0x08008564 + Address: 0x08008568 + Address: 0x0800856C + Address: 0x08008570 + Address: 0x08008574 + Address: 0x08008578 + Address: 0x08008590 + Address: 0x08008594 + Address: 0x08008598 + Address: 0x0800859C + Address: 0x080085A0 + Address: 0x080085A4 + Address: 0x080085A8 + Address: 0x080085AC + Address: 0x080085B0 + Address: 0x080085B4 + Address: 0x080085B8 + Address: 0x080085BC + Address: 0x080085C0 + Address: 0x080085C4 + Address: 0x080085C8 + Address: 0x080085CC + Address: 0x080085D0 + Address: 0x080085D4 + Address: 0x080085D8 + Address: 0x080085F0 + Address: 0x080085F4 + Address: 0x080085F8 + Address: 0x080085FC + Address: 0x08008600 + Address: 0x08008604 + Address: 0x08008608 + Address: 0x0800860C + Address: 0x08008610 + Address: 0x08008614 + Address: 0x08008618 + Address: 0x0800861C + Address: 0x08008620 + Address: 0x08008624 + Address: 0x08008628 + Address: 0x0800862C + Address: 0x08008630 + Address: 0x08008634 + Address: 0x08008638 + Address: 0x0800864C + Address: 0x08008650 + Address: 0x08008654 + Address: 0x08008658 + Address: 0x0800865C + Address: 0x08008660 + Address: 0x08008664 + Address: 0x08008668 + Address: 0x0800866C + Address: 0x08008670 + Address: 0x08008674 + Address: 0x08008678 + Address: 0x0800867C + Address: 0x08008680 + Address: 0x08008684 + Address: 0x08008688 + Address: 0x0800868C + Address: 0x08008690 + Address: 0x08008694 + Address: 0x080086A4 + Address: 0x080086A8 + Address: 0x080086AC + Address: 0x080086B0 + Address: 0x080086B4 + Address: 0x080086B8 + Address: 0x080086BC + Address: 0x080086C0 + Address: 0x080086C4 + Address: 0x080086C8 + Address: 0x080086CC + Address: 0x080086D0 + Address: 0x080086D4 + Address: 0x080086D8 + Address: 0x080086DC + Address: 0x080086E0 + Address: 0x080086E4 + Address: 0x080086E8 + Address: 0x08008708 + Address: 0x0800870C + Address: 0x08008710 + Address: 0x08008714 + Address: 0x08008718 + Address: 0x0800871C + Address: 0x08008720 + Address: 0x08008724 + Address: 0x08008728 + Address: 0x0800872C + Address: 0x08008730 + Address: 0x08008734 + Address: 0x08008738 + Address: 0x0800873C + Address: 0x08008740 + Address: 0x08008744 + Address: 0x08008748 + Address: 0x0800874C + Address: 0x08008750 + Address: 0x08008754 + Address: 0x08008764 + Address: 0x08008768 + Address: 0x0800876C + Address: 0x08008770 + Address: 0x08008774 + Address: 0x08008778 + Address: 0x0800877C + Address: 0x08008780 + Address: 0x08008784 + Address: 0x08008788 + Address: 0x0800878C + Address: 0x08008790 + Address: 0x08008794 + Address: 0x08008798 + Address: 0x0800879C + Address: 0x080087A0 + Address: 0x080087A4 + Address: 0x080087A8 + Address: 0x080087C0 + Address: 0x080087C4 + Address: 0x080087C8 + Address: 0x080087CC + Address: 0x080087D0 + Address: 0x080087D4 + Address: 0x080087D8 + Address: 0x080087DC + Address: 0x080087E0 + Address: 0x080087E4 + Address: 0x080087E8 + Address: 0x080087EC + Address: 0x080087F0 + Address: 0x080087F4 + Address: 0x080087F8 + Address: 0x080087FC + Address: 0x08008800 + Address: 0x08008804 + Address: 0x08008808 + Address: 0x08008818 + Address: 0x0800881C + Address: 0x08008820 + Address: 0x08008824 + Address: 0x08008828 + Address: 0x0800882C + Address: 0x08008830 + Address: 0x08008834 + Address: 0x08008838 + Address: 0x0800883C + Address: 0x08008840 + Address: 0x08008844 + Address: 0x08008848 + Address: 0x0800884C + Address: 0x08008850 + Address: 0x08008854 + Address: 0x08008858 + Address: 0x0800885C + Address: 0x0800887C + Address: 0x08008880 + Address: 0x08008884 + Address: 0x08008888 + Address: 0x0800888C + Address: 0x08008890 + Address: 0x08008894 + Address: 0x08008898 + Address: 0x0800889C + Address: 0x080088A0 + Address: 0x080088A4 + Address: 0x080088A8 + Address: 0x080088AC + Address: 0x080088B0 + Address: 0x080088B4 + Address: 0x080088B8 + Address: 0x080088BC + Address: 0x080088C0 + Address: 0x080088C4 + Address: 0x080088C8 + Address: 0x080088D0 + Address: 0x080088D4 + Address: 0x080088D8 + Address: 0x080088DC + Address: 0x080088E0 + Address: 0x080088E4 + Address: 0x080088E8 + Address: 0x080088EC + Address: 0x080088F0 + Address: 0x080088F4 + Address: 0x080088F8 + Address: 0x080088FC + Address: 0x08008900 + Address: 0x08008904 + Address: 0x08008908 + Address: 0x0800890C + Address: 0x08008910 + Address: 0x08008938 + Address: 0x0800893C + Address: 0x08008940 + Address: 0x08008944 + Address: 0x08008948 + Address: 0x0800894C + Address: 0x08008950 + Address: 0x08008954 + Address: 0x08008958 + Address: 0x0800895C + Address: 0x08008960 + Address: 0x08008964 + Address: 0x08008968 + Address: 0x0800896C + Address: 0x08008970 + Address: 0x08008974 + Address: 0x08008978 + Address: 0x0800897C + Address: 0x08008980 + Address: 0x08008984 + Address: 0x08008988 + Address: 0x0800898C + Address: 0x08008990 + Address: 0x08008994 + Address: 0x08008998 + Address: 0x0800899C + Address: 0x080089A0 + Address: 0x080089A4 + Address: 0x080089A8 + Address: 0x080089AC + Address: 0x080089B0 + Address: 0x080089B4 + Address: 0x080089B8 + Address: 0x080089BC + Address: 0x080089C0 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0x08008AB8 + Address: 0x08008ABC + Address: 0x08008AC0 + Address: 0x08008AC4 + Address: 0x08008AC8 + Address: 0x08008ACC + Address: 0x08008AD0 + Address: 0x08008AD4 + Address: 0x08008AD8 + Address: 0x08008ADC + Address: 0x08008AE0 + Address: 0x08008AE4 + Address: 0x08008AE8 + Address: 0x08008AEC + Address: 0x08008AF0 + Address: 0x08008AF4 + Address: 0x08008B00 + Address: 0x08008B04 + Address: 0x08008B08 + Address: 0x08008B0C + Address: 0x08008B10 + Address: 0x08008B14 + Address: 0x08008B18 + Address: 0x08008B1C + Address: 0x08008B20 + Address: 0x08008B24 + Address: 0x08008B28 + Address: 0x08008B2C + Address: 0x08008B30 + Address: 0x08008B34 + Address: 0x08008B38 + Address: 0x08008B3C + Address: 0x08008B40 + Address: 0x08008B44 + Address: 0x08008B5C + Address: 0x08008B60 + Address: 0x08008B64 + Address: 0x08008B68 + Address: 0x08008B6C + Address: 0x08008B70 + Address: 0x08008B74 + Address: 0x08008B78 + Address: 0x08008B7C + Address: 0x08008B80 + Address: 0x08008B84 + Address: 0x08008B88 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0x08008C74 + Address: 0x08008C78 + Address: 0x08008C7C + Address: 0x08008C80 + Address: 0x08008C84 + Address: 0x08008C88 + Address: 0x08008C8C + Address: 0x08008C90 + Address: 0x08008C94 + Address: 0x08008C98 + Address: 0x08008C9C + Address: 0x08008CA0 + Address: 0x08008CA4 + Address: 0x08008CA8 + Address: 0x08008CAC + Address: 0x08008CB0 + Address: 0x08008CB4 + Address: 0x08008CB8 + Address: 0x08008CD4 + Address: 0x08008CD8 + Address: 0x08008CDC + Address: 0x08008CE0 + Address: 0x08008CE4 + Address: 0x08008CE8 + Address: 0x08008CEC + Address: 0x08008CF0 + Address: 0x08008CF4 + Address: 0x08008CF8 + Address: 0x08008CFC + Address: 0x08008D00 + Address: 0x08008D04 + Address: 0x08008D08 + Address: 0x08008D0C + Address: 0x08008D10 + Address: 0x08008D14 + Address: 0x08008D18 + Address: 0x08008D1C + Address: 0x08008D34 + Address: 0x08008D38 + Address: 0x08008D3C + Address: 0x08008D40 + Address: 0x08008D44 + Address: 0x08008D48 + Address: 0x08008D4C + Address: 0x08008D50 + Address: 0x08008D54 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0x08008E2C + Address: 0x08008E30 + Address: 0x08008E48 + Address: 0x08008E4C + Address: 0x08008E50 + Address: 0x08008E54 + Address: 0x08008E58 + Address: 0x08008E5C + Address: 0x08008E60 + Address: 0x08008E64 + Address: 0x08008E68 + Address: 0x08008E6C + Address: 0x08008E70 + Address: 0x08008E74 + Address: 0x08008E78 + Address: 0x08008E7C + Address: 0x08008E80 + Address: 0x08008E84 + Address: 0x08008E88 + Address: 0x08008E8C + Address: 0x08008E90 + Address: 0x08008EA8 + Address: 0x08008EAC + Address: 0x08008EB0 + Address: 0x08008EB4 + Address: 0x08008EB8 + Address: 0x08008EBC + Address: 0x08008EC0 + Address: 0x08008EC4 + Address: 0x08008EC8 + Address: 0x08008ECC + Address: 0x08008ED0 + Address: 0x08008ED4 + Address: 0x08008ED8 + Address: 0x08008EDC + Address: 0x08008EE0 + Address: 0x08008EE4 + Address: 0x08008EE8 + Address: 0x08008EEC + Address: 0x08008EF0 + Address: 0x08008F04 + Address: 0x08008F08 + Address: 0x08008F0C + Address: 0x08008F10 + Address: 0x08008F14 + Address: 0x08008F18 + Address: 0x08008F1C + Address: 0x08008F20 + Address: 0x08008F24 + Address: 0x08008F28 + Address: 0x08008F2C + Address: 0x08008F30 + Address: 0x08008F34 + Address: 0x08008F38 + Address: 0x08008F3C + Address: 0x08008F40 + Address: 0x08008F44 + Address: 0x08008F48 + Address: 0x08008F4C + Address: 0x08008F64 + Address: 0x08008F68 + Address: 0x08008F6C + Address: 0x08008F70 + Address: 0x08008F74 + Address: 0x08008F78 + Address: 0x08008F7C + Address: 0x08008F80 + Address: 0x08008F84 + Address: 0x08008F88 + Address: 0x08008F8C + Address: 0x08008F90 + Address: 0x08008F94 + Address: 0x08008F98 + Address: 0x08008F9C + Address: 0x08008FA0 + Address: 0x08008FA4 + Address: 0x08008FA8 + Address: 0x08008FAC + Address: 0x08008FB8 + Address: 0x08008FBC + Address: 0x08008FC0 + Address: 0x08008FC4 + Address: 0x08008FC8 + Address: 0x08008FCC + Address: 0x08008FD0 + Address: 0x08008FD4 + Address: 0x08008FD8 + Address: 0x08008FDC + Address: 0x08008FE0 + Address: 0x08008FE4 + Address: 0x08008FE8 + Address: 0x08008FEC + Address: 0x08008FF0 + Address: 0x08008FF4 + Address: 0x08008FF8 + Address: 0x08008FFC + Address: 0x0800901C + Address: 0x08009020 + Address: 0x08009024 + Address: 0x08009028 + Address: 0x0800902C + Address: 0x08009030 + Address: 0x08009034 + Address: 0x08009038 + Address: 0x0800903C + Address: 0x08009040 + Address: 0x08009044 + Address: 0x08009048 + Address: 0x0800904C + Address: 0x08009050 + Address: 0x08009054 + Address: 0x08009058 + Address: 0x0800905C + Address: 0x08009060 + Address: 0x08009064 + Address: 0x08009068 + Address: 0x08009074 + Address: 0x08009078 + Address: 0x0800907C + Address: 0x08009080 + Address: 0x08009084 + Address: 0x08009088 + Address: 0x0800908C + Address: 0x08009090 + Address: 0x08009094 + Address: 0x08009098 + Address: 0x0800909C + Address: 0x080090A0 + Address: 0x080090A4 + Address: 0x080090A8 + Address: 0x080090AC + Address: 0x080090B0 + Address: 0x080090B4 + Address: 0x080090B8 + Address: 0x080090D8 + Address: 0x080090DC + Address: 0x080090E0 + Address: 0x080090E4 + Address: 0x080090E8 + Address: 0x080090EC + Address: 0x080090F0 + Address: 0x080090F4 + Address: 0x080090F8 + Address: 0x080090FC + Address: 0x08009100 + Address: 0x08009104 + Address: 0x08009108 + Address: 0x0800910C + Address: 0x08009110 + Address: 0x08009114 + Address: 0x08009118 + Address: 0x0800911C + Address: 0x08009120 + Address: 0x08009124 + Address: 0x08009128 + Address: 0x0800912C + Address: 0x08009130 + Address: 0x08009134 + Address: 0x08009138 + Address: 0x0800913C + Address: 0x08009140 + Address: 0x08009144 + Address: 0x08009148 + Address: 0x0800914C + Address: 0x08009150 + Address: 0x08009154 + Address: 0x08009158 + Address: 0x0800915C + Address: 0x08009160 + Address: 0x08009164 + Address: 0x08009168 + Address: 0x08009194 + Address: 0x08009198 + Address: 0x0800919C + Address: 0x080091A0 + Address: 0x080091A4 + Address: 0x080091A8 + Address: 0x080091AC + Address: 0x080091B0 + Address: 0x080091B4 + Address: 0x080091B8 + Address: 0x080091BC + Address: 0x080091C0 + Address: 0x080091C4 + Address: 0x080091C8 + Address: 0x080091CC + Address: 0x080091D0 + Address: 0x080091D4 + Address: 0x080091D8 + Address: 0x080091DC + Address: 0x080091E0 + Address: 0x080091E4 + Address: 0x080091E8 + Address: 0x080091EC + Address: 0x080091F0 + Address: 0x080091F4 + Address: 0x080091F8 + Address: 0x080091FC + Address: 0x08009200 + Address: 0x08009204 + Address: 0x08009208 + Address: 0x0800920C + Address: 0x08009210 + Address: 0x08009214 + Address: 0x08009218 + Address: 0x0800921C + Address: 0x08009220 + Address: 0x08009224 + Address: 0x08009228 + Address: 0x08009250 + Address: 0x08009254 + Address: 0x08009258 + Address: 0x0800925C + Address: 0x08009260 + Address: 0x08009264 + Address: 0x08009268 + Address: 0x0800926C + Address: 0x08009270 + Address: 0x08009274 + Address: 0x08009278 + Address: 0x0800927C + Address: 0x08009280 + Address: 0x08009284 + Address: 0x08009288 + Address: 0x0800928C + Address: 0x08009290 + Address: 0x08009294 + Address: 0x08009298 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0x08009378 + Address: 0x0800937C + Address: 0x08009380 + Address: 0x08009384 + Address: 0x08009388 + Address: 0x0800938C + Address: 0x08009390 + Address: 0x08009394 + Address: 0x08009398 + Address: 0x0800939C + Address: 0x080093A0 + Address: 0x080093BC + Address: 0x080093C0 + Address: 0x080093C4 + Address: 0x080093C8 + Address: 0x080093CC + Address: 0x080093D0 + Address: 0x080093D4 + Address: 0x080093D8 + Address: 0x080093DC + Address: 0x080093E0 + Address: 0x080093E4 + Address: 0x080093E8 + Address: 0x080093EC + Address: 0x080093F0 + Address: 0x080093F4 + Address: 0x080093F8 + Address: 0x080093FC + Address: 0x08009400 + Address: 0x08009404 + Address: 0x08009408 + Address: 0x08009410 + Address: 0x08009414 + Address: 0x08009418 + Address: 0x0800941C + Address: 0x08009420 + Address: 0x08009424 + Address: 0x08009428 + Address: 0x0800942C + Address: 0x08009430 + Address: 0x08009434 + Address: 0x08009438 + Address: 0x0800943C + Address: 0x08009440 + Address: 0x08009444 + Address: 0x08009448 + Address: 0x0800944C + Address: 0x08009450 + Address: 0x08009470 + Address: 0x08009474 + Address: 0x08009478 + Address: 0x0800947C + Address: 0x08009480 + Address: 0x08009484 + Address: 0x08009488 + Address: 0x0800948C + Address: 0x08009490 + Address: 0x08009494 + Address: 0x08009498 + Address: 0x0800949C + Address: 0x080094A0 + Address: 0x080094A4 + Address: 0x080094A8 + Address: 0x080094AC + Address: 0x080094B0 + Address: 0x080094B4 + Address: 0x080094B8 + Address: 0x080094BC + Address: 0x080094CC + Address: 0x080094D0 + Address: 0x080094D4 + Address: 0x080094D8 + Address: 0x080094DC + Address: 0x080094E0 + Address: 0x080094E4 + Address: 0x080094E8 + Address: 0x080094EC + Address: 0x080094F0 + Address: 0x080094F4 + Address: 0x080094F8 + Address: 0x080094FC + Address: 0x08009500 + Address: 0x08009504 + Address: 0x08009508 + Address: 0x0800950C + Address: 0x08009510 + Address: 0x08009530 + Address: 0x08009534 + Address: 0x08009538 + Address: 0x0800953C + Address: 0x08009540 + Address: 0x08009544 + Address: 0x08009548 + Address: 0x0800954C + Address: 0x08009550 + Address: 0x08009554 + Address: 0x08009558 + Address: 0x0800955C + Address: 0x08009560 + Address: 0x08009564 + Address: 0x08009568 + Address: 0x0800956C + Address: 0x08009570 + Address: 0x08009574 + Address: 0x08009578 + Address: 0x0800957C + Address: 0x0800958C + Address: 0x08009590 + Address: 0x08009594 + Address: 0x08009598 + Address: 0x0800959C + Address: 0x080095A0 + Address: 0x080095A4 + Address: 0x080095A8 + Address: 0x080095AC + Address: 0x080095B0 + Address: 0x080095B4 + Address: 0x080095B8 + Address: 0x080095BC + Address: 0x080095C0 + Address: 0x080095C4 + Address: 0x080095C8 + Address: 0x080095CC + Address: 0x080095D0 + Address: 0x080095E4 + Address: 0x080095E8 + Address: 0x080095EC + Address: 0x080095F0 + Address: 0x080095F4 + Address: 0x080095F8 + Address: 0x080095FC + Address: 0x08009600 + Address: 0x08009604 + Address: 0x08009608 + Address: 0x0800960C + Address: 0x08009610 + Address: 0x08009614 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0x08009708 + Address: 0x0800970C + Address: 0x08009710 + Address: 0x08009714 + Address: 0x08009718 + Address: 0x0800971C + Address: 0x08009720 + Address: 0x08009724 + Address: 0x08009728 + Address: 0x0800972C + Address: 0x08009730 + Address: 0x08009734 + Address: 0x08009738 + Address: 0x0800973C + Address: 0x08009740 + Address: 0x08009744 + Address: 0x08009748 + Address: 0x0800974C + Address: 0x08009758 + Address: 0x0800975C + Address: 0x08009760 + Address: 0x08009764 + Address: 0x08009768 + Address: 0x0800976C + Address: 0x08009770 + Address: 0x08009774 + Address: 0x08009778 + Address: 0x0800977C + Address: 0x08009780 + Address: 0x08009784 + Address: 0x08009788 + Address: 0x0800978C + Address: 0x08009790 + Address: 0x08009794 + Address: 0x08009798 + Address: 0x0800979C + Address: 0x080097C0 + Address: 0x080097C4 + Address: 0x080097C8 + Address: 0x080097CC + Address: 0x080097D0 + Address: 0x080097D4 + Address: 0x080097D8 + Address: 0x080097DC + Address: 0x080097E0 + Address: 0x080097E4 + Address: 0x080097E8 + Address: 0x080097EC + Address: 0x080097F0 + Address: 0x080097F4 + Address: 0x080097F8 + Address: 0x080097FC + Address: 0x08009800 + Address: 0x08009804 + Address: 0x08009808 + Address: 0x0800980C + Address: 0x0800981C + Address: 0x08009820 + Address: 0x08009824 + Address: 0x08009828 + Address: 0x0800982C + Address: 0x08009830 + Address: 0x08009834 + Address: 0x08009838 + Address: 0x0800983C + Address: 0x08009840 + Address: 0x08009844 + Address: 0x08009848 + Address: 0x0800984C + Address: 0x08009850 + Address: 0x08009854 + Address: 0x08009858 + Address: 0x0800985C + Address: 0x08009860 + Address: 0x08009878 + Address: 0x0800987C + Address: 0x08009880 + Address: 0x08009884 + Address: 0x08009888 + Address: 0x0800988C + Address: 0x08009890 + Address: 0x08009894 + Address: 0x08009898 + Address: 0x0800989C + Address: 0x080098A0 + Address: 0x080098A4 + Address: 0x080098A8 + Address: 0x080098AC + Address: 0x080098B0 + Address: 0x080098B4 + Address: 0x080098B8 + Address: 0x080098BC + Address: 0x080098C0 + Address: 0x080098D0 + Address: 0x080098D4 + Address: 0x080098D8 + Address: 0x080098DC + Address: 0x080098E0 + Address: 0x080098E4 + Address: 0x080098E8 + Address: 0x080098EC + Address: 0x080098F0 + Address: 0x080098F4 + Address: 0x080098F8 + Address: 0x080098FC + Address: 0x08009900 + Address: 0x08009904 + Address: 0x08009908 + Address: 0x0800990C + Address: 0x08009910 + Address: 0x08009914 + Address: 0x08009934 + Address: 0x08009938 + Address: 0x0800993C + Address: 0x08009940 + Address: 0x08009944 + Address: 0x08009948 + Address: 0x0800994C + Address: 0x08009950 + Address: 0x08009954 + Address: 0x08009958 + Address: 0x0800995C + Address: 0x08009960 + Address: 0x08009964 + Address: 0x08009968 + Address: 0x0800996C + Address: 0x08009970 + Address: 0x08009974 + Address: 0x08009978 + Address: 0x0800997C + Address: 0x08009980 + Address: 0x08009990 + Address: 0x08009994 + Address: 0x08009998 + Address: 0x0800999C + Address: 0x080099A0 + Address: 0x080099A4 + Address: 0x080099A8 + Address: 0x080099AC + Address: 0x080099B0 + Address: 0x080099B4 + Address: 0x080099B8 + Address: 0x080099BC + Address: 0x080099C0 + Address: 0x080099C4 + Address: 0x080099C8 + Address: 0x080099CC + Address: 0x080099D0 + Address: 0x080099D4 + Address: 0x080099EC + Address: 0x080099F0 + Address: 0x080099F4 + Address: 0x080099F8 + Address: 0x080099FC + Address: 0x08009A00 + Address: 0x08009A04 + Address: 0x08009A08 + Address: 0x08009A0C + Address: 0x08009A10 + Address: 0x08009A14 + Address: 0x08009A18 + Address: 0x08009A1C + Address: 0x08009A20 + Address: 0x08009A24 + Address: 0x08009A28 + Address: 0x08009A2C + Address: 0x08009A30 + Address: 0x08009A34 + Address: 0x08009A44 + Address: 0x08009A48 + Address: 0x08009A4C + Address: 0x08009A50 + Address: 0x08009A54 + Address: 0x08009A58 + Address: 0x08009A5C + Address: 0x08009A60 + Address: 0x08009A64 + Address: 0x08009A68 + Address: 0x08009A6C + Address: 0x08009A70 + Address: 0x08009A74 + Address: 0x08009A78 + Address: 0x08009A7C + Address: 0x08009A80 + Address: 0x08009A84 + Address: 0x08009A88 + Address: 0x08009AA8 + Address: 0x08009AAC + Address: 0x08009AB0 + Address: 0x08009AB4 + Address: 0x08009AB8 + Address: 0x08009ABC + Address: 0x08009AC0 + Address: 0x08009AC4 + Address: 0x08009AC8 + Address: 0x08009ACC + Address: 0x08009AD0 + Address: 0x08009AD4 + Address: 0x08009AD8 + Address: 0x08009ADC + Address: 0x08009AE0 + Address: 0x08009AE4 + Address: 0x08009AE8 + Address: 0x08009AEC + Address: 0x08009AF0 + Address: 0x08009AF4 + Address: 0x08009B04 + Address: 0x08009B08 + Address: 0x08009B0C + Address: 0x08009B10 + Address: 0x08009B14 + Address: 0x08009B18 + Address: 0x08009B1C + Address: 0x08009B20 + Address: 0x08009B24 + Address: 0x08009B28 + Address: 0x08009B2C + Address: 0x08009B30 + Address: 0x08009B34 + Address: 0x08009B38 + Address: 0x08009B3C + Address: 0x08009B40 + Address: 0x08009B44 + Address: 0x08009B48 + Address: 0x08009B68 + Address: 0x08009B6C + Address: 0x08009B70 + Address: 0x08009B74 + Address: 0x08009B78 + Address: 0x08009B7C + Address: 0x08009B80 + Address: 0x08009B84 + Address: 0x08009B88 + Address: 0x08009B8C + Address: 0x08009B90 + Address: 0x08009B94 + Address: 0x08009B98 + Address: 0x08009B9C + Address: 0x08009BA0 + Address: 0x08009BA4 + Address: 0x08009BA8 + Address: 0x08009BAC + Address: 0x08009BB0 + Address: 0x08009BB4 + Address: 0x08009BB8 + Address: 0x08009BBC + Address: 0x08009BC0 + Address: 0x08009BC4 + Address: 0x08009BC8 + Address: 0x08009BCC + Address: 0x08009BD0 + Address: 0x08009BD4 + Address: 0x08009BD8 + Address: 0x08009BDC + Address: 0x08009BE0 + Address: 0x08009BE4 + Address: 0x08009BE8 + Address: 0x08009BEC + Address: 0x08009BF0 + Address: 0x08009BF4 + Address: 0x08009C24 + Address: 0x08009C28 + Address: 0x08009C2C + Address: 0x08009C30 + Address: 0x08009C34 + Address: 0x08009C38 + Address: 0x08009C3C + Address: 0x08009C40 + Address: 0x08009C44 + Address: 0x08009C48 + Address: 0x08009C4C + Address: 0x08009C50 + Address: 0x08009C54 + Address: 0x08009C58 + Address: 0x08009C5C + Address: 0x08009C60 + Address: 0x08009C64 + Address: 0x08009C68 + Address: 0x08009C6C + Address: 0x08009C70 + Address: 0x08009C74 + Address: 0x08009C78 + Address: 0x08009C7C + Address: 0x08009C80 + Address: 0x08009C84 + Address: 0x08009C88 + Address: 0x08009C8C + Address: 0x08009C90 + Address: 0x08009C94 + Address: 0x08009C98 + Address: 0x08009C9C + Address: 0x08009CA0 + Address: 0x08009CA4 + Address: 0x08009CA8 + Address: 0x08009CAC + Address: 0x08009CB0 + Address: 0x08009CB4 + Address: 0x08009CB8 + Address: 0x08009CD8 + Address: 0x08009CDC + Address: 0x08009CE0 + Address: 0x08009CE4 + Address: 0x08009CE8 + Address: 0x08009CEC + Address: 0x08009CF0 + Address: 0x08009CF4 + Address: 0x08009CF8 + Address: 0x08009CFC + Address: 0x08009D00 + Address: 0x08009D04 + Address: 0x08009D08 + Address: 0x08009D0C + Address: 0x08009D10 + Address: 0x08009D14 + Address: 0x08009D18 + Address: 0x08009D1C + Address: 0x08009D20 + Address: 0x08009D24 + Address: 0x08009D2C + Address: 0x08009D30 + Address: 0x08009D34 + Address: 0x08009D38 + Address: 0x08009D3C + Address: 0x08009D40 + Address: 0x08009D44 + Address: 0x08009D48 + Address: 0x08009D4C + Address: 0x08009D50 + Address: 0x08009D54 + Address: 0x08009D58 + Address: 0x08009D5C + Address: 0x08009D60 + Address: 0x08009D64 + Address: 0x08009D68 + Address: 0x08009D6C + Address: 0x08009D98 + Address: 0x08009D9C + Address: 0x08009DA0 + Address: 0x08009DA4 + Address: 0x08009DA8 + Address: 0x08009DAC + Address: 0x08009DB0 + Address: 0x08009DB4 + Address: 0x08009DB8 + Address: 0x08009DBC + Address: 0x08009DC0 + Address: 0x08009DC4 + Address: 0x08009DC8 + Address: 0x08009DCC + Address: 0x08009DD0 + Address: 0x08009DD4 + Address: 0x08009DD8 + Address: 0x08009DDC + Address: 0x08009DE0 + Address: 0x08009DE4 + Address: 0x08009DE8 + Address: 0x08009DEC + Address: 0x08009DF0 + Address: 0x08009DF4 + Address: 0x08009DF8 + Address: 0x08009DFC + Address: 0x08009E00 + Address: 0x08009E04 + Address: 0x08009E08 + Address: 0x08009E0C + Address: 0x08009E10 + Address: 0x08009E14 + Address: 0x08009E18 + Address: 0x08009E1C + Address: 0x08009E20 + Address: 0x08009E24 + Address: 0x08009E28 + Address: 0x08009E2C + Address: 0x08009E54 + Address: 0x08009E58 + Address: 0x08009E5C + Address: 0x08009E60 + Address: 0x08009E64 + Address: 0x08009E68 + Address: 0x08009E6C + Address: 0x08009E70 + Address: 0x08009E74 + Address: 0x08009E78 + Address: 0x08009E7C + Address: 0x08009E80 + Address: 0x08009E84 + Address: 0x08009E88 + Address: 0x08009E8C + Address: 0x08009E90 + Address: 0x08009E94 + Address: 0x08009E98 + Address: 0x08009E9C + Address: 0x08009EA0 + Address: 0x08009EA4 + Address: 0x08009EA8 + Address: 0x08009EAC + Address: 0x08009EB0 + Address: 0x08009EB4 + Address: 0x08009EB8 + Address: 0x08009EBC + Address: 0x08009EC0 + Address: 0x08009EC4 + Address: 0x08009EC8 + Address: 0x08009ECC + Address: 0x08009ED0 + Address: 0x08009ED4 + Address: 0x08009ED8 + Address: 0x08009EDC + Address: 0x08009EE0 + Address: 0x08009EE4 + Address: 0x08009F08 + Address: 0x08009F0C + Address: 0x08009F10 + Address: 0x08009F14 + Address: 0x08009F18 + Address: 0x08009F1C + Address: 0x08009F20 + Address: 0x08009F24 + Address: 0x08009F28 + Address: 0x08009F2C + Address: 0x08009F30 + Address: 0x08009F34 + Address: 0x08009F38 + Address: 0x08009F3C + Address: 0x08009F40 + Address: 0x08009F44 + Address: 0x08009F48 + Address: 0x08009F4C + Address: 0x08009F50 + Address: 0x08009F54 + Address: 0x08009F60 + Address: 0x08009F64 + Address: 0x08009F68 + Address: 0x08009F6C + Address: 0x08009F70 + Address: 0x08009F74 + Address: 0x08009F78 + Address: 0x08009F7C + Address: 0x08009F80 + Address: 0x08009F84 + Address: 0x08009F88 + Address: 0x08009F8C + Address: 0x08009F90 + Address: 0x08009F94 + Address: 0x08009F98 + Address: 0x08009F9C + Address: 0x08009FA0 + Address: 0x08009FA4 + Address: 0x08009FC4 + Address: 0x08009FC8 + Address: 0x08009FCC + Address: 0x08009FD0 + Address: 0x08009FD4 + Address: 0x08009FD8 + Address: 0x08009FDC + Address: 0x08009FE0 + Address: 0x08009FE4 + Address: 0x08009FE8 + Address: 0x08009FEC + Address: 0x08009FF0 + Address: 0x08009FF4 + Address: 0x08009FF8 + Address: 0x08009FFC + Address: 0x0800A000 + Address: 0x0800A004 + Address: 0x0800A008 + Address: 0x0800A00C + Address: 0x0800A010 + Address: 0x0800A014 + Address: 0x0800A018 + Address: 0x0800A01C + Address: 0x0800A020 + Address: 0x0800A024 + Address: 0x0800A028 + Address: 0x0800A02C + Address: 0x0800A030 + Address: 0x0800A034 + Address: 0x0800A038 + Address: 0x0800A03C + Address: 0x0800A040 + Address: 0x0800A044 + Address: 0x0800A048 + Address: 0x0800A04C + Address: 0x0800A050 + Address: 0x0800A054 + Address: 0x0800A080 + Address: 0x0800A084 + Address: 0x0800A088 + Address: 0x0800A08C + Address: 0x0800A090 + Address: 0x0800A094 + Address: 0x0800A098 + Address: 0x0800A09C + Address: 0x0800A0A0 + Address: 0x0800A0A4 + Address: 0x0800A0A8 + Address: 0x0800A0AC + Address: 0x0800A0B0 + Address: 0x0800A0B4 + Address: 0x0800A0B8 + Address: 0x0800A0BC + Address: 0x0800A0C0 + Address: 0x0800A0C4 + Address: 0x0800A0C8 + Address: 0x0800A0CC + Address: 0x0800A0D0 + Address: 0x0800A0D4 + Address: 0x0800A0D8 + Address: 0x0800A0DC + Address: 0x0800A0E0 + Address: 0x0800A0E4 + Address: 0x0800A0E8 + Address: 0x0800A0EC + Address: 0x0800A0F0 + Address: 0x0800A0F4 + Address: 0x0800A0F8 + Address: 0x0800A0FC + Address: 0x0800A100 + Address: 0x0800A104 + Address: 0x0800A108 + Address: 0x0800A10C + Address: 0x0800A110 + Address: 0x0800A114 + Address: 0x0800A13C + Address: 0x0800A140 + Address: 0x0800A144 + Address: 0x0800A148 + Address: 0x0800A14C + Address: 0x0800A150 + Address: 0x0800A154 + Address: 0x0800A158 + Address: 0x0800A15C + Address: 0x0800A160 + Address: 0x0800A164 + Address: 0x0800A168 + Address: 0x0800A16C + Address: 0x0800A170 + Address: 0x0800A174 + Address: 0x0800A178 + Address: 0x0800A17C + Address: 0x0800A180 + Address: 0x0800A184 + Address: 0x0800A188 + Address: 0x0800A18C + Address: 0x0800A190 + Address: 0x0800A194 + Address: 0x0800A198 + Address: 0x0800A19C + Address: 0x0800A1A0 + Address: 0x0800A1A4 + Address: 0x0800A1A8 + Address: 0x0800A1AC + Address: 0x0800A1B0 + Address: 0x0800A1B4 + Address: 0x0800A1B8 + Address: 0x0800A1BC + Address: 0x0800A1C0 + Address: 0x0800A1C4 + Address: 0x0800A1C8 + Address: 0x0800A1CC + Address: 0x0800A1F4 + Address: 0x0800A1F8 + Address: 0x0800A1FC + Address: 0x0800A200 + Address: 0x0800A204 + Address: 0x0800A208 + Address: 0x0800A20C + Address: 0x0800A210 + Address: 0x0800A214 + Address: 0x0800A218 + Address: 0x0800A21C + Address: 0x0800A220 + Address: 0x0800A224 + Address: 0x0800A228 + Address: 0x0800A22C + Address: 0x0800A230 + Address: 0x0800A234 + Address: 0x0800A238 + Address: 0x0800A23C + Address: 0x0800A240 + Address: 0x0800A244 + Address: 0x0800A248 + Address: 0x0800A24C + Address: 0x0800A250 + Address: 0x0800A254 + Address: 0x0800A258 + Address: 0x0800A25C + Address: 0x0800A260 + Address: 0x0800A264 + Address: 0x0800A268 + Address: 0x0800A26C + Address: 0x0800A270 + Address: 0x0800A274 + Address: 0x0800A278 + Address: 0x0800A27C + Address: 0x0800A280 + Address: 0x0800A284 + Address: 0x0800A288 + Address: 0x0800A2B4 + Address: 0x0800A2B8 + Address: 0x0800A2BC + Address: 0x0800A2C0 + Address: 0x0800A2C4 + Address: 0x0800A2C8 + Address: 0x0800A2CC + Address: 0x0800A2D0 + Address: 0x0800A2D4 + Address: 0x0800A2D8 + Address: 0x0800A2DC + Address: 0x0800A2E0 + Address: 0x0800A2E4 + Address: 0x0800A2E8 + Address: 0x0800A2EC + Address: 0x0800A2F0 + Address: 0x0800A2F4 + Address: 0x0800A2F8 + Address: 0x0800A2FC + Address: 0x0800A300 + Address: 0x0800A304 + Address: 0x0800A308 + Address: 0x0800A30C + Address: 0x0800A310 + Address: 0x0800A314 + Address: 0x0800A318 + Address: 0x0800A31C + Address: 0x0800A320 + Address: 0x0800A324 + Address: 0x0800A328 + Address: 0x0800A32C + Address: 0x0800A330 + Address: 0x0800A334 + Address: 0x0800A338 + Address: 0x0800A33C + Address: 0x0800A340 + Address: 0x0800A344 + Address: 0x0800A364 + Address: 0x0800A368 + Address: 0x0800A36C + Address: 0x0800A370 + Address: 0x0800A374 + Address: 0x0800A378 + Address: 0x0800A37C + Address: 0x0800A380 + Address: 0x0800A384 + Address: 0x0800A388 + Address: 0x0800A38C + Address: 0x0800A390 + Address: 0x0800A394 + Address: 0x0800A398 + Address: 0x0800A39C + Address: 0x0800A3A0 + Address: 0x0800A3A4 + Address: 0x0800A3A8 + Address: 0x0800A3AC + Address: 0x0800A3B0 + Address: 0x0800A3C0 + Address: 0x0800A3C4 + Address: 0x0800A3C8 + Address: 0x0800A3CC + Address: 0x0800A3D0 + Address: 0x0800A3D4 + Address: 0x0800A3D8 + Address: 0x0800A3DC + Address: 0x0800A3E0 + Address: 0x0800A3E4 + Address: 0x0800A3E8 + Address: 0x0800A3EC + Address: 0x0800A3F0 + Address: 0x0800A3F4 + Address: 0x0800A3F8 + Address: 0x0800A3FC + Address: 0x0800A400 + Address: 0x0800A404 + Address: 0x0800A424 + Address: 0x0800A428 + Address: 0x0800A42C + Address: 0x0800A430 + Address: 0x0800A434 + Address: 0x0800A438 + Address: 0x0800A43C + Address: 0x0800A440 + Address: 0x0800A444 + Address: 0x0800A448 + Address: 0x0800A44C + Address: 0x0800A450 + Address: 0x0800A454 + Address: 0x0800A458 + Address: 0x0800A45C + Address: 0x0800A460 + Address: 0x0800A464 + Address: 0x0800A468 + Address: 0x0800A46C + Address: 0x0800A470 + Address: 0x0800A478 + Address: 0x0800A47C + Address: 0x0800A480 + Address: 0x0800A484 + Address: 0x0800A488 + Address: 0x0800A48C + Address: 0x0800A490 + Address: 0x0800A494 + Address: 0x0800A498 + Address: 0x0800A49C + Address: 0x0800A4A0 + Address: 0x0800A4A4 + Address: 0x0800A4A8 + Address: 0x0800A4AC + Address: 0x0800A4B0 + Address: 0x0800A4B4 + Address: 0x0800A4B8 + Address: 0x0800A4D4 + Address: 0x0800A4D8 + Address: 0x0800A4DC + Address: 0x0800A4E0 + Address: 0x0800A4E4 + Address: 0x0800A4E8 + Address: 0x0800A4EC + Address: 0x0800A4F0 + Address: 0x0800A4F4 + Address: 0x0800A4F8 + Address: 0x0800A4FC + Address: 0x0800A500 + Address: 0x0800A504 + Address: 0x0800A508 + Address: 0x0800A50C + Address: 0x0800A510 + Address: 0x0800A514 + Address: 0x0800A518 + Address: 0x0800A51C + Address: 0x0800A520 + Address: 0x0800A534 + Address: 0x0800A538 + Address: 0x0800A53C + Address: 0x0800A540 + Address: 0x0800A544 + Address: 0x0800A548 + Address: 0x0800A54C + Address: 0x0800A550 + Address: 0x0800A554 + Address: 0x0800A558 + Address: 0x0800A55C + Address: 0x0800A560 + Address: 0x0800A564 + Address: 0x0800A568 + Address: 0x0800A56C + Address: 0x0800A570 + Address: 0x0800A574 + Address: 0x0800A578 + Address: 0x0800A598 + Address: 0x0800A59C + Address: 0x0800A5A0 + Address: 0x0800A5A4 + Address: 0x0800A5A8 + Address: 0x0800A5AC + Address: 0x0800A5B0 + Address: 0x0800A5B4 + Address: 0x0800A5B8 + Address: 0x0800A5BC + Address: 0x0800A5C0 + Address: 0x0800A5C4 + Address: 0x0800A5C8 + Address: 0x0800A5CC + Address: 0x0800A5D0 + Address: 0x0800A5D4 + Address: 0x0800A5D8 + Address: 0x0800A5DC + Address: 0x0800A5E0 + Address: 0x0800A5E4 + Address: 0x0800A5F4 + Address: 0x0800A5F8 + Address: 0x0800A5FC + Address: 0x0800A600 + Address: 0x0800A604 + Address: 0x0800A608 + Address: 0x0800A60C + Address: 0x0800A610 + Address: 0x0800A614 + Address: 0x0800A618 + Address: 0x0800A61C + Address: 0x0800A620 + Address: 0x0800A624 + Address: 0x0800A628 + Address: 0x0800A62C + Address: 0x0800A630 + Address: 0x0800A634 + Address: 0x0800A638 + Address: 0x0800A650 + Address: 0x0800A654 + Address: 0x0800A658 + Address: 0x0800A65C + Address: 0x0800A660 + Address: 0x0800A664 + Address: 0x0800A668 + Address: 0x0800A66C + Address: 0x0800A670 + Address: 0x0800A674 + Address: 0x0800A678 + Address: 0x0800A67C + Address: 0x0800A680 + Address: 0x0800A684 + Address: 0x0800A688 + Address: 0x0800A68C + Address: 0x0800A690 + Address: 0x0800A694 + Address: 0x0800A698 + Address: 0x0800A6A8 + Address: 0x0800A6AC + Address: 0x0800A6B0 + Address: 0x0800A6B4 + Address: 0x0800A6B8 + Address: 0x0800A6BC + Address: 0x0800A6C0 + Address: 0x0800A6C4 + Address: 0x0800A6C8 + Address: 0x0800A6CC + Address: 0x0800A6D0 + Address: 0x0800A6D4 + Address: 0x0800A6D8 + Address: 0x0800A6DC + Address: 0x0800A6E0 + Address: 0x0800A6E4 + Address: 0x0800A6E8 + Address: 0x0800A6EC + Address: 0x0800A70C + Address: 0x0800A710 + Address: 0x0800A714 + Address: 0x0800A718 + Address: 0x0800A71C + Address: 0x0800A720 + Address: 0x0800A724 + Address: 0x0800A728 + Address: 0x0800A72C + Address: 0x0800A730 + Address: 0x0800A734 + Address: 0x0800A738 + Address: 0x0800A73C + Address: 0x0800A740 + Address: 0x0800A744 + Address: 0x0800A748 + Address: 0x0800A74C + Address: 0x0800A750 + Address: 0x0800A754 + Address: 0x0800A758 + Address: 0x0800A764 + Address: 0x0800A768 + Address: 0x0800A76C + Address: 0x0800A770 + Address: 0x0800A774 + Address: 0x0800A778 + Address: 0x0800A77C + Address: 0x0800A780 + Address: 0x0800A784 + Address: 0x0800A788 + Address: 0x0800A78C + Address: 0x0800A790 + Address: 0x0800A794 + Address: 0x0800A798 + Address: 0x0800A79C + Address: 0x0800A7A0 + Address: 0x0800A7A4 + Address: 0x0800A7A8 + Address: 0x0800A7C4 + Address: 0x0800A7C8 + Address: 0x0800A7CC + Address: 0x0800A7D0 + Address: 0x0800A7D4 + Address: 0x0800A7D8 + Address: 0x0800A7DC + Address: 0x0800A7E0 + Address: 0x0800A7E4 + Address: 0x0800A7E8 + Address: 0x0800A7EC + Address: 0x0800A7F0 + Address: 0x0800A7F4 + Address: 0x0800A7F8 + Address: 0x0800A7FC + Address: 0x0800A800 + Address: 0x0800A804 + Address: 0x0800A808 + Address: 0x0800A80C + Address: 0x0800A810 + Address: 0x0800A818 + Address: 0x0800A81C + Address: 0x0800A820 + Address: 0x0800A824 + Address: 0x0800A828 + Address: 0x0800A82C + Address: 0x0800A830 + Address: 0x0800A834 + Address: 0x0800A838 + Address: 0x0800A83C + Address: 0x0800A840 + Address: 0x0800A844 + Address: 0x0800A848 + Address: 0x0800A84C + Address: 0x0800A850 + Address: 0x0800A854 + Address: 0x0800A858 + Address: 0x0800A880 + Address: 0x0800A884 + Address: 0x0800A888 + Address: 0x0800A88C + Address: 0x0800A890 + Address: 0x0800A894 + Address: 0x0800A898 + Address: 0x0800A89C + Address: 0x0800A8A0 + Address: 0x0800A8A4 + Address: 0x0800A8A8 + Address: 0x0800A8AC + Address: 0x0800A8B0 + Address: 0x0800A8B4 + Address: 0x0800A8B8 + Address: 0x0800A8BC + Address: 0x0800A8C0 + Address: 0x0800A8C4 + Address: 0x0800A8C8 + Address: 0x0800A8CC + Address: 0x0800A8D0 + Address: 0x0800A8D8 + Address: 0x0800A8DC + Address: 0x0800A8E0 + Address: 0x0800A8E4 + Address: 0x0800A8E8 + Address: 0x0800A8EC + Address: 0x0800A8F0 + Address: 0x0800A8F4 + Address: 0x0800A8F8 + Address: 0x0800A8FC + Address: 0x0800A900 + Address: 0x0800A904 + Address: 0x0800A908 + Address: 0x0800A90C + Address: 0x0800A910 + Address: 0x0800A914 + Address: 0x0800A918 + Address: 0x0800A93C + Address: 0x0800A940 + Address: 0x0800A944 + Address: 0x0800A948 + Address: 0x0800A94C + Address: 0x0800A950 + Address: 0x0800A954 + Address: 0x0800A958 + Address: 0x0800A95C + Address: 0x0800A960 + Address: 0x0800A964 + Address: 0x0800A968 + Address: 0x0800A96C + Address: 0x0800A970 + Address: 0x0800A974 + Address: 0x0800A978 + Address: 0x0800A97C + Address: 0x0800A980 + Address: 0x0800A984 + Address: 0x0800A988 + Address: 0x0800A98C + Address: 0x0800A990 + Address: 0x0800A994 + Address: 0x0800A998 + Address: 0x0800A99C + Address: 0x0800A9A0 + Address: 0x0800A9A4 + Address: 0x0800A9A8 + Address: 0x0800A9AC + Address: 0x0800A9B0 + Address: 0x0800A9B4 + Address: 0x0800A9B8 + Address: 0x0800A9BC + Address: 0x0800A9C0 + Address: 0x0800A9C4 + Address: 0x0800A9C8 + Address: 0x0800A9CC + Address: 0x0800A9F4 + Address: 0x0800A9F8 + Address: 0x0800A9FC + Address: 0x0800AA00 + Address: 0x0800AA04 + Address: 0x0800AA08 + Address: 0x0800AA0C + Address: 0x0800AA10 + Address: 0x0800AA14 + Address: 0x0800AA18 + Address: 0x0800AA1C + Address: 0x0800AA20 + Address: 0x0800AA24 + Address: 0x0800AA28 + Address: 0x0800AA2C + Address: 0x0800AA30 + Address: 0x0800AA34 + Address: 0x0800AA38 + Address: 0x0800AA3C + Address: 0x0800AA40 + Address: 0x0800AA44 + Address: 0x0800AA4C + Address: 0x0800AA50 + Address: 0x0800AA54 + Address: 0x0800AA58 + Address: 0x0800AA5C + Address: 0x0800AA60 + Address: 0x0800AA64 + Address: 0x0800AA68 + Address: 0x0800AA6C + Address: 0x0800AA70 + Address: 0x0800AA74 + Address: 0x0800AA78 + Address: 0x0800AA7C + Address: 0x0800AA80 + Address: 0x0800AA84 + Address: 0x0800AA88 + Address: 0x0800AA8C + Address: 0x0800AAB0 + Address: 0x0800AAB4 + Address: 0x0800AAB8 + Address: 0x0800AABC + Address: 0x0800AAC0 + Address: 0x0800AAC4 + Address: 0x0800AAC8 + Address: 0x0800AACC + Address: 0x0800AAD0 + Address: 0x0800AAD4 + Address: 0x0800AAD8 + Address: 0x0800AADC + Address: 0x0800AAE0 + Address: 0x0800AAE4 + Address: 0x0800AAE8 + Address: 0x0800AAEC + Address: 0x0800AAF0 + Address: 0x0800AAF4 + Address: 0x0800AAF8 + Address: 0x0800AAFC + Address: 0x0800AB00 + Address: 0x0800AB04 + Address: 0x0800AB08 + Address: 0x0800AB0C + Address: 0x0800AB10 + Address: 0x0800AB14 + Address: 0x0800AB18 + Address: 0x0800AB1C + Address: 0x0800AB20 + Address: 0x0800AB24 + Address: 0x0800AB28 + Address: 0x0800AB2C + Address: 0x0800AB30 + Address: 0x0800AB34 + Address: 0x0800AB38 + Address: 0x0800AB3C + Address: 0x0800AB40 + Address: 0x0800AB6C + Address: 0x0800AB70 + Address: 0x0800AB74 + Address: 0x0800AB78 + Address: 0x0800AB7C + Address: 0x0800AB80 + Address: 0x0800AB84 + Address: 0x0800AB88 + Address: 0x0800AB8C + Address: 0x0800AB90 + Address: 0x0800AB94 + Address: 0x0800AB98 + Address: 0x0800AB9C + Address: 0x0800ABA0 + Address: 0x0800ABA4 + Address: 0x0800ABA8 + Address: 0x0800ABAC + Address: 0x0800ABB0 + Address: 0x0800ABB4 + Address: 0x0800ABB8 + Address: 0x0800ABBC + Address: 0x0800ABC0 + Address: 0x0800ABC4 + Address: 0x0800ABC8 + Address: 0x0800ABCC + Address: 0x0800ABD0 + Address: 0x0800ABD4 + Address: 0x0800ABD8 + Address: 0x0800ABDC + Address: 0x0800ABE0 + Address: 0x0800ABE4 + Address: 0x0800ABE8 + Address: 0x0800ABEC + Address: 0x0800ABF0 + Address: 0x0800ABF4 + Address: 0x0800ABF8 + Address: 0x0800ABFC + Address: 0x0800AC00 + Address: 0x0800AC28 + Address: 0x0800AC2C + Address: 0x0800AC30 + Address: 0x0800AC34 + Address: 0x0800AC38 + Address: 0x0800AC3C + Address: 0x0800AC40 + Address: 0x0800AC44 + Address: 0x0800AC48 + Address: 0x0800AC4C + Address: 0x0800AC50 + Address: 0x0800AC54 + Address: 0x0800AC58 + Address: 0x0800AC5C + Address: 0x0800AC60 + Address: 0x0800AC64 + Address: 0x0800AC68 + Address: 0x0800AC6C + Address: 0x0800AC70 + Address: 0x0800AC74 + Address: 0x0800AC78 + Address: 0x0800AC7C + Address: 0x0800AC80 + Address: 0x0800AC84 + Address: 0x0800AC88 + Address: 0x0800AC8C + Address: 0x0800AC90 + Address: 0x0800AC94 + Address: 0x0800AC98 + Address: 0x0800AC9C + Address: 0x0800ACA0 + Address: 0x0800ACA4 + Address: 0x0800ACA8 + Address: 0x0800ACAC + Address: 0x0800ACB0 + Address: 0x0800ACB4 + Address: 0x0800ACB8 + Address: 0x0800ACDC + Address: 0x0800ACE0 + Address: 0x0800ACE4 + Address: 0x0800ACE8 + Address: 0x0800ACEC + Address: 0x0800ACF0 + Address: 0x0800ACF4 + Address: 0x0800ACF8 + Address: 0x0800ACFC + Address: 0x0800AD00 + Address: 0x0800AD04 + Address: 0x0800AD08 + Address: 0x0800AD0C + Address: 0x0800AD10 + Address: 0x0800AD14 + Address: 0x0800AD18 + Address: 0x0800AD1C + Address: 0x0800AD20 + Address: 0x0800AD24 + Address: 0x0800AD28 + Address: 0x0800AD34 + Address: 0x0800AD38 + Address: 0x0800AD3C + Address: 0x0800AD40 + Address: 0x0800AD44 + Address: 0x0800AD48 + Address: 0x0800AD4C + Address: 0x0800AD50 + Address: 0x0800AD54 + Address: 0x0800AD58 + Address: 0x0800AD5C + Address: 0x0800AD60 + Address: 0x0800AD64 + Address: 0x0800AD68 + Address: 0x0800AD6C + Address: 0x0800AD70 + Address: 0x0800AD74 + Address: 0x0800AD78 + Address: 0x0800AD94 + Address: 0x0800AD98 + Address: 0x0800AD9C + Address: 0x0800ADA0 + Address: 0x0800ADA4 + Address: 0x0800ADA8 + Address: 0x0800ADAC + Address: 0x0800ADB0 + Address: 0x0800ADB4 + Address: 0x0800ADB8 + Address: 0x0800ADBC + Address: 0x0800ADC0 + Address: 0x0800ADC4 + Address: 0x0800ADC8 + Address: 0x0800ADCC + Address: 0x0800ADD0 + Address: 0x0800ADD4 + Address: 0x0800ADD8 + Address: 0x0800ADDC + Address: 0x0800ADE0 + Address: 0x0800ADE8 + Address: 0x0800ADEC + Address: 0x0800ADF0 + Address: 0x0800ADF4 + Address: 0x0800ADF8 + Address: 0x0800ADFC + Address: 0x0800AE00 + Address: 0x0800AE04 + Address: 0x0800AE08 + Address: 0x0800AE0C + Address: 0x0800AE10 + Address: 0x0800AE14 + Address: 0x0800AE18 + Address: 0x0800AE1C + Address: 0x0800AE20 + Address: 0x0800AE24 + Address: 0x0800AE28 + Address: 0x0800AE50 + Address: 0x0800AE54 + Address: 0x0800AE58 + Address: 0x0800AE5C + Address: 0x0800AE60 + Address: 0x0800AE64 + Address: 0x0800AE68 + Address: 0x0800AE6C + Address: 0x0800AE70 + Address: 0x0800AE74 + Address: 0x0800AE78 + Address: 0x0800AE7C + Address: 0x0800AE80 + Address: 0x0800AE84 + Address: 0x0800AE88 + Address: 0x0800AE8C + Address: 0x0800AE90 + Address: 0x0800AE94 + Address: 0x0800AE98 + Address: 0x0800AE9C + Address: 0x0800AEA0 + Address: 0x0800AEA8 + Address: 0x0800AEAC + Address: 0x0800AEB0 + Address: 0x0800AEB4 + Address: 0x0800AEB8 + Address: 0x0800AEBC + Address: 0x0800AEC0 + Address: 0x0800AEC4 + Address: 0x0800AEC8 + Address: 0x0800AECC + Address: 0x0800AED0 + Address: 0x0800AED4 + Address: 0x0800AED8 + Address: 0x0800AEDC + Address: 0x0800AEE0 + Address: 0x0800AEE4 + Address: 0x0800AEE8 + Address: 0x0800AF0C + Address: 0x0800AF10 + Address: 0x0800AF14 + Address: 0x0800AF18 + Address: 0x0800AF1C + Address: 0x0800AF20 + Address: 0x0800AF24 + Address: 0x0800AF28 + Address: 0x0800AF2C + Address: 0x0800AF30 + Address: 0x0800AF34 + Address: 0x0800AF38 + Address: 0x0800AF3C + Address: 0x0800AF40 + Address: 0x0800AF44 + Address: 0x0800AF48 + Address: 0x0800AF4C + Address: 0x0800AF50 + Address: 0x0800AF54 + Address: 0x0800AF58 + Address: 0x0800AF5C + Address: 0x0800AF60 + Address: 0x0800AF64 + Address: 0x0800AF68 + Address: 0x0800AF6C + Address: 0x0800AF70 + Address: 0x0800AF74 + Address: 0x0800AF78 + Address: 0x0800AF7C + Address: 0x0800AF80 + Address: 0x0800AF84 + Address: 0x0800AF88 + Address: 0x0800AF8C + Address: 0x0800AF90 + Address: 0x0800AF94 + Address: 0x0800AF98 + Address: 0x0800AF9C + Address: 0x0800AFA0 + Address: 0x0800AFC8 + Address: 0x0800AFCC + Address: 0x0800AFD0 + Address: 0x0800AFD4 + Address: 0x0800AFD8 + Address: 0x0800AFDC + Address: 0x0800AFE0 + Address: 0x0800AFE4 + Address: 0x0800AFE8 + Address: 0x0800AFEC + Address: 0x0800AFF0 + Address: 0x0800AFF4 + Address: 0x0800AFF8 + Address: 0x0800AFFC + Address: 0x0800B000 + Address: 0x0800B004 + Address: 0x0800B008 + Address: 0x0800B00C + Address: 0x0800B010 + Address: 0x0800B014 + Address: 0x0800B018 + Address: 0x0800B020 + Address: 0x0800B024 + Address: 0x0800B028 + Address: 0x0800B02C + Address: 0x0800B030 + Address: 0x0800B034 + Address: 0x0800B038 + Address: 0x0800B03C + Address: 0x0800B040 + Address: 0x0800B044 + Address: 0x0800B048 + Address: 0x0800B04C + Address: 0x0800B050 + Address: 0x0800B054 + Address: 0x0800B058 + Address: 0x0800B05C + Address: 0x0800B060 + Address: 0x0800B084 + Address: 0x0800B088 + Address: 0x0800B08C + Address: 0x0800B090 + Address: 0x0800B094 + Address: 0x0800B098 + Address: 0x0800B09C + Address: 0x0800B0A0 + Address: 0x0800B0A4 + Address: 0x0800B0A8 + Address: 0x0800B0AC + Address: 0x0800B0B0 + Address: 0x0800B0B4 + Address: 0x0800B0B8 + Address: 0x0800B0BC + Address: 0x0800B0C0 + Address: 0x0800B0C4 + Address: 0x0800B0C8 + Address: 0x0800B0CC + Address: 0x0800B0D0 + Address: 0x0800B0D4 + Address: 0x0800B0D8 + Address: 0x0800B0DC + Address: 0x0800B0E0 + Address: 0x0800B0E4 + Address: 0x0800B0E8 + Address: 0x0800B0EC + Address: 0x0800B0F0 + Address: 0x0800B0F4 + Address: 0x0800B0F8 + Address: 0x0800B0FC + Address: 0x0800B100 + Address: 0x0800B104 + Address: 0x0800B108 + Address: 0x0800B10C + Address: 0x0800B110 + Address: 0x0800B114 + Address: 0x0800B138 + Address: 0x0800B13C + Address: 0x0800B140 + Address: 0x0800B144 + Address: 0x0800B148 + Address: 0x0800B14C + Address: 0x0800B150 + Address: 0x0800B154 + Address: 0x0800B158 + Address: 0x0800B15C + Address: 0x0800B160 + Address: 0x0800B164 + Address: 0x0800B168 + Address: 0x0800B16C + Address: 0x0800B170 + Address: 0x0800B174 + Address: 0x0800B178 + Address: 0x0800B17C + Address: 0x0800B180 + Address: 0x0800B184 + Address: 0x0800B188 + Address: 0x0800B194 + Address: 0x0800B198 + Address: 0x0800B19C + Address: 0x0800B1A0 + Address: 0x0800B1A4 + Address: 0x0800B1A8 + Address: 0x0800B1AC + Address: 0x0800B1B0 + Address: 0x0800B1B4 + Address: 0x0800B1B8 + Address: 0x0800B1BC + Address: 0x0800B1C0 + Address: 0x0800B1C4 + Address: 0x0800B1C8 + Address: 0x0800B1CC + Address: 0x0800B1D0 + Address: 0x0800B1D4 + Address: 0x0800B1F4 + Address: 0x0800B1F8 + Address: 0x0800B1FC + Address: 0x0800B200 + Address: 0x0800B204 + Address: 0x0800B208 + Address: 0x0800B20C + Address: 0x0800B210 + Address: 0x0800B214 + Address: 0x0800B218 + Address: 0x0800B21C + Address: 0x0800B220 + Address: 0x0800B224 + Address: 0x0800B228 + Address: 0x0800B22C + Address: 0x0800B230 + Address: 0x0800B234 + Address: 0x0800B238 + Address: 0x0800B23C + Address: 0x0800B240 + Address: 0x0800B248 + Address: 0x0800B24C + Address: 0x0800B250 + Address: 0x0800B254 + Address: 0x0800B258 + Address: 0x0800B25C + Address: 0x0800B260 + Address: 0x0800B264 + Address: 0x0800B268 + Address: 0x0800B26C + Address: 0x0800B270 + Address: 0x0800B274 + Address: 0x0800B278 + Address: 0x0800B27C + Address: 0x0800B280 + Address: 0x0800B284 + Address: 0x0800B288 + Address: 0x0800B2AC + Address: 0x0800B2B0 + Address: 0x0800B2B4 + Address: 0x0800B2B8 + Address: 0x0800B2BC + Address: 0x0800B2C0 + Address: 0x0800B2C4 + Address: 0x0800B2C8 + Address: 0x0800B2CC + Address: 0x0800B2D0 + Address: 0x0800B2D4 + Address: 0x0800B2D8 + Address: 0x0800B2DC + Address: 0x0800B2E0 + Address: 0x0800B2E4 + Address: 0x0800B2E8 + Address: 0x0800B2EC + Address: 0x0800B2F0 + Address: 0x0800B2F4 + Address: 0x0800B2F8 + Address: 0x0800B2FC + Address: 0x0800B304 + Address: 0x0800B308 + Address: 0x0800B30C + Address: 0x0800B310 + Address: 0x0800B314 + Address: 0x0800B318 + Address: 0x0800B31C + Address: 0x0800B320 + Address: 0x0800B324 + Address: 0x0800B328 + Address: 0x0800B32C + Address: 0x0800B330 + Address: 0x0800B334 + Address: 0x0800B338 + Address: 0x0800B33C + Address: 0x0800B340 + Address: 0x0800B344 + Address: 0x0800B36C + Address: 0x0800B370 + Address: 0x0800B374 + Address: 0x0800B378 + Address: 0x0800B37C + Address: 0x0800B380 + Address: 0x0800B384 + Address: 0x0800B388 + Address: 0x0800B38C + Address: 0x0800B390 + Address: 0x0800B394 + Address: 0x0800B398 + Address: 0x0800B39C + Address: 0x0800B3A0 + Address: 0x0800B3A4 + Address: 0x0800B3A8 + Address: 0x0800B3AC + Address: 0x0800B3B0 + Address: 0x0800B3B4 + Address: 0x0800B3B8 + Address: 0x0800B3BC + Address: 0x0800B3C0 + Address: 0x0800B3C4 + Address: 0x0800B3C8 + Address: 0x0800B3CC + Address: 0x0800B3D0 + Address: 0x0800B3D4 + Address: 0x0800B3D8 + Address: 0x0800B3DC + Address: 0x0800B3E0 + Address: 0x0800B3E4 + Address: 0x0800B3E8 + Address: 0x0800B3EC + Address: 0x0800B3F0 + Address: 0x0800B3F4 + Address: 0x0800B3F8 + Address: 0x0800B3FC + Address: 0x0800B424 + Address: 0x0800B428 + Address: 0x0800B42C + Address: 0x0800B430 + Address: 0x0800B434 + Address: 0x0800B438 + Address: 0x0800B43C + Address: 0x0800B440 + Address: 0x0800B444 + Address: 0x0800B448 + Address: 0x0800B44C + Address: 0x0800B450 + Address: 0x0800B454 + Address: 0x0800B458 + Address: 0x0800B45C + Address: 0x0800B460 + Address: 0x0800B464 + Address: 0x0800B468 + Address: 0x0800B46C + Address: 0x0800B470 + Address: 0x0800B474 + Address: 0x0800B47C + Address: 0x0800B480 + Address: 0x0800B484 + Address: 0x0800B488 + Address: 0x0800B48C + Address: 0x0800B490 + Address: 0x0800B494 + Address: 0x0800B498 + Address: 0x0800B49C + Address: 0x0800B4A0 + Address: 0x0800B4A4 + Address: 0x0800B4A8 + Address: 0x0800B4AC + Address: 0x0800B4B0 + Address: 0x0800B4B4 + Address: 0x0800B4B8 + Address: 0x0800B4BC + Address: 0x0800B4D8 + Address: 0x0800B4DC + Address: 0x0800B4E0 + Address: 0x0800B4E4 + Address: 0x0800B4E8 + Address: 0x0800B4EC + Address: 0x0800B4F0 + Address: 0x0800B4F4 + Address: 0x0800B4F8 + Address: 0x0800B4FC + Address: 0x0800B500 + Address: 0x0800B504 + Address: 0x0800B508 + Address: 0x0800B50C + Address: 0x0800B510 + Address: 0x0800B514 + Address: 0x0800B518 + Address: 0x0800B51C + Address: 0x0800B520 + Address: 0x0800B524 + Address: 0x0800B52C + Address: 0x0800B530 + Address: 0x0800B534 + Address: 0x0800B538 + Address: 0x0800B53C + Address: 0x0800B540 + Address: 0x0800B544 + Address: 0x0800B548 + Address: 0x0800B54C + Address: 0x0800B550 + Address: 0x0800B554 + Address: 0x0800B558 + Address: 0x0800B55C + Address: 0x0800B560 + Address: 0x0800B564 + Address: 0x0800B568 + Address: 0x0800B56C + Address: 0x0800B594 + Address: 0x0800B598 + Address: 0x0800B59C + Address: 0x0800B5A0 + Address: 0x0800B5A4 + Address: 0x0800B5A8 + Address: 0x0800B5AC + Address: 0x0800B5B0 + Address: 0x0800B5B4 + Address: 0x0800B5B8 + Address: 0x0800B5BC + Address: 0x0800B5C0 + Address: 0x0800B5C4 + Address: 0x0800B5C8 + Address: 0x0800B5CC + Address: 0x0800B5D0 + Address: 0x0800B5D4 + Address: 0x0800B5D8 + Address: 0x0800B5DC + Address: 0x0800B5E0 + Address: 0x0800B5E4 + Address: 0x0800B5EC + Address: 0x0800B5F0 + Address: 0x0800B5F4 + Address: 0x0800B5F8 + Address: 0x0800B5FC + Address: 0x0800B600 + Address: 0x0800B604 + Address: 0x0800B608 + Address: 0x0800B60C + Address: 0x0800B610 + Address: 0x0800B614 + Address: 0x0800B618 + Address: 0x0800B61C + Address: 0x0800B620 + Address: 0x0800B624 + Address: 0x0800B628 + Address: 0x0800B62C + Address: 0x0800B650 + Address: 0x0800B654 + Address: 0x0800B658 + Address: 0x0800B65C + Address: 0x0800B660 + Address: 0x0800B664 + Address: 0x0800B668 + Address: 0x0800B66C + Address: 0x0800B670 + Address: 0x0800B674 + Address: 0x0800B678 + Address: 0x0800B67C + Address: 0x0800B680 + Address: 0x0800B684 + Address: 0x0800B688 + Address: 0x0800B68C + Address: 0x0800B690 + Address: 0x0800B694 + Address: 0x0800B698 + Address: 0x0800B69C + Address: 0x0800B6A0 + Address: 0x0800B6A4 + Address: 0x0800B6A8 + Address: 0x0800B6AC + Address: 0x0800B6B0 + Address: 0x0800B6B4 + Address: 0x0800B6B8 + Address: 0x0800B6BC + Address: 0x0800B6C0 + Address: 0x0800B6C4 + Address: 0x0800B6C8 + Address: 0x0800B6CC + Address: 0x0800B6D0 + Address: 0x0800B6D4 + Address: 0x0800B6D8 + Address: 0x0800B6DC + Address: 0x0800B6E0 + Address: 0x0800B708 + Address: 0x0800B70C + Address: 0x0800B710 + Address: 0x0800B714 + Address: 0x0800B718 + Address: 0x0800B71C + Address: 0x0800B720 + Address: 0x0800B724 + Address: 0x0800B728 + Address: 0x0800B72C + Address: 0x0800B730 + Address: 0x0800B734 + Address: 0x0800B738 + Address: 0x0800B73C + Address: 0x0800B740 + Address: 0x0800B744 + Address: 0x0800B748 + Address: 0x0800B74C + Address: 0x0800B750 + Address: 0x0800B754 + Address: 0x0800B758 + Address: 0x0800B760 + Address: 0x0800B764 + Address: 0x0800B768 + Address: 0x0800B76C + Address: 0x0800B770 + Address: 0x0800B774 + Address: 0x0800B778 + Address: 0x0800B77C + Address: 0x0800B780 + Address: 0x0800B784 + Address: 0x0800B788 + Address: 0x0800B78C + Address: 0x0800B790 + Address: 0x0800B794 + Address: 0x0800B798 + Address: 0x0800B79C + Address: 0x0800B7A0 + Address: 0x0800B7C4 + Address: 0x0800B7C8 + Address: 0x0800B7CC + Address: 0x0800B7D0 + Address: 0x0800B7D4 + Address: 0x0800B7D8 + Address: 0x0800B7DC + Address: 0x0800B7E0 + Address: 0x0800B7E4 + Address: 0x0800B7E8 + Address: 0x0800B7EC + Address: 0x0800B7F0 + Address: 0x0800B7F4 + Address: 0x0800B7F8 + Address: 0x0800B7FC + Address: 0x0800B800 + Address: 0x0800B804 + Address: 0x0800B808 + Address: 0x0800B80C + Address: 0x0800B810 + Address: 0x0800B814 + Address: 0x0800B818 + Address: 0x0800B81C + Address: 0x0800B820 + Address: 0x0800B824 + Address: 0x0800B828 + Address: 0x0800B82C + Address: 0x0800B830 + Address: 0x0800B834 + Address: 0x0800B838 + Address: 0x0800B83C + Address: 0x0800B840 + Address: 0x0800B844 + Address: 0x0800B848 + Address: 0x0800B84C + Address: 0x0800B850 + Address: 0x0800B854 + Address: 0x0800B884 + Address: 0x0800B888 + Address: 0x0800B88C + Address: 0x0800B890 + Address: 0x0800B894 + Address: 0x0800B898 + Address: 0x0800B89C + Address: 0x0800B8A0 + Address: 0x0800B8A4 + Address: 0x0800B8A8 + Address: 0x0800B8AC + Address: 0x0800B8B0 + Address: 0x0800B8B4 + Address: 0x0800B8B8 + Address: 0x0800B8BC + Address: 0x0800B8C0 + Address: 0x0800B8C4 + Address: 0x0800B8C8 + Address: 0x0800B8CC + Address: 0x0800B8D0 + Address: 0x0800B8D4 + Address: 0x0800B8D8 + Address: 0x0800B8DC + Address: 0x0800B8E0 + Address: 0x0800B8E4 + Address: 0x0800B8E8 + Address: 0x0800B8EC + Address: 0x0800B8F0 + Address: 0x0800B8F4 + Address: 0x0800B8F8 + Address: 0x0800B8FC + Address: 0x0800B900 + Address: 0x0800B904 + Address: 0x0800B908 + Address: 0x0800B90C + Address: 0x0800B910 + Address: 0x0800B914 + Address: 0x0800B918 + Address: 0x0800B93C + Address: 0x0800B940 + Address: 0x0800B944 + Address: 0x0800B948 + Address: 0x0800B94C + Address: 0x0800B950 + Address: 0x0800B954 + Address: 0x0800B958 + Address: 0x0800B95C + Address: 0x0800B960 + Address: 0x0800B964 + Address: 0x0800B968 + Address: 0x0800B96C + Address: 0x0800B970 + Address: 0x0800B974 + Address: 0x0800B978 + Address: 0x0800B97C + Address: 0x0800B980 + Address: 0x0800B984 + Address: 0x0800B988 + Address: 0x0800B98C + Address: 0x0800B990 + Address: 0x0800B994 + Address: 0x0800B998 + Address: 0x0800B99C + Address: 0x0800B9A0 + Address: 0x0800B9A4 + Address: 0x0800B9A8 + Address: 0x0800B9AC + Address: 0x0800B9B0 + Address: 0x0800B9B4 + Address: 0x0800B9B8 + Address: 0x0800B9BC + Address: 0x0800B9C0 + Address: 0x0800B9C4 + Address: 0x0800B9C8 + Address: 0x0800B9CC + Address: 0x0800B9F8 + Address: 0x0800B9FC + Address: 0x0800BA00 + Address: 0x0800BA04 + Address: 0x0800BA08 + Address: 0x0800BA0C + Address: 0x0800BA10 + Address: 0x0800BA14 + Address: 0x0800BA18 + Address: 0x0800BA1C + Address: 0x0800BA20 + Address: 0x0800BA24 + Address: 0x0800BA28 + Address: 0x0800BA2C + Address: 0x0800BA30 + Address: 0x0800BA34 + Address: 0x0800BA38 + Address: 0x0800BA3C + Address: 0x0800BA40 + Address: 0x0800BA44 + Address: 0x0800BA48 + Address: 0x0800BA4C + Address: 0x0800BA50 + Address: 0x0800BA54 + Address: 0x0800BA58 + Address: 0x0800BA5C + Address: 0x0800BA60 + Address: 0x0800BA64 + Address: 0x0800BA68 + Address: 0x0800BA6C + Address: 0x0800BA70 + Address: 0x0800BA74 + Address: 0x0800BA78 + Address: 0x0800BA7C + Address: 0x0800BA80 + Address: 0x0800BA84 + Address: 0x0800BA88 + Address: 0x0800BA8C + Address: 0x0800BAB4 + Address: 0x0800BAB8 + Address: 0x0800BABC + Address: 0x0800BAC0 + Address: 0x0800BAC4 + Address: 0x0800BAC8 + Address: 0x0800BACC + Address: 0x0800BAD0 + Address: 0x0800BAD4 + Address: 0x0800BAD8 + Address: 0x0800BADC + Address: 0x0800BAE0 + Address: 0x0800BAE4 + Address: 0x0800BAE8 + Address: 0x0800BAEC + Address: 0x0800BAF0 + Address: 0x0800BAF4 + Address: 0x0800BAF8 + Address: 0x0800BAFC + Address: 0x0800BB00 + Address: 0x0800BB04 + Address: 0x0800BB08 + Address: 0x0800BB0C + Address: 0x0800BB10 + Address: 0x0800BB14 + Address: 0x0800BB18 + Address: 0x0800BB1C + Address: 0x0800BB20 + Address: 0x0800BB24 + Address: 0x0800BB28 + Address: 0x0800BB2C + Address: 0x0800BB30 + Address: 0x0800BB34 + Address: 0x0800BB38 + Address: 0x0800BB3C + Address: 0x0800BB40 + Address: 0x0800BB44 + Address: 0x0800BB6C + Address: 0x0800BB70 + Address: 0x0800BB74 + Address: 0x0800BB78 + Address: 0x0800BB7C + Address: 0x0800BB80 + Address: 0x0800BB84 + Address: 0x0800BB88 + Address: 0x0800BB8C + Address: 0x0800BB90 + Address: 0x0800BB94 + Address: 0x0800BB98 + Address: 0x0800BB9C + Address: 0x0800BBA0 + Address: 0x0800BBA4 + Address: 0x0800BBA8 + Address: 0x0800BBAC + Address: 0x0800BBB0 + Address: 0x0800BBB4 + Address: 0x0800BBB8 + Address: 0x0800BBBC + Address: 0x0800BBC4 + Address: 0x0800BBC8 + Address: 0x0800BBCC + Address: 0x0800BBD0 + Address: 0x0800BBD4 + Address: 0x0800BBD8 + Address: 0x0800BBDC + Address: 0x0800BBE0 + Address: 0x0800BBE4 + Address: 0x0800BBE8 + Address: 0x0800BBEC + Address: 0x0800BBF0 + Address: 0x0800BBF4 + Address: 0x0800BBF8 + Address: 0x0800BBFC + Address: 0x0800BC00 + Address: 0x0800BC04 + Address: 0x0800BC24 + Address: 0x0800BC28 + Address: 0x0800BC2C + Address: 0x0800BC30 + Address: 0x0800BC34 + Address: 0x0800BC38 + Address: 0x0800BC3C + Address: 0x0800BC40 + Address: 0x0800BC44 + Address: 0x0800BC48 + Address: 0x0800BC4C + Address: 0x0800BC50 + Address: 0x0800BC54 + Address: 0x0800BC58 + Address: 0x0800BC5C + Address: 0x0800BC60 + Address: 0x0800BC64 + Address: 0x0800BC68 + Address: 0x0800BC6C + Address: 0x0800BC70 + Address: 0x0800BC78 + Address: 0x0800BC7C + Address: 0x0800BC80 + Address: 0x0800BC84 + Address: 0x0800BC88 + Address: 0x0800BC8C + Address: 0x0800BC90 + Address: 0x0800BC94 + Address: 0x0800BC98 + Address: 0x0800BC9C + Address: 0x0800BCA0 + Address: 0x0800BCA4 + Address: 0x0800BCA8 + Address: 0x0800BCAC + Address: 0x0800BCB0 + Address: 0x0800BCB4 + Address: 0x0800BCB8 + Address: 0x0800BCE0 + Address: 0x0800BCE4 + Address: 0x0800BCE8 + Address: 0x0800BCEC + Address: 0x0800BCF0 + Address: 0x0800BCF4 + Address: 0x0800BCF8 + Address: 0x0800BCFC + Address: 0x0800BD00 + Address: 0x0800BD04 + Address: 0x0800BD08 + Address: 0x0800BD0C + Address: 0x0800BD10 + Address: 0x0800BD14 + Address: 0x0800BD18 + Address: 0x0800BD1C + Address: 0x0800BD20 + Address: 0x0800BD24 + Address: 0x0800BD28 + Address: 0x0800BD2C + Address: 0x0800BD30 + Address: 0x0800BD38 + Address: 0x0800BD3C + Address: 0x0800BD40 + Address: 0x0800BD44 + Address: 0x0800BD48 + Address: 0x0800BD4C + Address: 0x0800BD50 + Address: 0x0800BD54 + Address: 0x0800BD58 + Address: 0x0800BD5C + Address: 0x0800BD60 + Address: 0x0800BD64 + Address: 0x0800BD68 + Address: 0x0800BD6C + Address: 0x0800BD70 + Address: 0x0800BD74 + Address: 0x0800BD78 + Address: 0x0800BD98 + Address: 0x0800BD9C + Address: 0x0800BDA0 + Address: 0x0800BDA4 + Address: 0x0800BDA8 + Address: 0x0800BDAC + Address: 0x0800BDB0 + Address: 0x0800BDB4 + Address: 0x0800BDB8 + Address: 0x0800BDBC + Address: 0x0800BDC0 + Address: 0x0800BDC4 + Address: 0x0800BDC8 + Address: 0x0800BDCC + Address: 0x0800BDD0 + Address: 0x0800BDD4 + Address: 0x0800BDD8 + Address: 0x0800BDDC + Address: 0x0800BDE0 + Address: 0x0800BDE4 + Address: 0x0800BDEC + Address: 0x0800BDF0 + Address: 0x0800BDF4 + Address: 0x0800BDF8 + Address: 0x0800BDFC + Address: 0x0800BE00 + Address: 0x0800BE04 + Address: 0x0800BE08 + Address: 0x0800BE0C + Address: 0x0800BE10 + Address: 0x0800BE14 + Address: 0x0800BE18 + Address: 0x0800BE1C + Address: 0x0800BE20 + Address: 0x0800BE24 + Address: 0x0800BE28 + Address: 0x0800BE2C + Address: 0x0800BE54 + Address: 0x0800BE58 + Address: 0x0800BE5C + Address: 0x0800BE60 + Address: 0x0800BE64 + Address: 0x0800BE68 + Address: 0x0800BE6C + Address: 0x0800BE70 + Address: 0x0800BE74 + Address: 0x0800BE78 + Address: 0x0800BE7C + Address: 0x0800BE80 + Address: 0x0800BE84 + Address: 0x0800BE88 + Address: 0x0800BE8C + Address: 0x0800BE90 + Address: 0x0800BE94 + Address: 0x0800BE98 + Address: 0x0800BE9C + Address: 0x0800BEA0 + Address: 0x0800BEA4 + Address: 0x0800BEAC + Address: 0x0800BEB0 + Address: 0x0800BEB4 + Address: 0x0800BEB8 + Address: 0x0800BEBC + Address: 0x0800BEC0 + Address: 0x0800BEC4 + Address: 0x0800BEC8 + Address: 0x0800BECC + Address: 0x0800BED0 + Address: 0x0800BED4 + Address: 0x0800BED8 + Address: 0x0800BEDC + Address: 0x0800BEE0 + Address: 0x0800BEE4 + Address: 0x0800BEE8 + Address: 0x0800BEEC + Address: 0x0800BF0C + Address: 0x0800BF10 + Address: 0x0800BF14 + Address: 0x0800BF18 + Address: 0x0800BF1C + Address: 0x0800BF20 + Address: 0x0800BF24 + Address: 0x0800BF28 + Address: 0x0800BF2C + Address: 0x0800BF30 + Address: 0x0800BF34 + Address: 0x0800BF38 + Address: 0x0800BF3C + Address: 0x0800BF40 + Address: 0x0800BF44 + Address: 0x0800BF48 + Address: 0x0800BF4C + Address: 0x0800BF50 + Address: 0x0800BF54 + Address: 0x0800BF58 + Address: 0x0800BF60 + Address: 0x0800BF64 + Address: 0x0800BF68 + Address: 0x0800BF6C + Address: 0x0800BF70 + Address: 0x0800BF74 + Address: 0x0800BF78 + Address: 0x0800BF7C + Address: 0x0800BF80 + Address: 0x0800BF84 + Address: 0x0800BF88 + Address: 0x0800BF8C + Address: 0x0800BF90 + Address: 0x0800BF94 + Address: 0x0800BF98 + Address: 0x0800BF9C + Address: 0x0800BFA0 + Address: 0x0800BFC8 + Address: 0x0800BFCC + Address: 0x0800BFD0 + Address: 0x0800BFD4 + Address: 0x0800BFD8 + Address: 0x0800BFDC + Address: 0x0800BFE0 + Address: 0x0800BFE4 + Address: 0x0800BFE8 + Address: 0x0800BFEC + Address: 0x0800BFF0 + Address: 0x0800BFF4 + Address: 0x0800BFF8 + Address: 0x0800BFFC + Address: 0x0800C000 + Address: 0x0800C004 + Address: 0x0800C008 + Address: 0x0800C00C + Address: 0x0800C010 + Address: 0x0800C014 + Address: 0x0800C018 + Address: 0x0800C020 + Address: 0x0800C024 + Address: 0x0800C028 + Address: 0x0800C02C + Address: 0x0800C030 + Address: 0x0800C034 + Address: 0x0800C038 + Address: 0x0800C03C + Address: 0x0800C040 + Address: 0x0800C044 + Address: 0x0800C048 + Address: 0x0800C04C + Address: 0x0800C050 + Address: 0x0800C054 + Address: 0x0800C058 + Address: 0x0800C05C + Address: 0x0800C060 + Address: 0x0800C080 + Address: 0x0800C084 + Address: 0x0800C088 + Address: 0x0800C08C + Address: 0x0800C090 + Address: 0x0800C094 + Address: 0x0800C098 + Address: 0x0800C09C + Address: 0x0800C0A0 + Address: 0x0800C0A4 + Address: 0x0800C0A8 + Address: 0x0800C0AC + Address: 0x0800C0B0 + Address: 0x0800C0B4 + Address: 0x0800C0B8 + Address: 0x0800C0BC + Address: 0x0800C0C0 + Address: 0x0800C0C4 + Address: 0x0800C0C8 + Address: 0x0800C0CC + Address: 0x0800C0D0 + Address: 0x0800C0D4 + Address: 0x0800C0D8 + Address: 0x0800C0DC + Address: 0x0800C0E0 + Address: 0x0800C0E4 + Address: 0x0800C0E8 + Address: 0x0800C0EC + Address: 0x0800C0F0 + Address: 0x0800C0F4 + Address: 0x0800C0F8 + Address: 0x0800C0FC + Address: 0x0800C100 + Address: 0x0800C104 + Address: 0x0800C108 + Address: 0x0800C10C + Address: 0x0800C110 + Address: 0x0800C13C + Address: 0x0800C140 + Address: 0x0800C144 + Address: 0x0800C148 + Address: 0x0800C14C + Address: 0x0800C150 + Address: 0x0800C154 + Address: 0x0800C158 + Address: 0x0800C15C + Address: 0x0800C160 + Address: 0x0800C164 + Address: 0x0800C168 + Address: 0x0800C16C + Address: 0x0800C170 + Address: 0x0800C174 + Address: 0x0800C178 + Address: 0x0800C17C + Address: 0x0800C180 + Address: 0x0800C184 + Address: 0x0800C188 + Address: 0x0800C18C + Address: 0x0800C190 + Address: 0x0800C194 + Address: 0x0800C198 + Address: 0x0800C19C + Address: 0x0800C1A0 + Address: 0x0800C1A4 + Address: 0x0800C1A8 + Address: 0x0800C1AC + Address: 0x0800C1B0 + Address: 0x0800C1B4 + Address: 0x0800C1B8 + Address: 0x0800C1BC + Address: 0x0800C1C0 + Address: 0x0800C1C4 + Address: 0x0800C1C8 + Address: 0x0800C1CC + Address: 0x0800C1D0 + Address: 0x0800C1F8 + Address: 0x0800C1FC + Address: 0x0800C200 + Address: 0x0800C204 + Address: 0x0800C208 + Address: 0x0800C20C + Address: 0x0800C210 + Address: 0x0800C214 + Address: 0x0800C218 + Address: 0x0800C21C + Address: 0x0800C220 + Address: 0x0800C224 + Address: 0x0800C228 + Address: 0x0800C22C + Address: 0x0800C230 + Address: 0x0800C234 + Address: 0x0800C238 + Address: 0x0800C23C + Address: 0x0800C240 + Address: 0x0800C244 + Address: 0x0800C248 + Address: 0x0800C24C + Address: 0x0800C250 + Address: 0x0800C254 + Address: 0x0800C258 + Address: 0x0800C25C + Address: 0x0800C260 + Address: 0x0800C264 + Address: 0x0800C268 + Address: 0x0800C26C + Address: 0x0800C270 + Address: 0x0800C274 + Address: 0x0800C278 + Address: 0x0800C27C + Address: 0x0800C280 + Address: 0x0800C284 + Address: 0x0800C288 + Address: 0x0800C2A8 + Address: 0x0800C2AC + Address: 0x0800C2B0 + Address: 0x0800C2B4 + Address: 0x0800C2B8 + Address: 0x0800C2BC + Address: 0x0800C2C0 + Address: 0x0800C2C4 + Address: 0x0800C2C8 + Address: 0x0800C2CC + Address: 0x0800C2D0 + Address: 0x0800C2D4 + Address: 0x0800C2D8 + Address: 0x0800C2DC + Address: 0x0800C2E0 + Address: 0x0800C2E4 + Address: 0x0800C2E8 + Address: 0x0800C2EC + Address: 0x0800C2F0 + Address: 0x0800C2F4 + Address: 0x0800C300 + Address: 0x0800C304 + Address: 0x0800C308 + Address: 0x0800C30C + Address: 0x0800C310 + Address: 0x0800C314 + Address: 0x0800C318 + Address: 0x0800C31C + Address: 0x0800C320 + Address: 0x0800C324 + Address: 0x0800C328 + Address: 0x0800C32C + Address: 0x0800C330 + Address: 0x0800C334 + Address: 0x0800C338 + Address: 0x0800C33C + Address: 0x0800C340 + Address: 0x0800C344 + Address: 0x0800C360 + Address: 0x0800C364 + Address: 0x0800C368 + Address: 0x0800C36C + Address: 0x0800C370 + Address: 0x0800C374 + Address: 0x0800C378 + Address: 0x0800C37C + Address: 0x0800C380 + Address: 0x0800C384 + Address: 0x0800C388 + Address: 0x0800C38C + Address: 0x0800C390 + Address: 0x0800C394 + Address: 0x0800C398 + Address: 0x0800C39C + Address: 0x0800C3A0 + Address: 0x0800C3A4 + Address: 0x0800C3A8 + Address: 0x0800C3B4 + Address: 0x0800C3B8 + Address: 0x0800C3BC + Address: 0x0800C3C0 + Address: 0x0800C3C4 + Address: 0x0800C3C8 + Address: 0x0800C3CC + Address: 0x0800C3D0 + Address: 0x0800C3D4 + Address: 0x0800C3D8 + Address: 0x0800C3DC + Address: 0x0800C3E0 + Address: 0x0800C3E4 + Address: 0x0800C3E8 + Address: 0x0800C3EC + Address: 0x0800C3F0 + Address: 0x0800C3F4 + Address: 0x0800C3F8 + Address: 0x0800C41C + Address: 0x0800C420 + Address: 0x0800C424 + Address: 0x0800C428 + Address: 0x0800C42C + Address: 0x0800C430 + Address: 0x0800C434 + Address: 0x0800C438 + Address: 0x0800C43C + Address: 0x0800C440 + Address: 0x0800C444 + Address: 0x0800C448 + Address: 0x0800C44C + Address: 0x0800C450 + Address: 0x0800C454 + Address: 0x0800C458 + Address: 0x0800C45C + Address: 0x0800C460 + Address: 0x0800C464 + Address: 0x0800C468 + Address: 0x0800C478 + Address: 0x0800C47C + Address: 0x0800C480 + Address: 0x0800C484 + Address: 0x0800C488 + Address: 0x0800C48C + Address: 0x0800C490 + Address: 0x0800C494 + Address: 0x0800C498 + Address: 0x0800C49C + Address: 0x0800C4A0 + Address: 0x0800C4A4 + Address: 0x0800C4A8 + Address: 0x0800C4AC + Address: 0x0800C4B0 + Address: 0x0800C4B4 + Address: 0x0800C4B8 + Address: 0x0800C4BC + Address: 0x0800C4D4 + Address: 0x0800C4D8 + Address: 0x0800C4DC + Address: 0x0800C4E0 + Address: 0x0800C4E4 + Address: 0x0800C4E8 + Address: 0x0800C4EC + Address: 0x0800C4F0 + Address: 0x0800C4F4 + Address: 0x0800C4F8 + Address: 0x0800C4FC + Address: 0x0800C500 + Address: 0x0800C504 + Address: 0x0800C508 + Address: 0x0800C50C + Address: 0x0800C510 + Address: 0x0800C514 + Address: 0x0800C518 + Address: 0x0800C51C + Address: 0x0800C528 + Address: 0x0800C52C + Address: 0x0800C530 + Address: 0x0800C534 + Address: 0x0800C538 + Address: 0x0800C53C + Address: 0x0800C540 + Address: 0x0800C544 + Address: 0x0800C548 + Address: 0x0800C54C + Address: 0x0800C550 + Address: 0x0800C554 + Address: 0x0800C558 + Address: 0x0800C55C + Address: 0x0800C560 + Address: 0x0800C564 + Address: 0x0800C568 + Address: 0x0800C56C + Address: 0x0800C590 + Address: 0x0800C594 + Address: 0x0800C598 + Address: 0x0800C59C + Address: 0x0800C5A0 + Address: 0x0800C5A4 + Address: 0x0800C5A8 + Address: 0x0800C5AC + Address: 0x0800C5B0 + Address: 0x0800C5B4 + Address: 0x0800C5B8 + Address: 0x0800C5BC + Address: 0x0800C5C0 + Address: 0x0800C5C4 + Address: 0x0800C5C8 + Address: 0x0800C5CC + Address: 0x0800C5D0 + Address: 0x0800C5D4 + Address: 0x0800C5D8 + Address: 0x0800C5DC + Address: 0x0800C5E8 + Address: 0x0800C5EC + Address: 0x0800C5F0 + Address: 0x0800C5F4 + Address: 0x0800C5F8 + Address: 0x0800C5FC + Address: 0x0800C600 + Address: 0x0800C604 + Address: 0x0800C608 + Address: 0x0800C60C + Address: 0x0800C610 + Address: 0x0800C614 + Address: 0x0800C618 + Address: 0x0800C61C + Address: 0x0800C620 + Address: 0x0800C624 + Address: 0x0800C628 + Address: 0x0800C62C + Address: 0x0800C648 + Address: 0x0800C64C + Address: 0x0800C650 + Address: 0x0800C654 + Address: 0x0800C658 + Address: 0x0800C65C + Address: 0x0800C660 + Address: 0x0800C664 + Address: 0x0800C668 + Address: 0x0800C66C + Address: 0x0800C670 + Address: 0x0800C674 + Address: 0x0800C678 + Address: 0x0800C67C + Address: 0x0800C680 + Address: 0x0800C684 + Address: 0x0800C688 + Address: 0x0800C68C + Address: 0x0800C690 + Address: 0x0800C694 + Address: 0x0800C698 + Address: 0x0800C69C + Address: 0x0800C6A0 + Address: 0x0800C6A4 + Address: 0x0800C6A8 + Address: 0x0800C6AC + Address: 0x0800C6B0 + Address: 0x0800C6B4 + Address: 0x0800C6B8 + Address: 0x0800C6BC + Address: 0x0800C6C0 + Address: 0x0800C6C4 + Address: 0x0800C6C8 + Address: 0x0800C6CC + Address: 0x0800C6D0 + Address: 0x0800C6D4 + Address: 0x0800C6D8 + Address: 0x0800C708 + Address: 0x0800C70C + Address: 0x0800C710 + Address: 0x0800C714 + Address: 0x0800C718 + Address: 0x0800C71C + Address: 0x0800C720 + Address: 0x0800C724 + Address: 0x0800C728 + Address: 0x0800C72C + Address: 0x0800C730 + Address: 0x0800C734 + Address: 0x0800C738 + Address: 0x0800C73C + Address: 0x0800C740 + Address: 0x0800C744 + Address: 0x0800C748 + Address: 0x0800C74C + Address: 0x0800C750 + Address: 0x0800C754 + Address: 0x0800C758 + Address: 0x0800C75C + Address: 0x0800C760 + Address: 0x0800C764 + Address: 0x0800C768 + Address: 0x0800C76C + Address: 0x0800C770 + Address: 0x0800C774 + Address: 0x0800C778 + Address: 0x0800C77C + Address: 0x0800C780 + Address: 0x0800C784 + Address: 0x0800C788 + Address: 0x0800C78C + Address: 0x0800C790 + Address: 0x0800C794 + Address: 0x0800C798 + Address: 0x0800C79C + Address: 0x0800C7C0 + Address: 0x0800C7C4 + Address: 0x0800C7C8 + Address: 0x0800C7CC + Address: 0x0800C7D0 + Address: 0x0800C7D4 + Address: 0x0800C7D8 + Address: 0x0800C7DC + Address: 0x0800C7E0 + Address: 0x0800C7E4 + Address: 0x0800C7E8 + Address: 0x0800C7EC + Address: 0x0800C7F0 + Address: 0x0800C7F4 + Address: 0x0800C7F8 + Address: 0x0800C7FC + Address: 0x0800C800 + Address: 0x0800C804 + Address: 0x0800C808 + Address: 0x0800C80C + Address: 0x0800C810 + Address: 0x0800C814 + Address: 0x0800C818 + Address: 0x0800C81C + Address: 0x0800C820 + Address: 0x0800C824 + Address: 0x0800C828 + Address: 0x0800C82C + Address: 0x0800C830 + Address: 0x0800C834 + Address: 0x0800C838 + Address: 0x0800C83C + Address: 0x0800C840 + Address: 0x0800C844 + Address: 0x0800C848 + Address: 0x0800C84C + Address: 0x0800C850 + Address: 0x0800C874 + Address: 0x0800C878 + Address: 0x0800C87C + Address: 0x0800C880 + Address: 0x0800C884 + Address: 0x0800C888 + Address: 0x0800C88C + Address: 0x0800C890 + Address: 0x0800C894 + Address: 0x0800C898 + Address: 0x0800C89C + Address: 0x0800C8A0 + Address: 0x0800C8A4 + Address: 0x0800C8A8 + Address: 0x0800C8AC + Address: 0x0800C8B0 + Address: 0x0800C8B4 + Address: 0x0800C8B8 + Address: 0x0800C8BC + Address: 0x0800C8C0 + Address: 0x0800C8C4 + Address: 0x0800C8CC + Address: 0x0800C8D0 + Address: 0x0800C8D4 + Address: 0x0800C8D8 + Address: 0x0800C8DC + Address: 0x0800C8E0 + Address: 0x0800C8E4 + Address: 0x0800C8E8 + Address: 0x0800C8EC + Address: 0x0800C8F0 + Address: 0x0800C8F4 + Address: 0x0800C8F8 + Address: 0x0800C8FC + Address: 0x0800C900 + Address: 0x0800C904 + Address: 0x0800C908 + Address: 0x0800C90C + Address: 0x0800C934 + Address: 0x0800C938 + Address: 0x0800C93C + Address: 0x0800C940 + Address: 0x0800C944 + Address: 0x0800C948 + Address: 0x0800C94C + Address: 0x0800C950 + Address: 0x0800C954 + Address: 0x0800C958 + Address: 0x0800C95C + Address: 0x0800C960 + Address: 0x0800C964 + Address: 0x0800C968 + Address: 0x0800C96C + Address: 0x0800C970 + Address: 0x0800C974 + Address: 0x0800C978 + Address: 0x0800C97C + Address: 0x0800C980 + Address: 0x0800C984 + Address: 0x0800C988 + Address: 0x0800C98C + Address: 0x0800C990 + Address: 0x0800C994 + Address: 0x0800C998 + Address: 0x0800C99C + Address: 0x0800C9A0 + Address: 0x0800C9A4 + Address: 0x0800C9A8 + Address: 0x0800C9AC + Address: 0x0800C9B0 + Address: 0x0800C9B4 + Address: 0x0800C9B8 + Address: 0x0800C9BC + Address: 0x0800C9C0 + Address: 0x0800C9C4 + Address: 0x0800C9EC + Address: 0x0800C9F0 + Address: 0x0800C9F4 + Address: 0x0800C9F8 + Address: 0x0800C9FC + Address: 0x0800CA00 + Address: 0x0800CA04 + Address: 0x0800CA08 + Address: 0x0800CA0C + Address: 0x0800CA10 + Address: 0x0800CA14 + Address: 0x0800CA18 + Address: 0x0800CA1C + Address: 0x0800CA20 + Address: 0x0800CA24 + Address: 0x0800CA28 + Address: 0x0800CA2C + Address: 0x0800CA30 + Address: 0x0800CA34 + Address: 0x0800CA38 + Address: 0x0800CA3C + Address: 0x0800CA44 + Address: 0x0800CA48 + Address: 0x0800CA4C + Address: 0x0800CA50 + Address: 0x0800CA54 + Address: 0x0800CA58 + Address: 0x0800CA5C + Address: 0x0800CA60 + Address: 0x0800CA64 + Address: 0x0800CA68 + Address: 0x0800CA6C + Address: 0x0800CA70 + Address: 0x0800CA74 + Address: 0x0800CA78 + Address: 0x0800CA7C + Address: 0x0800CA80 + Address: 0x0800CA84 + Address: 0x0800CAA4 + Address: 0x0800CAA8 + Address: 0x0800CAAC + Address: 0x0800CAB0 + Address: 0x0800CAB4 + Address: 0x0800CAB8 + Address: 0x0800CABC + Address: 0x0800CAC0 + Address: 0x0800CAC4 + Address: 0x0800CAC8 + Address: 0x0800CACC + Address: 0x0800CAD0 + Address: 0x0800CAD4 + Address: 0x0800CAD8 + Address: 0x0800CADC + Address: 0x0800CAE0 + Address: 0x0800CAE4 + Address: 0x0800CAE8 + Address: 0x0800CAEC + Address: 0x0800CAF0 + Address: 0x0800CAF8 + Address: 0x0800CAFC + Address: 0x0800CB00 + Address: 0x0800CB04 + Address: 0x0800CB08 + Address: 0x0800CB0C + Address: 0x0800CB10 + Address: 0x0800CB14 + Address: 0x0800CB18 + Address: 0x0800CB1C + Address: 0x0800CB20 + Address: 0x0800CB24 + Address: 0x0800CB28 + Address: 0x0800CB2C + Address: 0x0800CB30 + Address: 0x0800CB34 + Address: 0x0800CB38 + Address: 0x0800CB60 + Address: 0x0800CB64 + Address: 0x0800CB68 + Address: 0x0800CB6C + Address: 0x0800CB70 + Address: 0x0800CB74 + Address: 0x0800CB78 + Address: 0x0800CB7C + Address: 0x0800CB80 + Address: 0x0800CB84 + Address: 0x0800CB88 + Address: 0x0800CB8C + Address: 0x0800CB90 + Address: 0x0800CB94 + Address: 0x0800CB98 + Address: 0x0800CB9C + Address: 0x0800CBA0 + Address: 0x0800CBA4 + Address: 0x0800CBA8 + Address: 0x0800CBAC + Address: 0x0800CBB0 + Address: 0x0800CBB8 + Address: 0x0800CBBC + Address: 0x0800CBC0 + Address: 0x0800CBC4 + Address: 0x0800CBC8 + Address: 0x0800CBCC + Address: 0x0800CBD0 + Address: 0x0800CBD4 + Address: 0x0800CBD8 + Address: 0x0800CBDC + Address: 0x0800CBE0 + Address: 0x0800CBE4 + Address: 0x0800CBE8 + Address: 0x0800CBEC + Address: 0x0800CBF0 + Address: 0x0800CBF4 + Address: 0x0800CBF8 + Address: 0x0800CC18 + Address: 0x0800CC1C + Address: 0x0800CC20 + Address: 0x0800CC24 + Address: 0x0800CC28 + Address: 0x0800CC2C + Address: 0x0800CC30 + Address: 0x0800CC34 + Address: 0x0800CC38 + Address: 0x0800CC3C + Address: 0x0800CC40 + Address: 0x0800CC44 + Address: 0x0800CC48 + Address: 0x0800CC4C + Address: 0x0800CC50 + Address: 0x0800CC54 + Address: 0x0800CC58 + Address: 0x0800CC5C + Address: 0x0800CC60 + Address: 0x0800CC64 + Address: 0x0800CC68 + Address: 0x0800CC6C + Address: 0x0800CC70 + Address: 0x0800CC74 + Address: 0x0800CC78 + Address: 0x0800CC7C + Address: 0x0800CC80 + Address: 0x0800CC84 + Address: 0x0800CC88 + Address: 0x0800CC8C + Address: 0x0800CC90 + Address: 0x0800CC94 + Address: 0x0800CC98 + Address: 0x0800CC9C + Address: 0x0800CCA0 + Address: 0x0800CCA4 + Address: 0x0800CCA8 + Address: 0x0800CCD4 + Address: 0x0800CCD8 + Address: 0x0800CCDC + Address: 0x0800CCE0 + Address: 0x0800CCE4 + Address: 0x0800CCE8 + Address: 0x0800CCEC + Address: 0x0800CCF0 + Address: 0x0800CCF4 + Address: 0x0800CCF8 + Address: 0x0800CCFC + Address: 0x0800CD00 + Address: 0x0800CD04 + Address: 0x0800CD08 + Address: 0x0800CD0C + Address: 0x0800CD10 + Address: 0x0800CD14 + Address: 0x0800CD18 + Address: 0x0800CD1C + Address: 0x0800CD20 + Address: 0x0800CD24 + Address: 0x0800CD28 + Address: 0x0800CD2C + Address: 0x0800CD30 + Address: 0x0800CD34 + Address: 0x0800CD38 + Address: 0x0800CD3C + Address: 0x0800CD40 + Address: 0x0800CD44 + Address: 0x0800CD48 + Address: 0x0800CD4C + Address: 0x0800CD50 + Address: 0x0800CD54 + Address: 0x0800CD58 + Address: 0x0800CD5C + Address: 0x0800CD60 + Address: 0x0800CD64 + Address: 0x0800CD68 + Address: 0x0800CD90 + Address: 0x0800CD94 + Address: 0x0800CD98 + Address: 0x0800CD9C + Address: 0x0800CDA0 + Address: 0x0800CDA4 + Address: 0x0800CDA8 + Address: 0x0800CDAC + Address: 0x0800CDB0 + Address: 0x0800CDB4 + Address: 0x0800CDB8 + Address: 0x0800CDBC + Address: 0x0800CDC0 + Address: 0x0800CDC4 + Address: 0x0800CDC8 + Address: 0x0800CDCC + Address: 0x0800CDD0 + Address: 0x0800CDD4 + Address: 0x0800CDD8 + Address: 0x0800CDDC + Address: 0x0800CDE0 + Address: 0x0800CDE4 + Address: 0x0800CDE8 + Address: 0x0800CDEC + Address: 0x0800CDF0 + Address: 0x0800CDF4 + Address: 0x0800CDF8 + Address: 0x0800CDFC + Address: 0x0800CE00 + Address: 0x0800CE04 + Address: 0x0800CE08 + Address: 0x0800CE0C + Address: 0x0800CE10 + Address: 0x0800CE14 + Address: 0x0800CE18 + Address: 0x0800CE1C + Address: 0x0800CE20 + Address: 0x0800CE3C + Address: 0x0800CE40 + Address: 0x0800CE44 + Address: 0x0800CE48 + Address: 0x0800CE4C + Address: 0x0800CE50 + Address: 0x0800CE54 + Address: 0x0800CE58 + Address: 0x0800CE5C + Address: 0x0800CE60 + Address: 0x0800CE64 + Address: 0x0800CE68 + Address: 0x0800CE6C + Address: 0x0800CE70 + Address: 0x0800CE74 + Address: 0x0800CE78 + Address: 0x0800CE7C + Address: 0x0800CE80 + Address: 0x0800CE84 + Address: 0x0800CE88 + Address: 0x0800CE98 + Address: 0x0800CE9C + Address: 0x0800CEA0 + Address: 0x0800CEA4 + Address: 0x0800CEA8 + Address: 0x0800CEAC + Address: 0x0800CEB0 + Address: 0x0800CEB4 + Address: 0x0800CEB8 + Address: 0x0800CEBC + Address: 0x0800CEC0 + Address: 0x0800CEC4 + Address: 0x0800CEC8 + Address: 0x0800CECC + Address: 0x0800CED0 + Address: 0x0800CED4 + Address: 0x0800CED8 + Address: 0x0800CEDC + Address: 0x0800CEF8 + Address: 0x0800CEFC + Address: 0x0800CF00 + Address: 0x0800CF04 + Address: 0x0800CF08 + Address: 0x0800CF0C + Address: 0x0800CF10 + Address: 0x0800CF14 + Address: 0x0800CF18 + Address: 0x0800CF1C + Address: 0x0800CF20 + Address: 0x0800CF24 + Address: 0x0800CF28 + Address: 0x0800CF2C + Address: 0x0800CF30 + Address: 0x0800CF34 + Address: 0x0800CF38 + Address: 0x0800CF3C + Address: 0x0800CF40 + Address: 0x0800CF4C + Address: 0x0800CF50 + Address: 0x0800CF54 + Address: 0x0800CF58 + Address: 0x0800CF5C + Address: 0x0800CF60 + Address: 0x0800CF64 + Address: 0x0800CF68 + Address: 0x0800CF6C + Address: 0x0800CF70 + Address: 0x0800CF74 + Address: 0x0800CF78 + Address: 0x0800CF7C + Address: 0x0800CF80 + Address: 0x0800CF84 + Address: 0x0800CF88 + Address: 0x0800CF8C + Address: 0x0800CF90 + Address: 0x0800CFB4 + Address: 0x0800CFB8 + Address: 0x0800CFBC + Address: 0x0800CFC0 + Address: 0x0800CFC4 + Address: 0x0800CFC8 + Address: 0x0800CFCC + Address: 0x0800CFD0 + Address: 0x0800CFD4 + Address: 0x0800CFD8 + Address: 0x0800CFDC + Address: 0x0800CFE0 + Address: 0x0800CFE4 + Address: 0x0800CFE8 + Address: 0x0800CFEC + Address: 0x0800CFF0 + Address: 0x0800CFF4 + Address: 0x0800CFF8 + Address: 0x0800CFFC + Address: 0x0800D000 + Address: 0x0800D010 + Address: 0x0800D014 + Address: 0x0800D018 + Address: 0x0800D01C + Address: 0x0800D020 + Address: 0x0800D024 + Address: 0x0800D028 + Address: 0x0800D02C + Address: 0x0800D030 + Address: 0x0800D034 + Address: 0x0800D038 + Address: 0x0800D03C + Address: 0x0800D040 + Address: 0x0800D044 + Address: 0x0800D048 + Address: 0x0800D04C + Address: 0x0800D050 + Address: 0x0800D054 + Address: 0x0800D06C + Address: 0x0800D070 + Address: 0x0800D074 + Address: 0x0800D078 + Address: 0x0800D07C + Address: 0x0800D080 + Address: 0x0800D084 + Address: 0x0800D088 + Address: 0x0800D08C + Address: 0x0800D090 + Address: 0x0800D094 + Address: 0x0800D098 + Address: 0x0800D09C + Address: 0x0800D0A0 + Address: 0x0800D0A4 + Address: 0x0800D0A8 + Address: 0x0800D0AC + Address: 0x0800D0B0 + Address: 0x0800D0B4 + Address: 0x0800D0C0 + Address: 0x0800D0C4 + Address: 0x0800D0C8 + Address: 0x0800D0CC + Address: 0x0800D0D0 + Address: 0x0800D0D4 + Address: 0x0800D0D8 + Address: 0x0800D0DC + Address: 0x0800D0E0 + Address: 0x0800D0E4 + Address: 0x0800D0E8 + Address: 0x0800D0EC + Address: 0x0800D0F0 + Address: 0x0800D0F4 + Address: 0x0800D0F8 + Address: 0x0800D0FC + Address: 0x0800D100 + Address: 0x0800D104 + Address: 0x0800D128 + Address: 0x0800D12C + Address: 0x0800D130 + Address: 0x0800D134 + Address: 0x0800D138 + Address: 0x0800D13C + Address: 0x0800D140 + Address: 0x0800D144 + Address: 0x0800D148 + Address: 0x0800D14C + Address: 0x0800D150 + Address: 0x0800D154 + Address: 0x0800D158 + Address: 0x0800D15C + Address: 0x0800D160 + Address: 0x0800D164 + Address: 0x0800D168 + Address: 0x0800D16C + Address: 0x0800D170 + Address: 0x0800D174 + Address: 0x0800D180 + Address: 0x0800D184 + Address: 0x0800D188 + Address: 0x0800D18C + Address: 0x0800D190 + Address: 0x0800D194 + Address: 0x0800D198 + Address: 0x0800D19C + Address: 0x0800D1A0 + Address: 0x0800D1A4 + Address: 0x0800D1A8 + Address: 0x0800D1AC + Address: 0x0800D1B0 + Address: 0x0800D1B4 + Address: 0x0800D1B8 + Address: 0x0800D1BC + Address: 0x0800D1C0 + Address: 0x0800D1C4 + Address: 0x0800D1E0 + Address: 0x0800D1E4 + Address: 0x0800D1E8 + Address: 0x0800D1EC + Address: 0x0800D1F0 + Address: 0x0800D1F4 + Address: 0x0800D1F8 + Address: 0x0800D1FC + Address: 0x0800D200 + Address: 0x0800D204 + Address: 0x0800D208 + Address: 0x0800D20C + Address: 0x0800D210 + Address: 0x0800D214 + Address: 0x0800D218 + Address: 0x0800D21C + Address: 0x0800D220 + Address: 0x0800D224 + Address: 0x0800D228 + Address: 0x0800D22C + Address: 0x0800D230 + Address: 0x0800D234 + Address: 0x0800D238 + Address: 0x0800D23C + Address: 0x0800D240 + Address: 0x0800D244 + Address: 0x0800D248 + Address: 0x0800D24C + Address: 0x0800D250 + Address: 0x0800D254 + Address: 0x0800D258 + Address: 0x0800D25C + Address: 0x0800D260 + Address: 0x0800D264 + Address: 0x0800D268 + Address: 0x0800D26C + Address: 0x0800D270 + Address: 0x0800D2A0 + Address: 0x0800D2A4 + Address: 0x0800D2A8 + Address: 0x0800D2AC + Address: 0x0800D2B0 + Address: 0x0800D2B4 + Address: 0x0800D2B8 + Address: 0x0800D2BC + Address: 0x0800D2C0 + Address: 0x0800D2C4 + Address: 0x0800D2C8 + Address: 0x0800D2CC + Address: 0x0800D2D0 + Address: 0x0800D2D4 + Address: 0x0800D2D8 + Address: 0x0800D2DC + Address: 0x0800D2E0 + Address: 0x0800D2E4 + Address: 0x0800D2E8 + Address: 0x0800D2EC + Address: 0x0800D2F0 + Address: 0x0800D2F4 + Address: 0x0800D2F8 + Address: 0x0800D2FC + Address: 0x0800D300 + Address: 0x0800D304 + Address: 0x0800D308 + Address: 0x0800D30C + Address: 0x0800D310 + Address: 0x0800D314 + Address: 0x0800D318 + Address: 0x0800D31C + Address: 0x0800D320 + Address: 0x0800D324 + Address: 0x0800D328 + Address: 0x0800D32C + Address: 0x0800D330 + Address: 0x0800D334 + Address: 0x0800D358 + Address: 0x0800D35C + Address: 0x0800D360 + Address: 0x0800D364 + Address: 0x0800D368 + Address: 0x0800D36C + Address: 0x0800D370 + Address: 0x0800D374 + Address: 0x0800D378 + Address: 0x0800D37C + Address: 0x0800D380 + Address: 0x0800D384 + Address: 0x0800D388 + Address: 0x0800D38C + Address: 0x0800D390 + Address: 0x0800D394 + Address: 0x0800D398 + Address: 0x0800D39C + Address: 0x0800D3A0 + Address: 0x0800D3A4 + Address: 0x0800D3A8 + Address: 0x0800D3AC + Address: 0x0800D3B0 + Address: 0x0800D3B4 + Address: 0x0800D3B8 + Address: 0x0800D3BC + Address: 0x0800D3C0 + Address: 0x0800D3C4 + Address: 0x0800D3C8 + Address: 0x0800D3CC + Address: 0x0800D3D0 + Address: 0x0800D3D4 + Address: 0x0800D3D8 + Address: 0x0800D3DC + Address: 0x0800D3E0 + Address: 0x0800D3E4 + Address: 0x0800D3E8 + Address: 0x0800D404 + Address: 0x0800D408 + Address: 0x0800D40C + Address: 0x0800D410 + Address: 0x0800D414 + Address: 0x0800D418 + Address: 0x0800D41C + Address: 0x0800D420 + Address: 0x0800D424 + Address: 0x0800D428 + Address: 0x0800D42C + Address: 0x0800D430 + Address: 0x0800D434 + Address: 0x0800D438 + Address: 0x0800D43C + Address: 0x0800D440 + Address: 0x0800D444 + Address: 0x0800D448 + Address: 0x0800D44C + Address: 0x0800D450 + Address: 0x0800D460 + Address: 0x0800D464 + Address: 0x0800D468 + Address: 0x0800D46C + Address: 0x0800D470 + Address: 0x0800D474 + Address: 0x0800D478 + Address: 0x0800D47C + Address: 0x0800D480 + Address: 0x0800D484 + Address: 0x0800D488 + Address: 0x0800D48C + Address: 0x0800D490 + Address: 0x0800D494 + Address: 0x0800D498 + Address: 0x0800D49C + Address: 0x0800D4A0 + Address: 0x0800D4A4 + Address: 0x0800D4C0 + Address: 0x0800D4C4 + Address: 0x0800D4C8 + Address: 0x0800D4CC + Address: 0x0800D4D0 + Address: 0x0800D4D4 + Address: 0x0800D4D8 + Address: 0x0800D4DC + Address: 0x0800D4E0 + Address: 0x0800D4E4 + Address: 0x0800D4E8 + Address: 0x0800D4EC + Address: 0x0800D4F0 + Address: 0x0800D4F4 + Address: 0x0800D4F8 + Address: 0x0800D4FC + Address: 0x0800D500 + Address: 0x0800D504 + Address: 0x0800D508 + Address: 0x0800D50C + Address: 0x0800D514 + Address: 0x0800D518 + Address: 0x0800D51C + Address: 0x0800D520 + Address: 0x0800D524 + Address: 0x0800D528 + Address: 0x0800D52C + Address: 0x0800D530 + Address: 0x0800D534 + Address: 0x0800D538 + Address: 0x0800D53C + Address: 0x0800D540 + Address: 0x0800D544 + Address: 0x0800D548 + Address: 0x0800D54C + Address: 0x0800D550 + Address: 0x0800D554 + Address: 0x0800D57C + Address: 0x0800D580 + Address: 0x0800D584 + Address: 0x0800D588 + Address: 0x0800D58C + Address: 0x0800D590 + Address: 0x0800D594 + Address: 0x0800D598 + Address: 0x0800D59C + Address: 0x0800D5A0 + Address: 0x0800D5A4 + Address: 0x0800D5A8 + Address: 0x0800D5AC + Address: 0x0800D5B0 + Address: 0x0800D5B4 + Address: 0x0800D5B8 + Address: 0x0800D5BC + Address: 0x0800D5C0 + Address: 0x0800D5C4 + Address: 0x0800D5C8 + Address: 0x0800D5CC + Address: 0x0800D5D4 + Address: 0x0800D5D8 + Address: 0x0800D5DC + Address: 0x0800D5E0 + Address: 0x0800D5E4 + Address: 0x0800D5E8 + Address: 0x0800D5EC + Address: 0x0800D5F0 + Address: 0x0800D5F4 + Address: 0x0800D5F8 + Address: 0x0800D5FC + Address: 0x0800D600 + Address: 0x0800D604 + Address: 0x0800D608 + Address: 0x0800D60C + Address: 0x0800D610 + Address: 0x0800D614 + Address: 0x0800D63C + Address: 0x0800D640 + Address: 0x0800D644 + Address: 0x0800D648 + Address: 0x0800D64C + Address: 0x0800D650 + Address: 0x0800D654 + Address: 0x0800D658 + Address: 0x0800D65C + Address: 0x0800D660 + Address: 0x0800D664 + Address: 0x0800D668 + Address: 0x0800D66C + Address: 0x0800D670 + Address: 0x0800D674 + Address: 0x0800D678 + Address: 0x0800D67C + Address: 0x0800D680 + Address: 0x0800D684 + Address: 0x0800D688 + Address: 0x0800D68C + Address: 0x0800D690 + Address: 0x0800D694 + Address: 0x0800D698 + Address: 0x0800D69C + Address: 0x0800D6A0 + Address: 0x0800D6A4 + Address: 0x0800D6A8 + Address: 0x0800D6AC + Address: 0x0800D6B0 + Address: 0x0800D6B4 + Address: 0x0800D6B8 + Address: 0x0800D6BC + Address: 0x0800D6C0 + Address: 0x0800D6C4 + Address: 0x0800D6C8 + Address: 0x0800D6CC + Address: 0x0800D6F4 + Address: 0x0800D6F8 + Address: 0x0800D6FC + Address: 0x0800D700 + Address: 0x0800D704 + Address: 0x0800D708 + Address: 0x0800D70C + Address: 0x0800D710 + Address: 0x0800D714 + Address: 0x0800D718 + Address: 0x0800D71C + Address: 0x0800D720 + Address: 0x0800D724 + Address: 0x0800D728 + Address: 0x0800D72C + Address: 0x0800D730 + Address: 0x0800D734 + Address: 0x0800D738 + Address: 0x0800D73C + Address: 0x0800D740 + Address: 0x0800D744 + Address: 0x0800D748 + Address: 0x0800D74C + Address: 0x0800D750 + Address: 0x0800D754 + Address: 0x0800D758 + Address: 0x0800D75C + Address: 0x0800D760 + Address: 0x0800D764 + Address: 0x0800D768 + Address: 0x0800D76C + Address: 0x0800D770 + Address: 0x0800D774 + Address: 0x0800D778 + Address: 0x0800D77C + Address: 0x0800D780 + Address: 0x0800D784 + Address: 0x0800D788 + Address: 0x0800D7B0 + Address: 0x0800D7B4 + Address: 0x0800D7B8 + Address: 0x0800D7BC + Address: 0x0800D7C0 + Address: 0x0800D7C4 + Address: 0x0800D7C8 + Address: 0x0800D7CC + Address: 0x0800D7D0 + Address: 0x0800D7D4 + Address: 0x0800D7D8 + Address: 0x0800D7DC + Address: 0x0800D7E0 + Address: 0x0800D7E4 + Address: 0x0800D7E8 + Address: 0x0800D7EC + Address: 0x0800D7F0 + Address: 0x0800D7F4 + Address: 0x0800D7F8 + Address: 0x0800D7FC + Address: 0x0800D800 + Address: 0x0800D804 + Address: 0x0800D808 + Address: 0x0800D80C + Address: 0x0800D810 + Address: 0x0800D814 + Address: 0x0800D818 + Address: 0x0800D81C + Address: 0x0800D820 + Address: 0x0800D824 + Address: 0x0800D828 + Address: 0x0800D82C + Address: 0x0800D830 + Address: 0x0800D834 + Address: 0x0800D838 + Address: 0x0800D83C + Address: 0x0800D840 + Address: 0x0800D854 + Address: 0x0800D858 + Address: 0x0800D85C + Address: 0x0800D860 + Address: 0x0800D864 + Address: 0x0800D868 + Address: 0x0800D86C + Address: 0x0800D870 + Address: 0x0800D874 + Address: 0x0800D878 + Address: 0x0800D87C + Address: 0x0800D880 + Address: 0x0800D884 + Address: 0x0800D888 + Address: 0x0800D88C + Address: 0x0800D890 + Address: 0x0800D894 + Address: 0x0800D898 + Address: 0x0800D89C + Address: 0x0800D8B4 + Address: 0x0800D8B8 + Address: 0x0800D8BC + Address: 0x0800D8C0 + Address: 0x0800D8C4 + Address: 0x0800D8C8 + Address: 0x0800D8CC + Address: 0x0800D8D0 + Address: 0x0800D8D4 + Address: 0x0800D8D8 + Address: 0x0800D8DC + Address: 0x0800D8E0 + Address: 0x0800D8E4 + Address: 0x0800D8E8 + Address: 0x0800D8EC + Address: 0x0800D8F0 + Address: 0x0800D8F4 + Address: 0x0800D8F8 + Address: 0x0800D8FC + Address: 0x0800D914 + Address: 0x0800D918 + Address: 0x0800D91C + Address: 0x0800D920 + Address: 0x0800D924 + Address: 0x0800D928 + Address: 0x0800D92C + Address: 0x0800D930 + Address: 0x0800D934 + Address: 0x0800D938 + Address: 0x0800D93C + Address: 0x0800D940 + Address: 0x0800D944 + Address: 0x0800D948 + Address: 0x0800D94C + Address: 0x0800D950 + Address: 0x0800D954 + Address: 0x0800D958 + Address: 0x0800D95C + Address: 0x0800D970 + Address: 0x0800D974 + Address: 0x0800D978 + Address: 0x0800D97C + Address: 0x0800D980 + Address: 0x0800D984 + Address: 0x0800D988 + Address: 0x0800D98C + Address: 0x0800D990 + Address: 0x0800D994 + Address: 0x0800D998 + Address: 0x0800D99C + Address: 0x0800D9A0 + Address: 0x0800D9A4 + Address: 0x0800D9A8 + Address: 0x0800D9AC + Address: 0x0800D9B0 + Address: 0x0800D9B4 + Address: 0x0800D9B8 + Address: 0x0800D9C8 + Address: 0x0800D9CC + Address: 0x0800D9D0 + Address: 0x0800D9D4 + Address: 0x0800D9D8 + Address: 0x0800D9DC + Address: 0x0800D9E0 + Address: 0x0800D9E4 + Address: 0x0800D9E8 + Address: 0x0800D9EC + Address: 0x0800D9F0 + Address: 0x0800D9F4 + Address: 0x0800D9F8 + Address: 0x0800D9FC + Address: 0x0800DA00 + Address: 0x0800DA04 + Address: 0x0800DA08 + Address: 0x0800DA0C + Address: 0x0800DA2C + Address: 0x0800DA30 + Address: 0x0800DA34 + Address: 0x0800DA38 + Address: 0x0800DA3C + Address: 0x0800DA40 + Address: 0x0800DA44 + Address: 0x0800DA48 + Address: 0x0800DA4C + Address: 0x0800DA50 + Address: 0x0800DA54 + Address: 0x0800DA58 + Address: 0x0800DA5C + Address: 0x0800DA60 + Address: 0x0800DA64 + Address: 0x0800DA68 + Address: 0x0800DA6C + Address: 0x0800DA70 + Address: 0x0800DA74 + Address: 0x0800DA78 + Address: 0x0800DA8C + Address: 0x0800DA90 + Address: 0x0800DA94 + Address: 0x0800DA98 + Address: 0x0800DA9C + Address: 0x0800DAA0 + Address: 0x0800DAA4 + Address: 0x0800DAA8 + Address: 0x0800DAAC + Address: 0x0800DAB0 + Address: 0x0800DAB4 + Address: 0x0800DAB8 + Address: 0x0800DABC + Address: 0x0800DAC0 + Address: 0x0800DAC4 + Address: 0x0800DAC8 + Address: 0x0800DACC + Address: 0x0800DAD0 + Address: 0x0800DAE4 + Address: 0x0800DAE8 + Address: 0x0800DAEC + Address: 0x0800DAF0 + Address: 0x0800DAF4 + Address: 0x0800DAF8 + Address: 0x0800DAFC + Address: 0x0800DB00 + Address: 0x0800DB04 + Address: 0x0800DB08 + Address: 0x0800DB0C + Address: 0x0800DB10 + Address: 0x0800DB14 + Address: 0x0800DB18 + Address: 0x0800DB1C + Address: 0x0800DB20 + Address: 0x0800DB24 + Address: 0x0800DB28 + Address: 0x0800DB2C + Address: 0x0800DB3C + Address: 0x0800DB40 + Address: 0x0800DB44 + Address: 0x0800DB48 + Address: 0x0800DB4C + Address: 0x0800DB50 + Address: 0x0800DB54 + Address: 0x0800DB58 + Address: 0x0800DB5C + Address: 0x0800DB60 + Address: 0x0800DB64 + Address: 0x0800DB68 + Address: 0x0800DB6C + Address: 0x0800DB70 + Address: 0x0800DB74 + Address: 0x0800DB78 + Address: 0x0800DB7C + Address: 0x0800DB80 + Address: 0x0800DBA0 + Address: 0x0800DBA4 + Address: 0x0800DBA8 + Address: 0x0800DBAC + Address: 0x0800DBB0 + Address: 0x0800DBB4 + Address: 0x0800DBB8 + Address: 0x0800DBBC + Address: 0x0800DBC0 + Address: 0x0800DBC4 + Address: 0x0800DBC8 + Address: 0x0800DBCC + Address: 0x0800DBD0 + Address: 0x0800DBD4 + Address: 0x0800DBD8 + Address: 0x0800DBDC + Address: 0x0800DBE0 + Address: 0x0800DBE4 + Address: 0x0800DBE8 + Address: 0x0800DBEC + Address: 0x0800DBFC + Address: 0x0800DC00 + Address: 0x0800DC04 + Address: 0x0800DC08 + Address: 0x0800DC0C + Address: 0x0800DC10 + Address: 0x0800DC14 + Address: 0x0800DC18 + Address: 0x0800DC1C + Address: 0x0800DC20 + Address: 0x0800DC24 + Address: 0x0800DC28 + Address: 0x0800DC2C + Address: 0x0800DC30 + Address: 0x0800DC34 + Address: 0x0800DC38 + Address: 0x0800DC3C + Address: 0x0800DC40 + Address: 0x0800DC5C + Address: 0x0800DC60 + Address: 0x0800DC64 + Address: 0x0800DC68 + Address: 0x0800DC6C + Address: 0x0800DC70 + Address: 0x0800DC74 + Address: 0x0800DC78 + Address: 0x0800DC7C + Address: 0x0800DC80 + Address: 0x0800DC84 + Address: 0x0800DC88 + Address: 0x0800DC8C + Address: 0x0800DC90 + Address: 0x0800DC94 + Address: 0x0800DC98 + Address: 0x0800DC9C + Address: 0x0800DCA0 + Address: 0x0800DCA4 + Address: 0x0800DCA8 + Address: 0x0800DCAC + Address: 0x0800DCB0 + Address: 0x0800DCB4 + Address: 0x0800DCB8 + Address: 0x0800DCBC + Address: 0x0800DCC0 + Address: 0x0800DCC4 + Address: 0x0800DCC8 + Address: 0x0800DCCC + Address: 0x0800DCD0 + Address: 0x0800DCD4 + Address: 0x0800DCD8 + Address: 0x0800DCDC + Address: 0x0800DCE0 + Address: 0x0800DCE4 + Address: 0x0800DCE8 + Address: 0x0800DCEC + Address: 0x0800DD18 + Address: 0x0800DD1C + Address: 0x0800DD20 + Address: 0x0800DD24 + Address: 0x0800DD28 + Address: 0x0800DD2C + Address: 0x0800DD30 + Address: 0x0800DD34 + Address: 0x0800DD38 + Address: 0x0800DD3C + Address: 0x0800DD40 + Address: 0x0800DD44 + Address: 0x0800DD48 + Address: 0x0800DD4C + Address: 0x0800DD50 + Address: 0x0800DD54 + Address: 0x0800DD58 + Address: 0x0800DD5C + Address: 0x0800DD60 + Address: 0x0800DD64 + Address: 0x0800DD68 + Address: 0x0800DD70 + Address: 0x0800DD74 + Address: 0x0800DD78 + Address: 0x0800DD7C + Address: 0x0800DD80 + Address: 0x0800DD84 + Address: 0x0800DD88 + Address: 0x0800DD8C + Address: 0x0800DD90 + Address: 0x0800DD94 + Address: 0x0800DD98 + Address: 0x0800DD9C + Address: 0x0800DDA0 + Address: 0x0800DDA4 + Address: 0x0800DDA8 + Address: 0x0800DDAC + Address: 0x0800DDB0 + Address: 0x0800DDD0 + Address: 0x0800DDD4 + Address: 0x0800DDD8 + Address: 0x0800DDDC + Address: 0x0800DDE0 + Address: 0x0800DDE4 + Address: 0x0800DDE8 + Address: 0x0800DDEC + Address: 0x0800DDF0 + Address: 0x0800DDF4 + Address: 0x0800DDF8 + Address: 0x0800DDFC + Address: 0x0800DE00 + Address: 0x0800DE04 + Address: 0x0800DE08 + Address: 0x0800DE0C + Address: 0x0800DE10 + Address: 0x0800DE14 + Address: 0x0800DE18 + Address: 0x0800DE1C + Address: 0x0800DE20 + Address: 0x0800DE24 + Address: 0x0800DE28 + Address: 0x0800DE2C + Address: 0x0800DE30 + Address: 0x0800DE34 + Address: 0x0800DE38 + Address: 0x0800DE3C + Address: 0x0800DE40 + Address: 0x0800DE44 + Address: 0x0800DE48 + Address: 0x0800DE4C + Address: 0x0800DE50 + Address: 0x0800DE54 + Address: 0x0800DE58 + Address: 0x0800DE5C + Address: 0x0800DE60 + Address: 0x0800DE8C + Address: 0x0800DE90 + Address: 0x0800DE94 + Address: 0x0800DE98 + Address: 0x0800DE9C + Address: 0x0800DEA0 + Address: 0x0800DEA4 + Address: 0x0800DEA8 + Address: 0x0800DEAC + Address: 0x0800DEB0 + Address: 0x0800DEB4 + Address: 0x0800DEB8 + Address: 0x0800DEBC + Address: 0x0800DEC0 + Address: 0x0800DEC4 + Address: 0x0800DEC8 + Address: 0x0800DECC + Address: 0x0800DED0 + Address: 0x0800DED4 + Address: 0x0800DED8 + Address: 0x0800DEDC + Address: 0x0800DEE0 + Address: 0x0800DEE4 + Address: 0x0800DEE8 + Address: 0x0800DEEC + Address: 0x0800DEF0 + Address: 0x0800DEF4 + Address: 0x0800DEF8 + Address: 0x0800DEFC + Address: 0x0800DF00 + Address: 0x0800DF04 + Address: 0x0800DF08 + Address: 0x0800DF0C + Address: 0x0800DF10 + Address: 0x0800DF14 + Address: 0x0800DF18 + Address: 0x0800DF1C + Address: 0x0800DF20 + Address: 0x0800DF4C + Address: 0x0800DF50 + Address: 0x0800DF54 + Address: 0x0800DF58 + Address: 0x0800DF5C + Address: 0x0800DF60 + Address: 0x0800DF64 + Address: 0x0800DF68 + Address: 0x0800DF6C + Address: 0x0800DF70 + Address: 0x0800DF74 + Address: 0x0800DF78 + Address: 0x0800DF7C + Address: 0x0800DF80 + Address: 0x0800DF84 + Address: 0x0800DF88 + Address: 0x0800DF8C + Address: 0x0800DF90 + Address: 0x0800DF94 + Address: 0x0800DF98 + Address: 0x0800DF9C + Address: 0x0800DFA0 + Address: 0x0800DFA4 + Address: 0x0800DFA8 + Address: 0x0800DFAC + Address: 0x0800DFB0 + Address: 0x0800DFB4 + Address: 0x0800DFB8 + Address: 0x0800DFBC + Address: 0x0800DFC0 + Address: 0x0800DFC4 + Address: 0x0800DFC8 + Address: 0x0800DFCC + Address: 0x0800DFD0 + Address: 0x0800DFD4 + Address: 0x0800DFD8 + Address: 0x0800DFDC + Address: 0x0800DFE0 + Address: 0x0800E008 + Address: 0x0800E00C + Address: 0x0800E010 + Address: 0x0800E014 + Address: 0x0800E018 + Address: 0x0800E01C + Address: 0x0800E020 + Address: 0x0800E024 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0x0800E0FC + Address: 0x0800E100 + Address: 0x0800E104 + Address: 0x0800E108 + Address: 0x0800E118 + Address: 0x0800E11C + Address: 0x0800E120 + Address: 0x0800E124 + Address: 0x0800E128 + Address: 0x0800E12C + Address: 0x0800E130 + Address: 0x0800E134 + Address: 0x0800E138 + Address: 0x0800E13C + Address: 0x0800E140 + Address: 0x0800E144 + Address: 0x0800E148 + Address: 0x0800E14C + Address: 0x0800E150 + Address: 0x0800E154 + Address: 0x0800E158 + Address: 0x0800E15C + Address: 0x0800E174 + Address: 0x0800E178 + Address: 0x0800E17C + Address: 0x0800E180 + Address: 0x0800E184 + Address: 0x0800E188 + Address: 0x0800E18C + Address: 0x0800E190 + Address: 0x0800E194 + Address: 0x0800E198 + Address: 0x0800E19C + Address: 0x0800E1A0 + Address: 0x0800E1A4 + Address: 0x0800E1A8 + Address: 0x0800E1AC + Address: 0x0800E1B0 + Address: 0x0800E1B4 + Address: 0x0800E1B8 + Address: 0x0800E1BC + Address: 0x0800E1CC + Address: 0x0800E1D0 + Address: 0x0800E1D4 + Address: 0x0800E1D8 + Address: 0x0800E1DC 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0x0800E2B8 + Address: 0x0800E2BC + Address: 0x0800E2C0 + Address: 0x0800E2C4 + Address: 0x0800E2C8 + Address: 0x0800E2CC + Address: 0x0800E2E8 + Address: 0x0800E2EC + Address: 0x0800E2F0 + Address: 0x0800E2F4 + Address: 0x0800E2F8 + Address: 0x0800E2FC + Address: 0x0800E300 + Address: 0x0800E304 + Address: 0x0800E308 + Address: 0x0800E30C + Address: 0x0800E310 + Address: 0x0800E314 + Address: 0x0800E318 + Address: 0x0800E31C + Address: 0x0800E320 + Address: 0x0800E324 + Address: 0x0800E328 + Address: 0x0800E32C + Address: 0x0800E330 + Address: 0x0800E33C + Address: 0x0800E340 + Address: 0x0800E344 + Address: 0x0800E348 + Address: 0x0800E34C + Address: 0x0800E350 + Address: 0x0800E354 + Address: 0x0800E358 + Address: 0x0800E35C + Address: 0x0800E360 + Address: 0x0800E364 + Address: 0x0800E368 + Address: 0x0800E36C + Address: 0x0800E370 + Address: 0x0800E374 + Address: 0x0800E378 + Address: 0x0800E37C + Address: 0x0800E380 + Address: 0x0800E3A4 + Address: 0x0800E3A8 + Address: 0x0800E3AC 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0x0800E484 + Address: 0x0800E488 + Address: 0x0800E48C + Address: 0x0800E490 + Address: 0x0800E494 + Address: 0x0800E498 + Address: 0x0800E49C + Address: 0x0800E4A0 + Address: 0x0800E4A4 + Address: 0x0800E4B4 + Address: 0x0800E4B8 + Address: 0x0800E4BC + Address: 0x0800E4C0 + Address: 0x0800E4C4 + Address: 0x0800E4C8 + Address: 0x0800E4CC + Address: 0x0800E4D0 + Address: 0x0800E4D4 + Address: 0x0800E4D8 + Address: 0x0800E4DC + Address: 0x0800E4E0 + Address: 0x0800E4E4 + Address: 0x0800E4E8 + Address: 0x0800E4EC + Address: 0x0800E4F0 + Address: 0x0800E4F4 + Address: 0x0800E4F8 + Address: 0x0800E518 + Address: 0x0800E51C + Address: 0x0800E520 + Address: 0x0800E524 + Address: 0x0800E528 + Address: 0x0800E52C + Address: 0x0800E530 + Address: 0x0800E534 + Address: 0x0800E538 + Address: 0x0800E53C + Address: 0x0800E540 + Address: 0x0800E544 + Address: 0x0800E548 + Address: 0x0800E54C + Address: 0x0800E550 + Address: 0x0800E554 + Address: 0x0800E558 + Address: 0x0800E55C + Address: 0x0800E560 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0x0800E63C + Address: 0x0800E640 + Address: 0x0800E644 + Address: 0x0800E648 + Address: 0x0800E64C + Address: 0x0800E650 + Address: 0x0800E654 + Address: 0x0800E658 + Address: 0x0800E65C + Address: 0x0800E660 + Address: 0x0800E664 + Address: 0x0800E68C + Address: 0x0800E690 + Address: 0x0800E694 + Address: 0x0800E698 + Address: 0x0800E69C + Address: 0x0800E6A0 + Address: 0x0800E6A4 + Address: 0x0800E6A8 + Address: 0x0800E6AC + Address: 0x0800E6B0 + Address: 0x0800E6B4 + Address: 0x0800E6B8 + Address: 0x0800E6BC + Address: 0x0800E6C0 + Address: 0x0800E6C4 + Address: 0x0800E6C8 + Address: 0x0800E6CC + Address: 0x0800E6D0 + Address: 0x0800E6D4 + Address: 0x0800E6D8 + Address: 0x0800E6DC + Address: 0x0800E6E4 + Address: 0x0800E6E8 + Address: 0x0800E6EC + Address: 0x0800E6F0 + Address: 0x0800E6F4 + Address: 0x0800E6F8 + Address: 0x0800E6FC + Address: 0x0800E700 + Address: 0x0800E704 + Address: 0x0800E708 + Address: 0x0800E70C + Address: 0x0800E710 + Address: 0x0800E714 + Address: 0x0800E718 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0x0800E814 + Address: 0x0800E818 + Address: 0x0800E81C + Address: 0x0800E820 + Address: 0x0800E824 + Address: 0x0800E828 + Address: 0x0800E82C + Address: 0x0800E830 + Address: 0x0800E834 + Address: 0x0800E838 + Address: 0x0800E83C + Address: 0x0800E840 + Address: 0x0800E844 + Address: 0x0800E848 + Address: 0x0800E84C + Address: 0x0800E850 + Address: 0x0800E858 + Address: 0x0800E85C + Address: 0x0800E860 + Address: 0x0800E864 + Address: 0x0800E868 + Address: 0x0800E86C + Address: 0x0800E870 + Address: 0x0800E874 + Address: 0x0800E878 + Address: 0x0800E87C + Address: 0x0800E880 + Address: 0x0800E884 + Address: 0x0800E888 + Address: 0x0800E88C + Address: 0x0800E890 + Address: 0x0800E894 + Address: 0x0800E898 + Address: 0x0800E8B8 + Address: 0x0800E8BC + Address: 0x0800E8C0 + Address: 0x0800E8C4 + Address: 0x0800E8C8 + Address: 0x0800E8CC + Address: 0x0800E8D0 + Address: 0x0800E8D4 + Address: 0x0800E8D8 + Address: 0x0800E8DC + Address: 0x0800E8E0 + Address: 0x0800E8E4 + Address: 0x0800E8E8 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0x0800E9CC + Address: 0x0800E9D0 + Address: 0x0800E9D4 + Address: 0x0800E9D8 + Address: 0x0800E9DC + Address: 0x0800E9E0 + Address: 0x0800E9E4 + Address: 0x0800E9E8 + Address: 0x0800E9EC + Address: 0x0800E9F0 + Address: 0x0800E9F4 + Address: 0x0800E9F8 + Address: 0x0800E9FC + Address: 0x0800EA00 + Address: 0x0800EA04 + Address: 0x0800EA08 + Address: 0x0800EA0C + Address: 0x0800EA30 + Address: 0x0800EA34 + Address: 0x0800EA38 + Address: 0x0800EA3C + Address: 0x0800EA40 + Address: 0x0800EA44 + Address: 0x0800EA48 + Address: 0x0800EA4C + Address: 0x0800EA50 + Address: 0x0800EA54 + Address: 0x0800EA58 + Address: 0x0800EA5C + Address: 0x0800EA60 + Address: 0x0800EA64 + Address: 0x0800EA68 + Address: 0x0800EA6C + Address: 0x0800EA70 + Address: 0x0800EA74 + Address: 0x0800EA78 + Address: 0x0800EA7C + Address: 0x0800EA80 + Address: 0x0800EA84 + Address: 0x0800EA88 + Address: 0x0800EA8C + Address: 0x0800EA90 + Address: 0x0800EA94 + Address: 0x0800EA98 + Address: 0x0800EA9C + Address: 0x0800EAA0 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0x0800EB80 + Address: 0x0800EBA0 + Address: 0x0800EBA4 + Address: 0x0800EBA8 + Address: 0x0800EBAC + Address: 0x0800EBB0 + Address: 0x0800EBB4 + Address: 0x0800EBB8 + Address: 0x0800EBBC + Address: 0x0800EBC0 + Address: 0x0800EBC4 + Address: 0x0800EBC8 + Address: 0x0800EBCC + Address: 0x0800EBD0 + Address: 0x0800EBD4 + Address: 0x0800EBD8 + Address: 0x0800EBDC + Address: 0x0800EBE0 + Address: 0x0800EBE4 + Address: 0x0800EBE8 + Address: 0x0800EBEC + Address: 0x0800EBF0 + Address: 0x0800EBF4 + Address: 0x0800EBF8 + Address: 0x0800EBFC + Address: 0x0800EC00 + Address: 0x0800EC04 + Address: 0x0800EC08 + Address: 0x0800EC0C + Address: 0x0800EC10 + Address: 0x0800EC14 + Address: 0x0800EC18 + Address: 0x0800EC1C + Address: 0x0800EC20 + Address: 0x0800EC24 + Address: 0x0800EC28 + Address: 0x0800EC2C + Address: 0x0800EC30 + Address: 0x0800EC54 + Address: 0x0800EC58 + Address: 0x0800EC5C + Address: 0x0800EC60 + Address: 0x0800EC64 + Address: 0x0800EC68 + Address: 0x0800EC6C + Address: 0x0800EC70 + Address: 0x0800EC74 + Address: 0x0800EC78 + Address: 0x0800EC7C + Address: 0x0800EC80 + Address: 0x0800EC84 + Address: 0x0800EC88 + Address: 0x0800EC8C + Address: 0x0800EC90 + Address: 0x0800EC94 + Address: 0x0800EC98 + Address: 0x0800EC9C + Address: 0x0800ECA0 + Address: 0x0800ECB0 + Address: 0x0800ECB4 + Address: 0x0800ECB8 + Address: 0x0800ECBC + Address: 0x0800ECC0 + Address: 0x0800ECC4 + Address: 0x0800ECC8 + Address: 0x0800ECCC + Address: 0x0800ECD0 + Address: 0x0800ECD4 + Address: 0x0800ECD8 + Address: 0x0800ECDC + Address: 0x0800ECE0 + Address: 0x0800ECE4 + Address: 0x0800ECE8 + Address: 0x0800ECEC + Address: 0x0800ECF0 + Address: 0x0800ECF4 + Address: 0x0800ED14 + Address: 0x0800ED18 + Address: 0x0800ED1C + Address: 0x0800ED20 + Address: 0x0800ED24 + Address: 0x0800ED28 + Address: 0x0800ED2C + Address: 0x0800ED30 + Address: 0x0800ED34 + Address: 0x0800ED38 + Address: 0x0800ED3C + Address: 0x0800ED40 + Address: 0x0800ED44 + Address: 0x0800ED48 + Address: 0x0800ED4C + Address: 0x0800ED50 + Address: 0x0800ED54 + Address: 0x0800ED58 + Address: 0x0800ED5C + Address: 0x0800ED60 + Address: 0x0800ED6C + Address: 0x0800ED70 + Address: 0x0800ED74 + Address: 0x0800ED78 + Address: 0x0800ED7C + Address: 0x0800ED80 + Address: 0x0800ED84 + Address: 0x0800ED88 + Address: 0x0800ED8C + Address: 0x0800ED90 + Address: 0x0800ED94 + Address: 0x0800ED98 + Address: 0x0800ED9C + Address: 0x0800EDA0 + Address: 0x0800EDA4 + Address: 0x0800EDA8 + Address: 0x0800EDAC + Address: 0x0800EDB0 + Address: 0x0800EDC8 + Address: 0x0800EDCC + Address: 0x0800EDD0 + Address: 0x0800EDD4 + Address: 0x0800EDD8 + Address: 0x0800EDDC + Address: 0x0800EDE0 + Address: 0x0800EDE4 + Address: 0x0800EDE8 + Address: 0x0800EDEC + Address: 0x0800EDF0 + Address: 0x0800EDF4 + Address: 0x0800EDF8 + Address: 0x0800EDFC + Address: 0x0800EE00 + Address: 0x0800EE04 + Address: 0x0800EE08 + Address: 0x0800EE0C + Address: 0x0800EE10 + Address: 0x0800EE28 + Address: 0x0800EE2C + Address: 0x0800EE30 + Address: 0x0800EE34 + Address: 0x0800EE38 + Address: 0x0800EE3C + Address: 0x0800EE40 + Address: 0x0800EE44 + Address: 0x0800EE48 + Address: 0x0800EE4C + Address: 0x0800EE50 + Address: 0x0800EE54 + Address: 0x0800EE58 + Address: 0x0800EE5C + Address: 0x0800EE60 + Address: 0x0800EE64 + Address: 0x0800EE68 + Address: 0x0800EE6C + Address: 0x0800EE70 + Address: 0x0800EE88 + Address: 0x0800EE8C + Address: 0x0800EE90 + Address: 0x0800EE94 + Address: 0x0800EE98 + Address: 0x0800EE9C + Address: 0x0800EEA0 + Address: 0x0800EEA4 + Address: 0x0800EEA8 + Address: 0x0800EEAC + Address: 0x0800EEB0 + Address: 0x0800EEB4 + Address: 0x0800EEB8 + Address: 0x0800EEBC + Address: 0x0800EEC0 + Address: 0x0800EEC4 + Address: 0x0800EEC8 + Address: 0x0800EECC + Address: 0x0800EED0 + Address: 0x0800EEE0 + Address: 0x0800EEE4 + Address: 0x0800EEE8 + Address: 0x0800EEEC + Address: 0x0800EEF0 + Address: 0x0800EEF4 + Address: 0x0800EEF8 + Address: 0x0800EEFC + Address: 0x0800EF00 + Address: 0x0800EF04 + Address: 0x0800EF08 + Address: 0x0800EF0C + Address: 0x0800EF10 + Address: 0x0800EF14 + Address: 0x0800EF18 + Address: 0x0800EF1C + Address: 0x0800EF20 + Address: 0x0800EF24 + Address: 0x0800EF38 + Address: 0x0800EF3C + Address: 0x0800EF40 + Address: 0x0800EF44 + Address: 0x0800EF48 + Address: 0x0800EF4C + Address: 0x0800EF50 + Address: 0x0800EF54 + Address: 0x0800EF58 + Address: 0x0800EF5C + Address: 0x0800EF60 + Address: 0x0800EF64 + Address: 0x0800EF68 + Address: 0x0800EF6C + Address: 0x0800EF70 + Address: 0x0800EF74 + Address: 0x0800EF78 + Address: 0x0800EF7C + Address: 0x0800EF80 + Address: 0x0800EF9C + Address: 0x0800EFA0 + Address: 0x0800EFA4 + Address: 0x0800EFA8 + Address: 0x0800EFAC + Address: 0x0800EFB0 + Address: 0x0800EFB4 + Address: 0x0800EFB8 + Address: 0x0800EFBC + Address: 0x0800EFC0 + Address: 0x0800EFC4 + Address: 0x0800EFC8 + Address: 0x0800EFCC + Address: 0x0800EFD0 + Address: 0x0800EFD4 + Address: 0x0800EFD8 + Address: 0x0800EFDC + Address: 0x0800EFE0 + Address: 0x0800EFE4 + Address: 0x0800EFFC + Address: 0x0800F000 + Address: 0x0800F004 + Address: 0x0800F008 + Address: 0x0800F00C + Address: 0x0800F010 + Address: 0x0800F014 + Address: 0x0800F018 + Address: 0x0800F01C + Address: 0x0800F020 + Address: 0x0800F024 + Address: 0x0800F028 + Address: 0x0800F02C + Address: 0x0800F030 + Address: 0x0800F034 + Address: 0x0800F038 + Address: 0x0800F03C + Address: 0x0800F040 + Address: 0x0800F044 + Address: 0x0800F058 + Address: 0x0800F05C + Address: 0x0800F060 + Address: 0x0800F064 + Address: 0x0800F068 + Address: 0x0800F06C + Address: 0x0800F070 + Address: 0x0800F074 + Address: 0x0800F078 + Address: 0x0800F07C + Address: 0x0800F080 + Address: 0x0800F084 + Address: 0x0800F088 + Address: 0x0800F08C + Address: 0x0800F090 + Address: 0x0800F094 + Address: 0x0800F098 + Address: 0x0800F09C + Address: 0x0800F0B0 + Address: 0x0800F0B4 + Address: 0x0800F0B8 + Address: 0x0800F0BC + Address: 0x0800F0C0 + Address: 0x0800F0C4 + Address: 0x0800F0C8 + Address: 0x0800F0CC + Address: 0x0800F0D0 + Address: 0x0800F0D4 + Address: 0x0800F0D8 + Address: 0x0800F0DC + Address: 0x0800F0E0 + Address: 0x0800F0E4 + Address: 0x0800F0E8 + Address: 0x0800F0EC + Address: 0x0800F0F0 + Address: 0x0800F0F4 + Address: 0x0800F0F8 + Address: 0x0800F114 + Address: 0x0800F118 + Address: 0x0800F11C + Address: 0x0800F120 + Address: 0x0800F124 + Address: 0x0800F128 + Address: 0x0800F12C + Address: 0x0800F130 + Address: 0x0800F134 + Address: 0x0800F138 + Address: 0x0800F13C + Address: 0x0800F140 + Address: 0x0800F144 + Address: 0x0800F148 + Address: 0x0800F14C + Address: 0x0800F150 + Address: 0x0800F154 + Address: 0x0800F158 + Address: 0x0800F15C + Address: 0x0800F170 + Address: 0x0800F174 + Address: 0x0800F178 + Address: 0x0800F17C + Address: 0x0800F180 + Address: 0x0800F184 + Address: 0x0800F188 + Address: 0x0800F18C + Address: 0x0800F190 + Address: 0x0800F194 + Address: 0x0800F198 + Address: 0x0800F19C + Address: 0x0800F1A0 + Address: 0x0800F1A4 + Address: 0x0800F1A8 + Address: 0x0800F1AC + Address: 0x0800F1B0 + Address: 0x0800F1B4 + Address: 0x0800F1B8 + Address: 0x0800F1CC + Address: 0x0800F1D0 + Address: 0x0800F1D4 + Address: 0x0800F1D8 + Address: 0x0800F1DC + Address: 0x0800F1E0 + Address: 0x0800F1E4 + Address: 0x0800F1E8 + Address: 0x0800F1EC + Address: 0x0800F1F0 + Address: 0x0800F1F4 + Address: 0x0800F1F8 + Address: 0x0800F1FC + Address: 0x0800F200 + Address: 0x0800F204 + Address: 0x0800F208 + Address: 0x0800F20C + Address: 0x0800F210 + Address: 0x0800F214 + Address: 0x0800F224 + Address: 0x0800F228 + Address: 0x0800F22C + Address: 0x0800F230 + Address: 0x0800F234 + Address: 0x0800F238 + Address: 0x0800F23C + Address: 0x0800F240 + Address: 0x0800F244 + Address: 0x0800F248 + Address: 0x0800F24C + Address: 0x0800F250 + Address: 0x0800F254 + Address: 0x0800F258 + Address: 0x0800F25C + Address: 0x0800F260 + Address: 0x0800F264 + Address: 0x0800F268 + Address: 0x0800F28C + Address: 0x0800F290 + Address: 0x0800F294 + Address: 0x0800F298 + Address: 0x0800F29C + Address: 0x0800F2A0 + Address: 0x0800F2A4 + Address: 0x0800F2A8 + Address: 0x0800F2AC + Address: 0x0800F2B0 + Address: 0x0800F2B4 + Address: 0x0800F2B8 + Address: 0x0800F2BC + Address: 0x0800F2C0 + Address: 0x0800F2C4 + Address: 0x0800F2C8 + Address: 0x0800F2CC + Address: 0x0800F2D0 + Address: 0x0800F2D4 + Address: 0x0800F2D8 + Address: 0x0800F2E4 + Address: 0x0800F2E8 + Address: 0x0800F2EC + Address: 0x0800F2F0 + Address: 0x0800F2F4 + Address: 0x0800F2F8 + Address: 0x0800F2FC + Address: 0x0800F300 + Address: 0x0800F304 + Address: 0x0800F308 + Address: 0x0800F30C + Address: 0x0800F310 + Address: 0x0800F314 + Address: 0x0800F318 + Address: 0x0800F31C + Address: 0x0800F320 + Address: 0x0800F324 + Address: 0x0800F328 + Address: 0x0800F348 + Address: 0x0800F34C + Address: 0x0800F350 + Address: 0x0800F354 + Address: 0x0800F358 + Address: 0x0800F35C + Address: 0x0800F360 + Address: 0x0800F364 + Address: 0x0800F368 + Address: 0x0800F36C + Address: 0x0800F370 + Address: 0x0800F374 + Address: 0x0800F378 + Address: 0x0800F37C + Address: 0x0800F380 + Address: 0x0800F384 + Address: 0x0800F388 + Address: 0x0800F38C + Address: 0x0800F390 + Address: 0x0800F394 + Address: 0x0800F398 + Address: 0x0800F39C + Address: 0x0800F3A0 + Address: 0x0800F3A4 + Address: 0x0800F3A8 + Address: 0x0800F3AC + Address: 0x0800F3B0 + Address: 0x0800F3B4 + Address: 0x0800F3B8 + Address: 0x0800F3BC + Address: 0x0800F3C0 + Address: 0x0800F3C4 + Address: 0x0800F3C8 + Address: 0x0800F3CC + Address: 0x0800F3D0 + Address: 0x0800F3D4 + Address: 0x0800F3D8 + Address: 0x0800F404 + Address: 0x0800F408 + Address: 0x0800F40C + Address: 0x0800F410 + Address: 0x0800F414 + Address: 0x0800F418 + Address: 0x0800F41C + Address: 0x0800F420 + Address: 0x0800F424 + Address: 0x0800F428 + Address: 0x0800F42C + Address: 0x0800F430 + Address: 0x0800F434 + Address: 0x0800F438 + Address: 0x0800F43C + Address: 0x0800F440 + Address: 0x0800F444 + Address: 0x0800F448 + Address: 0x0800F44C + Address: 0x0800F450 + Address: 0x0800F454 + Address: 0x0800F45C + Address: 0x0800F460 + Address: 0x0800F464 + Address: 0x0800F468 + Address: 0x0800F46C + Address: 0x0800F470 + Address: 0x0800F474 + Address: 0x0800F478 + Address: 0x0800F47C + Address: 0x0800F480 + Address: 0x0800F484 + Address: 0x0800F488 + Address: 0x0800F48C + Address: 0x0800F490 + Address: 0x0800F494 + Address: 0x0800F498 + Address: 0x0800F49C + Address: 0x0800F4BC + Address: 0x0800F4C0 + Address: 0x0800F4C4 + Address: 0x0800F4C8 + Address: 0x0800F4CC + Address: 0x0800F4D0 + Address: 0x0800F4D4 + Address: 0x0800F4D8 + Address: 0x0800F4DC + Address: 0x0800F4E0 + Address: 0x0800F4E4 + Address: 0x0800F4E8 + Address: 0x0800F4EC + Address: 0x0800F4F0 + Address: 0x0800F4F4 + Address: 0x0800F4F8 + Address: 0x0800F4FC + Address: 0x0800F500 + Address: 0x0800F504 + Address: 0x0800F508 + Address: 0x0800F510 + Address: 0x0800F514 + Address: 0x0800F518 + Address: 0x0800F51C + Address: 0x0800F520 + Address: 0x0800F524 + Address: 0x0800F528 + Address: 0x0800F52C + Address: 0x0800F530 + Address: 0x0800F534 + Address: 0x0800F538 + Address: 0x0800F53C + Address: 0x0800F540 + Address: 0x0800F544 + Address: 0x0800F548 + Address: 0x0800F54C + Address: 0x0800F550 + Address: 0x0800F578 + Address: 0x0800F57C + Address: 0x0800F580 + Address: 0x0800F584 + Address: 0x0800F588 + Address: 0x0800F58C + Address: 0x0800F590 + Address: 0x0800F594 + Address: 0x0800F598 + Address: 0x0800F59C + Address: 0x0800F5A0 + Address: 0x0800F5A4 + Address: 0x0800F5A8 + Address: 0x0800F5AC + Address: 0x0800F5B0 + Address: 0x0800F5B4 + Address: 0x0800F5B8 + Address: 0x0800F5BC + Address: 0x0800F5C0 + Address: 0x0800F5C4 + Address: 0x0800F5C8 + Address: 0x0800F5D0 + Address: 0x0800F5D4 + Address: 0x0800F5D8 + Address: 0x0800F5DC + Address: 0x0800F5E0 + Address: 0x0800F5E4 + Address: 0x0800F5E8 + Address: 0x0800F5EC + Address: 0x0800F5F0 + Address: 0x0800F5F4 + Address: 0x0800F5F8 + Address: 0x0800F5FC + Address: 0x0800F600 + Address: 0x0800F604 + Address: 0x0800F608 + Address: 0x0800F60C + Address: 0x0800F610 + Address: 0x0800F630 + Address: 0x0800F634 + Address: 0x0800F638 + Address: 0x0800F63C + Address: 0x0800F640 + Address: 0x0800F644 + Address: 0x0800F648 + Address: 0x0800F64C + Address: 0x0800F650 + Address: 0x0800F654 + Address: 0x0800F658 + Address: 0x0800F65C + Address: 0x0800F660 + Address: 0x0800F664 + Address: 0x0800F668 + Address: 0x0800F66C + Address: 0x0800F670 + Address: 0x0800F674 + Address: 0x0800F678 + Address: 0x0800F67C + Address: 0x0800F684 + Address: 0x0800F688 + Address: 0x0800F68C + Address: 0x0800F690 + Address: 0x0800F694 + Address: 0x0800F698 + Address: 0x0800F69C + Address: 0x0800F6A0 + Address: 0x0800F6A4 + Address: 0x0800F6A8 + Address: 0x0800F6AC + Address: 0x0800F6B0 + Address: 0x0800F6B4 + Address: 0x0800F6B8 + Address: 0x0800F6BC + Address: 0x0800F6C0 + Address: 0x0800F6C4 + Address: 0x0800F6EC + Address: 0x0800F6F0 + Address: 0x0800F6F4 + Address: 0x0800F6F8 + Address: 0x0800F6FC + Address: 0x0800F700 + Address: 0x0800F704 + Address: 0x0800F708 + Address: 0x0800F70C + Address: 0x0800F710 + Address: 0x0800F714 + Address: 0x0800F718 + Address: 0x0800F71C + Address: 0x0800F720 + Address: 0x0800F724 + Address: 0x0800F728 + Address: 0x0800F72C + Address: 0x0800F730 + Address: 0x0800F734 + Address: 0x0800F738 + Address: 0x0800F73C + Address: 0x0800F744 + Address: 0x0800F748 + Address: 0x0800F74C + Address: 0x0800F750 + Address: 0x0800F754 + Address: 0x0800F758 + Address: 0x0800F75C + Address: 0x0800F760 + Address: 0x0800F764 + Address: 0x0800F768 + Address: 0x0800F76C + Address: 0x0800F770 + Address: 0x0800F774 + Address: 0x0800F778 + Address: 0x0800F77C + Address: 0x0800F780 + Address: 0x0800F784 + Address: 0x0800F7A8 + Address: 0x0800F7AC + Address: 0x0800F7B0 + Address: 0x0800F7B4 + Address: 0x0800F7B8 + Address: 0x0800F7BC + Address: 0x0800F7C0 + Address: 0x0800F7C4 + Address: 0x0800F7C8 + Address: 0x0800F7CC + Address: 0x0800F7D0 + Address: 0x0800F7D4 + Address: 0x0800F7D8 + Address: 0x0800F7DC + Address: 0x0800F7E0 + Address: 0x0800F7E4 + Address: 0x0800F7E8 + Address: 0x0800F7EC + Address: 0x0800F7F0 + Address: 0x0800F7F4 + Address: 0x0800F7F8 + Address: 0x0800F7FC + Address: 0x0800F800 + Address: 0x0800F804 + Address: 0x0800F808 + Address: 0x0800F80C + Address: 0x0800F810 + Address: 0x0800F814 + Address: 0x0800F818 + Address: 0x0800F81C + Address: 0x0800F820 + Address: 0x0800F824 + Address: 0x0800F828 + Address: 0x0800F82C + Address: 0x0800F830 + Address: 0x0800F834 + Address: 0x0800F838 + Address: 0x0800F860 + Address: 0x0800F864 + Address: 0x0800F868 + Address: 0x0800F86C + Address: 0x0800F870 + Address: 0x0800F874 + Address: 0x0800F878 + Address: 0x0800F87C + Address: 0x0800F880 + Address: 0x0800F884 + Address: 0x0800F888 + Address: 0x0800F88C + Address: 0x0800F890 + Address: 0x0800F894 + Address: 0x0800F898 + Address: 0x0800F89C + Address: 0x0800F8A0 + Address: 0x0800F8A4 + Address: 0x0800F8A8 + Address: 0x0800F8AC + Address: 0x0800F8B0 + Address: 0x0800F8B8 + Address: 0x0800F8BC + Address: 0x0800F8C0 + Address: 0x0800F8C4 + Address: 0x0800F8C8 + Address: 0x0800F8CC + Address: 0x0800F8D0 + Address: 0x0800F8D4 + Address: 0x0800F8D8 + Address: 0x0800F8DC + Address: 0x0800F8E0 + Address: 0x0800F8E4 + Address: 0x0800F8E8 + Address: 0x0800F8EC + Address: 0x0800F8F0 + Address: 0x0800F8F4 + Address: 0x0800F8F8 + Address: 0x0800F920 + Address: 0x0800F924 + Address: 0x0800F928 + Address: 0x0800F92C + Address: 0x0800F930 + Address: 0x0800F934 + Address: 0x0800F938 + Address: 0x0800F93C + Address: 0x0800F940 + Address: 0x0800F944 + Address: 0x0800F948 + Address: 0x0800F94C + Address: 0x0800F950 + Address: 0x0800F954 + Address: 0x0800F958 + Address: 0x0800F95C + Address: 0x0800F960 + Address: 0x0800F964 + Address: 0x0800F968 + Address: 0x0800F96C + Address: 0x0800F970 + Address: 0x0800F974 + Address: 0x0800F978 + Address: 0x0800F97C + Address: 0x0800F980 + Address: 0x0800F984 + Address: 0x0800F988 + Address: 0x0800F98C + Address: 0x0800F990 + Address: 0x0800F994 + Address: 0x0800F998 + Address: 0x0800F99C + Address: 0x0800F9A0 + Address: 0x0800F9A4 + Address: 0x0800F9A8 + Address: 0x0800F9AC + Address: 0x0800F9B0 + Address: 0x0800F9CC + Address: 0x0800F9D0 + Address: 0x0800F9D4 + Address: 0x0800F9D8 + Address: 0x0800F9DC + Address: 0x0800F9E0 + Address: 0x0800F9E4 + Address: 0x0800F9E8 + Address: 0x0800F9EC + Address: 0x0800F9F0 + Address: 0x0800F9F4 + Address: 0x0800F9F8 + Address: 0x0800F9FC + Address: 0x0800FA00 + Address: 0x0800FA04 + Address: 0x0800FA08 + Address: 0x0800FA0C + Address: 0x0800FA10 + Address: 0x0800FA14 + Address: 0x0800FA18 + Address: 0x0800FA28 + Address: 0x0800FA2C + Address: 0x0800FA30 + Address: 0x0800FA34 + Address: 0x0800FA38 + Address: 0x0800FA3C + Address: 0x0800FA40 + Address: 0x0800FA44 + Address: 0x0800FA48 + Address: 0x0800FA4C + Address: 0x0800FA50 + Address: 0x0800FA54 + Address: 0x0800FA58 + Address: 0x0800FA5C + Address: 0x0800FA60 + Address: 0x0800FA64 + Address: 0x0800FA68 + Address: 0x0800FA6C + Address: 0x0800FA84 + Address: 0x0800FA88 + Address: 0x0800FA8C + Address: 0x0800FA90 + Address: 0x0800FA94 + Address: 0x0800FA98 + Address: 0x0800FA9C + Address: 0x0800FAA0 + Address: 0x0800FAA4 + Address: 0x0800FAA8 + Address: 0x0800FAAC + Address: 0x0800FAB0 + Address: 0x0800FAB4 + Address: 0x0800FAB8 + Address: 0x0800FABC + Address: 0x0800FAC0 + Address: 0x0800FAC4 + Address: 0x0800FAC8 + Address: 0x0800FACC + Address: 0x0800FADC + Address: 0x0800FAE0 + Address: 0x0800FAE4 + Address: 0x0800FAE8 + Address: 0x0800FAEC + Address: 0x0800FAF0 + Address: 0x0800FAF4 + Address: 0x0800FAF8 + Address: 0x0800FAFC + Address: 0x0800FB00 + Address: 0x0800FB04 + Address: 0x0800FB08 + Address: 0x0800FB0C + Address: 0x0800FB10 + Address: 0x0800FB14 + Address: 0x0800FB18 + Address: 0x0800FB1C + Address: 0x0800FB20 + Address: 0x0800FB44 + Address: 0x0800FB48 + Address: 0x0800FB4C + Address: 0x0800FB50 + Address: 0x0800FB54 + Address: 0x0800FB58 + Address: 0x0800FB5C + Address: 0x0800FB60 + Address: 0x0800FB64 + Address: 0x0800FB68 + Address: 0x0800FB6C + Address: 0x0800FB70 + Address: 0x0800FB74 + Address: 0x0800FB78 + Address: 0x0800FB7C + Address: 0x0800FB80 + Address: 0x0800FB84 + Address: 0x0800FB88 + Address: 0x0800FB8C + Address: 0x0800FB90 + Address: 0x0800FB94 + Address: 0x0800FB98 + Address: 0x0800FB9C + Address: 0x0800FBA0 + Address: 0x0800FBA4 + Address: 0x0800FBA8 + Address: 0x0800FBAC + Address: 0x0800FBB0 + Address: 0x0800FBB4 + Address: 0x0800FBB8 + Address: 0x0800FBBC + Address: 0x0800FBC0 + Address: 0x0800FBC4 + Address: 0x0800FBC8 + Address: 0x0800FBCC + Address: 0x0800FBD0 + Address: 0x0800FBF4 + Address: 0x0800FBF8 + Address: 0x0800FBFC + Address: 0x0800FC00 + Address: 0x0800FC04 + Address: 0x0800FC08 + Address: 0x0800FC0C + Address: 0x0800FC10 + Address: 0x0800FC14 + Address: 0x0800FC18 + Address: 0x0800FC1C + Address: 0x0800FC20 + Address: 0x0800FC24 + Address: 0x0800FC28 + Address: 0x0800FC2C + Address: 0x0800FC30 + Address: 0x0800FC34 + Address: 0x0800FC38 + Address: 0x0800FC3C + Address: 0x0800FC40 + Address: 0x0800FC44 + Address: 0x0800FC48 + Address: 0x0800FC4C + Address: 0x0800FC50 + Address: 0x0800FC54 + Address: 0x0800FC58 + Address: 0x0800FC5C + Address: 0x0800FC60 + Address: 0x0800FC64 + Address: 0x0800FC68 + Address: 0x0800FC6C + Address: 0x0800FC70 + Address: 0x0800FC74 + Address: 0x0800FC78 + Address: 0x0800FC7C + Address: 0x0800FC80 + Address: 0x0800FC84 + Address: 0x0800FCAC + Address: 0x0800FCB0 + Address: 0x0800FCB4 + Address: 0x0800FCB8 + Address: 0x0800FCBC + Address: 0x0800FCC0 + Address: 0x0800FCC4 + Address: 0x0800FCC8 + Address: 0x0800FCCC + Address: 0x0800FCD0 + Address: 0x0800FCD4 + Address: 0x0800FCD8 + Address: 0x0800FCDC + Address: 0x0800FCE0 + Address: 0x0800FCE4 + Address: 0x0800FCE8 + Address: 0x0800FCEC + Address: 0x0800FCF0 + Address: 0x0800FCF4 + Address: 0x0800FCF8 + Address: 0x0800FCFC + Address: 0x0800FD04 + Address: 0x0800FD08 + Address: 0x0800FD0C + Address: 0x0800FD10 + Address: 0x0800FD14 + Address: 0x0800FD18 + Address: 0x0800FD1C + Address: 0x0800FD20 + Address: 0x0800FD24 + Address: 0x0800FD28 + Address: 0x0800FD2C + Address: 0x0800FD30 + Address: 0x0800FD34 + Address: 0x0800FD38 + Address: 0x0800FD3C + Address: 0x0800FD40 + Address: 0x0800FD44 + Address: 0x0800FD68 + Address: 0x0800FD6C + Address: 0x0800FD70 + Address: 0x0800FD74 + Address: 0x0800FD78 + Address: 0x0800FD7C + Address: 0x0800FD80 + Address: 0x0800FD84 + Address: 0x0800FD88 + Address: 0x0800FD8C + Address: 0x0800FD90 + Address: 0x0800FD94 + Address: 0x0800FD98 + Address: 0x0800FD9C + Address: 0x0800FDA0 + Address: 0x0800FDA4 + Address: 0x0800FDA8 + Address: 0x0800FDAC + Address: 0x0800FDB0 + Address: 0x0800FDB4 + Address: 0x0800FDB8 + Address: 0x0800FDBC + Address: 0x0800FDC0 + Address: 0x0800FDC4 + Address: 0x0800FDC8 + Address: 0x0800FDCC + Address: 0x0800FDD0 + Address: 0x0800FDD4 + Address: 0x0800FDD8 + Address: 0x0800FDDC + Address: 0x0800FDE0 + Address: 0x0800FDE4 + Address: 0x0800FDE8 + Address: 0x0800FDEC + Address: 0x0800FDF0 + Address: 0x0800FDF4 + Address: 0x0800FDF8 + Address: 0x0800FE20 + Address: 0x0800FE24 + Address: 0x0800FE28 + Address: 0x0800FE2C + Address: 0x0800FE30 + Address: 0x0800FE34 + Address: 0x0800FE38 + Address: 0x0800FE3C + Address: 0x0800FE40 + Address: 0x0800FE44 + Address: 0x0800FE48 + Address: 0x0800FE4C + Address: 0x0800FE50 + Address: 0x0800FE54 + Address: 0x0800FE58 + Address: 0x0800FE5C + Address: 0x0800FE60 + Address: 0x0800FE64 + Address: 0x0800FE68 + Address: 0x0800FE6C + Address: 0x0800FE70 + Address: 0x0800FE78 + Address: 0x0800FE7C + Address: 0x0800FE80 + Address: 0x0800FE84 + Address: 0x0800FE88 + Address: 0x0800FE8C + Address: 0x0800FE90 + Address: 0x0800FE94 + Address: 0x0800FE98 + Address: 0x0800FE9C + Address: 0x0800FEA0 + Address: 0x0800FEA4 + Address: 0x0800FEA8 + Address: 0x0800FEAC + Address: 0x0800FEB0 + Address: 0x0800FEB4 + Address: 0x0800FEB8 + Address: 0x0800FEDC + Address: 0x0800FEE0 + Address: 0x0800FEE4 + Address: 0x0800FEE8 + Address: 0x0800FEEC + Address: 0x0800FEF0 + Address: 0x0800FEF4 + Address: 0x0800FEF8 + Address: 0x0800FEFC + Address: 0x0800FF00 + Address: 0x0800FF04 + Address: 0x0800FF08 + Address: 0x0800FF0C + Address: 0x0800FF10 + Address: 0x0800FF14 + Address: 0x0800FF18 + Address: 0x0800FF1C + Address: 0x0800FF20 + Address: 0x0800FF24 + Address: 0x0800FF28 + Address: 0x0800FF2C + Address: 0x0800FF30 + Address: 0x0800FF34 + Address: 0x0800FF38 + Address: 0x0800FF3C + Address: 0x0800FF40 + Address: 0x0800FF44 + Address: 0x0800FF48 + Address: 0x0800FF4C + Address: 0x0800FF50 + Address: 0x0800FF54 + Address: 0x0800FF58 + Address: 0x0800FF5C + Address: 0x0800FF60 + Address: 0x0800FF64 + Address: 0x0800FF68 + Address: 0x0800FF6C + Address: 0x0800FF98 + Address: 0x0800FF9C + Address: 0x0800FFA0 + Address: 0x0800FFA4 + Address: 0x0800FFA8 + Address: 0x0800FFAC + Address: 0x0800FFB0 + Address: 0x0800FFB4 + Address: 0x0800FFB8 + Address: 0x0800FFBC + Address: 0x0800FFC0 + Address: 0x0800FFC4 + Address: 0x0800FFC8 + Address: 0x0800FFCC + Address: 0x0800FFD0 + Address: 0x0800FFD4 + Address: 0x0800FFD8 + Address: 0x0800FFDC + Address: 0x0800FFE0 + Address: 0x0800FFE4 + Address: 0x0800FFE8 + Address: 0x0800FFEC + Address: 0x0800FFF0 + Address: 0x0800FFF4 + Address: 0x0800FFF8 + Address: 0x0800FFFC + Address: 0x08010000 + Address: 0x08010004 + Address: 0x08010008 + Address: 0x0801000C + Address: 0x08010010 + Address: 0x08010014 + Address: 0x08010018 + Address: 0x0801001C + Address: 0x08010020 + Address: 0x08010024 + Address: 0x08010028 + Address: 0x0801002C + Address: 0x08010050 + Address: 0x08010054 + Address: 0x08010058 + Address: 0x0801005C + Address: 0x08010060 + Address: 0x08010064 + Address: 0x08010068 + Address: 0x0801006C + Address: 0x08010070 + Address: 0x08010074 + Address: 0x08010078 + Address: 0x0801007C + Address: 0x08010080 + Address: 0x08010084 + Address: 0x08010088 + Address: 0x0801008C + Address: 0x08010090 + Address: 0x08010094 + Address: 0x08010098 + Address: 0x0801009C + Address: 0x080100A0 + Address: 0x080100A4 + Address: 0x080100A8 + Address: 0x080100AC + Address: 0x080100B0 + Address: 0x080100B4 + Address: 0x080100B8 + Address: 0x080100BC + Address: 0x080100C0 + Address: 0x080100C4 + Address: 0x080100C8 + Address: 0x080100CC + Address: 0x080100D0 + Address: 0x080100D4 + Address: 0x080100D8 + Address: 0x080100DC + Address: 0x080100E0 + Address: 0x0801010C + Address: 0x08010110 + Address: 0x08010114 + Address: 0x08010118 + Address: 0x0801011C + Address: 0x08010120 + Address: 0x08010124 + Address: 0x08010128 + Address: 0x0801012C + Address: 0x08010130 + Address: 0x08010134 + Address: 0x08010138 + Address: 0x0801013C + Address: 0x08010140 + Address: 0x08010144 + Address: 0x08010148 + Address: 0x0801014C + Address: 0x08010150 + Address: 0x08010154 + Address: 0x08010158 + Address: 0x0801015C + Address: 0x08010160 + Address: 0x08010164 + Address: 0x08010168 + Address: 0x0801016C + Address: 0x08010170 + Address: 0x08010174 + Address: 0x08010178 + Address: 0x0801017C + Address: 0x08010180 + Address: 0x08010184 + Address: 0x08010188 + Address: 0x0801018C + Address: 0x08010190 + Address: 0x08010194 + Address: 0x08010198 + Address: 0x0801019C + Address: 0x080101A0 + Address: 0x080101C4 + Address: 0x080101C8 + Address: 0x080101CC + Address: 0x080101D0 + Address: 0x080101D4 + Address: 0x080101D8 + Address: 0x080101DC + Address: 0x080101E0 + Address: 0x080101E4 + Address: 0x080101E8 + Address: 0x080101EC + Address: 0x080101F0 + Address: 0x080101F4 + Address: 0x080101F8 + Address: 0x080101FC + Address: 0x08010200 + Address: 0x08010204 + Address: 0x08010208 + Address: 0x0801020C + Address: 0x08010210 + Address: 0x08010214 + Address: 0x08010218 + Address: 0x0801021C + Address: 0x08010220 + Address: 0x08010224 + Address: 0x08010228 + Address: 0x0801022C + Address: 0x08010230 + Address: 0x08010234 + Address: 0x08010238 + Address: 0x0801023C + Address: 0x08010240 + Address: 0x08010244 + Address: 0x08010248 + Address: 0x0801024C + Address: 0x08010250 + Address: 0x08010254 + Address: 0x08010278 + Address: 0x0801027C + Address: 0x08010280 + Address: 0x08010284 + Address: 0x08010288 + Address: 0x0801028C + Address: 0x08010290 + Address: 0x08010294 + Address: 0x08010298 + Address: 0x0801029C + Address: 0x080102A0 + Address: 0x080102A4 + Address: 0x080102A8 + Address: 0x080102AC + Address: 0x080102B0 + Address: 0x080102B4 + Address: 0x080102B8 + Address: 0x080102BC + Address: 0x080102C0 + Address: 0x080102C4 + Address: 0x080102C8 + Address: 0x080102D4 + Address: 0x080102D8 + Address: 0x080102DC + Address: 0x080102E0 + Address: 0x080102E4 + Address: 0x080102E8 + Address: 0x080102EC + Address: 0x080102F0 + Address: 0x080102F4 + Address: 0x080102F8 + Address: 0x080102FC + Address: 0x08010300 + Address: 0x08010304 + Address: 0x08010308 + Address: 0x0801030C + Address: 0x08010310 + Address: 0x08010314 + Address: 0x08010334 + Address: 0x08010338 + Address: 0x0801033C + Address: 0x08010340 + Address: 0x08010344 + Address: 0x08010348 + Address: 0x0801034C + Address: 0x08010350 + Address: 0x08010354 + Address: 0x08010358 + Address: 0x0801035C + Address: 0x08010360 + Address: 0x08010364 + Address: 0x08010368 + Address: 0x0801036C + Address: 0x08010370 + Address: 0x08010374 + Address: 0x08010378 + Address: 0x0801037C + Address: 0x08010380 + Address: 0x08010388 + Address: 0x0801038C + Address: 0x08010390 + Address: 0x08010394 + Address: 0x08010398 + Address: 0x0801039C + Address: 0x080103A0 + Address: 0x080103A4 + Address: 0x080103A8 + Address: 0x080103AC + Address: 0x080103B0 + Address: 0x080103B4 + Address: 0x080103B8 + Address: 0x080103BC + Address: 0x080103C0 + Address: 0x080103C4 + Address: 0x080103C8 + Address: 0x080103F0 + Address: 0x080103F4 + Address: 0x080103F8 + Address: 0x080103FC + Address: 0x08010400 + Address: 0x08010404 + Address: 0x08010408 + Address: 0x0801040C + Address: 0x08010410 + Address: 0x08010414 + Address: 0x08010418 + Address: 0x0801041C + Address: 0x08010420 + Address: 0x08010424 + Address: 0x08010428 + Address: 0x0801042C + Address: 0x08010430 + Address: 0x08010434 + Address: 0x08010438 + Address: 0x0801043C + Address: 0x08010440 + Address: 0x08010448 + Address: 0x0801044C + Address: 0x08010450 + Address: 0x08010454 + Address: 0x08010458 + Address: 0x0801045C + Address: 0x08010460 + Address: 0x08010464 + Address: 0x08010468 + Address: 0x0801046C + Address: 0x08010470 + Address: 0x08010474 + Address: 0x08010478 + Address: 0x0801047C + Address: 0x08010480 + Address: 0x08010484 + Address: 0x08010488 + Address: 0x080104A4 + Address: 0x080104A8 + Address: 0x080104AC + Address: 0x080104B0 + Address: 0x080104B4 + Address: 0x080104B8 + Address: 0x080104BC + Address: 0x080104C0 + Address: 0x080104C4 + Address: 0x080104C8 + Address: 0x080104CC + Address: 0x080104D0 + Address: 0x080104D4 + Address: 0x080104D8 + Address: 0x080104DC + Address: 0x080104E0 + Address: 0x080104E4 + Address: 0x080104E8 + Address: 0x080104EC + Address: 0x080104F0 + Address: 0x08010500 + Address: 0x08010504 + Address: 0x08010508 + Address: 0x0801050C + Address: 0x08010510 + Address: 0x08010514 + Address: 0x08010518 + Address: 0x0801051C + Address: 0x08010520 + Address: 0x08010524 + Address: 0x08010528 + Address: 0x0801052C + Address: 0x08010530 + Address: 0x08010534 + Address: 0x08010538 + Address: 0x0801053C + Address: 0x08010540 + Address: 0x08010544 + Address: 0x0801055C + Address: 0x08010560 + Address: 0x08010564 + Address: 0x08010568 + Address: 0x0801056C + Address: 0x08010570 + Address: 0x08010574 + Address: 0x08010578 + Address: 0x0801057C + Address: 0x08010580 + Address: 0x08010584 + Address: 0x08010588 + Address: 0x0801058C + Address: 0x08010590 + Address: 0x08010594 + Address: 0x08010598 + Address: 0x0801059C + Address: 0x080105A0 + Address: 0x080105A4 + Address: 0x080105BC + Address: 0x080105C0 + Address: 0x080105C4 + Address: 0x080105C8 + Address: 0x080105CC + Address: 0x080105D0 + Address: 0x080105D4 + Address: 0x080105D8 + Address: 0x080105DC + Address: 0x080105E0 + Address: 0x080105E4 + Address: 0x080105E8 + Address: 0x080105EC + Address: 0x080105F0 + Address: 0x080105F4 + Address: 0x080105F8 + Address: 0x080105FC + Address: 0x08010600 + Address: 0x08010604 + Address: 0x0801061C + Address: 0x08010620 + Address: 0x08010624 + Address: 0x08010628 + Address: 0x0801062C + Address: 0x08010630 + Address: 0x08010634 + Address: 0x08010638 + Address: 0x0801063C + Address: 0x08010640 + Address: 0x08010644 + Address: 0x08010648 + Address: 0x0801064C + Address: 0x08010650 + Address: 0x08010654 + Address: 0x08010658 + Address: 0x0801065C + Address: 0x08010660 + Address: 0x08010664 + Address: 0x08010674 + Address: 0x08010678 + Address: 0x0801067C + Address: 0x08010680 + Address: 0x08010684 + Address: 0x08010688 + Address: 0x0801068C + Address: 0x08010690 + Address: 0x08010694 + Address: 0x08010698 + Address: 0x0801069C + Address: 0x080106A0 + Address: 0x080106A4 + Address: 0x080106A8 + Address: 0x080106AC + Address: 0x080106B0 + Address: 0x080106B4 + Address: 0x080106B8 + Address: 0x080106D0 + Address: 0x080106D4 + Address: 0x080106D8 + Address: 0x080106DC + Address: 0x080106E0 + Address: 0x080106E4 + Address: 0x080106E8 + Address: 0x080106EC + Address: 0x080106F0 + Address: 0x080106F4 + Address: 0x080106F8 + Address: 0x080106FC + Address: 0x08010700 + Address: 0x08010704 + Address: 0x08010708 + Address: 0x0801070C + Address: 0x08010710 + Address: 0x08010714 + Address: 0x08010718 + Address: 0x08010730 + Address: 0x08010734 + Address: 0x08010738 + Address: 0x0801073C + Address: 0x08010740 + Address: 0x08010744 + Address: 0x08010748 + Address: 0x0801074C + Address: 0x08010750 + Address: 0x08010754 + Address: 0x08010758 + Address: 0x0801075C + Address: 0x08010760 + Address: 0x08010764 + Address: 0x08010768 + Address: 0x0801076C + Address: 0x08010770 + Address: 0x08010774 + Address: 0x08010778 + Address: 0x08010790 + Address: 0x08010794 + Address: 0x08010798 + Address: 0x0801079C + Address: 0x080107A0 + Address: 0x080107A4 + Address: 0x080107A8 + Address: 0x080107AC + Address: 0x080107B0 + Address: 0x080107B4 + Address: 0x080107B8 + Address: 0x080107BC + Address: 0x080107C0 + Address: 0x080107C4 + Address: 0x080107C8 + Address: 0x080107CC + Address: 0x080107D0 + Address: 0x080107D4 + Address: 0x080107D8 + Address: 0x080107E8 + Address: 0x080107EC + Address: 0x080107F0 + Address: 0x080107F4 + Address: 0x080107F8 + Address: 0x080107FC + Address: 0x08010800 + Address: 0x08010804 + Address: 0x08010808 + Address: 0x0801080C + Address: 0x08010810 + Address: 0x08010814 + Address: 0x08010818 + Address: 0x0801081C + Address: 0x08010820 + Address: 0x08010824 + Address: 0x08010828 + Address: 0x0801082C + Address: 0x08010844 + Address: 0x08010848 + Address: 0x0801084C + Address: 0x08010850 + Address: 0x08010854 + Address: 0x08010858 + Address: 0x0801085C + Address: 0x08010860 + Address: 0x08010864 + Address: 0x08010868 + Address: 0x0801086C + Address: 0x08010870 + Address: 0x08010874 + Address: 0x08010878 + Address: 0x0801087C + Address: 0x08010880 + Address: 0x08010884 + Address: 0x08010888 + Address: 0x0801088C + Address: 0x080108A0 + Address: 0x080108A4 + Address: 0x080108A8 + Address: 0x080108AC + Address: 0x080108B0 + Address: 0x080108B4 + Address: 0x080108B8 + Address: 0x080108BC + Address: 0x080108C0 + Address: 0x080108C4 + Address: 0x080108C8 + Address: 0x080108CC + Address: 0x080108D0 + Address: 0x080108D4 + Address: 0x080108D8 + Address: 0x080108DC + Address: 0x080108E0 + Address: 0x080108E4 + Address: 0x080108E8 + Address: 0x08010900 + Address: 0x08010904 + Address: 0x08010908 + Address: 0x0801090C + Address: 0x08010910 + Address: 0x08010914 + Address: 0x08010918 + Address: 0x0801091C + Address: 0x08010920 + Address: 0x08010924 + Address: 0x08010928 + Address: 0x0801092C + Address: 0x08010930 + Address: 0x08010934 + Address: 0x08010938 + Address: 0x0801093C + Address: 0x08010940 + Address: 0x08010944 + Address: 0x08010948 + Address: 0x08010960 + Address: 0x08010964 + Address: 0x08010968 + Address: 0x0801096C + Address: 0x08010970 + Address: 0x08010974 + Address: 0x08010978 + Address: 0x0801097C + Address: 0x08010980 + Address: 0x08010984 + Address: 0x08010988 + Address: 0x0801098C + Address: 0x08010990 + Address: 0x08010994 + Address: 0x08010998 + Address: 0x0801099C + Address: 0x080109A0 + Address: 0x080109A4 + Address: 0x080109A8 + Address: 0x080109B8 + Address: 0x080109BC + Address: 0x080109C0 + Address: 0x080109C4 + Address: 0x080109C8 + Address: 0x080109CC + Address: 0x080109D0 + Address: 0x080109D4 + Address: 0x080109D8 + Address: 0x080109DC + Address: 0x080109E0 + Address: 0x080109E4 + Address: 0x080109E8 + Address: 0x080109EC + Address: 0x080109F0 + Address: 0x080109F4 + Address: 0x080109F8 + Address: 0x080109FC + Address: 0x08010A1C + Address: 0x08010A20 + Address: 0x08010A24 + Address: 0x08010A28 + Address: 0x08010A2C + Address: 0x08010A30 + Address: 0x08010A34 + Address: 0x08010A38 + Address: 0x08010A3C + Address: 0x08010A40 + Address: 0x08010A44 + Address: 0x08010A48 + Address: 0x08010A4C + Address: 0x08010A50 + Address: 0x08010A54 + Address: 0x08010A58 + Address: 0x08010A5C + Address: 0x08010A60 + Address: 0x08010A64 + Address: 0x08010A68 + Address: 0x08010A78 + Address: 0x08010A7C + Address: 0x08010A80 + Address: 0x08010A84 + Address: 0x08010A88 + Address: 0x08010A8C + Address: 0x08010A90 + Address: 0x08010A94 + Address: 0x08010A98 + Address: 0x08010A9C + Address: 0x08010AA0 + Address: 0x08010AA4 + Address: 0x08010AA8 + Address: 0x08010AAC + Address: 0x08010AB0 + Address: 0x08010AB4 + Address: 0x08010AB8 + Address: 0x08010ABC + Address: 0x08010ADC + Address: 0x08010AE0 + Address: 0x08010AE4 + Address: 0x08010AE8 + Address: 0x08010AEC + Address: 0x08010AF0 + Address: 0x08010AF4 + Address: 0x08010AF8 + Address: 0x08010AFC + Address: 0x08010B00 + Address: 0x08010B04 + Address: 0x08010B08 + Address: 0x08010B0C + Address: 0x08010B10 + Address: 0x08010B14 + Address: 0x08010B18 + Address: 0x08010B1C + Address: 0x08010B20 + Address: 0x08010B24 + Address: 0x08010B28 + Address: 0x08010B2C + Address: 0x08010B30 + Address: 0x08010B34 + Address: 0x08010B38 + Address: 0x08010B3C + Address: 0x08010B40 + Address: 0x08010B44 + Address: 0x08010B48 + Address: 0x08010B4C + Address: 0x08010B50 + Address: 0x08010B54 + Address: 0x08010B58 + Address: 0x08010B5C + Address: 0x08010B60 + Address: 0x08010B64 + Address: 0x08010B68 + Address: 0x08010B6C + Address: 0x08010B98 + Address: 0x08010B9C + Address: 0x08010BA0 + Address: 0x08010BA4 + Address: 0x08010BA8 + Address: 0x08010BAC + Address: 0x08010BB0 + Address: 0x08010BB4 + Address: 0x08010BB8 + Address: 0x08010BBC + Address: 0x08010BC0 + Address: 0x08010BC4 + Address: 0x08010BC8 + Address: 0x08010BCC + Address: 0x08010BD0 + Address: 0x08010BD4 + Address: 0x08010BD8 + Address: 0x08010BDC + Address: 0x08010BE0 + Address: 0x08010BE4 + Address: 0x08010BE8 + Address: 0x08010BEC + Address: 0x08010BF0 + Address: 0x08010BF4 + Address: 0x08010BF8 + Address: 0x08010BFC + Address: 0x08010C00 + Address: 0x08010C04 + Address: 0x08010C08 + Address: 0x08010C0C + Address: 0x08010C10 + Address: 0x08010C14 + Address: 0x08010C18 + Address: 0x08010C1C + Address: 0x08010C20 + Address: 0x08010C24 + Address: 0x08010C28 + Address: 0x08010C2C + Address: 0x08010C54 + Address: 0x08010C58 + Address: 0x08010C5C + Address: 0x08010C60 + Address: 0x08010C64 + Address: 0x08010C68 + Address: 0x08010C6C + Address: 0x08010C70 + Address: 0x08010C74 + Address: 0x08010C78 + Address: 0x08010C7C + Address: 0x08010C80 + Address: 0x08010C84 + Address: 0x08010C88 + Address: 0x08010C8C + Address: 0x08010C90 + Address: 0x08010C94 + Address: 0x08010C98 + Address: 0x08010C9C + Address: 0x08010CA0 + Address: 0x08010CA4 + Address: 0x08010CA8 + Address: 0x08010CAC + Address: 0x08010CB0 + Address: 0x08010CB4 + Address: 0x08010CB8 + Address: 0x08010CBC + Address: 0x08010CC0 + Address: 0x08010CC4 + Address: 0x08010CC8 + Address: 0x08010CCC + Address: 0x08010CD0 + Address: 0x08010CD4 + Address: 0x08010CD8 + Address: 0x08010CDC + Address: 0x08010CE0 + Address: 0x08010CE4 + Address: 0x08010D08 + Address: 0x08010D0C + Address: 0x08010D10 + Address: 0x08010D14 + Address: 0x08010D18 + Address: 0x08010D1C + Address: 0x08010D20 + Address: 0x08010D24 + Address: 0x08010D28 + Address: 0x08010D2C + Address: 0x08010D30 + Address: 0x08010D34 + Address: 0x08010D38 + Address: 0x08010D3C + Address: 0x08010D40 + Address: 0x08010D44 + Address: 0x08010D48 + Address: 0x08010D4C + Address: 0x08010D50 + Address: 0x08010D54 + Address: 0x08010D64 + Address: 0x08010D68 + Address: 0x08010D6C + Address: 0x08010D70 + Address: 0x08010D74 + Address: 0x08010D78 + Address: 0x08010D7C + Address: 0x08010D80 + Address: 0x08010D84 + Address: 0x08010D88 + Address: 0x08010D8C + Address: 0x08010D90 + Address: 0x08010D94 + Address: 0x08010D98 + Address: 0x08010D9C + Address: 0x08010DA0 + Address: 0x08010DA4 + Address: 0x08010DA8 + Address: 0x08010DC0 + Address: 0x08010DC4 + Address: 0x08010DC8 + Address: 0x08010DCC + Address: 0x08010DD0 + Address: 0x08010DD4 + Address: 0x08010DD8 + Address: 0x08010DDC + Address: 0x08010DE0 + Address: 0x08010DE4 + Address: 0x08010DE8 + Address: 0x08010DEC + Address: 0x08010DF0 + Address: 0x08010DF4 + Address: 0x08010DF8 + Address: 0x08010DFC + Address: 0x08010E00 + Address: 0x08010E04 + Address: 0x08010E08 + Address: 0x08010E18 + Address: 0x08010E1C + Address: 0x08010E20 + Address: 0x08010E24 + Address: 0x08010E28 + Address: 0x08010E2C + Address: 0x08010E30 + Address: 0x08010E34 + Address: 0x08010E38 + Address: 0x08010E3C + Address: 0x08010E40 + Address: 0x08010E44 + Address: 0x08010E48 + Address: 0x08010E4C + Address: 0x08010E50 + Address: 0x08010E54 + Address: 0x08010E58 + Address: 0x08010E5C + Address: 0x08010E78 + Address: 0x08010E7C + Address: 0x08010E80 + Address: 0x08010E84 + Address: 0x08010E88 + Address: 0x08010E8C + Address: 0x08010E90 + Address: 0x08010E94 + Address: 0x08010E98 + Address: 0x08010E9C + Address: 0x08010EA0 + Address: 0x08010EA4 + Address: 0x08010EA8 + Address: 0x08010EAC + Address: 0x08010EB0 + Address: 0x08010EB4 + Address: 0x08010EB8 + Address: 0x08010EBC + Address: 0x08010EC0 + Address: 0x08010EC4 + Address: 0x08010ED4 + Address: 0x08010ED8 + Address: 0x08010EDC + Address: 0x08010EE0 + Address: 0x08010EE4 + Address: 0x08010EE8 + Address: 0x08010EEC + Address: 0x08010EF0 + Address: 0x08010EF4 + Address: 0x08010EF8 + Address: 0x08010EFC + Address: 0x08010F00 + Address: 0x08010F04 + Address: 0x08010F08 + Address: 0x08010F0C + Address: 0x08010F10 + Address: 0x08010F14 + Address: 0x08010F18 + Address: 0x08010F34 + Address: 0x08010F38 + Address: 0x08010F3C + Address: 0x08010F40 + Address: 0x08010F44 + Address: 0x08010F48 + Address: 0x08010F4C + Address: 0x08010F50 + Address: 0x08010F54 + Address: 0x08010F58 + Address: 0x08010F5C + Address: 0x08010F60 + Address: 0x08010F64 + Address: 0x08010F68 + Address: 0x08010F6C + Address: 0x08010F70 + Address: 0x08010F74 + Address: 0x08010F78 + Address: 0x08010F7C + Address: 0x08010F88 + Address: 0x08010F8C + Address: 0x08010F90 + Address: 0x08010F94 + Address: 0x08010F98 + Address: 0x08010F9C + Address: 0x08010FA0 + Address: 0x08010FA4 + Address: 0x08010FA8 + Address: 0x08010FAC + Address: 0x08010FB0 + Address: 0x08010FB4 + Address: 0x08010FB8 + Address: 0x08010FBC + Address: 0x08010FC0 + Address: 0x08010FC4 + Address: 0x08010FC8 + Address: 0x08010FCC + Address: 0x08010FF0 + Address: 0x08010FF4 + Address: 0x08010FF8 + Address: 0x08010FFC + Address: 0x08011000 + Address: 0x08011004 + Address: 0x08011008 + Address: 0x0801100C + Address: 0x08011010 + Address: 0x08011014 + Address: 0x08011018 + Address: 0x0801101C + Address: 0x08011020 + Address: 0x08011024 + Address: 0x08011028 + Address: 0x0801102C + Address: 0x08011030 + Address: 0x08011034 + Address: 0x08011038 + Address: 0x0801103C + Address: 0x08011048 + Address: 0x0801104C + Address: 0x08011050 + Address: 0x08011054 + Address: 0x08011058 + Address: 0x0801105C + Address: 0x08011060 + Address: 0x08011064 + Address: 0x08011068 + Address: 0x0801106C + Address: 0x08011070 + Address: 0x08011074 + Address: 0x08011078 + Address: 0x0801107C + Address: 0x08011080 + Address: 0x08011084 + Address: 0x08011088 + Address: 0x0801108C + Address: 0x080110AC + Address: 0x080110B0 + Address: 0x080110B4 + Address: 0x080110B8 + Address: 0x080110BC + Address: 0x080110C0 + Address: 0x080110C4 + Address: 0x080110C8 + Address: 0x080110CC + Address: 0x080110D0 + Address: 0x080110D4 + Address: 0x080110D8 + Address: 0x080110DC + Address: 0x080110E0 + Address: 0x080110E4 + Address: 0x080110E8 + Address: 0x080110EC + Address: 0x080110F0 + Address: 0x080110F4 + Address: 0x080110F8 + Address: 0x08011100 + Address: 0x08011104 + Address: 0x08011108 + Address: 0x0801110C + Address: 0x08011110 + Address: 0x08011114 + Address: 0x08011118 + Address: 0x0801111C + Address: 0x08011120 + Address: 0x08011124 + Address: 0x08011128 + Address: 0x0801112C + Address: 0x08011130 + Address: 0x08011134 + Address: 0x08011138 + Address: 0x0801113C + Address: 0x08011140 + Address: 0x08011168 + Address: 0x0801116C + Address: 0x08011170 + Address: 0x08011174 + Address: 0x08011178 + Address: 0x0801117C + Address: 0x08011180 + Address: 0x08011184 + Address: 0x08011188 + Address: 0x0801118C + Address: 0x08011190 + Address: 0x08011194 + Address: 0x08011198 + Address: 0x0801119C + Address: 0x080111A0 + Address: 0x080111A4 + Address: 0x080111A8 + Address: 0x080111AC + Address: 0x080111B0 + Address: 0x080111B4 + Address: 0x080111B8 + Address: 0x080111C0 + Address: 0x080111C4 + Address: 0x080111C8 + Address: 0x080111CC + Address: 0x080111D0 + Address: 0x080111D4 + Address: 0x080111D8 + Address: 0x080111DC + Address: 0x080111E0 + Address: 0x080111E4 + Address: 0x080111E8 + Address: 0x080111EC + Address: 0x080111F0 + Address: 0x080111F4 + Address: 0x080111F8 + Address: 0x080111FC + Address: 0x08011200 + Address: 0x08011220 + Address: 0x08011224 + Address: 0x08011228 + Address: 0x0801122C + Address: 0x08011230 + Address: 0x08011234 + Address: 0x08011238 + Address: 0x0801123C + Address: 0x08011240 + Address: 0x08011244 + Address: 0x08011248 + Address: 0x0801124C + Address: 0x08011250 + Address: 0x08011254 + Address: 0x08011258 + Address: 0x0801125C + Address: 0x08011260 + Address: 0x08011264 + Address: 0x08011268 + Address: 0x0801126C + Address: 0x08011270 + Address: 0x08011274 + Address: 0x08011278 + Address: 0x0801127C + Address: 0x08011280 + Address: 0x08011284 + Address: 0x08011288 + Address: 0x0801128C + Address: 0x08011290 + Address: 0x08011294 + Address: 0x08011298 + Address: 0x0801129C + Address: 0x080112A0 + Address: 0x080112A4 + Address: 0x080112A8 + Address: 0x080112AC + Address: 0x080112B0 + Address: 0x080112D8 + Address: 0x080112DC + Address: 0x080112E0 + Address: 0x080112E4 + Address: 0x080112E8 + Address: 0x080112EC + Address: 0x080112F0 + Address: 0x080112F4 + Address: 0x080112F8 + Address: 0x080112FC + Address: 0x08011300 + Address: 0x08011304 + Address: 0x08011308 + Address: 0x0801130C + Address: 0x08011310 + Address: 0x08011314 + Address: 0x08011318 + Address: 0x0801131C + Address: 0x08011320 + Address: 0x08011324 + Address: 0x08011328 + Address: 0x08011334 + Address: 0x08011338 + Address: 0x0801133C + Address: 0x08011340 + Address: 0x08011344 + Address: 0x08011348 + Address: 0x0801134C + Address: 0x08011350 + Address: 0x08011354 + Address: 0x08011358 + Address: 0x0801135C + Address: 0x08011360 + Address: 0x08011364 + Address: 0x08011368 + Address: 0x0801136C + Address: 0x08011370 + Address: 0x08011374 + Address: 0x08011394 + Address: 0x08011398 + Address: 0x0801139C + Address: 0x080113A0 + Address: 0x080113A4 + Address: 0x080113A8 + Address: 0x080113AC + Address: 0x080113B0 + Address: 0x080113B4 + Address: 0x080113B8 + Address: 0x080113BC + Address: 0x080113C0 + Address: 0x080113C4 + Address: 0x080113C8 + Address: 0x080113CC + Address: 0x080113D0 + Address: 0x080113D4 + Address: 0x080113D8 + Address: 0x080113DC + Address: 0x080113E0 + Address: 0x080113E8 + Address: 0x080113EC + Address: 0x080113F0 + Address: 0x080113F4 + Address: 0x080113F8 + Address: 0x080113FC + Address: 0x08011400 + Address: 0x08011404 + Address: 0x08011408 + Address: 0x0801140C + Address: 0x08011410 + Address: 0x08011414 + Address: 0x08011418 + Address: 0x0801141C + Address: 0x08011420 + Address: 0x08011424 + Address: 0x08011428 + Address: 0x0801144C + Address: 0x08011450 + Address: 0x08011454 + Address: 0x08011458 + Address: 0x0801145C + Address: 0x08011460 + Address: 0x08011464 + Address: 0x08011468 + Address: 0x0801146C + Address: 0x08011470 + Address: 0x08011474 + Address: 0x08011478 + Address: 0x0801147C + Address: 0x08011480 + Address: 0x08011484 + Address: 0x08011488 + Address: 0x0801148C + Address: 0x08011490 + Address: 0x08011494 + Address: 0x08011498 + Address: 0x0801149C + Address: 0x080114A8 + Address: 0x080114AC + Address: 0x080114B0 + Address: 0x080114B4 + Address: 0x080114B8 + Address: 0x080114BC + Address: 0x080114C0 + Address: 0x080114C4 + Address: 0x080114C8 + Address: 0x080114CC + Address: 0x080114D0 + Address: 0x080114D4 + Address: 0x080114D8 + Address: 0x080114DC + Address: 0x080114E0 + Address: 0x080114E4 + Address: 0x080114E8 + Address: 0x08011508 + Address: 0x0801150C + Address: 0x08011510 + Address: 0x08011514 + Address: 0x08011518 + Address: 0x0801151C + Address: 0x08011520 + Address: 0x08011524 + Address: 0x08011528 + Address: 0x0801152C + Address: 0x08011530 + Address: 0x08011534 + Address: 0x08011538 + Address: 0x0801153C + Address: 0x08011540 + Address: 0x08011544 + Address: 0x08011548 + Address: 0x0801154C + Address: 0x08011550 + Address: 0x08011554 + Address: 0x0801155C + Address: 0x08011560 + Address: 0x08011564 + Address: 0x08011568 + Address: 0x0801156C + Address: 0x08011570 + Address: 0x08011574 + Address: 0x08011578 + Address: 0x0801157C + Address: 0x08011580 + Address: 0x08011584 + Address: 0x08011588 + Address: 0x0801158C + Address: 0x08011590 + Address: 0x08011594 + Address: 0x08011598 + Address: 0x0801159C + Address: 0x080115C0 + Address: 0x080115C4 + Address: 0x080115C8 + Address: 0x080115CC + Address: 0x080115D0 + Address: 0x080115D4 + Address: 0x080115D8 + Address: 0x080115DC + Address: 0x080115E0 + Address: 0x080115E4 + Address: 0x080115E8 + Address: 0x080115EC + Address: 0x080115F0 + Address: 0x080115F4 + Address: 0x080115F8 + Address: 0x080115FC + Address: 0x08011600 + Address: 0x08011604 + Address: 0x08011608 + Address: 0x0801160C + Address: 0x08011610 + Address: 0x08011618 + Address: 0x0801161C + Address: 0x08011620 + Address: 0x08011624 + Address: 0x08011628 + Address: 0x0801162C + Address: 0x08011630 + Address: 0x08011634 + Address: 0x08011638 + Address: 0x0801163C + Address: 0x08011640 + Address: 0x08011644 + Address: 0x08011648 + Address: 0x0801164C + Address: 0x08011650 + Address: 0x08011654 + Address: 0x08011658 + Address: 0x08011680 + Address: 0x08011684 + Address: 0x08011688 + Address: 0x0801168C + Address: 0x08011690 + Address: 0x08011694 + Address: 0x08011698 + Address: 0x0801169C + Address: 0x080116A0 + Address: 0x080116A4 + Address: 0x080116A8 + Address: 0x080116AC + Address: 0x080116B0 + Address: 0x080116B4 + Address: 0x080116B8 + Address: 0x080116BC + Address: 0x080116C0 + Address: 0x080116C4 + Address: 0x080116C8 + Address: 0x080116CC + Address: 0x080116D0 + Address: 0x080116D4 + Address: 0x080116D8 + Address: 0x080116DC + Address: 0x080116E0 + Address: 0x080116E4 + Address: 0x080116E8 + Address: 0x080116EC + Address: 0x080116F0 + Address: 0x080116F4 + Address: 0x080116F8 + Address: 0x080116FC + Address: 0x08011700 + Address: 0x08011704 + Address: 0x08011708 + Address: 0x0801170C + Address: 0x08011710 + Address: 0x08011738 + Address: 0x0801173C + Address: 0x08011740 + Address: 0x08011744 + Address: 0x08011748 + Address: 0x0801174C + Address: 0x08011750 + Address: 0x08011754 + Address: 0x08011758 + Address: 0x0801175C + Address: 0x08011760 + Address: 0x08011764 + Address: 0x08011768 + Address: 0x0801176C + Address: 0x08011770 + Address: 0x08011774 + Address: 0x08011778 + Address: 0x0801177C + Address: 0x08011780 + Address: 0x08011784 + Address: 0x08011788 + Address: 0x08011790 + Address: 0x08011794 + Address: 0x08011798 + Address: 0x0801179C + Address: 0x080117A0 + Address: 0x080117A4 + Address: 0x080117A8 + Address: 0x080117AC + Address: 0x080117B0 + Address: 0x080117B4 + Address: 0x080117B8 + Address: 0x080117BC + Address: 0x080117C0 + Address: 0x080117C4 + Address: 0x080117C8 + Address: 0x080117CC + Address: 0x080117D0 + Address: 0x080117EC + Address: 0x080117F0 + Address: 0x080117F4 + Address: 0x080117F8 + Address: 0x080117FC + Address: 0x08011800 + Address: 0x08011804 + Address: 0x08011808 + Address: 0x0801180C + Address: 0x08011810 + Address: 0x08011814 + Address: 0x08011818 + Address: 0x0801181C + Address: 0x08011820 + Address: 0x08011824 + Address: 0x08011828 + Address: 0x0801182C + Address: 0x08011830 + Address: 0x08011834 + Address: 0x08011838 + Address: 0x08011840 + Address: 0x08011844 + Address: 0x08011848 + Address: 0x0801184C + Address: 0x08011850 + Address: 0x08011854 + Address: 0x08011858 + Address: 0x0801185C + Address: 0x08011860 + Address: 0x08011864 + Address: 0x08011868 + Address: 0x0801186C + Address: 0x08011870 + Address: 0x08011874 + Address: 0x08011878 + Address: 0x0801187C + Address: 0x08011880 + Address: 0x080118AC + Address: 0x080118B0 + Address: 0x080118B4 + Address: 0x080118B8 + Address: 0x080118BC + Address: 0x080118C0 + Address: 0x080118C4 + Address: 0x080118C8 + Address: 0x080118CC + Address: 0x080118D0 + Address: 0x080118D4 + Address: 0x080118D8 + Address: 0x080118DC + Address: 0x080118E0 + Address: 0x080118E4 + Address: 0x080118E8 + Address: 0x080118EC + Address: 0x080118F0 + Address: 0x080118F4 + Address: 0x080118F8 + Address: 0x080118FC + Address: 0x08011900 + Address: 0x08011904 + Address: 0x08011908 + Address: 0x0801190C + Address: 0x08011910 + Address: 0x08011914 + Address: 0x08011918 + Address: 0x0801191C + Address: 0x08011920 + Address: 0x08011924 + Address: 0x08011928 + Address: 0x0801192C + Address: 0x08011930 + Address: 0x08011934 + Address: 0x08011938 + Address: 0x0801193C + Address: 0x08011940 + Address: 0x08011968 + Address: 0x0801196C + Address: 0x08011970 + Address: 0x08011974 + Address: 0x08011978 + Address: 0x0801197C + Address: 0x08011980 + Address: 0x08011984 + Address: 0x08011988 + Address: 0x0801198C + Address: 0x08011990 + Address: 0x08011994 + Address: 0x08011998 + Address: 0x0801199C + Address: 0x080119A0 + Address: 0x080119A4 + Address: 0x080119A8 + Address: 0x080119AC + Address: 0x080119B0 + Address: 0x080119B4 + Address: 0x080119B8 + Address: 0x080119BC + Address: 0x080119C0 + Address: 0x080119C4 + Address: 0x080119C8 + Address: 0x080119CC + Address: 0x080119D0 + Address: 0x080119D4 + Address: 0x080119D8 + Address: 0x080119DC + Address: 0x080119E0 + Address: 0x080119E4 + Address: 0x080119E8 + Address: 0x080119EC + Address: 0x080119F0 + Address: 0x080119F4 + Address: 0x080119F8 + Address: 0x08011A14 + Address: 0x08011A18 + Address: 0x08011A1C + Address: 0x08011A20 + Address: 0x08011A24 + Address: 0x08011A28 + Address: 0x08011A2C + Address: 0x08011A30 + Address: 0x08011A34 + Address: 0x08011A38 + Address: 0x08011A3C + Address: 0x08011A40 + Address: 0x08011A44 + Address: 0x08011A48 + Address: 0x08011A4C + Address: 0x08011A50 + Address: 0x08011A54 + Address: 0x08011A58 + Address: 0x08011A5C + Address: 0x08011A60 + Address: 0x08011A70 + Address: 0x08011A74 + Address: 0x08011A78 + Address: 0x08011A7C + Address: 0x08011A80 + Address: 0x08011A84 + Address: 0x08011A88 + Address: 0x08011A8C + Address: 0x08011A90 + Address: 0x08011A94 + Address: 0x08011A98 + Address: 0x08011A9C + Address: 0x08011AA0 + Address: 0x08011AA4 + Address: 0x08011AA8 + Address: 0x08011AAC + Address: 0x08011AB0 + Address: 0x08011AB4 + Address: 0x08011ACC + Address: 0x08011AD0 + Address: 0x08011AD4 + Address: 0x08011AD8 + Address: 0x08011ADC + Address: 0x08011AE0 + Address: 0x08011AE4 + Address: 0x08011AE8 + Address: 0x08011AEC + Address: 0x08011AF0 + Address: 0x08011AF4 + Address: 0x08011AF8 + Address: 0x08011AFC + Address: 0x08011B00 + Address: 0x08011B04 + Address: 0x08011B08 + Address: 0x08011B0C + Address: 0x08011B10 + Address: 0x08011B14 + Address: 0x08011B24 + Address: 0x08011B28 + Address: 0x08011B2C + Address: 0x08011B30 + Address: 0x08011B34 + Address: 0x08011B38 + Address: 0x08011B3C + Address: 0x08011B40 + Address: 0x08011B44 + Address: 0x08011B48 + Address: 0x08011B4C + Address: 0x08011B50 + Address: 0x08011B54 + Address: 0x08011B58 + Address: 0x08011B5C + Address: 0x08011B60 + Address: 0x08011B64 + Address: 0x08011B68 + Address: 0x08011B88 + Address: 0x08011B8C + Address: 0x08011B90 + Address: 0x08011B94 + Address: 0x08011B98 + Address: 0x08011B9C + Address: 0x08011BA0 + Address: 0x08011BA4 + Address: 0x08011BA8 + Address: 0x08011BAC + Address: 0x08011BB0 + Address: 0x08011BB4 + Address: 0x08011BB8 + Address: 0x08011BBC + Address: 0x08011BC0 + Address: 0x08011BC4 + Address: 0x08011BC8 + Address: 0x08011BCC + Address: 0x08011BD0 + Address: 0x08011BD4 + Address: 0x08011BE4 + Address: 0x08011BE8 + Address: 0x08011BEC + Address: 0x08011BF0 + Address: 0x08011BF4 + Address: 0x08011BF8 + Address: 0x08011BFC + Address: 0x08011C00 + Address: 0x08011C04 + Address: 0x08011C08 + Address: 0x08011C0C + Address: 0x08011C10 + Address: 0x08011C14 + Address: 0x08011C18 + Address: 0x08011C1C + Address: 0x08011C20 + Address: 0x08011C24 + Address: 0x08011C28 + Address: 0x08011C48 + Address: 0x08011C4C + Address: 0x08011C50 + Address: 0x08011C54 + Address: 0x08011C58 + Address: 0x08011C5C + Address: 0x08011C60 + Address: 0x08011C64 + Address: 0x08011C68 + Address: 0x08011C6C + Address: 0x08011C70 + Address: 0x08011C74 + Address: 0x08011C78 + Address: 0x08011C7C + Address: 0x08011C80 + Address: 0x08011C84 + Address: 0x08011C88 + Address: 0x08011C8C + Address: 0x08011C90 + Address: 0x08011C94 + Address: 0x08011C98 + Address: 0x08011C9C + Address: 0x08011CA0 + Address: 0x08011CA4 + Address: 0x08011CA8 + Address: 0x08011CAC + Address: 0x08011CB0 + Address: 0x08011CB4 + Address: 0x08011CB8 + Address: 0x08011CBC + Address: 0x08011CC0 + Address: 0x08011CC4 + Address: 0x08011CC8 + Address: 0x08011CCC + Address: 0x08011CD0 + Address: 0x08011CD4 + Address: 0x08011CD8 + Address: 0x08011D04 + Address: 0x08011D08 + Address: 0x08011D0C + Address: 0x08011D10 + Address: 0x08011D14 + Address: 0x08011D18 + Address: 0x08011D1C + Address: 0x08011D20 + Address: 0x08011D24 + Address: 0x08011D28 + Address: 0x08011D2C + Address: 0x08011D30 + Address: 0x08011D34 + Address: 0x08011D38 + Address: 0x08011D3C + Address: 0x08011D40 + Address: 0x08011D44 + Address: 0x08011D48 + Address: 0x08011D4C + Address: 0x08011D50 + Address: 0x08011D54 + Address: 0x08011D58 + Address: 0x08011D5C + Address: 0x08011D60 + Address: 0x08011D64 + Address: 0x08011D68 + Address: 0x08011D6C + Address: 0x08011D70 + Address: 0x08011D74 + Address: 0x08011D78 + Address: 0x08011D7C + Address: 0x08011D80 + Address: 0x08011D84 + Address: 0x08011D88 + Address: 0x08011D8C + Address: 0x08011D90 + Address: 0x08011D94 + Address: 0x08011D98 + Address: 0x08011DC0 + Address: 0x08011DC4 + Address: 0x08011DC8 + Address: 0x08011DCC + Address: 0x08011DD0 + Address: 0x08011DD4 + Address: 0x08011DD8 + Address: 0x08011DDC + Address: 0x08011DE0 + Address: 0x08011DE4 + Address: 0x08011DE8 + Address: 0x08011DEC + Address: 0x08011DF0 + Address: 0x08011DF4 + Address: 0x08011DF8 + Address: 0x08011DFC + Address: 0x08011E00 + Address: 0x08011E04 + Address: 0x08011E08 + Address: 0x08011E0C + Address: 0x08011E10 + Address: 0x08011E14 + Address: 0x08011E18 + Address: 0x08011E1C + Address: 0x08011E20 + Address: 0x08011E24 + Address: 0x08011E28 + Address: 0x08011E2C + Address: 0x08011E30 + Address: 0x08011E34 + Address: 0x08011E38 + Address: 0x08011E3C + Address: 0x08011E40 + Address: 0x08011E44 + Address: 0x08011E48 + Address: 0x08011E4C + Address: 0x08011E50 + Address: 0x08011E78 + Address: 0x08011E7C + Address: 0x08011E80 + Address: 0x08011E84 + Address: 0x08011E88 + Address: 0x08011E8C + Address: 0x08011E90 + Address: 0x08011E94 + Address: 0x08011E98 + Address: 0x08011E9C + Address: 0x08011EA0 + Address: 0x08011EA4 + Address: 0x08011EA8 + Address: 0x08011EAC + Address: 0x08011EB0 + Address: 0x08011EB4 + Address: 0x08011EB8 + Address: 0x08011EBC + Address: 0x08011EC0 + Address: 0x08011EC4 + Address: 0x08011EC8 + Address: 0x08011ED0 + Address: 0x08011ED4 + Address: 0x08011ED8 + Address: 0x08011EDC + Address: 0x08011EE0 + Address: 0x08011EE4 + Address: 0x08011EE8 + Address: 0x08011EEC + Address: 0x08011EF0 + Address: 0x08011EF4 + Address: 0x08011EF8 + Address: 0x08011EFC + Address: 0x08011F00 + Address: 0x08011F04 + Address: 0x08011F08 + Address: 0x08011F0C + Address: 0x08011F10 + Address: 0x08011F38 + Address: 0x08011F3C + Address: 0x08011F40 + Address: 0x08011F44 + Address: 0x08011F48 + Address: 0x08011F4C + Address: 0x08011F50 + Address: 0x08011F54 + Address: 0x08011F58 + Address: 0x08011F5C + Address: 0x08011F60 + Address: 0x08011F64 + Address: 0x08011F68 + Address: 0x08011F6C + Address: 0x08011F70 + Address: 0x08011F74 + Address: 0x08011F78 + Address: 0x08011F7C + Address: 0x08011F80 + Address: 0x08011F84 + Address: 0x08011F88 + Address: 0x08011F8C + Address: 0x08011F90 + Address: 0x08011F94 + Address: 0x08011F98 + Address: 0x08011F9C + Address: 0x08011FA0 + Address: 0x08011FA4 + Address: 0x08011FA8 + Address: 0x08011FAC + Address: 0x08011FB0 + Address: 0x08011FB4 + Address: 0x08011FB8 + Address: 0x08011FBC + Address: 0x08011FC0 + Address: 0x08011FC4 + Address: 0x08011FC8 + Address: 0x08011FE4 + Address: 0x08011FE8 + Address: 0x08011FEC + Address: 0x08011FF0 + Address: 0x08011FF4 + Address: 0x08011FF8 + Address: 0x08011FFC + Address: 0x08012000 + Address: 0x08012004 + Address: 0x08012008 + Address: 0x0801200C + Address: 0x08012010 + Address: 0x08012014 + Address: 0x08012018 + Address: 0x0801201C + Address: 0x08012020 + Address: 0x08012024 + Address: 0x08012028 + Address: 0x0801202C + Address: 0x08012030 + Address: 0x08012040 + Address: 0x08012044 + Address: 0x08012048 + Address: 0x0801204C + Address: 0x08012050 + Address: 0x08012054 + Address: 0x08012058 + Address: 0x0801205C + Address: 0x08012060 + Address: 0x08012064 + Address: 0x08012068 + Address: 0x0801206C + Address: 0x08012070 + Address: 0x08012074 + Address: 0x08012078 + Address: 0x0801207C + Address: 0x08012080 + Address: 0x08012084 + Address: 0x080120A4 + Address: 0x080120A8 + Address: 0x080120AC + Address: 0x080120B0 + Address: 0x080120B4 + Address: 0x080120B8 + Address: 0x080120BC + Address: 0x080120C0 + Address: 0x080120C4 + Address: 0x080120C8 + Address: 0x080120CC + Address: 0x080120D0 + Address: 0x080120D4 + Address: 0x080120D8 + Address: 0x080120DC + Address: 0x080120E0 + Address: 0x080120E4 + Address: 0x080120E8 + Address: 0x080120EC + Address: 0x080120F0 + Address: 0x080120F8 + Address: 0x080120FC + Address: 0x08012100 + Address: 0x08012104 + Address: 0x08012108 + Address: 0x0801210C + Address: 0x08012110 + Address: 0x08012114 + Address: 0x08012118 + Address: 0x0801211C + Address: 0x08012120 + Address: 0x08012124 + Address: 0x08012128 + Address: 0x0801212C + Address: 0x08012130 + Address: 0x08012134 + Address: 0x08012138 + Address: 0x08012158 + Address: 0x0801215C + Address: 0x08012160 + Address: 0x08012164 + Address: 0x08012168 + Address: 0x0801216C + Address: 0x08012170 + Address: 0x08012174 + Address: 0x08012178 + Address: 0x0801217C + Address: 0x08012180 + Address: 0x08012184 + Address: 0x08012188 + Address: 0x0801218C + Address: 0x08012190 + Address: 0x08012194 + Address: 0x08012198 + Address: 0x0801219C + Address: 0x080121A0 + Address: 0x080121A4 + Address: 0x080121B8 + Address: 0x080121BC + Address: 0x080121C0 + Address: 0x080121C4 + Address: 0x080121C8 + Address: 0x080121CC + Address: 0x080121D0 + Address: 0x080121D4 + Address: 0x080121D8 + Address: 0x080121DC + Address: 0x080121E0 + Address: 0x080121E4 + Address: 0x080121E8 + Address: 0x080121EC + Address: 0x080121F0 + Address: 0x080121F4 + Address: 0x080121F8 + Address: 0x080121FC + Address: 0x08012218 + Address: 0x0801221C + Address: 0x08012220 + Address: 0x08012224 + Address: 0x08012228 + Address: 0x0801222C + Address: 0x08012230 + Address: 0x08012234 + Address: 0x08012238 + Address: 0x0801223C + Address: 0x08012240 + Address: 0x08012244 + Address: 0x08012248 + Address: 0x0801224C + Address: 0x08012250 + Address: 0x08012254 + Address: 0x08012258 + Address: 0x0801225C + Address: 0x08012260 + Address: 0x08012264 + Address: 0x08012274 + Address: 0x08012278 + Address: 0x0801227C + Address: 0x08012280 + Address: 0x08012284 + Address: 0x08012288 + Address: 0x0801228C + Address: 0x08012290 + Address: 0x08012294 + Address: 0x08012298 + Address: 0x0801229C + Address: 0x080122A0 + Address: 0x080122A4 + Address: 0x080122A8 + Address: 0x080122AC + Address: 0x080122B0 + Address: 0x080122B4 + Address: 0x080122B8 + Address: 0x080122D0 + Address: 0x080122D4 + Address: 0x080122D8 + Address: 0x080122DC + Address: 0x080122E0 + Address: 0x080122E4 + Address: 0x080122E8 + Address: 0x080122EC + Address: 0x080122F0 + Address: 0x080122F4 + Address: 0x080122F8 + Address: 0x080122FC + Address: 0x08012300 + Address: 0x08012304 + Address: 0x08012308 + Address: 0x0801230C + Address: 0x08012310 + Address: 0x08012314 + Address: 0x08012318 + Address: 0x08012330 + Address: 0x08012334 + Address: 0x08012338 + Address: 0x0801233C + Address: 0x08012340 + Address: 0x08012344 + Address: 0x08012348 + Address: 0x0801234C + Address: 0x08012350 + Address: 0x08012354 + Address: 0x08012358 + Address: 0x0801235C + Address: 0x08012360 + Address: 0x08012364 + Address: 0x08012368 + Address: 0x0801236C + Address: 0x08012370 + Address: 0x08012374 + Address: 0x08012378 + Address: 0x08012390 + Address: 0x08012394 + Address: 0x08012398 + Address: 0x0801239C + Address: 0x080123A0 + Address: 0x080123A4 + Address: 0x080123A8 + Address: 0x080123AC + Address: 0x080123B0 + Address: 0x080123B4 + Address: 0x080123B8 + Address: 0x080123BC + Address: 0x080123C0 + Address: 0x080123C4 + Address: 0x080123C8 + Address: 0x080123CC + Address: 0x080123D0 + Address: 0x080123D4 + Address: 0x080123D8 + Address: 0x080123E8 + Address: 0x080123EC + Address: 0x080123F0 + Address: 0x080123F4 + Address: 0x080123F8 + Address: 0x080123FC + Address: 0x08012400 + Address: 0x08012404 + Address: 0x08012408 + Address: 0x0801240C + Address: 0x08012410 + Address: 0x08012414 + Address: 0x08012418 + Address: 0x0801241C + Address: 0x08012420 + Address: 0x08012424 + Address: 0x08012428 + Address: 0x0801242C + Address: 0x08012444 + Address: 0x08012448 + Address: 0x0801244C + Address: 0x08012450 + Address: 0x08012454 + Address: 0x08012458 + Address: 0x0801245C + Address: 0x08012460 + Address: 0x08012464 + Address: 0x08012468 + Address: 0x0801246C + Address: 0x08012470 + Address: 0x08012474 + Address: 0x08012478 + Address: 0x0801247C + Address: 0x08012480 + Address: 0x08012484 + Address: 0x08012488 + Address: 0x0801248C + Address: 0x080124A4 + Address: 0x080124A8 + Address: 0x080124AC + Address: 0x080124B0 + Address: 0x080124B4 + Address: 0x080124B8 + Address: 0x080124BC + Address: 0x080124C0 + Address: 0x080124C4 + Address: 0x080124C8 + Address: 0x080124CC + Address: 0x080124D0 + Address: 0x080124D4 + Address: 0x080124D8 + Address: 0x080124DC + Address: 0x080124E0 + Address: 0x080124E4 + Address: 0x080124E8 + Address: 0x080124EC + Address: 0x08012504 + Address: 0x08012508 + Address: 0x0801250C + Address: 0x08012510 + Address: 0x08012514 + Address: 0x08012518 + Address: 0x0801251C + Address: 0x08012520 + Address: 0x08012524 + Address: 0x08012528 + Address: 0x0801252C + Address: 0x08012530 + Address: 0x08012534 + Address: 0x08012538 + Address: 0x0801253C + Address: 0x08012540 + Address: 0x08012544 + Address: 0x08012548 + Address: 0x0801254C + Address: 0x0801255C + Address: 0x08012560 + Address: 0x08012564 + Address: 0x08012568 + Address: 0x0801256C + Address: 0x08012570 + Address: 0x08012574 + Address: 0x08012578 + Address: 0x0801257C + Address: 0x08012580 + Address: 0x08012584 + Address: 0x08012588 + Address: 0x0801258C + Address: 0x08012590 + Address: 0x08012594 + Address: 0x08012598 + Address: 0x0801259C + Address: 0x080125A0 + Address: 0x080125B8 + Address: 0x080125BC + Address: 0x080125C0 + Address: 0x080125C4 + Address: 0x080125C8 + Address: 0x080125CC + Address: 0x080125D0 + Address: 0x080125D4 + Address: 0x080125D8 + Address: 0x080125DC + Address: 0x080125E0 + Address: 0x080125E4 + Address: 0x080125E8 + Address: 0x080125EC + Address: 0x080125F0 + Address: 0x080125F4 + Address: 0x080125F8 + Address: 0x080125FC + Address: 0x08012600 + Address: 0x08012614 + Address: 0x08012618 + Address: 0x0801261C + Address: 0x08012620 + Address: 0x08012624 + Address: 0x08012628 + Address: 0x0801262C + Address: 0x08012630 + Address: 0x08012634 + Address: 0x08012638 + Address: 0x0801263C + Address: 0x08012640 + Address: 0x08012644 + Address: 0x08012648 + Address: 0x0801264C + Address: 0x08012650 + Address: 0x08012654 + Address: 0x08012658 + Address: 0x0801265C + Address: 0x08012674 + Address: 0x08012678 + Address: 0x0801267C + Address: 0x08012680 + Address: 0x08012684 + Address: 0x08012688 + Address: 0x0801268C + Address: 0x08012690 + Address: 0x08012694 + Address: 0x08012698 + Address: 0x0801269C + Address: 0x080126A0 + Address: 0x080126A4 + Address: 0x080126A8 + Address: 0x080126AC + Address: 0x080126B0 + Address: 0x080126B4 + Address: 0x080126B8 + Address: 0x080126BC + Address: 0x080126D4 + Address: 0x080126D8 + Address: 0x080126DC + Address: 0x080126E0 + Address: 0x080126E4 + Address: 0x080126E8 + Address: 0x080126EC + Address: 0x080126F0 + Address: 0x080126F4 + Address: 0x080126F8 + Address: 0x080126FC + Address: 0x08012700 + Address: 0x08012704 + Address: 0x08012708 + Address: 0x0801270C + Address: 0x08012710 + Address: 0x08012714 + Address: 0x08012718 + Address: 0x0801271C + Address: 0x0801272C + Address: 0x08012730 + Address: 0x08012734 + Address: 0x08012738 + Address: 0x0801273C + Address: 0x08012740 + Address: 0x08012744 + Address: 0x08012748 + Address: 0x0801274C + Address: 0x08012750 + Address: 0x08012754 + Address: 0x08012758 + Address: 0x0801275C + Address: 0x08012760 + Address: 0x08012764 + Address: 0x08012768 + Address: 0x0801276C + Address: 0x08012770 + Address: 0x08012790 + Address: 0x08012794 + Address: 0x08012798 + Address: 0x0801279C + Address: 0x080127A0 + Address: 0x080127A4 + Address: 0x080127A8 + Address: 0x080127AC + Address: 0x080127B0 + Address: 0x080127B4 + Address: 0x080127B8 + Address: 0x080127BC + Address: 0x080127C0 + Address: 0x080127C4 + Address: 0x080127C8 + Address: 0x080127CC + Address: 0x080127D0 + Address: 0x080127D4 + Address: 0x080127D8 + Address: 0x080127DC + Address: 0x080127EC + Address: 0x080127F0 + Address: 0x080127F4 + Address: 0x080127F8 + Address: 0x080127FC + Address: 0x08012800 + Address: 0x08012804 + Address: 0x08012808 + Address: 0x0801280C + Address: 0x08012810 + Address: 0x08012814 + Address: 0x08012818 + Address: 0x0801281C + Address: 0x08012820 + Address: 0x08012824 + Address: 0x08012828 + Address: 0x0801282C + Address: 0x08012830 + Address: 0x08012850 + Address: 0x08012854 + Address: 0x08012858 + Address: 0x0801285C + Address: 0x08012860 + Address: 0x08012864 + Address: 0x08012868 + Address: 0x0801286C + Address: 0x08012870 + Address: 0x08012874 + Address: 0x08012878 + Address: 0x0801287C + Address: 0x08012880 + Address: 0x08012884 + Address: 0x08012888 + Address: 0x0801288C + Address: 0x08012890 + Address: 0x08012894 + Address: 0x08012898 + Address: 0x0801289C + Address: 0x080128A0 + Address: 0x080128A4 + Address: 0x080128A8 + Address: 0x080128AC + Address: 0x080128B0 + Address: 0x080128B4 + Address: 0x080128B8 + Address: 0x080128BC + Address: 0x080128C0 + Address: 0x080128C4 + Address: 0x080128C8 + Address: 0x080128CC + Address: 0x080128D0 + Address: 0x080128D4 + Address: 0x080128D8 + Address: 0x080128DC + Address: 0x080128E0 + Address: 0x0801290C + Address: 0x08012910 + Address: 0x08012914 + Address: 0x08012918 + Address: 0x0801291C + Address: 0x08012920 + Address: 0x08012924 + Address: 0x08012928 + Address: 0x0801292C + Address: 0x08012930 + Address: 0x08012934 + Address: 0x08012938 + Address: 0x0801293C + Address: 0x08012940 + Address: 0x08012944 + Address: 0x08012948 + Address: 0x0801294C + Address: 0x08012950 + Address: 0x08012954 + Address: 0x08012958 + Address: 0x0801295C + Address: 0x08012960 + Address: 0x08012964 + Address: 0x08012968 + Address: 0x0801296C + Address: 0x08012970 + Address: 0x08012974 + Address: 0x08012978 + Address: 0x0801297C + Address: 0x08012980 + Address: 0x08012984 + Address: 0x08012988 + Address: 0x0801298C + Address: 0x08012990 + Address: 0x08012994 + Address: 0x08012998 + Address: 0x0801299C + Address: 0x080129A0 + Address: 0x080129C0 + Address: 0x080129C4 + Address: 0x080129C8 + Address: 0x080129CC + Address: 0x080129D0 + Address: 0x080129D4 + Address: 0x080129D8 + Address: 0x080129DC + Address: 0x080129E0 + Address: 0x080129E4 + Address: 0x080129E8 + Address: 0x080129EC + Address: 0x080129F0 + Address: 0x080129F4 + Address: 0x080129F8 + Address: 0x080129FC + Address: 0x08012A00 + Address: 0x08012A04 + Address: 0x08012A08 + Address: 0x08012A0C + Address: 0x08012A10 + Address: 0x08012A14 + Address: 0x08012A18 + Address: 0x08012A1C + Address: 0x08012A20 + Address: 0x08012A24 + Address: 0x08012A28 + Address: 0x08012A2C + Address: 0x08012A30 + Address: 0x08012A34 + Address: 0x08012A38 + Address: 0x08012A3C + Address: 0x08012A40 + Address: 0x08012A44 + Address: 0x08012A48 + Address: 0x08012A4C + Address: 0x08012A50 + Address: 0x08012A7C + Address: 0x08012A80 + Address: 0x08012A84 + Address: 0x08012A88 + Address: 0x08012A8C + Address: 0x08012A90 + Address: 0x08012A94 + Address: 0x08012A98 + Address: 0x08012A9C + Address: 0x08012AA0 + Address: 0x08012AA4 + Address: 0x08012AA8 + Address: 0x08012AAC + Address: 0x08012AB0 + Address: 0x08012AB4 + Address: 0x08012AB8 + Address: 0x08012ABC + Address: 0x08012AC0 + Address: 0x08012AC4 + Address: 0x08012AC8 + Address: 0x08012ACC + Address: 0x08012AD4 + Address: 0x08012AD8 + Address: 0x08012ADC + Address: 0x08012AE0 + Address: 0x08012AE4 + Address: 0x08012AE8 + Address: 0x08012AEC + Address: 0x08012AF0 + Address: 0x08012AF4 + Address: 0x08012AF8 + Address: 0x08012AFC + Address: 0x08012B00 + Address: 0x08012B04 + Address: 0x08012B08 + Address: 0x08012B0C + Address: 0x08012B10 + Address: 0x08012B14 + Address: 0x08012B34 + Address: 0x08012B38 + Address: 0x08012B3C + Address: 0x08012B40 + Address: 0x08012B44 + Address: 0x08012B48 + Address: 0x08012B4C + Address: 0x08012B50 + Address: 0x08012B54 + Address: 0x08012B58 + Address: 0x08012B5C + Address: 0x08012B60 + Address: 0x08012B64 + Address: 0x08012B68 + Address: 0x08012B6C + Address: 0x08012B70 + Address: 0x08012B74 + Address: 0x08012B78 + Address: 0x08012B7C + Address: 0x08012B80 + Address: 0x08012B88 + Address: 0x08012B8C + Address: 0x08012B90 + Address: 0x08012B94 + Address: 0x08012B98 + Address: 0x08012B9C + Address: 0x08012BA0 + Address: 0x08012BA4 + Address: 0x08012BA8 + Address: 0x08012BAC + Address: 0x08012BB0 + Address: 0x08012BB4 + Address: 0x08012BB8 + Address: 0x08012BBC + Address: 0x08012BC0 + Address: 0x08012BC4 + Address: 0x08012BC8 + Address: 0x08012BE8 + Address: 0x08012BEC + Address: 0x08012BF0 + Address: 0x08012BF4 + Address: 0x08012BF8 + Address: 0x08012BFC + Address: 0x08012C00 + Address: 0x08012C04 + Address: 0x08012C08 + Address: 0x08012C0C + Address: 0x08012C10 + Address: 0x08012C14 + Address: 0x08012C18 + Address: 0x08012C1C + Address: 0x08012C20 + Address: 0x08012C24 + Address: 0x08012C28 + Address: 0x08012C2C + Address: 0x08012C30 + Address: 0x08012C34 + Address: 0x08012C44 + Address: 0x08012C48 + Address: 0x08012C4C + Address: 0x08012C50 + Address: 0x08012C54 + Address: 0x08012C58 + Address: 0x08012C5C + Address: 0x08012C60 + Address: 0x08012C64 + Address: 0x08012C68 + Address: 0x08012C6C + Address: 0x08012C70 + Address: 0x08012C74 + Address: 0x08012C78 + Address: 0x08012C7C + Address: 0x08012C80 + Address: 0x08012C84 + Address: 0x08012C88 + Address: 0x08012CA0 + Address: 0x08012CA4 + Address: 0x08012CA8 + Address: 0x08012CAC + Address: 0x08012CB0 + Address: 0x08012CB4 + Address: 0x08012CB8 + Address: 0x08012CBC + Address: 0x08012CC0 + Address: 0x08012CC4 + Address: 0x08012CC8 + Address: 0x08012CCC + Address: 0x08012CD0 + Address: 0x08012CD4 + Address: 0x08012CD8 + Address: 0x08012CDC + Address: 0x08012CE0 + Address: 0x08012CE4 + Address: 0x08012CE8 + Address: 0x08012CF8 + Address: 0x08012CFC + Address: 0x08012D00 + Address: 0x08012D04 + Address: 0x08012D08 + Address: 0x08012D0C + Address: 0x08012D10 + Address: 0x08012D14 + Address: 0x08012D18 + Address: 0x08012D1C + Address: 0x08012D20 + Address: 0x08012D24 + Address: 0x08012D28 + Address: 0x08012D2C + Address: 0x08012D30 + Address: 0x08012D34 + Address: 0x08012D38 + Address: 0x08012D3C + Address: 0x08012D5C + Address: 0x08012D60 + Address: 0x08012D64 + Address: 0x08012D68 + Address: 0x08012D6C + Address: 0x08012D70 + Address: 0x08012D74 + Address: 0x08012D78 + Address: 0x08012D7C + Address: 0x08012D80 + Address: 0x08012D84 + Address: 0x08012D88 + Address: 0x08012D8C + Address: 0x08012D90 + Address: 0x08012D94 + Address: 0x08012D98 + Address: 0x08012D9C + Address: 0x08012DA0 + Address: 0x08012DA4 + Address: 0x08012DA8 + Address: 0x08012DB8 + Address: 0x08012DBC + Address: 0x08012DC0 + Address: 0x08012DC4 + Address: 0x08012DC8 + Address: 0x08012DCC + Address: 0x08012DD0 + Address: 0x08012DD4 + Address: 0x08012DD8 + Address: 0x08012DDC + Address: 0x08012DE0 + Address: 0x08012DE4 + Address: 0x08012DE8 + Address: 0x08012DEC + Address: 0x08012DF0 + Address: 0x08012DF4 + Address: 0x08012DF8 + Address: 0x08012DFC + Address: 0x08012E1C + Address: 0x08012E20 + Address: 0x08012E24 + Address: 0x08012E28 + Address: 0x08012E2C + Address: 0x08012E30 + Address: 0x08012E34 + Address: 0x08012E38 + Address: 0x08012E3C + Address: 0x08012E40 + Address: 0x08012E44 + Address: 0x08012E48 + Address: 0x08012E4C + Address: 0x08012E50 + Address: 0x08012E54 + Address: 0x08012E58 + Address: 0x08012E5C + Address: 0x08012E60 + Address: 0x08012E64 + Address: 0x08012E68 + Address: 0x08012E70 + Address: 0x08012E74 + Address: 0x08012E78 + Address: 0x08012E7C + Address: 0x08012E80 + Address: 0x08012E84 + Address: 0x08012E88 + Address: 0x08012E8C + Address: 0x08012E90 + Address: 0x08012E94 + Address: 0x08012E98 + Address: 0x08012E9C + Address: 0x08012EA0 + Address: 0x08012EA4 + Address: 0x08012EA8 + Address: 0x08012EAC + Address: 0x08012EB0 + Address: 0x08012ED8 + Address: 0x08012EDC + Address: 0x08012EE0 + Address: 0x08012EE4 + Address: 0x08012EE8 + Address: 0x08012EEC + Address: 0x08012EF0 + Address: 0x08012EF4 + Address: 0x08012EF8 + Address: 0x08012EFC + Address: 0x08012F00 + Address: 0x08012F04 + Address: 0x08012F08 + Address: 0x08012F0C + Address: 0x08012F10 + Address: 0x08012F14 + Address: 0x08012F18 + Address: 0x08012F1C + Address: 0x08012F20 + Address: 0x08012F24 + Address: 0x08012F28 + Address: 0x08012F30 + Address: 0x08012F34 + Address: 0x08012F38 + Address: 0x08012F3C + Address: 0x08012F40 + Address: 0x08012F44 + Address: 0x08012F48 + Address: 0x08012F4C + Address: 0x08012F50 + Address: 0x08012F54 + Address: 0x08012F58 + Address: 0x08012F5C + Address: 0x08012F60 + Address: 0x08012F64 + Address: 0x08012F68 + Address: 0x08012F6C + Address: 0x08012F70 + Address: 0x08012F8C + Address: 0x08012F90 + Address: 0x08012F94 + Address: 0x08012F98 + Address: 0x08012F9C + Address: 0x08012FA0 + Address: 0x08012FA4 + Address: 0x08012FA8 + Address: 0x08012FAC + Address: 0x08012FB0 + Address: 0x08012FB4 + Address: 0x08012FB8 + Address: 0x08012FBC + Address: 0x08012FC0 + Address: 0x08012FC4 + Address: 0x08012FC8 + Address: 0x08012FCC + Address: 0x08012FD0 + Address: 0x08012FD4 + Address: 0x08012FD8 + Address: 0x08012FE0 + Address: 0x08012FE4 + Address: 0x08012FE8 + Address: 0x08012FEC + Address: 0x08012FF0 + Address: 0x08012FF4 + Address: 0x08012FF8 + Address: 0x08012FFC + Address: 0x08013000 + Address: 0x08013004 + Address: 0x08013008 + Address: 0x0801300C + Address: 0x08013010 + Address: 0x08013014 + Address: 0x08013018 + Address: 0x0801301C + Address: 0x08013020 + Address: 0x08013048 + Address: 0x0801304C + Address: 0x08013050 + Address: 0x08013054 + Address: 0x08013058 + Address: 0x0801305C + Address: 0x08013060 + Address: 0x08013064 + Address: 0x08013068 + Address: 0x0801306C + Address: 0x08013070 + Address: 0x08013074 + Address: 0x08013078 + Address: 0x0801307C + Address: 0x08013080 + Address: 0x08013084 + Address: 0x08013088 + Address: 0x0801308C + Address: 0x08013090 + Address: 0x08013094 + Address: 0x08013098 + Address: 0x080130A0 + Address: 0x080130A4 + Address: 0x080130A8 + Address: 0x080130AC + Address: 0x080130B0 + Address: 0x080130B4 + Address: 0x080130B8 + Address: 0x080130BC + Address: 0x080130C0 + Address: 0x080130C4 + Address: 0x080130C8 + Address: 0x080130CC + Address: 0x080130D0 + Address: 0x080130D4 + Address: 0x080130D8 + Address: 0x080130DC + Address: 0x080130E0 + Address: 0x08013104 + Address: 0x08013108 + Address: 0x0801310C + Address: 0x08013110 + Address: 0x08013114 + Address: 0x08013118 + Address: 0x0801311C + Address: 0x08013120 + Address: 0x08013124 + Address: 0x08013128 + Address: 0x0801312C + Address: 0x08013130 + Address: 0x08013134 + Address: 0x08013138 + Address: 0x0801313C + Address: 0x08013140 + Address: 0x08013144 + Address: 0x08013148 + Address: 0x0801314C + Address: 0x08013150 + Address: 0x08013154 + Address: 0x08013158 + Address: 0x0801315C + Address: 0x08013160 + Address: 0x08013164 + Address: 0x08013168 + Address: 0x0801316C + Address: 0x08013170 + Address: 0x08013174 + Address: 0x08013178 + Address: 0x0801317C + Address: 0x08013180 + Address: 0x08013184 + Address: 0x08013188 + Address: 0x0801318C + Address: 0x08013190 + Address: 0x08013194 + Address: 0x08013198 + Address: 0x080131C0 + Address: 0x080131C4 + Address: 0x080131C8 + Address: 0x080131CC + Address: 0x080131D0 + Address: 0x080131D4 + Address: 0x080131D8 + Address: 0x080131DC + Address: 0x080131E0 + Address: 0x080131E4 + Address: 0x080131E8 + Address: 0x080131EC + Address: 0x080131F0 + Address: 0x080131F4 + Address: 0x080131F8 + Address: 0x080131FC + Address: 0x08013200 + Address: 0x08013204 + Address: 0x08013208 + Address: 0x0801320C + Address: 0x08013210 + Address: 0x0801321C + Address: 0x08013220 + Address: 0x08013224 + Address: 0x08013228 + Address: 0x0801322C + Address: 0x08013230 + Address: 0x08013234 + Address: 0x08013238 + Address: 0x0801323C + Address: 0x08013240 + Address: 0x08013244 + Address: 0x08013248 + Address: 0x0801324C + Address: 0x08013250 + Address: 0x08013254 + Address: 0x08013258 + Address: 0x0801325C + Address: 0x0801327C + Address: 0x08013280 + Address: 0x08013284 + Address: 0x08013288 + Address: 0x0801328C + Address: 0x08013290 + Address: 0x08013294 + Address: 0x08013298 + Address: 0x0801329C + Address: 0x080132A0 + Address: 0x080132A4 + Address: 0x080132A8 + Address: 0x080132AC + Address: 0x080132B0 + Address: 0x080132B4 + Address: 0x080132B8 + Address: 0x080132BC + Address: 0x080132C0 + Address: 0x080132C4 + Address: 0x080132C8 + Address: 0x080132D0 + Address: 0x080132D4 + Address: 0x080132D8 + Address: 0x080132DC + Address: 0x080132E0 + Address: 0x080132E4 + Address: 0x080132E8 + Address: 0x080132EC + Address: 0x080132F0 + Address: 0x080132F4 + Address: 0x080132F8 + Address: 0x080132FC + Address: 0x08013300 + Address: 0x08013304 + Address: 0x08013308 + Address: 0x0801330C + Address: 0x08013310 + Address: 0x08013338 + Address: 0x0801333C + Address: 0x08013340 + Address: 0x08013344 + Address: 0x08013348 + Address: 0x0801334C + Address: 0x08013350 + Address: 0x08013354 + Address: 0x08013358 + Address: 0x0801335C + Address: 0x08013360 + Address: 0x08013364 + Address: 0x08013368 + Address: 0x0801336C + Address: 0x08013370 + Address: 0x08013374 + Address: 0x08013378 + Address: 0x0801337C + Address: 0x08013380 + Address: 0x08013384 + Address: 0x08013388 + Address: 0x08013390 + Address: 0x08013394 + Address: 0x08013398 + Address: 0x0801339C + Address: 0x080133A0 + Address: 0x080133A4 + Address: 0x080133A8 + Address: 0x080133AC + Address: 0x080133B0 + Address: 0x080133B4 + Address: 0x080133B8 + Address: 0x080133BC + Address: 0x080133C0 + Address: 0x080133C4 + Address: 0x080133C8 + Address: 0x080133CC + Address: 0x080133D0 + Address: 0x080133F0 + Address: 0x080133F4 + Address: 0x080133F8 + Address: 0x080133FC + Address: 0x08013400 + Address: 0x08013404 + Address: 0x08013408 + Address: 0x0801340C + Address: 0x08013410 + Address: 0x08013414 + Address: 0x08013418 + Address: 0x0801341C + Address: 0x08013420 + Address: 0x08013424 + Address: 0x08013428 + Address: 0x0801342C + Address: 0x08013430 + Address: 0x08013434 + Address: 0x08013438 + Address: 0x0801343C + Address: 0x08013444 + Address: 0x08013448 + Address: 0x0801344C + Address: 0x08013450 + Address: 0x08013454 + Address: 0x08013458 + Address: 0x0801345C + Address: 0x08013460 + Address: 0x08013464 + Address: 0x08013468 + Address: 0x0801346C + Address: 0x08013470 + Address: 0x08013474 + Address: 0x08013478 + Address: 0x0801347C + Address: 0x08013480 + Address: 0x08013484 + Address: 0x080134AC + Address: 0x080134B0 + Address: 0x080134B4 + Address: 0x080134B8 + Address: 0x080134BC + Address: 0x080134C0 + Address: 0x080134C4 + Address: 0x080134C8 + Address: 0x080134CC + Address: 0x080134D0 + Address: 0x080134D4 + Address: 0x080134D8 + Address: 0x080134DC + Address: 0x080134E0 + Address: 0x080134E4 + Address: 0x080134E8 + Address: 0x080134EC + Address: 0x080134F0 + Address: 0x080134F4 + Address: 0x080134F8 + Address: 0x080134FC + Address: 0x08013508 + Address: 0x0801350C + Address: 0x08013510 + Address: 0x08013514 + Address: 0x08013518 + Address: 0x0801351C + Address: 0x08013520 + Address: 0x08013524 + Address: 0x08013528 + Address: 0x0801352C + Address: 0x08013530 + Address: 0x08013534 + Address: 0x08013538 + Address: 0x0801353C + Address: 0x08013540 + Address: 0x08013544 + Address: 0x08013548 + Address: 0x0801354C + Address: 0x0801356C + Address: 0x08013570 + Address: 0x08013574 + Address: 0x08013578 + Address: 0x0801357C + Address: 0x08013580 + Address: 0x08013584 + Address: 0x08013588 + Address: 0x0801358C + Address: 0x08013590 + Address: 0x08013594 + Address: 0x08013598 + Address: 0x0801359C + Address: 0x080135A0 + Address: 0x080135A4 + Address: 0x080135A8 + Address: 0x080135AC + Address: 0x080135B0 + Address: 0x080135B4 + Address: 0x080135B8 + Address: 0x080135C8 + Address: 0x080135CC + Address: 0x080135D0 + Address: 0x080135D4 + Address: 0x080135D8 + Address: 0x080135DC + Address: 0x080135E0 + Address: 0x080135E4 + Address: 0x080135E8 + Address: 0x080135EC + Address: 0x080135F0 + Address: 0x080135F4 + Address: 0x080135F8 + Address: 0x080135FC + Address: 0x08013600 + Address: 0x08013604 + Address: 0x08013608 + Address: 0x0801360C + Address: 0x08013624 + Address: 0x08013628 + Address: 0x0801362C + Address: 0x08013630 + Address: 0x08013634 + Address: 0x08013638 + Address: 0x0801363C + Address: 0x08013640 + Address: 0x08013644 + Address: 0x08013648 + Address: 0x0801364C + Address: 0x08013650 + Address: 0x08013654 + Address: 0x08013658 + Address: 0x0801365C + Address: 0x08013660 + Address: 0x08013664 + Address: 0x08013668 + Address: 0x0801366C + Address: 0x0801367C + Address: 0x08013680 + Address: 0x08013684 + Address: 0x08013688 + Address: 0x0801368C + Address: 0x08013690 + Address: 0x08013694 + Address: 0x08013698 + Address: 0x0801369C + Address: 0x080136A0 + Address: 0x080136A4 + Address: 0x080136A8 + Address: 0x080136AC + Address: 0x080136B0 + Address: 0x080136B4 + Address: 0x080136B8 + Address: 0x080136BC + Address: 0x080136C0 + Address: 0x080136E0 + Address: 0x080136E4 + Address: 0x080136E8 + Address: 0x080136EC + Address: 0x080136F0 + Address: 0x080136F4 + Address: 0x080136F8 + Address: 0x080136FC + Address: 0x08013700 + Address: 0x08013704 + Address: 0x08013708 + Address: 0x0801370C + Address: 0x08013710 + Address: 0x08013714 + Address: 0x08013718 + Address: 0x0801371C + Address: 0x08013720 + Address: 0x08013724 + Address: 0x08013728 + Address: 0x0801372C + Address: 0x0801373C + Address: 0x08013740 + Address: 0x08013744 + Address: 0x08013748 + Address: 0x0801374C + Address: 0x08013750 + Address: 0x08013754 + Address: 0x08013758 + Address: 0x0801375C + Address: 0x08013760 + Address: 0x08013764 + Address: 0x08013768 + Address: 0x0801376C + Address: 0x08013770 + Address: 0x08013774 + Address: 0x08013778 + Address: 0x0801377C + Address: 0x08013780 + Address: 0x0801379C + Address: 0x080137A0 + Address: 0x080137A4 + Address: 0x080137A8 + Address: 0x080137AC + Address: 0x080137B0 + Address: 0x080137B4 + Address: 0x080137B8 + Address: 0x080137BC + Address: 0x080137C0 + Address: 0x080137C4 + Address: 0x080137C8 + Address: 0x080137CC + Address: 0x080137D0 + Address: 0x080137D4 + Address: 0x080137D8 + Address: 0x080137DC + Address: 0x080137E0 + Address: 0x080137E4 + Address: 0x080137F0 + Address: 0x080137F4 + Address: 0x080137F8 + Address: 0x080137FC + Address: 0x08013800 + Address: 0x08013804 + Address: 0x08013808 + Address: 0x0801380C + Address: 0x08013810 + Address: 0x08013814 + Address: 0x08013818 + Address: 0x0801381C + Address: 0x08013820 + Address: 0x08013824 + Address: 0x08013828 + Address: 0x0801382C + Address: 0x08013830 + Address: 0x08013834 + Address: 0x08013854 + Address: 0x08013858 + Address: 0x0801385C + Address: 0x08013860 + Address: 0x08013864 + Address: 0x08013868 + Address: 0x0801386C + Address: 0x08013870 + Address: 0x08013874 + Address: 0x08013878 + Address: 0x0801387C + Address: 0x08013880 + Address: 0x08013884 + Address: 0x08013888 + Address: 0x0801388C + Address: 0x08013890 + Address: 0x08013894 + Address: 0x08013898 + Address: 0x0801389C + Address: 0x080138A0 + Address: 0x080138AC + Address: 0x080138B0 + Address: 0x080138B4 + Address: 0x080138B8 + Address: 0x080138BC + Address: 0x080138C0 + Address: 0x080138C4 + Address: 0x080138C8 + Address: 0x080138CC + Address: 0x080138D0 + Address: 0x080138D4 + Address: 0x080138D8 + Address: 0x080138DC + Address: 0x080138E0 + Address: 0x080138E4 + Address: 0x080138E8 + Address: 0x080138EC + Address: 0x080138F0 + Address: 0x08013910 + Address: 0x08013914 + Address: 0x08013918 + Address: 0x0801391C + Address: 0x08013920 + Address: 0x08013924 + Address: 0x08013928 + Address: 0x0801392C + Address: 0x08013930 + Address: 0x08013934 + Address: 0x08013938 + Address: 0x0801393C + Address: 0x08013940 + Address: 0x08013944 + Address: 0x08013948 + Address: 0x0801394C + Address: 0x08013950 + Address: 0x08013954 + Address: 0x08013958 + Address: 0x0801395C + Address: 0x08013964 + Address: 0x08013968 + Address: 0x0801396C + Address: 0x08013970 + Address: 0x08013974 + Address: 0x08013978 + Address: 0x0801397C + Address: 0x08013980 + Address: 0x08013984 + Address: 0x08013988 + Address: 0x0801398C + Address: 0x08013990 + Address: 0x08013994 + Address: 0x08013998 + Address: 0x0801399C + Address: 0x080139A0 + Address: 0x080139A4 + Address: 0x080139CC + Address: 0x080139D0 + Address: 0x080139D4 + Address: 0x080139D8 + Address: 0x080139DC + Address: 0x080139E0 + Address: 0x080139E4 + Address: 0x080139E8 + Address: 0x080139EC + Address: 0x080139F0 + Address: 0x080139F4 + Address: 0x080139F8 + Address: 0x080139FC + Address: 0x08013A00 + Address: 0x08013A04 + Address: 0x08013A08 + Address: 0x08013A0C + Address: 0x08013A10 + Address: 0x08013A14 + Address: 0x08013A18 + Address: 0x08013A1C + Address: 0x08013A20 + Address: 0x08013A24 + Address: 0x08013A28 + Address: 0x08013A2C + Address: 0x08013A30 + Address: 0x08013A34 + Address: 0x08013A38 + Address: 0x08013A3C + Address: 0x08013A40 + Address: 0x08013A44 + Address: 0x08013A48 + Address: 0x08013A4C + Address: 0x08013A50 + Address: 0x08013A54 + Address: 0x08013A58 + Address: 0x08013A5C + Address: 0x08013A60 + Address: 0x08013A88 + Address: 0x08013A8C + Address: 0x08013A90 + Address: 0x08013A94 + Address: 0x08013A98 + Address: 0x08013A9C + Address: 0x08013AA0 + Address: 0x08013AA4 + Address: 0x08013AA8 + Address: 0x08013AAC + Address: 0x08013AB0 + Address: 0x08013AB4 + Address: 0x08013AB8 + Address: 0x08013ABC + Address: 0x08013AC0 + Address: 0x08013AC4 + Address: 0x08013AC8 + Address: 0x08013ACC + Address: 0x08013AD0 + Address: 0x08013AD4 + Address: 0x08013AD8 + Address: 0x08013ADC + Address: 0x08013AE0 + Address: 0x08013AE4 + Address: 0x08013AE8 + Address: 0x08013AEC + Address: 0x08013AF0 + Address: 0x08013AF4 + Address: 0x08013AF8 + Address: 0x08013AFC + Address: 0x08013B00 + Address: 0x08013B04 + Address: 0x08013B08 + Address: 0x08013B0C + Address: 0x08013B10 + Address: 0x08013B14 + Address: 0x08013B18 + Address: 0x08013B40 + Address: 0x08013B44 + Address: 0x08013B48 + Address: 0x08013B4C + Address: 0x08013B50 + Address: 0x08013B54 + Address: 0x08013B58 + Address: 0x08013B5C + Address: 0x08013B60 + Address: 0x08013B64 + Address: 0x08013B68 + Address: 0x08013B6C + Address: 0x08013B70 + Address: 0x08013B74 + Address: 0x08013B78 + Address: 0x08013B7C + Address: 0x08013B80 + Address: 0x08013B84 + Address: 0x08013B88 + Address: 0x08013B8C + Address: 0x08013B90 + Address: 0x08013B98 + Address: 0x08013B9C + Address: 0x08013BA0 + Address: 0x08013BA4 + Address: 0x08013BA8 + Address: 0x08013BAC + Address: 0x08013BB0 + Address: 0x08013BB4 + Address: 0x08013BB8 + Address: 0x08013BBC + Address: 0x08013BC0 + Address: 0x08013BC4 + Address: 0x08013BC8 + Address: 0x08013BCC + Address: 0x08013BD0 + Address: 0x08013BD4 + Address: 0x08013BD8 + Address: 0x08013BF4 + Address: 0x08013BF8 + Address: 0x08013BFC + Address: 0x08013C00 + Address: 0x08013C04 + Address: 0x08013C08 + Address: 0x08013C0C + Address: 0x08013C10 + Address: 0x08013C14 + Address: 0x08013C18 + Address: 0x08013C1C + Address: 0x08013C20 + Address: 0x08013C24 + Address: 0x08013C28 + Address: 0x08013C2C + Address: 0x08013C30 + Address: 0x08013C34 + Address: 0x08013C38 + Address: 0x08013C3C + Address: 0x08013C40 + Address: 0x08013C48 + Address: 0x08013C4C + Address: 0x08013C50 + Address: 0x08013C54 + Address: 0x08013C58 + Address: 0x08013C5C + Address: 0x08013C60 + Address: 0x08013C64 + Address: 0x08013C68 + Address: 0x08013C6C + Address: 0x08013C70 + Address: 0x08013C74 + Address: 0x08013C78 + Address: 0x08013C7C + Address: 0x08013C80 + Address: 0x08013C84 + Address: 0x08013C88 + Address: 0x08013CB0 + Address: 0x08013CB4 + Address: 0x08013CB8 + Address: 0x08013CBC + Address: 0x08013CC0 + Address: 0x08013CC4 + Address: 0x08013CC8 + Address: 0x08013CCC + Address: 0x08013CD0 + Address: 0x08013CD4 + Address: 0x08013CD8 + Address: 0x08013CDC + Address: 0x08013CE0 + Address: 0x08013CE4 + Address: 0x08013CE8 + Address: 0x08013CEC + Address: 0x08013CF0 + Address: 0x08013CF4 + Address: 0x08013CF8 + Address: 0x08013CFC + Address: 0x08013D00 + Address: 0x08013D08 + Address: 0x08013D0C + Address: 0x08013D10 + Address: 0x08013D14 + Address: 0x08013D18 + Address: 0x08013D1C + Address: 0x08013D20 + Address: 0x08013D24 + Address: 0x08013D28 + Address: 0x08013D2C + Address: 0x08013D30 + Address: 0x08013D34 + Address: 0x08013D38 + Address: 0x08013D3C + Address: 0x08013D40 + Address: 0x08013D44 + Address: 0x08013D48 + Address: 0x08013D6C + Address: 0x08013D70 + Address: 0x08013D74 + Address: 0x08013D78 + Address: 0x08013D7C + Address: 0x08013D80 + Address: 0x08013D84 + Address: 0x08013D88 + Address: 0x08013D8C + Address: 0x08013D90 + Address: 0x08013D94 + Address: 0x08013D98 + Address: 0x08013D9C + Address: 0x08013DA0 + Address: 0x08013DA4 + Address: 0x08013DA8 + Address: 0x08013DAC + Address: 0x08013DB0 + Address: 0x08013DB4 + Address: 0x08013DB8 + Address: 0x08013DBC + Address: 0x08013DC0 + Address: 0x08013DC4 + Address: 0x08013DC8 + Address: 0x08013DCC + Address: 0x08013DD0 + Address: 0x08013DD4 + Address: 0x08013DD8 + Address: 0x08013DDC + Address: 0x08013DE0 + Address: 0x08013DE4 + Address: 0x08013DE8 + Address: 0x08013DEC + Address: 0x08013DF0 + Address: 0x08013DF4 + Address: 0x08013DF8 + Address: 0x08013DFC + Address: 0x08013E24 + Address: 0x08013E28 + Address: 0x08013E2C + Address: 0x08013E30 + Address: 0x08013E34 + Address: 0x08013E38 + Address: 0x08013E3C + Address: 0x08013E40 + Address: 0x08013E44 + Address: 0x08013E48 + Address: 0x08013E4C + Address: 0x08013E50 + Address: 0x08013E54 + Address: 0x08013E58 + Address: 0x08013E5C + Address: 0x08013E60 + Address: 0x08013E64 + Address: 0x08013E68 + Address: 0x08013E6C + Address: 0x08013E70 + Address: 0x08013E74 + Address: 0x08013E7C + Address: 0x08013E80 + Address: 0x08013E84 + Address: 0x08013E88 + Address: 0x08013E8C + Address: 0x08013E90 + Address: 0x08013E94 + Address: 0x08013E98 + Address: 0x08013E9C + Address: 0x08013EA0 + Address: 0x08013EA4 + Address: 0x08013EA8 + Address: 0x08013EAC + Address: 0x08013EB0 + Address: 0x08013EB4 + Address: 0x08013EB8 + Address: 0x08013EBC + Address: 0x08013EDC + Address: 0x08013EE0 + Address: 0x08013EE4 + Address: 0x08013EE8 + Address: 0x08013EEC + Address: 0x08013EF0 + Address: 0x08013EF4 + Address: 0x08013EF8 + Address: 0x08013EFC + Address: 0x08013F00 + Address: 0x08013F04 + Address: 0x08013F08 + Address: 0x08013F0C + Address: 0x08013F10 + Address: 0x08013F14 + Address: 0x08013F18 + Address: 0x08013F1C + Address: 0x08013F20 + Address: 0x08013F24 + Address: 0x08013F28 + Address: 0x08013F30 + Address: 0x08013F34 + Address: 0x08013F38 + Address: 0x08013F3C + Address: 0x08013F40 + Address: 0x08013F44 + Address: 0x08013F48 + Address: 0x08013F4C + Address: 0x08013F50 + Address: 0x08013F54 + Address: 0x08013F58 + Address: 0x08013F5C + Address: 0x08013F60 + Address: 0x08013F64 + Address: 0x08013F68 + Address: 0x08013F6C + Address: 0x08013F70 + Address: 0x08013F90 + Address: 0x08013F94 + Address: 0x08013F98 + Address: 0x08013F9C + Address: 0x08013FA0 + Address: 0x08013FA4 + Address: 0x08013FA8 + Address: 0x08013FAC + Address: 0x08013FB0 + Address: 0x08013FB4 + Address: 0x08013FB8 + Address: 0x08013FBC + Address: 0x08013FC0 + Address: 0x08013FC4 + Address: 0x08013FC8 + Address: 0x08013FCC + Address: 0x08013FD0 + Address: 0x08013FD4 + Address: 0x08013FD8 + Address: 0x08013FDC + Address: 0x08013FEC + Address: 0x08013FF0 + Address: 0x08013FF4 + Address: 0x08013FF8 + Address: 0x08013FFC + Address: 0x08014000 + Address: 0x08014004 + Address: 0x08014008 + Address: 0x0801400C + Address: 0x08014010 + Address: 0x08014014 + Address: 0x08014018 + Address: 0x0801401C + Address: 0x08014020 + Address: 0x08014024 + Address: 0x08014028 + Address: 0x0801402C + Address: 0x08014030 + Address: 0x08014054 + Address: 0x08014058 + Address: 0x0801405C + Address: 0x08014060 + Address: 0x08014064 + Address: 0x08014068 + Address: 0x0801406C + Address: 0x08014070 + Address: 0x08014074 + Address: 0x08014078 + Address: 0x0801407C + Address: 0x08014080 + Address: 0x08014084 + Address: 0x08014088 + Address: 0x0801408C + Address: 0x08014090 + Address: 0x08014094 + Address: 0x08014098 + Address: 0x0801409C + Address: 0x080140A0 + Address: 0x080140AC + Address: 0x080140B0 + Address: 0x080140B4 + Address: 0x080140B8 + Address: 0x080140BC + Address: 0x080140C0 + Address: 0x080140C4 + Address: 0x080140C8 + Address: 0x080140CC + Address: 0x080140D0 + Address: 0x080140D4 + Address: 0x080140D8 + Address: 0x080140DC + Address: 0x080140E0 + Address: 0x080140E4 + Address: 0x080140E8 + Address: 0x080140EC + Address: 0x080140F0 + Address: 0x08014108 + Address: 0x0801410C + Address: 0x08014110 + Address: 0x08014114 + Address: 0x08014118 + Address: 0x0801411C + Address: 0x08014120 + Address: 0x08014124 + Address: 0x08014128 + Address: 0x0801412C + Address: 0x08014130 + Address: 0x08014134 + Address: 0x08014138 + Address: 0x0801413C + Address: 0x08014140 + Address: 0x08014144 + Address: 0x08014148 + Address: 0x0801414C + Address: 0x08014150 + Address: 0x08014168 + Address: 0x0801416C + Address: 0x08014170 + Address: 0x08014174 + Address: 0x08014178 + Address: 0x0801417C + Address: 0x08014180 + Address: 0x08014184 + Address: 0x08014188 + Address: 0x0801418C + Address: 0x08014190 + Address: 0x08014194 + Address: 0x08014198 + Address: 0x0801419C + Address: 0x080141A0 + Address: 0x080141A4 + Address: 0x080141A8 + Address: 0x080141AC + Address: 0x080141B0 + Address: 0x080141C8 + Address: 0x080141CC + Address: 0x080141D0 + Address: 0x080141D4 + Address: 0x080141D8 + Address: 0x080141DC + Address: 0x080141E0 + Address: 0x080141E4 + Address: 0x080141E8 + Address: 0x080141EC + Address: 0x080141F0 + Address: 0x080141F4 + Address: 0x080141F8 + Address: 0x080141FC + Address: 0x08014200 + Address: 0x08014204 + Address: 0x08014208 + Address: 0x0801420C + Address: 0x08014210 + Address: 0x08014224 + Address: 0x08014228 + Address: 0x0801422C + Address: 0x08014230 + Address: 0x08014234 + Address: 0x08014238 + Address: 0x0801423C + Address: 0x08014240 + Address: 0x08014244 + Address: 0x08014248 + Address: 0x0801424C + Address: 0x08014250 + Address: 0x08014254 + Address: 0x08014258 + Address: 0x0801425C + Address: 0x08014260 + Address: 0x08014264 + Address: 0x08014268 + Address: 0x0801426C + Address: 0x0801427C + Address: 0x08014280 + Address: 0x08014284 + Address: 0x08014288 + Address: 0x0801428C + Address: 0x08014290 + Address: 0x08014294 + Address: 0x08014298 + Address: 0x0801429C + Address: 0x080142A0 + Address: 0x080142A4 + Address: 0x080142A8 + Address: 0x080142AC + Address: 0x080142B0 + Address: 0x080142B4 + Address: 0x080142B8 + Address: 0x080142BC + Address: 0x080142C0 + Address: 0x080142E0 + Address: 0x080142E4 + Address: 0x080142E8 + Address: 0x080142EC + Address: 0x080142F0 + Address: 0x080142F4 + Address: 0x080142F8 + Address: 0x080142FC + Address: 0x08014300 + Address: 0x08014304 + Address: 0x08014308 + Address: 0x0801430C + Address: 0x08014310 + Address: 0x08014314 + Address: 0x08014318 + Address: 0x0801431C + Address: 0x08014320 + Address: 0x08014324 + Address: 0x08014328 + Address: 0x0801432C + Address: 0x0801433C + Address: 0x08014340 + Address: 0x08014344 + Address: 0x08014348 + Address: 0x0801434C + Address: 0x08014350 + Address: 0x08014354 + Address: 0x08014358 + Address: 0x0801435C + Address: 0x08014360 + Address: 0x08014364 + Address: 0x08014368 + Address: 0x0801436C + Address: 0x08014370 + Address: 0x08014374 + Address: 0x08014378 + Address: 0x0801437C + Address: 0x08014380 + Address: 0x080143A0 + Address: 0x080143A4 + Address: 0x080143A8 + Address: 0x080143AC + Address: 0x080143B0 + Address: 0x080143B4 + Address: 0x080143B8 + Address: 0x080143BC + Address: 0x080143C0 + Address: 0x080143C4 + Address: 0x080143C8 + Address: 0x080143CC + Address: 0x080143D0 + Address: 0x080143D4 + Address: 0x080143D8 + Address: 0x080143DC + Address: 0x080143E0 + Address: 0x080143E4 + Address: 0x080143E8 + Address: 0x080143EC + Address: 0x080143F0 + Address: 0x080143F4 + Address: 0x080143F8 + Address: 0x080143FC + Address: 0x08014400 + Address: 0x08014404 + Address: 0x08014408 + Address: 0x0801440C + Address: 0x08014410 + Address: 0x08014414 + Address: 0x08014418 + Address: 0x0801441C + Address: 0x08014420 + Address: 0x08014424 + Address: 0x08014428 + Address: 0x0801442C + Address: 0x08014430 + Address: 0x0801445C + Address: 0x08014460 + Address: 0x08014464 + Address: 0x08014468 + Address: 0x0801446C + Address: 0x08014470 + Address: 0x08014474 + Address: 0x08014478 + Address: 0x0801447C + Address: 0x08014480 + Address: 0x08014484 + Address: 0x08014488 + Address: 0x0801448C + Address: 0x08014490 + Address: 0x08014494 + Address: 0x08014498 + Address: 0x0801449C + Address: 0x080144A0 + Address: 0x080144A4 + Address: 0x080144A8 + Address: 0x080144AC + Address: 0x080144B0 + Address: 0x080144B4 + Address: 0x080144B8 + Address: 0x080144BC + Address: 0x080144C0 + Address: 0x080144C4 + Address: 0x080144C8 + Address: 0x080144CC + Address: 0x080144D0 + Address: 0x080144D4 + Address: 0x080144D8 + Address: 0x080144DC + Address: 0x080144E0 + Address: 0x080144E4 + Address: 0x080144E8 + Address: 0x080144EC + Address: 0x080144F0 + Address: 0x08014518 + Address: 0x0801451C + Address: 0x08014520 + Address: 0x08014524 + Address: 0x08014528 + Address: 0x0801452C + Address: 0x08014530 + Address: 0x08014534 + Address: 0x08014538 + Address: 0x0801453C + Address: 0x08014540 + Address: 0x08014544 + Address: 0x08014548 + Address: 0x0801454C + Address: 0x08014550 + Address: 0x08014554 + Address: 0x08014558 + Address: 0x0801455C + Address: 0x08014560 + Address: 0x08014564 + Address: 0x08014568 + Address: 0x0801456C + Address: 0x08014570 + Address: 0x08014574 + Address: 0x08014578 + Address: 0x0801457C + Address: 0x08014580 + Address: 0x08014584 + Address: 0x08014588 + Address: 0x0801458C + Address: 0x08014590 + Address: 0x08014594 + Address: 0x08014598 + Address: 0x0801459C + Address: 0x080145A0 + Address: 0x080145A4 + Address: 0x080145A8 + Address: 0x080145D0 + Address: 0x080145D4 + Address: 0x080145D8 + Address: 0x080145DC + Address: 0x080145E0 + Address: 0x080145E4 + Address: 0x080145E8 + Address: 0x080145EC + Address: 0x080145F0 + Address: 0x080145F4 + Address: 0x080145F8 + Address: 0x080145FC + Address: 0x08014600 + Address: 0x08014604 + Address: 0x08014608 + Address: 0x0801460C + Address: 0x08014610 + Address: 0x08014614 + Address: 0x08014618 + Address: 0x0801461C + Address: 0x08014620 + Address: 0x08014624 + Address: 0x08014628 + Address: 0x0801462C + Address: 0x08014630 + Address: 0x08014634 + Address: 0x08014638 + Address: 0x0801463C + Address: 0x08014640 + Address: 0x08014644 + Address: 0x08014648 + Address: 0x0801464C + Address: 0x08014650 + Address: 0x08014654 + Address: 0x08014658 + Address: 0x0801465C + Address: 0x08014660 + Address: 0x08014664 + Address: 0x0801468C + Address: 0x08014690 + Address: 0x08014694 + Address: 0x08014698 + Address: 0x0801469C + Address: 0x080146A0 + Address: 0x080146A4 + Address: 0x080146A8 + Address: 0x080146AC + Address: 0x080146B0 + Address: 0x080146B4 + Address: 0x080146B8 + Address: 0x080146BC + Address: 0x080146C0 + Address: 0x080146C4 + Address: 0x080146C8 + Address: 0x080146CC + Address: 0x080146D0 + Address: 0x080146D4 + Address: 0x080146D8 + Address: 0x080146DC + Address: 0x080146E0 + Address: 0x080146E4 + Address: 0x080146E8 + Address: 0x080146EC + Address: 0x080146F0 + Address: 0x080146F4 + Address: 0x080146F8 + Address: 0x080146FC + Address: 0x08014700 + Address: 0x08014704 + Address: 0x08014708 + Address: 0x0801470C + Address: 0x08014710 + Address: 0x08014714 + Address: 0x08014718 + Address: 0x0801471C + Address: 0x08014744 + Address: 0x08014748 + Address: 0x0801474C + Address: 0x08014750 + Address: 0x08014754 + Address: 0x08014758 + Address: 0x0801475C + Address: 0x08014760 + Address: 0x08014764 + Address: 0x08014768 + Address: 0x0801476C + Address: 0x08014770 + Address: 0x08014774 + Address: 0x08014778 + Address: 0x0801477C + Address: 0x08014780 + Address: 0x08014784 + Address: 0x08014788 + Address: 0x0801478C + Address: 0x08014790 + Address: 0x08014794 + Address: 0x0801479C + Address: 0x080147A0 + Address: 0x080147A4 + Address: 0x080147A8 + Address: 0x080147AC + Address: 0x080147B0 + Address: 0x080147B4 + Address: 0x080147B8 + Address: 0x080147BC + Address: 0x080147C0 + Address: 0x080147C4 + Address: 0x080147C8 + Address: 0x080147CC + Address: 0x080147D0 + Address: 0x080147D4 + Address: 0x080147D8 + Address: 0x080147DC + Address: 0x080147FC + Address: 0x08014800 + Address: 0x08014804 + Address: 0x08014808 + Address: 0x0801480C + Address: 0x08014810 + Address: 0x08014814 + Address: 0x08014818 + Address: 0x0801481C + Address: 0x08014820 + Address: 0x08014824 + Address: 0x08014828 + Address: 0x0801482C + Address: 0x08014830 + Address: 0x08014834 + Address: 0x08014838 + Address: 0x0801483C + Address: 0x08014840 + Address: 0x08014844 + Address: 0x08014848 + Address: 0x0801484C + Address: 0x08014850 + Address: 0x08014854 + Address: 0x08014858 + Address: 0x0801485C + Address: 0x08014860 + Address: 0x08014864 + Address: 0x08014868 + Address: 0x0801486C + Address: 0x08014870 + Address: 0x08014874 + Address: 0x08014878 + Address: 0x0801487C + Address: 0x08014880 + Address: 0x08014884 + Address: 0x08014888 + Address: 0x0801488C + Address: 0x080148B4 + Address: 0x080148B8 + Address: 0x080148BC + Address: 0x080148C0 + Address: 0x080148C4 + Address: 0x080148C8 + Address: 0x080148CC + Address: 0x080148D0 + Address: 0x080148D4 + Address: 0x080148D8 + Address: 0x080148DC + Address: 0x080148E0 + Address: 0x080148E4 + Address: 0x080148E8 + Address: 0x080148EC + Address: 0x080148F0 + Address: 0x080148F4 + Address: 0x080148F8 + Address: 0x080148FC + Address: 0x08014900 + Address: 0x08014904 + Address: 0x0801490C + Address: 0x08014910 + Address: 0x08014914 + Address: 0x08014918 + Address: 0x0801491C + Address: 0x08014920 + Address: 0x08014924 + Address: 0x08014928 + Address: 0x0801492C + Address: 0x08014930 + Address: 0x08014934 + Address: 0x08014938 + Address: 0x0801493C + Address: 0x08014940 + Address: 0x08014944 + Address: 0x08014948 + Address: 0x0801494C + Address: 0x08014974 + Address: 0x08014978 + Address: 0x0801497C + Address: 0x08014980 + Address: 0x08014984 + Address: 0x08014988 + Address: 0x0801498C + Address: 0x08014990 + Address: 0x08014994 + Address: 0x08014998 + Address: 0x0801499C + Address: 0x080149A0 + Address: 0x080149A4 + Address: 0x080149A8 + Address: 0x080149AC + Address: 0x080149B0 + Address: 0x080149B4 + Address: 0x080149B8 + Address: 0x080149BC + Address: 0x080149C0 + Address: 0x080149C4 + Address: 0x080149C8 + Address: 0x080149CC + Address: 0x080149D0 + Address: 0x080149D4 + Address: 0x080149D8 + Address: 0x080149DC + Address: 0x080149E0 + Address: 0x080149E4 + Address: 0x080149E8 + Address: 0x080149EC + Address: 0x080149F0 + Address: 0x080149F4 + Address: 0x080149F8 + Address: 0x080149FC + Address: 0x08014A00 + Address: 0x08014A04 + Address: 0x08014A20 + Address: 0x08014A24 + Address: 0x08014A28 + Address: 0x08014A2C + Address: 0x08014A30 + Address: 0x08014A34 + Address: 0x08014A38 + Address: 0x08014A3C + Address: 0x08014A40 + Address: 0x08014A44 + Address: 0x08014A48 + Address: 0x08014A4C + Address: 0x08014A50 + Address: 0x08014A54 + Address: 0x08014A58 + Address: 0x08014A5C + Address: 0x08014A60 + Address: 0x08014A64 + Address: 0x08014A68 + Address: 0x08014A6C + Address: 0x08014A7C + Address: 0x08014A80 + Address: 0x08014A84 + Address: 0x08014A88 + Address: 0x08014A8C + Address: 0x08014A90 + Address: 0x08014A94 + Address: 0x08014A98 + Address: 0x08014A9C + Address: 0x08014AA0 + Address: 0x08014AA4 + Address: 0x08014AA8 + Address: 0x08014AAC + Address: 0x08014AB0 + Address: 0x08014AB4 + Address: 0x08014AB8 + Address: 0x08014ABC + Address: 0x08014AC0 + Address: 0x08014AD8 + Address: 0x08014ADC + Address: 0x08014AE0 + Address: 0x08014AE4 + Address: 0x08014AE8 + Address: 0x08014AEC + Address: 0x08014AF0 + Address: 0x08014AF4 + Address: 0x08014AF8 + Address: 0x08014AFC + Address: 0x08014B00 + Address: 0x08014B04 + Address: 0x08014B08 + Address: 0x08014B0C + Address: 0x08014B10 + Address: 0x08014B14 + Address: 0x08014B18 + Address: 0x08014B1C + Address: 0x08014B20 + Address: 0x08014B30 + Address: 0x08014B34 + Address: 0x08014B38 + Address: 0x08014B3C + Address: 0x08014B40 + Address: 0x08014B44 + Address: 0x08014B48 + Address: 0x08014B4C + Address: 0x08014B50 + Address: 0x08014B54 + Address: 0x08014B58 + Address: 0x08014B5C + Address: 0x08014B60 + Address: 0x08014B64 + Address: 0x08014B68 + Address: 0x08014B6C + Address: 0x08014B70 + Address: 0x08014B74 + Address: 0x08014B94 + Address: 0x08014B98 + Address: 0x08014B9C + Address: 0x08014BA0 + Address: 0x08014BA4 + Address: 0x08014BA8 + Address: 0x08014BAC + Address: 0x08014BB0 + Address: 0x08014BB4 + Address: 0x08014BB8 + Address: 0x08014BBC + Address: 0x08014BC0 + Address: 0x08014BC4 + Address: 0x08014BC8 + Address: 0x08014BCC + Address: 0x08014BD0 + Address: 0x08014BD4 + Address: 0x08014BD8 + Address: 0x08014BDC + Address: 0x08014BE0 + Address: 0x08014BF4 + Address: 0x08014BF8 + Address: 0x08014BFC + Address: 0x08014C00 + Address: 0x08014C04 + Address: 0x08014C08 + Address: 0x08014C0C + Address: 0x08014C10 + Address: 0x08014C14 + Address: 0x08014C18 + Address: 0x08014C1C + Address: 0x08014C20 + Address: 0x08014C24 + Address: 0x08014C28 + Address: 0x08014C2C + Address: 0x08014C30 + Address: 0x08014C34 + Address: 0x08014C38 + Address: 0x08014C4C + Address: 0x08014C50 + Address: 0x08014C54 + Address: 0x08014C58 + Address: 0x08014C5C + Address: 0x08014C60 + Address: 0x08014C64 + Address: 0x08014C68 + Address: 0x08014C6C + Address: 0x08014C70 + Address: 0x08014C74 + Address: 0x08014C78 + Address: 0x08014C7C + Address: 0x08014C80 + Address: 0x08014C84 + Address: 0x08014C88 + Address: 0x08014C8C + Address: 0x08014C90 + Address: 0x08014C94 + Address: 0x08014CA4 + Address: 0x08014CA8 + Address: 0x08014CAC + Address: 0x08014CB0 + Address: 0x08014CB4 + Address: 0x08014CB8 + Address: 0x08014CBC + Address: 0x08014CC0 + Address: 0x08014CC4 + Address: 0x08014CC8 + Address: 0x08014CCC + Address: 0x08014CD0 + Address: 0x08014CD4 + Address: 0x08014CD8 + Address: 0x08014CDC + Address: 0x08014CE0 + Address: 0x08014CE4 + Address: 0x08014CE8 + Address: 0x08014D08 + Address: 0x08014D0C + Address: 0x08014D10 + Address: 0x08014D14 + Address: 0x08014D18 + Address: 0x08014D1C + Address: 0x08014D20 + Address: 0x08014D24 + Address: 0x08014D28 + Address: 0x08014D2C + Address: 0x08014D30 + Address: 0x08014D34 + Address: 0x08014D38 + Address: 0x08014D3C + Address: 0x08014D40 + Address: 0x08014D44 + Address: 0x08014D48 + Address: 0x08014D4C + Address: 0x08014D50 + Address: 0x08014D54 + Address: 0x08014D64 + Address: 0x08014D68 + Address: 0x08014D6C + Address: 0x08014D70 + Address: 0x08014D74 + Address: 0x08014D78 + Address: 0x08014D7C + Address: 0x08014D80 + Address: 0x08014D84 + Address: 0x08014D88 + Address: 0x08014D8C + Address: 0x08014D90 + Address: 0x08014D94 + Address: 0x08014D98 + Address: 0x08014D9C + Address: 0x08014DA0 + Address: 0x08014DA4 + Address: 0x08014DA8 + Address: 0x08014DC0 + Address: 0x08014DC4 + Address: 0x08014DC8 + Address: 0x08014DCC + Address: 0x08014DD0 + Address: 0x08014DD4 + Address: 0x08014DD8 + Address: 0x08014DDC + Address: 0x08014DE0 + Address: 0x08014DE4 + Address: 0x08014DE8 + Address: 0x08014DEC + Address: 0x08014DF0 + Address: 0x08014DF4 + Address: 0x08014DF8 + Address: 0x08014DFC + Address: 0x08014E00 + Address: 0x08014E04 + Address: 0x08014E08 + Address: 0x08014E18 + Address: 0x08014E1C + Address: 0x08014E20 + Address: 0x08014E24 + Address: 0x08014E28 + Address: 0x08014E2C + Address: 0x08014E30 + Address: 0x08014E34 + Address: 0x08014E38 + Address: 0x08014E3C + Address: 0x08014E40 + Address: 0x08014E44 + Address: 0x08014E48 + Address: 0x08014E4C + Address: 0x08014E50 + Address: 0x08014E54 + Address: 0x08014E58 + Address: 0x08014E5C + Address: 0x08014E7C + Address: 0x08014E80 + Address: 0x08014E84 + Address: 0x08014E88 + Address: 0x08014E8C + Address: 0x08014E90 + Address: 0x08014E94 + Address: 0x08014E98 + Address: 0x08014E9C + Address: 0x08014EA0 + Address: 0x08014EA4 + Address: 0x08014EA8 + Address: 0x08014EAC + Address: 0x08014EB0 + Address: 0x08014EB4 + Address: 0x08014EB8 + Address: 0x08014EBC + Address: 0x08014EC0 + Address: 0x08014EC4 + Address: 0x08014EC8 + Address: 0x08014ED8 + Address: 0x08014EDC + Address: 0x08014EE0 + Address: 0x08014EE4 + Address: 0x08014EE8 + Address: 0x08014EEC + Address: 0x08014EF0 + Address: 0x08014EF4 + Address: 0x08014EF8 + Address: 0x08014EFC + Address: 0x08014F00 + Address: 0x08014F04 + Address: 0x08014F08 + Address: 0x08014F0C + Address: 0x08014F10 + Address: 0x08014F14 + Address: 0x08014F18 + Address: 0x08014F1C + Address: 0x08014F3C + Address: 0x08014F40 + Address: 0x08014F44 + Address: 0x08014F48 + Address: 0x08014F4C + Address: 0x08014F50 + Address: 0x08014F54 + Address: 0x08014F58 + Address: 0x08014F5C + Address: 0x08014F60 + Address: 0x08014F64 + Address: 0x08014F68 + Address: 0x08014F6C + Address: 0x08014F70 + Address: 0x08014F74 + Address: 0x08014F78 + Address: 0x08014F7C + Address: 0x08014F80 + Address: 0x08014F84 + Address: 0x08014F88 + Address: 0x08014F8C + Address: 0x08014F90 + Address: 0x08014F94 + Address: 0x08014F98 + Address: 0x08014F9C + Address: 0x08014FA0 + Address: 0x08014FA4 + Address: 0x08014FA8 + Address: 0x08014FAC + Address: 0x08014FB0 + Address: 0x08014FB4 + Address: 0x08014FB8 + Address: 0x08014FBC + Address: 0x08014FC0 + Address: 0x08014FC4 + Address: 0x08014FC8 + Address: 0x08014FCC + Address: 0x08014FF4 + Address: 0x08014FF8 + Address: 0x08014FFC + Address: 0x08015000 + Address: 0x08015004 + Address: 0x08015008 + Address: 0x0801500C + Address: 0x08015010 + Address: 0x08015014 + Address: 0x08015018 + Address: 0x0801501C + Address: 0x08015020 + Address: 0x08015024 + Address: 0x08015028 + Address: 0x0801502C + Address: 0x08015030 + Address: 0x08015034 + Address: 0x08015038 + Address: 0x0801503C + Address: 0x08015040 + Address: 0x08015044 + Address: 0x0801504C + Address: 0x08015050 + Address: 0x08015054 + Address: 0x08015058 + Address: 0x0801505C + Address: 0x08015060 + Address: 0x08015064 + Address: 0x08015068 + Address: 0x0801506C + Address: 0x08015070 + Address: 0x08015074 + Address: 0x08015078 + Address: 0x0801507C + Address: 0x08015080 + Address: 0x08015084 + Address: 0x08015088 + Address: 0x0801508C + Address: 0x080150B4 + Address: 0x080150B8 + Address: 0x080150BC + Address: 0x080150C0 + Address: 0x080150C4 + Address: 0x080150C8 + Address: 0x080150CC + Address: 0x080150D0 + Address: 0x080150D4 + Address: 0x080150D8 + Address: 0x080150DC + Address: 0x080150E0 + Address: 0x080150E4 + Address: 0x080150E8 + Address: 0x080150EC + Address: 0x080150F0 + Address: 0x080150F4 + Address: 0x080150F8 + Address: 0x080150FC + Address: 0x08015100 + Address: 0x08015104 + Address: 0x08015108 + Address: 0x0801510C + Address: 0x08015110 + Address: 0x08015114 + Address: 0x08015118 + Address: 0x0801511C + Address: 0x08015120 + Address: 0x08015124 + Address: 0x08015128 + Address: 0x0801512C + Address: 0x08015130 + Address: 0x08015134 + Address: 0x08015138 + Address: 0x0801513C + Address: 0x08015140 + Address: 0x08015144 + Address: 0x08015168 + Address: 0x0801516C + Address: 0x08015170 + Address: 0x08015174 + Address: 0x08015178 + Address: 0x0801517C + Address: 0x08015180 + Address: 0x08015184 + Address: 0x08015188 + Address: 0x0801518C + Address: 0x08015190 + Address: 0x08015194 + Address: 0x08015198 + Address: 0x0801519C + Address: 0x080151A0 + Address: 0x080151A4 + Address: 0x080151A8 + Address: 0x080151AC + Address: 0x080151B0 + Address: 0x080151B4 + Address: 0x080151C4 + Address: 0x080151C8 + Address: 0x080151CC + Address: 0x080151D0 + Address: 0x080151D4 + Address: 0x080151D8 + Address: 0x080151DC + Address: 0x080151E0 + Address: 0x080151E4 + Address: 0x080151E8 + Address: 0x080151EC + Address: 0x080151F0 + Address: 0x080151F4 + Address: 0x080151F8 + Address: 0x080151FC + Address: 0x08015200 + Address: 0x08015204 + Address: 0x08015208 + Address: 0x08015228 + Address: 0x0801522C + Address: 0x08015230 + Address: 0x08015234 + Address: 0x08015238 + Address: 0x0801523C + Address: 0x08015240 + Address: 0x08015244 + Address: 0x08015248 + Address: 0x0801524C + Address: 0x08015250 + Address: 0x08015254 + Address: 0x08015258 + Address: 0x0801525C + Address: 0x08015260 + Address: 0x08015264 + Address: 0x08015268 + Address: 0x0801526C + Address: 0x08015270 + Address: 0x08015274 + Address: 0x08015280 + Address: 0x08015284 + Address: 0x08015288 + Address: 0x0801528C + Address: 0x08015290 + Address: 0x08015294 + Address: 0x08015298 + Address: 0x0801529C + Address: 0x080152A0 + Address: 0x080152A4 + Address: 0x080152A8 + Address: 0x080152AC + Address: 0x080152B0 + Address: 0x080152B4 + Address: 0x080152B8 + Address: 0x080152BC + Address: 0x080152C0 + Address: 0x080152C4 + Address: 0x080152E0 + Address: 0x080152E4 + Address: 0x080152E8 + Address: 0x080152EC + Address: 0x080152F0 + Address: 0x080152F4 + Address: 0x080152F8 + Address: 0x080152FC + Address: 0x08015300 + Address: 0x08015304 + Address: 0x08015308 + Address: 0x0801530C + Address: 0x08015310 + Address: 0x08015314 + Address: 0x08015318 + Address: 0x0801531C + Address: 0x08015320 + Address: 0x08015324 + Address: 0x08015328 + Address: 0x08015340 + Address: 0x08015344 + Address: 0x08015348 + Address: 0x0801534C + Address: 0x08015350 + Address: 0x08015354 + Address: 0x08015358 + Address: 0x0801535C + Address: 0x08015360 + Address: 0x08015364 + Address: 0x08015368 + Address: 0x0801536C + Address: 0x08015370 + Address: 0x08015374 + Address: 0x08015378 + Address: 0x0801537C + Address: 0x08015380 + Address: 0x08015384 + Address: 0x08015388 + Address: 0x080153A0 + Address: 0x080153A4 + Address: 0x080153A8 + Address: 0x080153AC + Address: 0x080153B0 + Address: 0x080153B4 + Address: 0x080153B8 + Address: 0x080153BC + Address: 0x080153C0 + Address: 0x080153C4 + Address: 0x080153C8 + Address: 0x080153CC + Address: 0x080153D0 + Address: 0x080153D4 + Address: 0x080153D8 + Address: 0x080153DC + Address: 0x080153E0 + Address: 0x080153E4 + Address: 0x080153E8 + Address: 0x080153F4 + Address: 0x080153F8 + Address: 0x080153FC + Address: 0x08015400 + Address: 0x08015404 + Address: 0x08015408 + Address: 0x0801540C + Address: 0x08015410 + Address: 0x08015414 + Address: 0x08015418 + Address: 0x0801541C + Address: 0x08015420 + Address: 0x08015424 + Address: 0x08015428 + Address: 0x0801542C + Address: 0x08015430 + Address: 0x08015434 + Address: 0x08015438 + Address: 0x08015454 + Address: 0x08015458 + Address: 0x0801545C + Address: 0x08015460 + Address: 0x08015464 + Address: 0x08015468 + Address: 0x0801546C + Address: 0x08015470 + Address: 0x08015474 + Address: 0x08015478 + Address: 0x0801547C + Address: 0x08015480 + Address: 0x08015484 + Address: 0x08015488 + Address: 0x0801548C + Address: 0x08015490 + Address: 0x08015494 + Address: 0x08015498 + Address: 0x0801549C + Address: 0x080154B0 + Address: 0x080154B4 + Address: 0x080154B8 + Address: 0x080154BC + Address: 0x080154C0 + Address: 0x080154C4 + Address: 0x080154C8 + Address: 0x080154CC + Address: 0x080154D0 + Address: 0x080154D4 + Address: 0x080154D8 + Address: 0x080154DC + Address: 0x080154E0 + Address: 0x080154E4 + Address: 0x080154E8 + Address: 0x080154EC + Address: 0x080154F0 + Address: 0x080154F4 + Address: 0x080154F8 + Address: 0x08015510 + Address: 0x08015514 + Address: 0x08015518 + Address: 0x0801551C + Address: 0x08015520 + Address: 0x08015524 + Address: 0x08015528 + Address: 0x0801552C + Address: 0x08015530 + Address: 0x08015534 + Address: 0x08015538 + Address: 0x0801553C + Address: 0x08015540 + Address: 0x08015544 + Address: 0x08015548 + Address: 0x0801554C + Address: 0x08015550 + Address: 0x08015554 + Address: 0x08015558 + Address: 0x08015570 + Address: 0x08015574 + Address: 0x08015578 + Address: 0x0801557C + Address: 0x08015580 + Address: 0x08015584 + Address: 0x08015588 + Address: 0x0801558C + Address: 0x08015590 + Address: 0x08015594 + Address: 0x08015598 + Address: 0x0801559C + Address: 0x080155A0 + Address: 0x080155A4 + Address: 0x080155A8 + Address: 0x080155AC + Address: 0x080155B0 + Address: 0x080155B4 + Address: 0x080155B8 + Address: 0x080155C4 + Address: 0x080155C8 + Address: 0x080155CC + Address: 0x080155D0 + Address: 0x080155D4 + Address: 0x080155D8 + Address: 0x080155DC + Address: 0x080155E0 + Address: 0x080155E4 + Address: 0x080155E8 + Address: 0x080155EC + Address: 0x080155F0 + Address: 0x080155F4 + Address: 0x080155F8 + Address: 0x080155FC + Address: 0x08015600 + Address: 0x08015604 + Address: 0x08015608 + Address: 0x08015628 + Address: 0x0801562C + Address: 0x08015630 + Address: 0x08015634 + Address: 0x08015638 + Address: 0x0801563C + Address: 0x08015640 + Address: 0x08015644 + Address: 0x08015648 + Address: 0x0801564C + Address: 0x08015650 + Address: 0x08015654 + Address: 0x08015658 + Address: 0x0801565C + Address: 0x08015660 + Address: 0x08015664 + Address: 0x08015668 + Address: 0x0801566C + Address: 0x08015670 + Address: 0x08015674 + Address: 0x08015680 + Address: 0x08015684 + Address: 0x08015688 + Address: 0x0801568C + Address: 0x08015690 + Address: 0x08015694 + Address: 0x08015698 + Address: 0x0801569C + Address: 0x080156A0 + Address: 0x080156A4 + Address: 0x080156A8 + Address: 0x080156AC + Address: 0x080156B0 + Address: 0x080156B4 + Address: 0x080156B8 + Address: 0x080156BC + Address: 0x080156C0 + Address: 0x080156C4 + Address: 0x080156E0 + Address: 0x080156E4 + Address: 0x080156E8 + Address: 0x080156EC + Address: 0x080156F0 + Address: 0x080156F4 + Address: 0x080156F8 + Address: 0x080156FC + Address: 0x08015700 + Address: 0x08015704 + Address: 0x08015708 + Address: 0x0801570C + Address: 0x08015710 + Address: 0x08015714 + Address: 0x08015718 + Address: 0x0801571C + Address: 0x08015720 + Address: 0x08015724 + Address: 0x08015728 + Address: 0x08015734 + Address: 0x08015738 + Address: 0x0801573C + Address: 0x08015740 + Address: 0x08015744 + Address: 0x08015748 + Address: 0x0801574C + Address: 0x08015750 + Address: 0x08015754 + Address: 0x08015758 + Address: 0x0801575C + Address: 0x08015760 + Address: 0x08015764 + Address: 0x08015768 + Address: 0x0801576C + Address: 0x08015770 + Address: 0x08015774 + Address: 0x08015778 + Address: 0x0801579C + Address: 0x080157A0 + Address: 0x080157A4 + Address: 0x080157A8 + Address: 0x080157AC + Address: 0x080157B0 + Address: 0x080157B4 + Address: 0x080157B8 + Address: 0x080157BC + Address: 0x080157C0 + Address: 0x080157C4 + Address: 0x080157C8 + Address: 0x080157CC + Address: 0x080157D0 + Address: 0x080157D4 + Address: 0x080157D8 + Address: 0x080157DC + Address: 0x080157E0 + Address: 0x080157E4 + Address: 0x080157E8 + Address: 0x080157F4 + Address: 0x080157F8 + Address: 0x080157FC + Address: 0x08015800 + Address: 0x08015804 + Address: 0x08015808 + Address: 0x0801580C + Address: 0x08015810 + Address: 0x08015814 + Address: 0x08015818 + Address: 0x0801581C + Address: 0x08015820 + Address: 0x08015824 + Address: 0x08015828 + Address: 0x0801582C + Address: 0x08015830 + Address: 0x08015834 + Address: 0x08015838 + Address: 0x08015858 + Address: 0x0801585C + Address: 0x08015860 + Address: 0x08015864 + Address: 0x08015868 + Address: 0x0801586C + Address: 0x08015870 + Address: 0x08015874 + Address: 0x08015878 + Address: 0x0801587C + Address: 0x08015880 + Address: 0x08015884 + Address: 0x08015888 + Address: 0x0801588C + Address: 0x08015890 + Address: 0x08015894 + Address: 0x08015898 + Address: 0x0801589C + Address: 0x080158A0 + Address: 0x080158A4 + Address: 0x080158AC + Address: 0x080158B0 + Address: 0x080158B4 + Address: 0x080158B8 + Address: 0x080158BC + Address: 0x080158C0 + Address: 0x080158C4 + Address: 0x080158C8 + Address: 0x080158CC + Address: 0x080158D0 + Address: 0x080158D4 + Address: 0x080158D8 + Address: 0x080158DC + Address: 0x080158E0 + Address: 0x080158E4 + Address: 0x080158E8 + Address: 0x080158EC + Address: 0x08015918 + Address: 0x0801591C + Address: 0x08015920 + Address: 0x08015924 + Address: 0x08015928 + Address: 0x0801592C + Address: 0x08015930 + Address: 0x08015934 + Address: 0x08015938 + Address: 0x0801593C + Address: 0x08015940 + Address: 0x08015944 + Address: 0x08015948 + Address: 0x0801594C + Address: 0x08015950 + Address: 0x08015954 + Address: 0x08015958 + Address: 0x0801595C + Address: 0x08015960 + Address: 0x08015964 + Address: 0x08015968 + Address: 0x0801596C + Address: 0x08015970 + Address: 0x08015974 + Address: 0x08015978 + Address: 0x0801597C + Address: 0x08015980 + Address: 0x08015984 + Address: 0x08015988 + Address: 0x0801598C + Address: 0x08015990 + Address: 0x08015994 + Address: 0x08015998 + Address: 0x0801599C + Address: 0x080159A0 + Address: 0x080159A4 + Address: 0x080159A8 + Address: 0x080159AC + Address: 0x080159CC + Address: 0x080159D0 + Address: 0x080159D4 + Address: 0x080159D8 + Address: 0x080159DC + Address: 0x080159E0 + Address: 0x080159E4 + Address: 0x080159E8 + Address: 0x080159EC + Address: 0x080159F0 + Address: 0x080159F4 + Address: 0x080159F8 + Address: 0x080159FC + Address: 0x08015A00 + Address: 0x08015A04 + Address: 0x08015A08 + Address: 0x08015A0C + Address: 0x08015A10 + Address: 0x08015A14 + Address: 0x08015A18 + Address: 0x08015A1C + Address: 0x08015A20 + Address: 0x08015A24 + Address: 0x08015A28 + Address: 0x08015A2C + Address: 0x08015A30 + Address: 0x08015A34 + Address: 0x08015A38 + Address: 0x08015A3C + Address: 0x08015A40 + Address: 0x08015A44 + Address: 0x08015A48 + Address: 0x08015A4C + Address: 0x08015A50 + Address: 0x08015A54 + Address: 0x08015A58 + Address: 0x08015A5C + Address: 0x08015A88 + Address: 0x08015A8C + Address: 0x08015A90 + Address: 0x08015A94 + Address: 0x08015A98 + Address: 0x08015A9C + Address: 0x08015AA0 + Address: 0x08015AA4 + Address: 0x08015AA8 + Address: 0x08015AAC + Address: 0x08015AB0 + Address: 0x08015AB4 + Address: 0x08015AB8 + Address: 0x08015ABC + Address: 0x08015AC0 + Address: 0x08015AC4 + Address: 0x08015AC8 + Address: 0x08015ACC + Address: 0x08015AD0 + Address: 0x08015AD4 + Address: 0x08015AD8 + Address: 0x08015ADC + Address: 0x08015AE0 + Address: 0x08015AE4 + Address: 0x08015AE8 + Address: 0x08015AEC + Address: 0x08015AF0 + Address: 0x08015AF4 + Address: 0x08015AF8 + Address: 0x08015AFC + Address: 0x08015B00 + Address: 0x08015B04 + Address: 0x08015B08 + Address: 0x08015B0C + Address: 0x08015B10 + Address: 0x08015B14 + Address: 0x08015B18 + Address: 0x08015B1C + Address: 0x08015B44 + Address: 0x08015B48 + Address: 0x08015B4C + Address: 0x08015B50 + Address: 0x08015B54 + Address: 0x08015B58 + Address: 0x08015B5C + Address: 0x08015B60 + Address: 0x08015B64 + Address: 0x08015B68 + Address: 0x08015B6C + Address: 0x08015B70 + Address: 0x08015B74 + Address: 0x08015B78 + Address: 0x08015B7C + Address: 0x08015B80 + Address: 0x08015B84 + Address: 0x08015B88 + Address: 0x08015B8C + Address: 0x08015B90 + Address: 0x08015B94 + Address: 0x08015B98 + Address: 0x08015B9C + Address: 0x08015BA0 + Address: 0x08015BA4 + Address: 0x08015BA8 + Address: 0x08015BAC + Address: 0x08015BB0 + Address: 0x08015BB4 + Address: 0x08015BB8 + Address: 0x08015BBC + Address: 0x08015BC0 + Address: 0x08015BC4 + Address: 0x08015BC8 + Address: 0x08015BCC + Address: 0x08015BD0 + Address: 0x08015BD4 + Address: 0x08015BF4 + Address: 0x08015BF8 + Address: 0x08015BFC + Address: 0x08015C00 + Address: 0x08015C04 + Address: 0x08015C08 + Address: 0x08015C0C + Address: 0x08015C10 + Address: 0x08015C14 + Address: 0x08015C18 + Address: 0x08015C1C + Address: 0x08015C20 + Address: 0x08015C24 + Address: 0x08015C28 + Address: 0x08015C2C + Address: 0x08015C30 + Address: 0x08015C34 + Address: 0x08015C38 + Address: 0x08015C3C + Address: 0x08015C40 + Address: 0x08015C4C + Address: 0x08015C50 + Address: 0x08015C54 + Address: 0x08015C58 + Address: 0x08015C5C + Address: 0x08015C60 + Address: 0x08015C64 + Address: 0x08015C68 + Address: 0x08015C6C + Address: 0x08015C70 + Address: 0x08015C74 + Address: 0x08015C78 + Address: 0x08015C7C + Address: 0x08015C80 + Address: 0x08015C84 + Address: 0x08015C88 + Address: 0x08015C8C + Address: 0x08015C90 + Address: 0x08015CB4 + Address: 0x08015CB8 + Address: 0x08015CBC + Address: 0x08015CC0 + Address: 0x08015CC4 + Address: 0x08015CC8 + Address: 0x08015CCC + Address: 0x08015CD0 + Address: 0x08015CD4 + Address: 0x08015CD8 + Address: 0x08015CDC + Address: 0x08015CE0 + Address: 0x08015CE4 + Address: 0x08015CE8 + Address: 0x08015CEC + Address: 0x08015CF0 + Address: 0x08015CF4 + Address: 0x08015CF8 + Address: 0x08015CFC + Address: 0x08015D00 + Address: 0x08015D08 + Address: 0x08015D0C + Address: 0x08015D10 + Address: 0x08015D14 + Address: 0x08015D18 + Address: 0x08015D1C + Address: 0x08015D20 + Address: 0x08015D24 + Address: 0x08015D28 + Address: 0x08015D2C + Address: 0x08015D30 + Address: 0x08015D34 + Address: 0x08015D38 + Address: 0x08015D3C + Address: 0x08015D40 + Address: 0x08015D44 + Address: 0x08015D48 + Address: 0x08015D68 + Address: 0x08015D6C + Address: 0x08015D70 + Address: 0x08015D74 + Address: 0x08015D78 + Address: 0x08015D7C + Address: 0x08015D80 + Address: 0x08015D84 + Address: 0x08015D88 + Address: 0x08015D8C + Address: 0x08015D90 + Address: 0x08015D94 + Address: 0x08015D98 + Address: 0x08015D9C + Address: 0x08015DA0 + Address: 0x08015DA4 + Address: 0x08015DA8 + Address: 0x08015DAC + Address: 0x08015DB0 + Address: 0x08015DB4 + Address: 0x08015DC4 + Address: 0x08015DC8 + Address: 0x08015DCC + Address: 0x08015DD0 + Address: 0x08015DD4 + Address: 0x08015DD8 + Address: 0x08015DDC + Address: 0x08015DE0 + Address: 0x08015DE4 + Address: 0x08015DE8 + Address: 0x08015DEC + Address: 0x08015DF0 + Address: 0x08015DF4 + Address: 0x08015DF8 + Address: 0x08015DFC + Address: 0x08015E00 + Address: 0x08015E04 + Address: 0x08015E08 + Address: 0x08015E28 + Address: 0x08015E2C + Address: 0x08015E30 + Address: 0x08015E34 + Address: 0x08015E38 + Address: 0x08015E3C + Address: 0x08015E40 + Address: 0x08015E44 + Address: 0x08015E48 + Address: 0x08015E4C + Address: 0x08015E50 + Address: 0x08015E54 + Address: 0x08015E58 + Address: 0x08015E5C + Address: 0x08015E60 + Address: 0x08015E64 + Address: 0x08015E68 + Address: 0x08015E6C + Address: 0x08015E70 + Address: 0x08015E74 + Address: 0x08015E84 + Address: 0x08015E88 + Address: 0x08015E8C + Address: 0x08015E90 + Address: 0x08015E94 + Address: 0x08015E98 + Address: 0x08015E9C + Address: 0x08015EA0 + Address: 0x08015EA4 + Address: 0x08015EA8 + Address: 0x08015EAC + Address: 0x08015EB0 + Address: 0x08015EB4 + Address: 0x08015EB8 + Address: 0x08015EBC + Address: 0x08015EC0 + Address: 0x08015EC4 + Address: 0x08015EC8 + Address: 0x08015EDC + Address: 0x08015EE0 + Address: 0x08015EE4 + Address: 0x08015EE8 + Address: 0x08015EEC + Address: 0x08015EF0 + Address: 0x08015EF4 + Address: 0x08015EF8 + Address: 0x08015EFC + Address: 0x08015F00 + Address: 0x08015F04 + Address: 0x08015F08 + Address: 0x08015F0C + Address: 0x08015F10 + Address: 0x08015F14 + Address: 0x08015F18 + Address: 0x08015F1C + Address: 0x08015F20 + Address: 0x08015F24 + Address: 0x08015F44 + Address: 0x08015F48 + Address: 0x08015F4C + Address: 0x08015F50 + Address: 0x08015F54 + Address: 0x08015F58 + Address: 0x08015F5C + Address: 0x08015F60 + Address: 0x08015F64 + Address: 0x08015F68 + Address: 0x08015F6C + Address: 0x08015F70 + Address: 0x08015F74 + Address: 0x08015F78 + Address: 0x08015F7C + Address: 0x08015F80 + Address: 0x08015F84 + Address: 0x08015F88 + Address: 0x08015F8C + Address: 0x08015F90 + Address: 0x08015F9C + Address: 0x08015FA0 + Address: 0x08015FA4 + Address: 0x08015FA8 + Address: 0x08015FAC + Address: 0x08015FB0 + Address: 0x08015FB4 + Address: 0x08015FB8 + Address: 0x08015FBC + Address: 0x08015FC0 + Address: 0x08015FC4 + Address: 0x08015FC8 + Address: 0x08015FCC + Address: 0x08015FD0 + Address: 0x08015FD4 + Address: 0x08015FD8 + Address: 0x08015FDC + Address: 0x08015FE0 + Address: 0x08015FFC + Address: 0x08016000 + Address: 0x08016004 + Address: 0x08016008 + Address: 0x0801600C + Address: 0x08016010 + Address: 0x08016014 + Address: 0x08016018 + Address: 0x0801601C + Address: 0x08016020 + Address: 0x08016024 + Address: 0x08016028 + Address: 0x0801602C + Address: 0x08016030 + Address: 0x08016034 + Address: 0x08016038 + Address: 0x0801603C + Address: 0x08016040 + Address: 0x08016044 + Address: 0x08016048 + Address: 0x08016050 + Address: 0x08016054 + Address: 0x08016058 + Address: 0x0801605C + Address: 0x08016060 + Address: 0x08016064 + Address: 0x08016068 + Address: 0x0801606C + Address: 0x08016070 + Address: 0x08016074 + Address: 0x08016078 + Address: 0x0801607C + Address: 0x08016080 + Address: 0x08016084 + Address: 0x08016088 + Address: 0x0801608C + Address: 0x08016090 + Address: 0x080160B8 + Address: 0x080160BC + Address: 0x080160C0 + Address: 0x080160C4 + Address: 0x080160C8 + Address: 0x080160CC + Address: 0x080160D0 + Address: 0x080160D4 + Address: 0x080160D8 + Address: 0x080160DC + Address: 0x080160E0 + Address: 0x080160E4 + Address: 0x080160E8 + Address: 0x080160EC + Address: 0x080160F0 + Address: 0x080160F4 + Address: 0x080160F8 + Address: 0x080160FC + Address: 0x08016100 + Address: 0x08016104 + Address: 0x08016108 + Address: 0x08016110 + Address: 0x08016114 + Address: 0x08016118 + Address: 0x0801611C + Address: 0x08016120 + Address: 0x08016124 + Address: 0x08016128 + Address: 0x0801612C + Address: 0x08016130 + Address: 0x08016134 + Address: 0x08016138 + Address: 0x0801613C + Address: 0x08016140 + Address: 0x08016144 + Address: 0x08016148 + Address: 0x0801614C + Address: 0x08016150 + Address: 0x08016174 + Address: 0x08016178 + Address: 0x0801617C + Address: 0x08016180 + Address: 0x08016184 + Address: 0x08016188 + Address: 0x0801618C + Address: 0x08016190 + Address: 0x08016194 + Address: 0x08016198 + Address: 0x0801619C + Address: 0x080161A0 + Address: 0x080161A4 + Address: 0x080161A8 + Address: 0x080161AC + Address: 0x080161B0 + Address: 0x080161B4 + Address: 0x080161B8 + Address: 0x080161BC + Address: 0x080161C0 + Address: 0x080161C4 + Address: 0x080161C8 + Address: 0x080161CC + Address: 0x080161D0 + Address: 0x080161D4 + Address: 0x080161D8 + Address: 0x080161DC + Address: 0x080161E0 + Address: 0x080161E4 + Address: 0x080161E8 + Address: 0x080161EC + Address: 0x080161F0 + Address: 0x080161F4 + Address: 0x080161F8 + Address: 0x080161FC + Address: 0x08016200 + Address: 0x08016204 + Address: 0x08016228 + Address: 0x0801622C + Address: 0x08016230 + Address: 0x08016234 + Address: 0x08016238 + Address: 0x0801623C + Address: 0x08016240 + Address: 0x08016244 + Address: 0x08016248 + Address: 0x0801624C + Address: 0x08016250 + Address: 0x08016254 + Address: 0x08016258 + Address: 0x0801625C + Address: 0x08016260 + Address: 0x08016264 + Address: 0x08016268 + Address: 0x0801626C + Address: 0x08016270 + Address: 0x08016274 + Address: 0x08016278 + Address: 0x08016284 + Address: 0x08016288 + Address: 0x0801628C + Address: 0x08016290 + Address: 0x08016294 + Address: 0x08016298 + Address: 0x0801629C + Address: 0x080162A0 + Address: 0x080162A4 + Address: 0x080162A8 + Address: 0x080162AC + Address: 0x080162B0 + Address: 0x080162B4 + Address: 0x080162B8 + Address: 0x080162BC + Address: 0x080162C0 + Address: 0x080162C4 + Address: 0x080162E4 + Address: 0x080162E8 + Address: 0x080162EC + Address: 0x080162F0 + Address: 0x080162F4 + Address: 0x080162F8 + Address: 0x080162FC + Address: 0x08016300 + Address: 0x08016304 + Address: 0x08016308 + Address: 0x0801630C + Address: 0x08016310 + Address: 0x08016314 + Address: 0x08016318 + Address: 0x0801631C + Address: 0x08016320 + Address: 0x08016324 + Address: 0x08016328 + Address: 0x0801632C + Address: 0x08016330 + Address: 0x08016338 + Address: 0x0801633C + Address: 0x08016340 + Address: 0x08016344 + Address: 0x08016348 + Address: 0x0801634C + Address: 0x08016350 + Address: 0x08016354 + Address: 0x08016358 + Address: 0x0801635C + Address: 0x08016360 + Address: 0x08016364 + Address: 0x08016368 + Address: 0x0801636C + Address: 0x08016370 + Address: 0x08016374 + Address: 0x08016378 + Address: 0x080163A0 + Address: 0x080163A4 + Address: 0x080163A8 + Address: 0x080163AC + Address: 0x080163B0 + Address: 0x080163B4 + Address: 0x080163B8 + Address: 0x080163BC + Address: 0x080163C0 + Address: 0x080163C4 + Address: 0x080163C8 + Address: 0x080163CC + Address: 0x080163D0 + Address: 0x080163D4 + Address: 0x080163D8 + Address: 0x080163DC + Address: 0x080163E0 + Address: 0x080163E4 + Address: 0x080163E8 + Address: 0x080163EC + Address: 0x080163F0 + Address: 0x080163F8 + Address: 0x080163FC + Address: 0x08016400 + Address: 0x08016404 + Address: 0x08016408 + Address: 0x0801640C + Address: 0x08016410 + Address: 0x08016414 + Address: 0x08016418 + Address: 0x0801641C + Address: 0x08016420 + Address: 0x08016424 + Address: 0x08016428 + Address: 0x0801642C + Address: 0x08016430 + Address: 0x08016434 + Address: 0x08016438 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0x08016534 + Address: 0x08016538 + Address: 0x0801653C + Address: 0x08016540 + Address: 0x08016544 + Address: 0x08016548 + Address: 0x0801654C + Address: 0x08016550 + Address: 0x08016554 + Address: 0x08016558 + Address: 0x0801655C + Address: 0x08016560 + Address: 0x08016564 + Address: 0x0801656C + Address: 0x08016570 + Address: 0x08016574 + Address: 0x08016578 + Address: 0x0801657C + Address: 0x08016580 + Address: 0x08016584 + Address: 0x08016588 + Address: 0x0801658C + Address: 0x08016590 + Address: 0x08016594 + Address: 0x08016598 + Address: 0x0801659C + Address: 0x080165A0 + Address: 0x080165A4 + Address: 0x080165A8 + Address: 0x080165AC + Address: 0x080165CC + Address: 0x080165D0 + Address: 0x080165D4 + Address: 0x080165D8 + Address: 0x080165DC + Address: 0x080165E0 + Address: 0x080165E4 + Address: 0x080165E8 + Address: 0x080165EC + Address: 0x080165F0 + Address: 0x080165F4 + Address: 0x080165F8 + Address: 0x080165FC + Address: 0x08016600 + Address: 0x08016604 + Address: 0x08016608 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0x080166E8 + Address: 0x080166EC + Address: 0x080166F0 + Address: 0x080166F4 + Address: 0x080166F8 + Address: 0x080166FC + Address: 0x08016700 + Address: 0x08016704 + Address: 0x08016708 + Address: 0x0801670C + Address: 0x08016710 + Address: 0x08016714 + Address: 0x08016718 + Address: 0x08016738 + Address: 0x0801673C + Address: 0x08016740 + Address: 0x08016744 + Address: 0x08016748 + Address: 0x0801674C + Address: 0x08016750 + Address: 0x08016754 + Address: 0x08016758 + Address: 0x0801675C + Address: 0x08016760 + Address: 0x08016764 + Address: 0x08016768 + Address: 0x0801676C + Address: 0x08016770 + Address: 0x08016774 + Address: 0x08016778 + Address: 0x0801677C + Address: 0x08016780 + Address: 0x08016784 + Address: 0x0801678C + Address: 0x08016790 + Address: 0x08016794 + Address: 0x08016798 + Address: 0x0801679C + Address: 0x080167A0 + Address: 0x080167A4 + Address: 0x080167A8 + Address: 0x080167AC + Address: 0x080167B0 + Address: 0x080167B4 + Address: 0x080167B8 + Address: 0x080167BC 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0x080168BC + Address: 0x080168C0 + Address: 0x080168C4 + Address: 0x080168C8 + Address: 0x080168CC + Address: 0x080168D0 + Address: 0x080168D4 + Address: 0x080168D8 + Address: 0x080168DC + Address: 0x080168E0 + Address: 0x080168E4 + Address: 0x080168E8 + Address: 0x080168EC + Address: 0x080168F0 + Address: 0x080168F4 + Address: 0x080168F8 + Address: 0x080168FC + Address: 0x08016900 + Address: 0x08016904 + Address: 0x08016908 + Address: 0x0801690C + Address: 0x08016910 + Address: 0x08016914 + Address: 0x08016918 + Address: 0x0801691C + Address: 0x08016920 + Address: 0x08016924 + Address: 0x08016928 + Address: 0x0801692C + Address: 0x08016930 + Address: 0x08016934 + Address: 0x08016938 + Address: 0x0801693C + Address: 0x08016968 + Address: 0x0801696C + Address: 0x08016970 + Address: 0x08016974 + Address: 0x08016978 + Address: 0x0801697C + Address: 0x08016980 + Address: 0x08016984 + Address: 0x08016988 + Address: 0x0801698C + Address: 0x08016990 + Address: 0x08016994 + Address: 0x08016998 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0x08016A74 + Address: 0x08016A78 + Address: 0x08016A7C + Address: 0x08016A80 + Address: 0x08016A84 + Address: 0x08016A88 + Address: 0x08016A8C + Address: 0x08016A90 + Address: 0x08016A94 + Address: 0x08016A98 + Address: 0x08016A9C + Address: 0x08016AA0 + Address: 0x08016AA4 + Address: 0x08016AA8 + Address: 0x08016AAC + Address: 0x08016AB0 + Address: 0x08016AB4 + Address: 0x08016AD4 + Address: 0x08016AD8 + Address: 0x08016ADC + Address: 0x08016AE0 + Address: 0x08016AE4 + Address: 0x08016AE8 + Address: 0x08016AEC + Address: 0x08016AF0 + Address: 0x08016AF4 + Address: 0x08016AF8 + Address: 0x08016AFC + Address: 0x08016B00 + Address: 0x08016B04 + Address: 0x08016B08 + Address: 0x08016B0C + Address: 0x08016B10 + Address: 0x08016B14 + Address: 0x08016B18 + Address: 0x08016B1C + Address: 0x08016B20 + Address: 0x08016B2C + Address: 0x08016B30 + Address: 0x08016B34 + Address: 0x08016B38 + Address: 0x08016B3C + Address: 0x08016B40 + Address: 0x08016B44 + Address: 0x08016B48 + Address: 0x08016B4C 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0x08016C24 + Address: 0x08016C48 + Address: 0x08016C4C + Address: 0x08016C50 + Address: 0x08016C54 + Address: 0x08016C58 + Address: 0x08016C5C + Address: 0x08016C60 + Address: 0x08016C64 + Address: 0x08016C68 + Address: 0x08016C6C + Address: 0x08016C70 + Address: 0x08016C74 + Address: 0x08016C78 + Address: 0x08016C7C + Address: 0x08016C80 + Address: 0x08016C84 + Address: 0x08016C88 + Address: 0x08016C8C + Address: 0x08016C90 + Address: 0x08016C94 + Address: 0x08016CA4 + Address: 0x08016CA8 + Address: 0x08016CAC + Address: 0x08016CB0 + Address: 0x08016CB4 + Address: 0x08016CB8 + Address: 0x08016CBC + Address: 0x08016CC0 + Address: 0x08016CC4 + Address: 0x08016CC8 + Address: 0x08016CCC + Address: 0x08016CD0 + Address: 0x08016CD4 + Address: 0x08016CD8 + Address: 0x08016CDC + Address: 0x08016CE0 + Address: 0x08016CE4 + Address: 0x08016CE8 + Address: 0x08016D00 + Address: 0x08016D04 + Address: 0x08016D08 + Address: 0x08016D0C + Address: 0x08016D10 + Address: 0x08016D14 + Address: 0x08016D18 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0x08016DF8 + Address: 0x08016DFC + Address: 0x08016E00 + Address: 0x08016E04 + Address: 0x08016E08 + Address: 0x08016E14 + Address: 0x08016E18 + Address: 0x08016E1C + Address: 0x08016E20 + Address: 0x08016E24 + Address: 0x08016E28 + Address: 0x08016E2C + Address: 0x08016E30 + Address: 0x08016E34 + Address: 0x08016E38 + Address: 0x08016E3C + Address: 0x08016E40 + Address: 0x08016E44 + Address: 0x08016E48 + Address: 0x08016E4C + Address: 0x08016E50 + Address: 0x08016E54 + Address: 0x08016E58 + Address: 0x08016E74 + Address: 0x08016E78 + Address: 0x08016E7C + Address: 0x08016E80 + Address: 0x08016E84 + Address: 0x08016E88 + Address: 0x08016E8C + Address: 0x08016E90 + Address: 0x08016E94 + Address: 0x08016E98 + Address: 0x08016E9C + Address: 0x08016EA0 + Address: 0x08016EA4 + Address: 0x08016EA8 + Address: 0x08016EAC + Address: 0x08016EB0 + Address: 0x08016EB4 + Address: 0x08016EB8 + Address: 0x08016EBC + Address: 0x08016EC0 + Address: 0x08016EC8 + Address: 0x08016ECC + Address: 0x08016ED0 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0x08016FB0 + Address: 0x08016FB4 + Address: 0x08016FB8 + Address: 0x08016FBC + Address: 0x08016FC0 + Address: 0x08016FC4 + Address: 0x08016FC8 + Address: 0x08016FE8 + Address: 0x08016FEC + Address: 0x08016FF0 + Address: 0x08016FF4 + Address: 0x08016FF8 + Address: 0x08016FFC + Address: 0x08017000 + Address: 0x08017004 + Address: 0x08017008 + Address: 0x0801700C + Address: 0x08017010 + Address: 0x08017014 + Address: 0x08017018 + Address: 0x0801701C + Address: 0x08017020 + Address: 0x08017024 + Address: 0x08017028 + Address: 0x0801702C + Address: 0x08017030 + Address: 0x08017034 + Address: 0x0801703C + Address: 0x08017040 + Address: 0x08017044 + Address: 0x08017048 + Address: 0x0801704C + Address: 0x08017050 + Address: 0x08017054 + Address: 0x08017058 + Address: 0x0801705C + Address: 0x08017060 + Address: 0x08017064 + Address: 0x08017068 + Address: 0x0801706C + Address: 0x08017070 + Address: 0x08017074 + Address: 0x08017078 + Address: 0x0801707C + Address: 0x080170A4 + Address: 0x080170A8 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0x08017184 + Address: 0x08017188 + Address: 0x0801718C + Address: 0x08017190 + Address: 0x08017194 + Address: 0x08017198 + Address: 0x0801719C + Address: 0x080171A0 + Address: 0x080171A4 + Address: 0x080171A8 + Address: 0x080171AC + Address: 0x080171B0 + Address: 0x080171B4 + Address: 0x080171B8 + Address: 0x080171BC + Address: 0x080171C0 + Address: 0x080171C4 + Address: 0x080171C8 + Address: 0x080171CC + Address: 0x080171D0 + Address: 0x080171D4 + Address: 0x080171D8 + Address: 0x080171DC + Address: 0x080171E0 + Address: 0x080171E4 + Address: 0x080171E8 + Address: 0x080171EC + Address: 0x080171F0 + Address: 0x08017218 + Address: 0x0801721C + Address: 0x08017220 + Address: 0x08017224 + Address: 0x08017228 + Address: 0x0801722C + Address: 0x08017230 + Address: 0x08017234 + Address: 0x08017238 + Address: 0x0801723C + Address: 0x08017240 + Address: 0x08017244 + Address: 0x08017248 + Address: 0x0801724C + Address: 0x08017250 + Address: 0x08017254 + Address: 0x08017258 + Address: 0x0801725C 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0x08017338 + Address: 0x0801733C + Address: 0x08017340 + Address: 0x08017344 + Address: 0x08017348 + Address: 0x0801734C + Address: 0x08017350 + Address: 0x08017354 + Address: 0x08017358 + Address: 0x0801735C + Address: 0x08017360 + Address: 0x08017364 + Address: 0x08017394 + Address: 0x08017398 + Address: 0x0801739C + Address: 0x080173A0 + Address: 0x080173A4 + Address: 0x080173A8 + Address: 0x080173AC + Address: 0x080173B0 + Address: 0x080173B4 + Address: 0x080173B8 + Address: 0x080173BC + Address: 0x080173C0 + Address: 0x080173C4 + Address: 0x080173C8 + Address: 0x080173CC + Address: 0x080173D0 + Address: 0x080173D4 + Address: 0x080173D8 + Address: 0x080173DC + Address: 0x080173E0 + Address: 0x080173E4 + Address: 0x080173E8 + Address: 0x080173EC + Address: 0x080173F0 + Address: 0x080173F4 + Address: 0x080173F8 + Address: 0x080173FC + Address: 0x08017400 + Address: 0x08017404 + Address: 0x08017408 + Address: 0x0801740C + Address: 0x08017410 + Address: 0x08017414 + Address: 0x08017418 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0x0801750C + Address: 0x08017510 + Address: 0x08017514 + Address: 0x08017518 + Address: 0x0801751C + Address: 0x08017520 + Address: 0x08017524 + Address: 0x08017528 + Address: 0x0801752C + Address: 0x08017530 + Address: 0x08017534 + Address: 0x08017538 + Address: 0x0801753C + Address: 0x08017540 + Address: 0x08017544 + Address: 0x08017548 + Address: 0x08017558 + Address: 0x0801755C + Address: 0x08017560 + Address: 0x08017564 + Address: 0x08017568 + Address: 0x0801756C + Address: 0x08017570 + Address: 0x08017574 + Address: 0x08017578 + Address: 0x0801757C + Address: 0x08017580 + Address: 0x08017584 + Address: 0x08017588 + Address: 0x0801758C + Address: 0x08017590 + Address: 0x08017594 + Address: 0x08017598 + Address: 0x0801759C + Address: 0x080175B8 + Address: 0x080175BC + Address: 0x080175C0 + Address: 0x080175C4 + Address: 0x080175C8 + Address: 0x080175CC + Address: 0x080175D0 + Address: 0x080175D4 + Address: 0x080175D8 + Address: 0x080175DC + Address: 0x080175E0 + Address: 0x080175E4 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0x080176C8 + Address: 0x080176CC + Address: 0x080176D0 + Address: 0x080176D4 + Address: 0x080176D8 + Address: 0x080176DC + Address: 0x080176E0 + Address: 0x080176E4 + Address: 0x080176E8 + Address: 0x080176EC + Address: 0x080176F0 + Address: 0x080176F4 + Address: 0x080176F8 + Address: 0x080176FC + Address: 0x08017700 + Address: 0x08017704 + Address: 0x08017708 + Address: 0x0801770C + Address: 0x0801772C + Address: 0x08017730 + Address: 0x08017734 + Address: 0x08017738 + Address: 0x0801773C + Address: 0x08017740 + Address: 0x08017744 + Address: 0x08017748 + Address: 0x0801774C + Address: 0x08017750 + Address: 0x08017754 + Address: 0x08017758 + Address: 0x0801775C + Address: 0x08017760 + Address: 0x08017764 + Address: 0x08017768 + Address: 0x0801776C + Address: 0x08017770 + Address: 0x08017774 + Address: 0x08017778 + Address: 0x0801777C + Address: 0x08017780 + Address: 0x08017784 + Address: 0x08017788 + Address: 0x0801778C + Address: 0x08017790 + Address: 0x08017794 + Address: 0x08017798 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0x0801787C + Address: 0x08017880 + Address: 0x080178A4 + Address: 0x080178A8 + Address: 0x080178AC + Address: 0x080178B0 + Address: 0x080178B4 + Address: 0x080178B8 + Address: 0x080178BC + Address: 0x080178C0 + Address: 0x080178C4 + Address: 0x080178C8 + Address: 0x080178CC + Address: 0x080178D0 + Address: 0x080178D4 + Address: 0x080178D8 + Address: 0x080178DC + Address: 0x080178E0 + Address: 0x080178E4 + Address: 0x080178E8 + Address: 0x080178EC + Address: 0x080178F0 + Address: 0x080178F8 + Address: 0x080178FC + Address: 0x08017900 + Address: 0x08017904 + Address: 0x08017908 + Address: 0x0801790C + Address: 0x08017910 + Address: 0x08017914 + Address: 0x08017918 + Address: 0x0801791C + Address: 0x08017920 + Address: 0x08017924 + Address: 0x08017928 + Address: 0x0801792C + Address: 0x08017930 + Address: 0x08017934 + Address: 0x08017938 + Address: 0x08017960 + Address: 0x08017964 + Address: 0x08017968 + Address: 0x0801796C + Address: 0x08017970 + Address: 0x08017974 + Address: 0x08017978 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0x08017A54 + Address: 0x08017A58 + Address: 0x08017A5C + Address: 0x08017A60 + Address: 0x08017A64 + Address: 0x08017A68 + Address: 0x08017A6C + Address: 0x08017A70 + Address: 0x08017A74 + Address: 0x08017A78 + Address: 0x08017A7C + Address: 0x08017A80 + Address: 0x08017A84 + Address: 0x08017A88 + Address: 0x08017A8C + Address: 0x08017A90 + Address: 0x08017A94 + Address: 0x08017A98 + Address: 0x08017A9C + Address: 0x08017AA0 + Address: 0x08017AA4 + Address: 0x08017AA8 + Address: 0x08017AAC + Address: 0x08017ACC + Address: 0x08017AD0 + Address: 0x08017AD4 + Address: 0x08017AD8 + Address: 0x08017ADC + Address: 0x08017AE0 + Address: 0x08017AE4 + Address: 0x08017AE8 + Address: 0x08017AEC + Address: 0x08017AF0 + Address: 0x08017AF4 + Address: 0x08017AF8 + Address: 0x08017AFC + Address: 0x08017B00 + Address: 0x08017B04 + Address: 0x08017B08 + Address: 0x08017B0C + Address: 0x08017B10 + Address: 0x08017B14 + Address: 0x08017B18 + Address: 0x08017B2C + Address: 0x08017B30 + Address: 0x08017B34 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0x08017C0C + Address: 0x08017C10 + Address: 0x08017C14 + Address: 0x08017C18 + Address: 0x08017C1C + Address: 0x08017C20 + Address: 0x08017C24 + Address: 0x08017C40 + Address: 0x08017C44 + Address: 0x08017C48 + Address: 0x08017C4C + Address: 0x08017C50 + Address: 0x08017C54 + Address: 0x08017C58 + Address: 0x08017C5C + Address: 0x08017C60 + Address: 0x08017C64 + Address: 0x08017C68 + Address: 0x08017C6C + Address: 0x08017C70 + Address: 0x08017C74 + Address: 0x08017C78 + Address: 0x08017C7C + Address: 0x08017C80 + Address: 0x08017C84 + Address: 0x08017C88 + Address: 0x08017C8C + Address: 0x08017C9C + Address: 0x08017CA0 + Address: 0x08017CA4 + Address: 0x08017CA8 + Address: 0x08017CAC + Address: 0x08017CB0 + Address: 0x08017CB4 + Address: 0x08017CB8 + Address: 0x08017CBC + Address: 0x08017CC0 + Address: 0x08017CC4 + Address: 0x08017CC8 + Address: 0x08017CCC + Address: 0x08017CD0 + Address: 0x08017CD4 + Address: 0x08017CD8 + Address: 0x08017CDC + Address: 0x08017CE0 + Address: 0x08017CF8 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0x08017DD8 + Address: 0x08017DDC + Address: 0x08017DE0 + Address: 0x08017DE4 + Address: 0x08017DE8 + Address: 0x08017DEC + Address: 0x08017DF0 + Address: 0x08017DF4 + Address: 0x08017DF8 + Address: 0x08017DFC + Address: 0x08017E00 + Address: 0x08017E14 + Address: 0x08017E18 + Address: 0x08017E1C + Address: 0x08017E20 + Address: 0x08017E24 + Address: 0x08017E28 + Address: 0x08017E2C + Address: 0x08017E30 + Address: 0x08017E34 + Address: 0x08017E38 + Address: 0x08017E3C + Address: 0x08017E40 + Address: 0x08017E44 + Address: 0x08017E48 + Address: 0x08017E4C + Address: 0x08017E50 + Address: 0x08017E54 + Address: 0x08017E58 + Address: 0x08017E6C + Address: 0x08017E70 + Address: 0x08017E74 + Address: 0x08017E78 + Address: 0x08017E7C + Address: 0x08017E80 + Address: 0x08017E84 + Address: 0x08017E88 + Address: 0x08017E8C + Address: 0x08017E90 + Address: 0x08017E94 + Address: 0x08017E98 + Address: 0x08017E9C + Address: 0x08017EA0 + Address: 0x08017EA4 + Address: 0x08017EA8 + Address: 0x08017EAC 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0x08017F98 + Address: 0x08017F9C + Address: 0x08017FA0 + Address: 0x08017FA4 + Address: 0x08017FA8 + Address: 0x08017FAC + Address: 0x08017FB0 + Address: 0x08017FB4 + Address: 0x08017FB8 + Address: 0x08017FBC + Address: 0x08017FC0 + Address: 0x08017FC4 + Address: 0x08017FC8 + Address: 0x08017FE0 + Address: 0x08017FE4 + Address: 0x08017FE8 + Address: 0x08017FEC + Address: 0x08017FF0 + Address: 0x08017FF4 + Address: 0x08017FF8 + Address: 0x08017FFC + Address: 0x08018000 + Address: 0x08018004 + Address: 0x08018008 + Address: 0x0801800C + Address: 0x08018010 + Address: 0x08018014 + Address: 0x08018018 + Address: 0x0801801C + Address: 0x08018020 + Address: 0x08018024 + Address: 0x08018028 + Address: 0x08018038 + Address: 0x0801803C + Address: 0x08018040 + Address: 0x08018044 + Address: 0x08018048 + Address: 0x0801804C + Address: 0x08018050 + Address: 0x08018054 + Address: 0x08018058 + Address: 0x0801805C + Address: 0x08018060 + Address: 0x08018064 + Address: 0x08018068 + Address: 0x0801806C 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0x0801815C + Address: 0x08018160 + Address: 0x08018164 + Address: 0x08018168 + Address: 0x0801816C + Address: 0x08018170 + Address: 0x08018174 + Address: 0x08018178 + Address: 0x0801817C + Address: 0x08018180 + Address: 0x08018184 + Address: 0x08018188 + Address: 0x0801818C + Address: 0x08018190 + Address: 0x08018194 + Address: 0x08018198 + Address: 0x080181B0 + Address: 0x080181B4 + Address: 0x080181B8 + Address: 0x080181BC + Address: 0x080181C0 + Address: 0x080181C4 + Address: 0x080181C8 + Address: 0x080181CC + Address: 0x080181D0 + Address: 0x080181D4 + Address: 0x080181D8 + Address: 0x080181DC + Address: 0x080181E0 + Address: 0x080181E4 + Address: 0x080181E8 + Address: 0x080181EC + Address: 0x080181F0 + Address: 0x080181F4 + Address: 0x080181F8 + Address: 0x08018210 + Address: 0x08018214 + Address: 0x08018218 + Address: 0x0801821C + Address: 0x08018220 + Address: 0x08018224 + Address: 0x08018228 + Address: 0x0801822C + Address: 0x08018230 + Address: 0x08018234 + Address: 0x08018238 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0x08018314 + Address: 0x08018320 + Address: 0x08018324 + Address: 0x08018328 + Address: 0x0801832C + Address: 0x08018330 + Address: 0x08018334 + Address: 0x08018338 + Address: 0x0801833C + Address: 0x08018340 + Address: 0x08018344 + Address: 0x08018348 + Address: 0x0801834C + Address: 0x08018350 + Address: 0x08018354 + Address: 0x08018358 + Address: 0x0801835C + Address: 0x08018360 + Address: 0x08018364 + Address: 0x08018384 + Address: 0x08018388 + Address: 0x0801838C + Address: 0x08018390 + Address: 0x08018394 + Address: 0x08018398 + Address: 0x0801839C + Address: 0x080183A0 + Address: 0x080183A4 + Address: 0x080183A8 + Address: 0x080183AC + Address: 0x080183B0 + Address: 0x080183B4 + Address: 0x080183B8 + Address: 0x080183BC + Address: 0x080183C0 + Address: 0x080183C4 + Address: 0x080183C8 + Address: 0x080183CC + Address: 0x080183D0 + Address: 0x080183E0 + Address: 0x080183E4 + Address: 0x080183E8 + Address: 0x080183EC + Address: 0x080183F0 + Address: 0x080183F4 + Address: 0x080183F8 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0x080184D0 + Address: 0x080184D4 + Address: 0x080184D8 + Address: 0x080184F8 + Address: 0x080184FC + Address: 0x08018500 + Address: 0x08018504 + Address: 0x08018508 + Address: 0x0801850C + Address: 0x08018510 + Address: 0x08018514 + Address: 0x08018518 + Address: 0x0801851C + Address: 0x08018520 + Address: 0x08018524 + Address: 0x08018528 + Address: 0x0801852C + Address: 0x08018530 + Address: 0x08018534 + Address: 0x08018538 + Address: 0x0801853C + Address: 0x08018540 + Address: 0x08018544 + Address: 0x08018558 + Address: 0x0801855C + Address: 0x08018560 + Address: 0x08018564 + Address: 0x08018568 + Address: 0x0801856C + Address: 0x08018570 + Address: 0x08018574 + Address: 0x08018578 + Address: 0x0801857C + Address: 0x08018580 + Address: 0x08018584 + Address: 0x08018588 + Address: 0x0801858C + Address: 0x08018590 + Address: 0x08018594 + Address: 0x08018598 + Address: 0x0801859C + Address: 0x080185B4 + Address: 0x080185B8 + Address: 0x080185BC + Address: 0x080185C0 + Address: 0x080185C4 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0x080186A0 + Address: 0x080186A4 + Address: 0x080186A8 + Address: 0x080186AC + Address: 0x080186B0 + Address: 0x080186B4 + Address: 0x080186B8 + Address: 0x080186C8 + Address: 0x080186CC + Address: 0x080186D0 + Address: 0x080186D4 + Address: 0x080186D8 + Address: 0x080186DC + Address: 0x080186E0 + Address: 0x080186E4 + Address: 0x080186E8 + Address: 0x080186EC + Address: 0x080186F0 + Address: 0x080186F4 + Address: 0x080186F8 + Address: 0x080186FC + Address: 0x08018700 + Address: 0x08018704 + Address: 0x08018708 + Address: 0x0801870C + Address: 0x08018728 + Address: 0x0801872C + Address: 0x08018730 + Address: 0x08018734 + Address: 0x08018738 + Address: 0x0801873C + Address: 0x08018740 + Address: 0x08018744 + Address: 0x08018748 + Address: 0x0801874C + Address: 0x08018750 + Address: 0x08018754 + Address: 0x08018758 + Address: 0x0801875C + Address: 0x08018760 + Address: 0x08018764 + Address: 0x08018768 + Address: 0x0801876C + Address: 0x08018770 + Address: 0x08018774 + Address: 0x0801877C + Address: 0x08018780 + Address: 0x08018784 + Address: 0x08018788 + Address: 0x0801878C + Address: 0x08018790 + Address: 0x08018794 + Address: 0x08018798 + Address: 0x0801879C + Address: 0x080187A0 + Address: 0x080187A4 + Address: 0x080187A8 + Address: 0x080187AC + Address: 0x080187B0 + Address: 0x080187B4 + Address: 0x080187B8 + Address: 0x080187BC + Address: 0x080187E0 + Address: 0x080187E4 + Address: 0x080187E8 + Address: 0x080187EC + Address: 0x080187F0 + Address: 0x080187F4 + Address: 0x080187F8 + Address: 0x080187FC + Address: 0x08018800 + Address: 0x08018804 + Address: 0x08018808 + Address: 0x0801880C + Address: 0x08018810 + Address: 0x08018814 + Address: 0x08018818 + Address: 0x0801881C + Address: 0x08018820 + Address: 0x08018824 + Address: 0x08018828 + Address: 0x0801882C + Address: 0x08018830 + Address: 0x0801883C + Address: 0x08018840 + Address: 0x08018844 + Address: 0x08018848 + Address: 0x0801884C + Address: 0x08018850 + Address: 0x08018854 + Address: 0x08018858 + Address: 0x0801885C + Address: 0x08018860 + Address: 0x08018864 + Address: 0x08018868 + Address: 0x0801886C + Address: 0x08018870 + Address: 0x08018874 + Address: 0x08018878 + Address: 0x0801887C + Address: 0x0801889C + Address: 0x080188A0 + Address: 0x080188A4 + Address: 0x080188A8 + Address: 0x080188AC + Address: 0x080188B0 + Address: 0x080188B4 + Address: 0x080188B8 + Address: 0x080188BC + Address: 0x080188C0 + Address: 0x080188C4 + Address: 0x080188C8 + Address: 0x080188CC + Address: 0x080188D0 + Address: 0x080188D4 + Address: 0x080188D8 + Address: 0x080188DC + Address: 0x080188E0 + Address: 0x080188E4 + Address: 0x080188E8 + Address: 0x080188F0 + Address: 0x080188F4 + Address: 0x080188F8 + Address: 0x080188FC + Address: 0x08018900 + Address: 0x08018904 + Address: 0x08018908 + Address: 0x0801890C + Address: 0x08018910 + Address: 0x08018914 + Address: 0x08018918 + Address: 0x0801891C + Address: 0x08018920 + Address: 0x08018924 + Address: 0x08018928 + Address: 0x0801892C + Address: 0x08018930 + Address: 0x08018954 + Address: 0x08018958 + Address: 0x0801895C + Address: 0x08018960 + Address: 0x08018964 + Address: 0x08018968 + Address: 0x0801896C + Address: 0x08018970 + Address: 0x08018974 + Address: 0x08018978 + Address: 0x0801897C + Address: 0x08018980 + Address: 0x08018984 + Address: 0x08018988 + Address: 0x0801898C + Address: 0x08018990 + Address: 0x08018994 + Address: 0x08018998 + Address: 0x0801899C + Address: 0x080189A0 + Address: 0x080189A4 + Address: 0x080189B0 + Address: 0x080189B4 + Address: 0x080189B8 + Address: 0x080189BC + Address: 0x080189C0 + Address: 0x080189C4 + Address: 0x080189C8 + Address: 0x080189CC + Address: 0x080189D0 + Address: 0x080189D4 + Address: 0x080189D8 + Address: 0x080189DC + Address: 0x080189E0 + Address: 0x080189E4 + Address: 0x080189E8 + Address: 0x080189EC + Address: 0x080189F0 + Address: 0x080189F4 + Address: 0x08018A14 + Address: 0x08018A18 + Address: 0x08018A1C + Address: 0x08018A20 + Address: 0x08018A24 + Address: 0x08018A28 + Address: 0x08018A2C + Address: 0x08018A30 + Address: 0x08018A34 + Address: 0x08018A38 + Address: 0x08018A3C + Address: 0x08018A40 + Address: 0x08018A44 + Address: 0x08018A48 + Address: 0x08018A4C + Address: 0x08018A50 + Address: 0x08018A54 + Address: 0x08018A58 + Address: 0x08018A5C + Address: 0x08018A60 + Address: 0x08018A64 + Address: 0x08018A68 + Address: 0x08018A6C + Address: 0x08018A70 + Address: 0x08018A74 + Address: 0x08018A78 + Address: 0x08018A7C + Address: 0x08018A80 + Address: 0x08018A84 + Address: 0x08018A88 + Address: 0x08018A8C + Address: 0x08018A90 + Address: 0x08018A94 + Address: 0x08018A98 + Address: 0x08018A9C + Address: 0x08018AA0 + Address: 0x08018AA4 + Address: 0x08018AD0 + Address: 0x08018AD4 + Address: 0x08018AD8 + Address: 0x08018ADC + Address: 0x08018AE0 + Address: 0x08018AE4 + Address: 0x08018AE8 + Address: 0x08018AEC + Address: 0x08018AF0 + Address: 0x08018AF4 + Address: 0x08018AF8 + Address: 0x08018AFC + Address: 0x08018B00 + Address: 0x08018B04 + Address: 0x08018B08 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0x08018BE0 + Address: 0x08018BE4 + Address: 0x08018BE8 + Address: 0x08018BEC + Address: 0x08018BF0 + Address: 0x08018BF4 + Address: 0x08018BF8 + Address: 0x08018BFC + Address: 0x08018C00 + Address: 0x08018C04 + Address: 0x08018C08 + Address: 0x08018C0C + Address: 0x08018C10 + Address: 0x08018C14 + Address: 0x08018C2C + Address: 0x08018C30 + Address: 0x08018C34 + Address: 0x08018C38 + Address: 0x08018C3C + Address: 0x08018C40 + Address: 0x08018C44 + Address: 0x08018C48 + Address: 0x08018C4C + Address: 0x08018C50 + Address: 0x08018C54 + Address: 0x08018C58 + Address: 0x08018C5C + Address: 0x08018C60 + Address: 0x08018C64 + Address: 0x08018C68 + Address: 0x08018C6C + Address: 0x08018C70 + Address: 0x08018C74 + Address: 0x08018C8C + Address: 0x08018C90 + Address: 0x08018C94 + Address: 0x08018C98 + Address: 0x08018C9C + Address: 0x08018CA0 + Address: 0x08018CA4 + Address: 0x08018CA8 + Address: 0x08018CAC + Address: 0x08018CB0 + Address: 0x08018CB4 + Address: 0x08018CB8 + Address: 0x08018CBC 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0x08018DA8 + Address: 0x08018DAC + Address: 0x08018DB0 + Address: 0x08018DB4 + Address: 0x08018DB8 + Address: 0x08018DBC + Address: 0x08018DC0 + Address: 0x08018DC4 + Address: 0x08018DC8 + Address: 0x08018DCC + Address: 0x08018DD0 + Address: 0x08018DD4 + Address: 0x08018DD8 + Address: 0x08018DDC + Address: 0x08018DE0 + Address: 0x08018DE4 + Address: 0x08018DE8 + Address: 0x08018DFC + Address: 0x08018E00 + Address: 0x08018E04 + Address: 0x08018E08 + Address: 0x08018E0C + Address: 0x08018E10 + Address: 0x08018E14 + Address: 0x08018E18 + Address: 0x08018E1C + Address: 0x08018E20 + Address: 0x08018E24 + Address: 0x08018E28 + Address: 0x08018E2C + Address: 0x08018E30 + Address: 0x08018E34 + Address: 0x08018E38 + Address: 0x08018E3C + Address: 0x08018E40 + Address: 0x08018E44 + Address: 0x08018E60 + Address: 0x08018E64 + Address: 0x08018E68 + Address: 0x08018E6C + Address: 0x08018E70 + Address: 0x08018E74 + Address: 0x08018E78 + Address: 0x08018E7C + Address: 0x08018E80 + Address: 0x08018E84 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0x08018F58 + Address: 0x08018F70 + Address: 0x08018F74 + Address: 0x08018F78 + Address: 0x08018F7C + Address: 0x08018F80 + Address: 0x08018F84 + Address: 0x08018F88 + Address: 0x08018F8C + Address: 0x08018F90 + Address: 0x08018F94 + Address: 0x08018F98 + Address: 0x08018F9C + Address: 0x08018FA0 + Address: 0x08018FA4 + Address: 0x08018FA8 + Address: 0x08018FAC + Address: 0x08018FB0 + Address: 0x08018FB4 + Address: 0x08018FB8 + Address: 0x08018FD4 + Address: 0x08018FD8 + Address: 0x08018FDC + Address: 0x08018FE0 + Address: 0x08018FE4 + Address: 0x08018FE8 + Address: 0x08018FEC + Address: 0x08018FF0 + Address: 0x08018FF4 + Address: 0x08018FF8 + Address: 0x08018FFC + Address: 0x08019000 + Address: 0x08019004 + Address: 0x08019008 + Address: 0x0801900C + Address: 0x08019010 + Address: 0x08019014 + Address: 0x08019018 + Address: 0x0801901C + Address: 0x0801902C + Address: 0x08019030 + Address: 0x08019034 + Address: 0x08019038 + Address: 0x0801903C + Address: 0x08019040 + Address: 0x08019044 + Address: 0x08019048 + Address: 0x0801904C + Address: 0x08019050 + Address: 0x08019054 + Address: 0x08019058 + Address: 0x0801905C + Address: 0x08019060 + Address: 0x08019064 + Address: 0x08019068 + Address: 0x0801906C + Address: 0x08019070 + Address: 0x08019088 + Address: 0x0801908C + Address: 0x08019090 + Address: 0x08019094 + Address: 0x08019098 + Address: 0x0801909C + Address: 0x080190A0 + Address: 0x080190A4 + Address: 0x080190A8 + Address: 0x080190AC + Address: 0x080190B0 + Address: 0x080190B4 + Address: 0x080190B8 + Address: 0x080190BC + Address: 0x080190C0 + Address: 0x080190C4 + Address: 0x080190C8 + Address: 0x080190CC + Address: 0x080190D0 + Address: 0x080190E8 + Address: 0x080190EC + Address: 0x080190F0 + Address: 0x080190F4 + Address: 0x080190F8 + Address: 0x080190FC + Address: 0x08019100 + Address: 0x08019104 + Address: 0x08019108 + Address: 0x0801910C + Address: 0x08019110 + Address: 0x08019114 + Address: 0x08019118 + Address: 0x0801911C + Address: 0x08019120 + Address: 0x08019124 + Address: 0x08019128 + Address: 0x0801912C + Address: 0x08019130 + Address: 0x08019148 + Address: 0x0801914C + Address: 0x08019150 + Address: 0x08019154 + Address: 0x08019158 + Address: 0x0801915C + Address: 0x08019160 + Address: 0x08019164 + Address: 0x08019168 + Address: 0x0801916C + Address: 0x08019170 + Address: 0x08019174 + Address: 0x08019178 + Address: 0x0801917C + Address: 0x08019180 + Address: 0x08019184 + Address: 0x08019188 + Address: 0x0801918C + Address: 0x08019190 + Address: 0x080191A0 + Address: 0x080191A4 + Address: 0x080191A8 + Address: 0x080191AC + Address: 0x080191B0 + Address: 0x080191B4 + Address: 0x080191B8 + Address: 0x080191BC + Address: 0x080191C0 + Address: 0x080191C4 + Address: 0x080191C8 + Address: 0x080191CC + Address: 0x080191D0 + Address: 0x080191D4 + Address: 0x080191D8 + Address: 0x080191DC + Address: 0x080191E0 + Address: 0x080191E4 + Address: 0x080191F8 + Address: 0x080191FC + Address: 0x08019200 + Address: 0x08019204 + Address: 0x08019208 + Address: 0x0801920C + Address: 0x08019210 + Address: 0x08019214 + Address: 0x08019218 + Address: 0x0801921C + Address: 0x08019220 + Address: 0x08019224 + Address: 0x08019228 + Address: 0x0801922C + Address: 0x08019230 + Address: 0x08019234 + Address: 0x08019238 + Address: 0x0801923C + Address: 0x08019240 + Address: 0x08019260 + Address: 0x08019264 + Address: 0x08019268 + Address: 0x0801926C + Address: 0x08019270 + Address: 0x08019274 + Address: 0x08019278 + Address: 0x0801927C + Address: 0x08019280 + Address: 0x08019284 + Address: 0x08019288 + Address: 0x0801928C + Address: 0x08019290 + Address: 0x08019294 + Address: 0x08019298 + Address: 0x0801929C + Address: 0x080192A0 + Address: 0x080192A4 + Address: 0x080192A8 + Address: 0x080192AC + Address: 0x080192BC + Address: 0x080192C0 + Address: 0x080192C4 + Address: 0x080192C8 + Address: 0x080192CC + Address: 0x080192D0 + Address: 0x080192D4 + Address: 0x080192D8 + Address: 0x080192DC + Address: 0x080192E0 + Address: 0x080192E4 + Address: 0x080192E8 + Address: 0x080192EC + Address: 0x080192F0 + Address: 0x080192F4 + Address: 0x080192F8 + Address: 0x080192FC + Address: 0x08019300 + Address: 0x0801931C + Address: 0x08019320 + Address: 0x08019324 + Address: 0x08019328 + Address: 0x0801932C + Address: 0x08019330 + Address: 0x08019334 + Address: 0x08019338 + Address: 0x0801933C + Address: 0x08019340 + Address: 0x08019344 + Address: 0x08019348 + Address: 0x0801934C + Address: 0x08019350 + Address: 0x08019354 + Address: 0x08019358 + Address: 0x0801935C + Address: 0x08019360 + Address: 0x08019364 + Address: 0x08019370 + Address: 0x08019374 + Address: 0x08019378 + Address: 0x0801937C + Address: 0x08019380 + Address: 0x08019384 + Address: 0x08019388 + Address: 0x0801938C + Address: 0x08019390 + Address: 0x08019394 + Address: 0x08019398 + Address: 0x0801939C + Address: 0x080193A0 + Address: 0x080193A4 + Address: 0x080193A8 + Address: 0x080193AC + Address: 0x080193B0 + Address: 0x080193B4 + Address: 0x080193D4 + Address: 0x080193D8 + Address: 0x080193DC + Address: 0x080193E0 + Address: 0x080193E4 + Address: 0x080193E8 + Address: 0x080193EC + Address: 0x080193F0 + Address: 0x080193F4 + Address: 0x080193F8 + Address: 0x080193FC + Address: 0x08019400 + Address: 0x08019404 + Address: 0x08019408 + Address: 0x0801940C + Address: 0x08019410 + Address: 0x08019414 + Address: 0x08019418 + Address: 0x0801941C + Address: 0x08019420 + Address: 0x0801942C + Address: 0x08019430 + Address: 0x08019434 + Address: 0x08019438 + Address: 0x0801943C + Address: 0x08019440 + Address: 0x08019444 + Address: 0x08019448 + Address: 0x0801944C + Address: 0x08019450 + Address: 0x08019454 + Address: 0x08019458 + Address: 0x0801945C + Address: 0x08019460 + Address: 0x08019464 + Address: 0x08019468 + Address: 0x0801946C + Address: 0x08019470 + Address: 0x0801948C + Address: 0x08019490 + Address: 0x08019494 + Address: 0x08019498 + Address: 0x0801949C + Address: 0x080194A0 + Address: 0x080194A4 + Address: 0x080194A8 + Address: 0x080194AC + Address: 0x080194B0 + Address: 0x080194B4 + Address: 0x080194B8 + Address: 0x080194BC + Address: 0x080194C0 + Address: 0x080194C4 + Address: 0x080194C8 + Address: 0x080194CC + Address: 0x080194D0 + Address: 0x080194D4 + Address: 0x080194E0 + Address: 0x080194E4 + Address: 0x080194E8 + Address: 0x080194EC + Address: 0x080194F0 + Address: 0x080194F4 + Address: 0x080194F8 + Address: 0x080194FC + Address: 0x08019500 + Address: 0x08019504 + Address: 0x08019508 + Address: 0x0801950C + Address: 0x08019510 + Address: 0x08019514 + Address: 0x08019518 + Address: 0x0801951C + Address: 0x08019520 + Address: 0x08019524 + Address: 0x08019540 + Address: 0x08019544 + Address: 0x08019548 + Address: 0x0801954C + Address: 0x08019550 + Address: 0x08019554 + Address: 0x08019558 + Address: 0x0801955C + Address: 0x08019560 + Address: 0x08019564 + Address: 0x08019568 + Address: 0x0801956C + Address: 0x08019570 + Address: 0x08019574 + Address: 0x08019578 + Address: 0x0801957C + Address: 0x08019580 + Address: 0x08019584 + Address: 0x08019588 + Address: 0x080195A0 + Address: 0x080195A4 + Address: 0x080195A8 + Address: 0x080195AC + Address: 0x080195B0 + Address: 0x080195B4 + Address: 0x080195B8 + Address: 0x080195BC + Address: 0x080195C0 + Address: 0x080195C4 + Address: 0x080195C8 + Address: 0x080195CC + Address: 0x080195D0 + Address: 0x080195D4 + Address: 0x080195D8 + Address: 0x080195DC + Address: 0x080195E0 + Address: 0x080195E4 + Address: 0x080195E8 + Address: 0x08019600 + Address: 0x08019604 + Address: 0x08019608 + Address: 0x0801960C + Address: 0x08019610 + Address: 0x08019614 + Address: 0x08019618 + Address: 0x0801961C + Address: 0x08019620 + Address: 0x08019624 + Address: 0x08019628 + Address: 0x0801962C + Address: 0x08019630 + Address: 0x08019634 + Address: 0x08019638 + Address: 0x0801963C + Address: 0x08019640 + Address: 0x08019644 + Address: 0x08019648 + Address: 0x08019658 + Address: 0x0801965C + Address: 0x08019660 + Address: 0x08019664 + Address: 0x08019668 + Address: 0x0801966C + Address: 0x08019670 + Address: 0x08019674 + Address: 0x08019678 + Address: 0x0801967C + Address: 0x08019680 + Address: 0x08019684 + Address: 0x08019688 + Address: 0x0801968C + Address: 0x08019690 + Address: 0x08019694 + Address: 0x08019698 + Address: 0x0801969C + Address: 0x080196B4 + Address: 0x080196B8 + Address: 0x080196BC + Address: 0x080196C0 + Address: 0x080196C4 + Address: 0x080196C8 + Address: 0x080196CC + Address: 0x080196D0 + Address: 0x080196D4 + Address: 0x080196D8 + Address: 0x080196DC + Address: 0x080196E0 + Address: 0x080196E4 + Address: 0x080196E8 + Address: 0x080196EC + Address: 0x080196F0 + Address: 0x080196F4 + Address: 0x080196F8 + Address: 0x080196FC + Address: 0x08019714 + Address: 0x08019718 + Address: 0x0801971C + Address: 0x08019720 + Address: 0x08019724 + Address: 0x08019728 + Address: 0x0801972C + Address: 0x08019730 + Address: 0x08019734 + Address: 0x08019738 + Address: 0x0801973C + Address: 0x08019740 + Address: 0x08019744 + Address: 0x08019748 + Address: 0x0801974C + Address: 0x08019750 + Address: 0x08019754 + Address: 0x08019758 + Address: 0x0801975C + Address: 0x08019770 + Address: 0x08019774 + Address: 0x08019778 + Address: 0x0801977C + Address: 0x08019780 + Address: 0x08019784 + Address: 0x08019788 + Address: 0x0801978C + Address: 0x08019790 + Address: 0x08019794 + Address: 0x08019798 + Address: 0x0801979C + Address: 0x080197A0 + Address: 0x080197A4 + Address: 0x080197A8 + Address: 0x080197AC + Address: 0x080197B0 + Address: 0x080197B4 + Address: 0x080197B8 + Address: 0x080197CC + Address: 0x080197D0 + Address: 0x080197D4 + Address: 0x080197D8 + Address: 0x080197DC + Address: 0x080197E0 + Address: 0x080197E4 + Address: 0x080197E8 + Address: 0x080197EC + Address: 0x080197F0 + Address: 0x080197F4 + Address: 0x080197F8 + Address: 0x080197FC + Address: 0x08019800 + Address: 0x08019804 + Address: 0x08019808 + Address: 0x0801980C + Address: 0x08019810 + Address: 0x08019824 + Address: 0x08019828 + Address: 0x0801982C + Address: 0x08019830 + Address: 0x08019834 + Address: 0x08019838 + Address: 0x0801983C + Address: 0x08019840 + Address: 0x08019844 + Address: 0x08019848 + Address: 0x0801984C + Address: 0x08019850 + Address: 0x08019854 + Address: 0x08019858 + Address: 0x0801985C + Address: 0x08019860 + Address: 0x08019864 + Address: 0x08019868 + Address: 0x0801986C + Address: 0x08019884 + Address: 0x08019888 + Address: 0x0801988C + Address: 0x08019890 + Address: 0x08019894 + Address: 0x08019898 + Address: 0x0801989C + Address: 0x080198A0 + Address: 0x080198A4 + Address: 0x080198A8 + Address: 0x080198AC + Address: 0x080198B0 + Address: 0x080198B4 + Address: 0x080198B8 + Address: 0x080198BC + Address: 0x080198C0 + Address: 0x080198C4 + Address: 0x080198C8 + Address: 0x080198CC + Address: 0x080198E4 + Address: 0x080198E8 + Address: 0x080198EC + Address: 0x080198F0 + Address: 0x080198F4 + Address: 0x080198F8 + Address: 0x080198FC + Address: 0x08019900 + Address: 0x08019904 + Address: 0x08019908 + Address: 0x0801990C + Address: 0x08019910 + Address: 0x08019914 + Address: 0x08019918 + Address: 0x0801991C + Address: 0x08019920 + Address: 0x08019924 + Address: 0x08019928 + Address: 0x0801992C + Address: 0x0801993C + Address: 0x08019940 + Address: 0x08019944 + Address: 0x08019948 + Address: 0x0801994C + Address: 0x08019950 + Address: 0x08019954 + Address: 0x08019958 + Address: 0x0801995C + Address: 0x08019960 + Address: 0x08019964 + Address: 0x08019968 + Address: 0x0801996C + Address: 0x08019970 + Address: 0x08019974 + Address: 0x08019978 + Address: 0x0801997C + Address: 0x08019980 + Address: 0x08019994 + Address: 0x08019998 + Address: 0x0801999C + Address: 0x080199A0 + Address: 0x080199A4 + Address: 0x080199A8 + Address: 0x080199AC + Address: 0x080199B0 + Address: 0x080199B4 + Address: 0x080199B8 + Address: 0x080199BC + Address: 0x080199C0 + Address: 0x080199C4 + Address: 0x080199C8 + Address: 0x080199CC + Address: 0x080199D0 + Address: 0x080199D4 + Address: 0x080199D8 + Address: 0x080199DC + Address: 0x080199F8 + Address: 0x080199FC + Address: 0x08019A00 + Address: 0x08019A04 + Address: 0x08019A08 + Address: 0x08019A0C + Address: 0x08019A10 + Address: 0x08019A14 + Address: 0x08019A18 + Address: 0x08019A1C + Address: 0x08019A20 + Address: 0x08019A24 + Address: 0x08019A28 + Address: 0x08019A2C + Address: 0x08019A30 + Address: 0x08019A34 + Address: 0x08019A38 + Address: 0x08019A3C + Address: 0x08019A40 + Address: 0x08019A58 + Address: 0x08019A5C + Address: 0x08019A60 + Address: 0x08019A64 + Address: 0x08019A68 + Address: 0x08019A6C + Address: 0x08019A70 + Address: 0x08019A74 + Address: 0x08019A78 + Address: 0x08019A7C + Address: 0x08019A80 + Address: 0x08019A84 + Address: 0x08019A88 + Address: 0x08019A8C + Address: 0x08019A90 + Address: 0x08019A94 + Address: 0x08019A98 + Address: 0x08019A9C + Address: 0x08019AA0 + Address: 0x08019AB0 + Address: 0x08019AB4 + Address: 0x08019AB8 + Address: 0x08019ABC + Address: 0x08019AC0 + Address: 0x08019AC4 + Address: 0x08019AC8 + Address: 0x08019ACC + Address: 0x08019AD0 + Address: 0x08019AD4 + Address: 0x08019AD8 + Address: 0x08019ADC + Address: 0x08019AE0 + Address: 0x08019AE4 + Address: 0x08019AE8 + Address: 0x08019AEC + Address: 0x08019AF0 + Address: 0x08019AF4 + Address: 0x08019B0C + Address: 0x08019B10 + Address: 0x08019B14 + Address: 0x08019B18 + Address: 0x08019B1C + Address: 0x08019B20 + Address: 0x08019B24 + Address: 0x08019B28 + Address: 0x08019B2C + Address: 0x08019B30 + Address: 0x08019B34 + Address: 0x08019B38 + Address: 0x08019B3C + Address: 0x08019B40 + Address: 0x08019B44 + Address: 0x08019B48 + Address: 0x08019B4C + Address: 0x08019B50 + Address: 0x08019B54 + Address: 0x08019B6C + Address: 0x08019B70 + Address: 0x08019B74 + Address: 0x08019B78 + Address: 0x08019B7C + Address: 0x08019B80 + Address: 0x08019B84 + Address: 0x08019B88 + Address: 0x08019B8C + Address: 0x08019B90 + Address: 0x08019B94 + Address: 0x08019B98 + Address: 0x08019B9C + Address: 0x08019BA0 + Address: 0x08019BA4 + Address: 0x08019BA8 + Address: 0x08019BAC + Address: 0x08019BB0 + Address: 0x08019BB4 + Address: 0x08019BCC + Address: 0x08019BD0 + Address: 0x08019BD4 + Address: 0x08019BD8 + Address: 0x08019BDC + Address: 0x08019BE0 + Address: 0x08019BE4 + Address: 0x08019BE8 + Address: 0x08019BEC + Address: 0x08019BF0 + Address: 0x08019BF4 + Address: 0x08019BF8 + Address: 0x08019BFC + Address: 0x08019C00 + Address: 0x08019C04 + Address: 0x08019C08 + Address: 0x08019C0C + Address: 0x08019C10 + Address: 0x08019C14 + Address: 0x08019C24 + Address: 0x08019C28 + Address: 0x08019C2C + Address: 0x08019C30 + Address: 0x08019C34 + Address: 0x08019C38 + Address: 0x08019C3C + Address: 0x08019C40 + Address: 0x08019C44 + Address: 0x08019C48 + Address: 0x08019C4C + Address: 0x08019C50 + Address: 0x08019C54 + Address: 0x08019C58 + Address: 0x08019C5C + Address: 0x08019C60 + Address: 0x08019C64 + Address: 0x08019C68 + Address: 0x08019C80 + Address: 0x08019C84 + Address: 0x08019C88 + Address: 0x08019C8C + Address: 0x08019C90 + Address: 0x08019C94 + Address: 0x08019C98 + Address: 0x08019C9C + Address: 0x08019CA0 + Address: 0x08019CA4 + Address: 0x08019CA8 + Address: 0x08019CAC + Address: 0x08019CB0 + Address: 0x08019CB4 + Address: 0x08019CB8 + Address: 0x08019CBC + Address: 0x08019CC0 + Address: 0x08019CC4 + Address: 0x08019CC8 + Address: 0x08019CE0 + Address: 0x08019CE4 + Address: 0x08019CE8 + Address: 0x08019CEC + Address: 0x08019CF0 + Address: 0x08019CF4 + Address: 0x08019CF8 + Address: 0x08019CFC + Address: 0x08019D00 + Address: 0x08019D04 + Address: 0x08019D08 + Address: 0x08019D0C + Address: 0x08019D10 + Address: 0x08019D14 + Address: 0x08019D18 + Address: 0x08019D1C + Address: 0x08019D20 + Address: 0x08019D24 + Address: 0x08019D28 + Address: 0x08019D40 + Address: 0x08019D44 + Address: 0x08019D48 + Address: 0x08019D4C + Address: 0x08019D50 + Address: 0x08019D54 + Address: 0x08019D58 + Address: 0x08019D5C + Address: 0x08019D60 + Address: 0x08019D64 + Address: 0x08019D68 + Address: 0x08019D6C + Address: 0x08019D70 + Address: 0x08019D74 + Address: 0x08019D78 + Address: 0x08019D7C + Address: 0x08019D80 + Address: 0x08019D84 + Address: 0x08019D88 + Address: 0x08019D98 + Address: 0x08019D9C + Address: 0x08019DA0 + Address: 0x08019DA4 + Address: 0x08019DA8 + Address: 0x08019DAC + Address: 0x08019DB0 + Address: 0x08019DB4 + Address: 0x08019DB8 + Address: 0x08019DBC + Address: 0x08019DC0 + Address: 0x08019DC4 + Address: 0x08019DC8 + Address: 0x08019DCC + Address: 0x08019DD0 + Address: 0x08019DD4 + Address: 0x08019DD8 + Address: 0x08019DDC + Address: 0x08019DF4 + Address: 0x08019DF8 + Address: 0x08019DFC + Address: 0x08019E00 + Address: 0x08019E04 + Address: 0x08019E08 + Address: 0x08019E0C + Address: 0x08019E10 + Address: 0x08019E14 + Address: 0x08019E18 + Address: 0x08019E1C + Address: 0x08019E20 + Address: 0x08019E24 + Address: 0x08019E28 + Address: 0x08019E2C + Address: 0x08019E30 + Address: 0x08019E34 + Address: 0x08019E38 + Address: 0x08019E3C + Address: 0x08019E50 + Address: 0x08019E54 + Address: 0x08019E58 + Address: 0x08019E5C + Address: 0x08019E60 + Address: 0x08019E64 + Address: 0x08019E68 + Address: 0x08019E6C + Address: 0x08019E70 + Address: 0x08019E74 + Address: 0x08019E78 + Address: 0x08019E7C + Address: 0x08019E80 + Address: 0x08019E84 + Address: 0x08019E88 + Address: 0x08019E8C + Address: 0x08019E90 + Address: 0x08019E94 + Address: 0x08019E98 + Address: 0x08019EB4 + Address: 0x08019EB8 + Address: 0x08019EBC + Address: 0x08019EC0 + Address: 0x08019EC4 + Address: 0x08019EC8 + Address: 0x08019ECC + Address: 0x08019ED0 + Address: 0x08019ED4 + Address: 0x08019ED8 + Address: 0x08019EDC + Address: 0x08019EE0 + Address: 0x08019EE4 + Address: 0x08019EE8 + Address: 0x08019EEC + Address: 0x08019EF0 + Address: 0x08019EF4 + Address: 0x08019EF8 + Address: 0x08019EFC + Address: 0x08019F0C + Address: 0x08019F10 + Address: 0x08019F14 + Address: 0x08019F18 + Address: 0x08019F1C + Address: 0x08019F20 + Address: 0x08019F24 + Address: 0x08019F28 + Address: 0x08019F2C + Address: 0x08019F30 + Address: 0x08019F34 + Address: 0x08019F38 + Address: 0x08019F3C + Address: 0x08019F40 + Address: 0x08019F44 + Address: 0x08019F48 + Address: 0x08019F4C + Address: 0x08019F50 + Address: 0x08019F68 + Address: 0x08019F6C + Address: 0x08019F70 + Address: 0x08019F74 + Address: 0x08019F78 + Address: 0x08019F7C + Address: 0x08019F80 + Address: 0x08019F84 + Address: 0x08019F88 + Address: 0x08019F8C + Address: 0x08019F90 + Address: 0x08019F94 + Address: 0x08019F98 + Address: 0x08019F9C + Address: 0x08019FA0 + Address: 0x08019FA4 + Address: 0x08019FA8 + Address: 0x08019FAC + Address: 0x08019FB0 + Address: 0x08019FC4 + Address: 0x08019FC8 + Address: 0x08019FCC + Address: 0x08019FD0 + Address: 0x08019FD4 + Address: 0x08019FD8 + Address: 0x08019FDC + Address: 0x08019FE0 + Address: 0x08019FE4 + Address: 0x08019FE8 + Address: 0x08019FEC + Address: 0x08019FF0 + Address: 0x08019FF4 + Address: 0x08019FF8 + Address: 0x08019FFC + Address: 0x0801A000 + Address: 0x0801A004 + Address: 0x0801A008 + Address: 0x0801A00C + Address: 0x0801A028 + Address: 0x0801A02C + Address: 0x0801A030 + Address: 0x0801A034 + Address: 0x0801A038 + Address: 0x0801A03C + Address: 0x0801A040 + Address: 0x0801A044 + Address: 0x0801A048 + Address: 0x0801A04C + Address: 0x0801A050 + Address: 0x0801A054 + Address: 0x0801A058 + Address: 0x0801A05C + Address: 0x0801A060 + Address: 0x0801A064 + Address: 0x0801A068 + Address: 0x0801A06C + Address: 0x0801A070 + Address: 0x0801A080 + Address: 0x0801A084 + Address: 0x0801A088 + Address: 0x0801A08C + Address: 0x0801A090 + Address: 0x0801A094 + Address: 0x0801A098 + Address: 0x0801A09C + Address: 0x0801A0A0 + Address: 0x0801A0A4 + Address: 0x0801A0A8 + Address: 0x0801A0AC + Address: 0x0801A0B0 + Address: 0x0801A0B4 + Address: 0x0801A0B8 + Address: 0x0801A0BC + Address: 0x0801A0C0 + Address: 0x0801A0C4 + Address: 0x0801A0DC + Address: 0x0801A0E0 + Address: 0x0801A0E4 + Address: 0x0801A0E8 + Address: 0x0801A0EC + Address: 0x0801A0F0 + Address: 0x0801A0F4 + Address: 0x0801A0F8 + Address: 0x0801A0FC + Address: 0x0801A100 + Address: 0x0801A104 + Address: 0x0801A108 + Address: 0x0801A10C + Address: 0x0801A110 + Address: 0x0801A114 + Address: 0x0801A118 + Address: 0x0801A11C + Address: 0x0801A120 + Address: 0x0801A124 + Address: 0x0801A13C + Address: 0x0801A140 + Address: 0x0801A144 + Address: 0x0801A148 + Address: 0x0801A14C + Address: 0x0801A150 + Address: 0x0801A154 + Address: 0x0801A158 + Address: 0x0801A15C + Address: 0x0801A160 + Address: 0x0801A164 + Address: 0x0801A168 + Address: 0x0801A16C + Address: 0x0801A170 + Address: 0x0801A174 + Address: 0x0801A178 + Address: 0x0801A17C + Address: 0x0801A180 + Address: 0x0801A184 + Address: 0x0801A19C + Address: 0x0801A1A0 + Address: 0x0801A1A4 + Address: 0x0801A1A8 + Address: 0x0801A1AC + Address: 0x0801A1B0 + Address: 0x0801A1B4 + Address: 0x0801A1B8 + Address: 0x0801A1BC + Address: 0x0801A1C0 + Address: 0x0801A1C4 + Address: 0x0801A1C8 + Address: 0x0801A1CC + Address: 0x0801A1D0 + Address: 0x0801A1D4 + Address: 0x0801A1D8 + Address: 0x0801A1DC + Address: 0x0801A1E0 + Address: 0x0801A1E4 + Address: 0x0801A1F4 + Address: 0x0801A1F8 + Address: 0x0801A1FC + Address: 0x0801A200 + Address: 0x0801A204 + Address: 0x0801A208 + Address: 0x0801A20C + Address: 0x0801A210 + Address: 0x0801A214 + Address: 0x0801A218 + Address: 0x0801A21C + Address: 0x0801A220 + Address: 0x0801A224 + Address: 0x0801A228 + Address: 0x0801A22C + Address: 0x0801A230 + Address: 0x0801A234 + Address: 0x0801A238 + Address: 0x0801A250 + Address: 0x0801A254 + Address: 0x0801A258 + Address: 0x0801A25C + Address: 0x0801A260 + Address: 0x0801A264 + Address: 0x0801A268 + Address: 0x0801A26C + Address: 0x0801A270 + Address: 0x0801A274 + Address: 0x0801A278 + Address: 0x0801A27C + Address: 0x0801A280 + Address: 0x0801A284 + Address: 0x0801A288 + Address: 0x0801A28C + Address: 0x0801A290 + Address: 0x0801A294 + Address: 0x0801A298 + Address: 0x0801A2AC + Address: 0x0801A2B0 + Address: 0x0801A2B4 + Address: 0x0801A2B8 + Address: 0x0801A2BC + Address: 0x0801A2C0 + Address: 0x0801A2C4 + Address: 0x0801A2C8 + Address: 0x0801A2CC + Address: 0x0801A2D0 + Address: 0x0801A2D4 + Address: 0x0801A2D8 + Address: 0x0801A2DC + Address: 0x0801A2E0 + Address: 0x0801A2E4 + Address: 0x0801A2E8 + Address: 0x0801A2EC + Address: 0x0801A2F0 + Address: 0x0801A2F4 + Address: 0x0801A30C + Address: 0x0801A310 + Address: 0x0801A314 + Address: 0x0801A318 + Address: 0x0801A31C + Address: 0x0801A320 + Address: 0x0801A324 + Address: 0x0801A328 + Address: 0x0801A32C + Address: 0x0801A330 + Address: 0x0801A334 + Address: 0x0801A338 + Address: 0x0801A33C + Address: 0x0801A340 + Address: 0x0801A344 + Address: 0x0801A348 + Address: 0x0801A34C + Address: 0x0801A350 + Address: 0x0801A354 + Address: 0x0801A36C + Address: 0x0801A370 + Address: 0x0801A374 + Address: 0x0801A378 + Address: 0x0801A37C + Address: 0x0801A380 + Address: 0x0801A384 + Address: 0x0801A388 + Address: 0x0801A38C + Address: 0x0801A390 + Address: 0x0801A394 + Address: 0x0801A398 + Address: 0x0801A39C + Address: 0x0801A3A0 + Address: 0x0801A3A4 + Address: 0x0801A3A8 + Address: 0x0801A3AC + Address: 0x0801A3B0 + Address: 0x0801A3B4 + Address: 0x0801A3C0 + Address: 0x0801A3C4 + Address: 0x0801A3C8 + Address: 0x0801A3CC + Address: 0x0801A3D0 + Address: 0x0801A3D4 + Address: 0x0801A3D8 + Address: 0x0801A3DC + Address: 0x0801A3E0 + Address: 0x0801A3E4 + Address: 0x0801A3E8 + Address: 0x0801A3EC + Address: 0x0801A3F0 + Address: 0x0801A3F4 + Address: 0x0801A3F8 + Address: 0x0801A3FC + Address: 0x0801A400 + Address: 0x0801A404 + Address: 0x0801A424 + Address: 0x0801A428 + Address: 0x0801A42C + Address: 0x0801A430 + Address: 0x0801A434 + Address: 0x0801A438 + Address: 0x0801A43C + Address: 0x0801A440 + Address: 0x0801A444 + Address: 0x0801A448 + Address: 0x0801A44C + Address: 0x0801A450 + Address: 0x0801A454 + Address: 0x0801A458 + Address: 0x0801A45C + Address: 0x0801A460 + Address: 0x0801A464 + Address: 0x0801A468 + Address: 0x0801A46C + Address: 0x0801A470 + Address: 0x0801A47C + Address: 0x0801A480 + Address: 0x0801A484 + Address: 0x0801A488 + Address: 0x0801A48C + Address: 0x0801A490 + Address: 0x0801A494 + Address: 0x0801A498 + Address: 0x0801A49C + Address: 0x0801A4A0 + Address: 0x0801A4A4 + Address: 0x0801A4A8 + Address: 0x0801A4AC + Address: 0x0801A4B0 + Address: 0x0801A4B4 + Address: 0x0801A4B8 + Address: 0x0801A4BC + Address: 0x0801A4C0 + Address: 0x0801A4E0 + Address: 0x0801A4E4 + Address: 0x0801A4E8 + Address: 0x0801A4EC + Address: 0x0801A4F0 + Address: 0x0801A4F4 + Address: 0x0801A4F8 + Address: 0x0801A4FC + Address: 0x0801A500 + Address: 0x0801A504 + Address: 0x0801A508 + Address: 0x0801A50C + Address: 0x0801A510 + Address: 0x0801A514 + Address: 0x0801A518 + Address: 0x0801A51C + Address: 0x0801A520 + Address: 0x0801A524 + Address: 0x0801A528 + Address: 0x0801A52C + Address: 0x0801A530 + Address: 0x0801A534 + Address: 0x0801A538 + Address: 0x0801A53C + Address: 0x0801A540 + Address: 0x0801A544 + Address: 0x0801A548 + Address: 0x0801A54C + Address: 0x0801A550 + Address: 0x0801A554 + Address: 0x0801A558 + Address: 0x0801A55C + Address: 0x0801A560 + Address: 0x0801A564 + Address: 0x0801A568 + Address: 0x0801A56C + Address: 0x0801A570 + Address: 0x0801A59C + Address: 0x0801A5A0 + Address: 0x0801A5A4 + Address: 0x0801A5A8 + Address: 0x0801A5AC + Address: 0x0801A5B0 + Address: 0x0801A5B4 + Address: 0x0801A5B8 + Address: 0x0801A5BC + Address: 0x0801A5C0 + Address: 0x0801A5C4 + Address: 0x0801A5C8 + Address: 0x0801A5CC + Address: 0x0801A5D0 + Address: 0x0801A5D4 + Address: 0x0801A5D8 + Address: 0x0801A5DC + Address: 0x0801A5E0 + Address: 0x0801A5E4 + Address: 0x0801A5E8 + Address: 0x0801A5EC + Address: 0x0801A5F0 + Address: 0x0801A5F4 + Address: 0x0801A5F8 + Address: 0x0801A5FC + Address: 0x0801A600 + Address: 0x0801A604 + Address: 0x0801A608 + Address: 0x0801A60C + Address: 0x0801A610 + Address: 0x0801A614 + Address: 0x0801A618 + Address: 0x0801A61C + Address: 0x0801A620 + Address: 0x0801A624 + Address: 0x0801A628 + Address: 0x0801A62C + Address: 0x0801A630 + Address: 0x0801A654 + Address: 0x0801A658 + Address: 0x0801A65C + Address: 0x0801A660 + Address: 0x0801A664 + Address: 0x0801A668 + Address: 0x0801A66C + Address: 0x0801A670 + Address: 0x0801A674 + Address: 0x0801A678 + Address: 0x0801A67C + Address: 0x0801A680 + Address: 0x0801A684 + Address: 0x0801A688 + Address: 0x0801A68C + Address: 0x0801A690 + Address: 0x0801A694 + Address: 0x0801A698 + Address: 0x0801A69C + Address: 0x0801A6A0 + Address: 0x0801A6A4 + Address: 0x0801A6A8 + Address: 0x0801A6AC + Address: 0x0801A6B0 + Address: 0x0801A6B4 + Address: 0x0801A6B8 + Address: 0x0801A6BC + Address: 0x0801A6C0 + Address: 0x0801A6C4 + Address: 0x0801A6C8 + Address: 0x0801A6CC + Address: 0x0801A6D0 + Address: 0x0801A6D4 + Address: 0x0801A6D8 + Address: 0x0801A6DC + Address: 0x0801A6E0 + Address: 0x0801A6E4 + Address: 0x0801A710 + Address: 0x0801A714 + Address: 0x0801A718 + Address: 0x0801A71C + Address: 0x0801A720 + Address: 0x0801A724 + Address: 0x0801A728 + Address: 0x0801A72C + Address: 0x0801A730 + Address: 0x0801A734 + Address: 0x0801A738 + Address: 0x0801A73C + Address: 0x0801A740 + Address: 0x0801A744 + Address: 0x0801A748 + Address: 0x0801A74C + Address: 0x0801A750 + Address: 0x0801A754 + Address: 0x0801A758 + Address: 0x0801A75C + Address: 0x0801A760 + Address: 0x0801A768 + Address: 0x0801A76C + Address: 0x0801A770 + Address: 0x0801A774 + Address: 0x0801A778 + Address: 0x0801A77C + Address: 0x0801A780 + Address: 0x0801A784 + Address: 0x0801A788 + Address: 0x0801A78C + Address: 0x0801A790 + Address: 0x0801A794 + Address: 0x0801A798 + Address: 0x0801A79C + Address: 0x0801A7A0 + Address: 0x0801A7A4 + Address: 0x0801A7A8 + Address: 0x0801A7D0 + Address: 0x0801A7D4 + Address: 0x0801A7D8 + Address: 0x0801A7DC + Address: 0x0801A7E0 + Address: 0x0801A7E4 + Address: 0x0801A7E8 + Address: 0x0801A7EC + Address: 0x0801A7F0 + Address: 0x0801A7F4 + Address: 0x0801A7F8 + Address: 0x0801A7FC + Address: 0x0801A800 + Address: 0x0801A804 + Address: 0x0801A808 + Address: 0x0801A80C + Address: 0x0801A810 + Address: 0x0801A814 + Address: 0x0801A818 + Address: 0x0801A81C + Address: 0x0801A820 + Address: 0x0801A824 + Address: 0x0801A828 + Address: 0x0801A82C + Address: 0x0801A830 + Address: 0x0801A834 + Address: 0x0801A838 + Address: 0x0801A83C + Address: 0x0801A840 + Address: 0x0801A844 + Address: 0x0801A848 + Address: 0x0801A84C + Address: 0x0801A850 + Address: 0x0801A854 + Address: 0x0801A858 + Address: 0x0801A85C + Address: 0x0801A860 + Address: 0x0801A880 + Address: 0x0801A884 + Address: 0x0801A888 + Address: 0x0801A88C + Address: 0x0801A890 + Address: 0x0801A894 + Address: 0x0801A898 + Address: 0x0801A89C + Address: 0x0801A8A0 + Address: 0x0801A8A4 + Address: 0x0801A8A8 + Address: 0x0801A8AC + Address: 0x0801A8B0 + Address: 0x0801A8B4 + Address: 0x0801A8B8 + Address: 0x0801A8BC + Address: 0x0801A8C0 + Address: 0x0801A8C4 + Address: 0x0801A8C8 + Address: 0x0801A8CC + Address: 0x0801A8E0 + Address: 0x0801A8E4 + Address: 0x0801A8E8 + Address: 0x0801A8EC + Address: 0x0801A8F0 + Address: 0x0801A8F4 + Address: 0x0801A8F8 + Address: 0x0801A8FC + Address: 0x0801A900 + Address: 0x0801A904 + Address: 0x0801A908 + Address: 0x0801A90C + Address: 0x0801A910 + Address: 0x0801A914 + Address: 0x0801A918 + Address: 0x0801A91C + Address: 0x0801A920 + Address: 0x0801A924 + Address: 0x0801A944 + Address: 0x0801A948 + Address: 0x0801A94C + Address: 0x0801A950 + Address: 0x0801A954 + Address: 0x0801A958 + Address: 0x0801A95C + Address: 0x0801A960 + Address: 0x0801A964 + Address: 0x0801A968 + Address: 0x0801A96C + Address: 0x0801A970 + Address: 0x0801A974 + Address: 0x0801A978 + Address: 0x0801A97C + Address: 0x0801A980 + Address: 0x0801A984 + Address: 0x0801A988 + Address: 0x0801A98C + Address: 0x0801A990 + Address: 0x0801A998 + Address: 0x0801A99C + Address: 0x0801A9A0 + Address: 0x0801A9A4 + Address: 0x0801A9A8 + Address: 0x0801A9AC + Address: 0x0801A9B0 + Address: 0x0801A9B4 + Address: 0x0801A9B8 + Address: 0x0801A9BC + Address: 0x0801A9C0 + Address: 0x0801A9C4 + Address: 0x0801A9C8 + Address: 0x0801A9CC + Address: 0x0801A9D0 + Address: 0x0801A9D4 + Address: 0x0801A9D8 + Address: 0x0801A9F4 + Address: 0x0801A9F8 + Address: 0x0801A9FC + Address: 0x0801AA00 + Address: 0x0801AA04 + Address: 0x0801AA08 + Address: 0x0801AA0C + Address: 0x0801AA10 + Address: 0x0801AA14 + Address: 0x0801AA18 + Address: 0x0801AA1C + Address: 0x0801AA20 + Address: 0x0801AA24 + Address: 0x0801AA28 + Address: 0x0801AA2C + Address: 0x0801AA30 + Address: 0x0801AA34 + Address: 0x0801AA38 + Address: 0x0801AA3C + Address: 0x0801AA40 + Address: 0x0801AA50 + Address: 0x0801AA54 + Address: 0x0801AA58 + Address: 0x0801AA5C + Address: 0x0801AA60 + Address: 0x0801AA64 + Address: 0x0801AA68 + Address: 0x0801AA6C + Address: 0x0801AA70 + Address: 0x0801AA74 + Address: 0x0801AA78 + Address: 0x0801AA7C + Address: 0x0801AA80 + Address: 0x0801AA84 + Address: 0x0801AA88 + Address: 0x0801AA8C + Address: 0x0801AA90 + Address: 0x0801AA94 + Address: 0x0801AAB4 + Address: 0x0801AAB8 + Address: 0x0801AABC + Address: 0x0801AAC0 + Address: 0x0801AAC4 + Address: 0x0801AAC8 + Address: 0x0801AACC + Address: 0x0801AAD0 + Address: 0x0801AAD4 + Address: 0x0801AAD8 + Address: 0x0801AADC + Address: 0x0801AAE0 + Address: 0x0801AAE4 + Address: 0x0801AAE8 + Address: 0x0801AAEC + Address: 0x0801AAF0 + Address: 0x0801AAF4 + Address: 0x0801AAF8 + Address: 0x0801AAFC + Address: 0x0801AB00 + Address: 0x0801AB0C + Address: 0x0801AB10 + Address: 0x0801AB14 + Address: 0x0801AB18 + Address: 0x0801AB1C + Address: 0x0801AB20 + Address: 0x0801AB24 + Address: 0x0801AB28 + Address: 0x0801AB2C + Address: 0x0801AB30 + Address: 0x0801AB34 + Address: 0x0801AB38 + Address: 0x0801AB3C + Address: 0x0801AB40 + Address: 0x0801AB44 + Address: 0x0801AB48 + Address: 0x0801AB4C + Address: 0x0801AB50 + Address: 0x0801AB68 + Address: 0x0801AB6C + Address: 0x0801AB70 + Address: 0x0801AB74 + Address: 0x0801AB78 + Address: 0x0801AB7C + Address: 0x0801AB80 + Address: 0x0801AB84 + Address: 0x0801AB88 + Address: 0x0801AB8C + Address: 0x0801AB90 + Address: 0x0801AB94 + Address: 0x0801AB98 + Address: 0x0801AB9C + Address: 0x0801ABA0 + Address: 0x0801ABA4 + Address: 0x0801ABA8 + Address: 0x0801ABAC + Address: 0x0801ABB0 + Address: 0x0801ABC8 + Address: 0x0801ABCC + Address: 0x0801ABD0 + Address: 0x0801ABD4 + Address: 0x0801ABD8 + Address: 0x0801ABDC + Address: 0x0801ABE0 + Address: 0x0801ABE4 + Address: 0x0801ABE8 + Address: 0x0801ABEC + Address: 0x0801ABF0 + Address: 0x0801ABF4 + Address: 0x0801ABF8 + Address: 0x0801ABFC + Address: 0x0801AC00 + Address: 0x0801AC04 + Address: 0x0801AC08 + Address: 0x0801AC0C + Address: 0x0801AC10 + Address: 0x0801AC28 + Address: 0x0801AC2C + Address: 0x0801AC30 + Address: 0x0801AC34 + Address: 0x0801AC38 + Address: 0x0801AC3C + Address: 0x0801AC40 + Address: 0x0801AC44 + Address: 0x0801AC48 + Address: 0x0801AC4C + Address: 0x0801AC50 + Address: 0x0801AC54 + Address: 0x0801AC58 + Address: 0x0801AC5C + Address: 0x0801AC60 + Address: 0x0801AC64 + Address: 0x0801AC68 + Address: 0x0801AC6C + Address: 0x0801AC70 + Address: 0x0801AC84 + Address: 0x0801AC88 + Address: 0x0801AC8C + Address: 0x0801AC90 + Address: 0x0801AC94 + Address: 0x0801AC98 + Address: 0x0801AC9C + Address: 0x0801ACA0 + Address: 0x0801ACA4 + Address: 0x0801ACA8 + Address: 0x0801ACAC + Address: 0x0801ACB0 + Address: 0x0801ACB4 + Address: 0x0801ACB8 + Address: 0x0801ACBC + Address: 0x0801ACC0 + Address: 0x0801ACC4 + Address: 0x0801ACC8 + Address: 0x0801ACE0 + Address: 0x0801ACE4 + Address: 0x0801ACE8 + Address: 0x0801ACEC + Address: 0x0801ACF0 + Address: 0x0801ACF4 + Address: 0x0801ACF8 + Address: 0x0801ACFC + Address: 0x0801AD00 + Address: 0x0801AD04 + Address: 0x0801AD08 + Address: 0x0801AD0C + Address: 0x0801AD10 + Address: 0x0801AD14 + Address: 0x0801AD18 + Address: 0x0801AD1C + Address: 0x0801AD20 + Address: 0x0801AD24 + Address: 0x0801AD28 + Address: 0x0801AD40 + Address: 0x0801AD44 + Address: 0x0801AD48 + Address: 0x0801AD4C + Address: 0x0801AD50 + Address: 0x0801AD54 + Address: 0x0801AD58 + Address: 0x0801AD5C + Address: 0x0801AD60 + Address: 0x0801AD64 + Address: 0x0801AD68 + Address: 0x0801AD6C + Address: 0x0801AD70 + Address: 0x0801AD74 + Address: 0x0801AD78 + Address: 0x0801AD7C + Address: 0x0801AD80 + Address: 0x0801AD84 + Address: 0x0801AD88 + Address: 0x0801ADA0 + Address: 0x0801ADA4 + Address: 0x0801ADA8 + Address: 0x0801ADAC + Address: 0x0801ADB0 + Address: 0x0801ADB4 + Address: 0x0801ADB8 + Address: 0x0801ADBC + Address: 0x0801ADC0 + Address: 0x0801ADC4 + Address: 0x0801ADC8 + Address: 0x0801ADCC + Address: 0x0801ADD0 + Address: 0x0801ADD4 + Address: 0x0801ADD8 + Address: 0x0801ADDC + Address: 0x0801ADE0 + Address: 0x0801ADE4 + Address: 0x0801ADE8 + Address: 0x0801ADF8 + Address: 0x0801ADFC + Address: 0x0801AE00 + Address: 0x0801AE04 + Address: 0x0801AE08 + Address: 0x0801AE0C + Address: 0x0801AE10 + Address: 0x0801AE14 + Address: 0x0801AE18 + Address: 0x0801AE1C + Address: 0x0801AE20 + Address: 0x0801AE24 + Address: 0x0801AE28 + Address: 0x0801AE2C + Address: 0x0801AE30 + Address: 0x0801AE34 + Address: 0x0801AE38 + Address: 0x0801AE3C + Address: 0x0801AE54 + Address: 0x0801AE58 + Address: 0x0801AE5C + Address: 0x0801AE60 + Address: 0x0801AE64 + Address: 0x0801AE68 + Address: 0x0801AE6C + Address: 0x0801AE70 + Address: 0x0801AE74 + Address: 0x0801AE78 + Address: 0x0801AE7C + Address: 0x0801AE80 + Address: 0x0801AE84 + Address: 0x0801AE88 + Address: 0x0801AE8C + Address: 0x0801AE90 + Address: 0x0801AE94 + Address: 0x0801AE98 + Address: 0x0801AE9C + Address: 0x0801AEB0 + Address: 0x0801AEB4 + Address: 0x0801AEB8 + Address: 0x0801AEBC + Address: 0x0801AEC0 + Address: 0x0801AEC4 + Address: 0x0801AEC8 + Address: 0x0801AECC + Address: 0x0801AED0 + Address: 0x0801AED4 + Address: 0x0801AED8 + Address: 0x0801AEDC + Address: 0x0801AEE0 + Address: 0x0801AEE4 + Address: 0x0801AEE8 + Address: 0x0801AEEC + Address: 0x0801AEF0 + Address: 0x0801AEF4 + Address: 0x0801AEF8 + Address: 0x0801AF10 + Address: 0x0801AF14 + Address: 0x0801AF18 + Address: 0x0801AF1C + Address: 0x0801AF20 + Address: 0x0801AF24 + Address: 0x0801AF28 + Address: 0x0801AF2C + Address: 0x0801AF30 + Address: 0x0801AF34 + Address: 0x0801AF38 + Address: 0x0801AF3C + Address: 0x0801AF40 + Address: 0x0801AF44 + Address: 0x0801AF48 + Address: 0x0801AF4C + Address: 0x0801AF50 + Address: 0x0801AF54 + Address: 0x0801AF58 + Address: 0x0801AF6C + Address: 0x0801AF70 + Address: 0x0801AF74 + Address: 0x0801AF78 + Address: 0x0801AF7C + Address: 0x0801AF80 + Address: 0x0801AF84 + Address: 0x0801AF88 + Address: 0x0801AF8C + Address: 0x0801AF90 + Address: 0x0801AF94 + Address: 0x0801AF98 + Address: 0x0801AF9C + Address: 0x0801AFA0 + Address: 0x0801AFA4 + Address: 0x0801AFA8 + Address: 0x0801AFAC + Address: 0x0801AFB0 + Address: 0x0801AFB4 + Address: 0x0801AFC4 + Address: 0x0801AFC8 + Address: 0x0801AFCC + Address: 0x0801AFD0 + Address: 0x0801AFD4 + Address: 0x0801AFD8 + Address: 0x0801AFDC + Address: 0x0801AFE0 + Address: 0x0801AFE4 + Address: 0x0801AFE8 + Address: 0x0801AFEC + Address: 0x0801AFF0 + Address: 0x0801AFF4 + Address: 0x0801AFF8 + Address: 0x0801AFFC + Address: 0x0801B000 + Address: 0x0801B004 + Address: 0x0801B008 + Address: 0x0801B024 + Address: 0x0801B028 + Address: 0x0801B02C + Address: 0x0801B030 + Address: 0x0801B034 + Address: 0x0801B038 + Address: 0x0801B03C + Address: 0x0801B040 + Address: 0x0801B044 + Address: 0x0801B048 + Address: 0x0801B04C + Address: 0x0801B050 + Address: 0x0801B054 + Address: 0x0801B058 + Address: 0x0801B05C + Address: 0x0801B060 + Address: 0x0801B064 + Address: 0x0801B068 + Address: 0x0801B06C + Address: 0x0801B070 + Address: 0x0801B080 + Address: 0x0801B084 + Address: 0x0801B088 + Address: 0x0801B08C + Address: 0x0801B090 + Address: 0x0801B094 + Address: 0x0801B098 + Address: 0x0801B09C + Address: 0x0801B0A0 + Address: 0x0801B0A4 + Address: 0x0801B0A8 + Address: 0x0801B0AC + Address: 0x0801B0B0 + Address: 0x0801B0B4 + Address: 0x0801B0B8 + Address: 0x0801B0BC + Address: 0x0801B0C0 + Address: 0x0801B0C4 + Address: 0x0801B0E4 + Address: 0x0801B0E8 + Address: 0x0801B0EC + Address: 0x0801B0F0 + Address: 0x0801B0F4 + Address: 0x0801B0F8 + Address: 0x0801B0FC + Address: 0x0801B100 + Address: 0x0801B104 + Address: 0x0801B108 + Address: 0x0801B10C + Address: 0x0801B110 + Address: 0x0801B114 + Address: 0x0801B118 + Address: 0x0801B11C + Address: 0x0801B120 + Address: 0x0801B124 + Address: 0x0801B128 + Address: 0x0801B12C + Address: 0x0801B130 + Address: 0x0801B138 + Address: 0x0801B13C + Address: 0x0801B140 + Address: 0x0801B144 + Address: 0x0801B148 + Address: 0x0801B14C + Address: 0x0801B150 + Address: 0x0801B154 + Address: 0x0801B158 + Address: 0x0801B15C + Address: 0x0801B160 + Address: 0x0801B164 + Address: 0x0801B168 + Address: 0x0801B16C + Address: 0x0801B170 + Address: 0x0801B174 + Address: 0x0801B178 + Address: 0x0801B19C + Address: 0x0801B1A0 + Address: 0x0801B1A4 + Address: 0x0801B1A8 + Address: 0x0801B1AC + Address: 0x0801B1B0 + Address: 0x0801B1B4 + Address: 0x0801B1B8 + Address: 0x0801B1BC + Address: 0x0801B1C0 + Address: 0x0801B1C4 + Address: 0x0801B1C8 + Address: 0x0801B1CC + Address: 0x0801B1D0 + Address: 0x0801B1D4 + Address: 0x0801B1D8 + Address: 0x0801B1DC + Address: 0x0801B1E0 + Address: 0x0801B1E4 + Address: 0x0801B1E8 + Address: 0x0801B1EC + Address: 0x0801B1F8 + Address: 0x0801B1FC + Address: 0x0801B200 + Address: 0x0801B204 + Address: 0x0801B208 + Address: 0x0801B20C + Address: 0x0801B210 + Address: 0x0801B214 + Address: 0x0801B218 + Address: 0x0801B21C + Address: 0x0801B220 + Address: 0x0801B224 + Address: 0x0801B228 + Address: 0x0801B22C + Address: 0x0801B230 + Address: 0x0801B234 + Address: 0x0801B238 + Address: 0x0801B23C + Address: 0x0801B25C + Address: 0x0801B260 + Address: 0x0801B264 + Address: 0x0801B268 + Address: 0x0801B26C + Address: 0x0801B270 + Address: 0x0801B274 + Address: 0x0801B278 + Address: 0x0801B27C + Address: 0x0801B280 + Address: 0x0801B284 + Address: 0x0801B288 + Address: 0x0801B28C + Address: 0x0801B290 + Address: 0x0801B294 + Address: 0x0801B298 + Address: 0x0801B29C + Address: 0x0801B2A0 + Address: 0x0801B2A4 + Address: 0x0801B2A8 + Address: 0x0801B2B0 + Address: 0x0801B2B4 + Address: 0x0801B2B8 + Address: 0x0801B2BC + Address: 0x0801B2C0 + Address: 0x0801B2C4 + Address: 0x0801B2C8 + Address: 0x0801B2CC + Address: 0x0801B2D0 + Address: 0x0801B2D4 + Address: 0x0801B2D8 + Address: 0x0801B2DC + Address: 0x0801B2E0 + Address: 0x0801B2E4 + Address: 0x0801B2E8 + Address: 0x0801B2EC + Address: 0x0801B2F0 + Address: 0x0801B318 + Address: 0x0801B31C + Address: 0x0801B320 + Address: 0x0801B324 + Address: 0x0801B328 + Address: 0x0801B32C + Address: 0x0801B330 + Address: 0x0801B334 + Address: 0x0801B338 + Address: 0x0801B33C + Address: 0x0801B340 + Address: 0x0801B344 + Address: 0x0801B348 + Address: 0x0801B34C + Address: 0x0801B350 + Address: 0x0801B354 + Address: 0x0801B358 + Address: 0x0801B35C + Address: 0x0801B360 + Address: 0x0801B364 + Address: 0x0801B368 + Address: 0x0801B36C + Address: 0x0801B370 + Address: 0x0801B374 + Address: 0x0801B378 + Address: 0x0801B37C + Address: 0x0801B380 + Address: 0x0801B384 + Address: 0x0801B388 + Address: 0x0801B38C + Address: 0x0801B390 + Address: 0x0801B394 + Address: 0x0801B398 + Address: 0x0801B39C + Address: 0x0801B3A0 + Address: 0x0801B3A4 + Address: 0x0801B3A8 + Address: 0x0801B3AC + Address: 0x0801B3D4 + Address: 0x0801B3D8 + Address: 0x0801B3DC + Address: 0x0801B3E0 + Address: 0x0801B3E4 + Address: 0x0801B3E8 + Address: 0x0801B3EC + Address: 0x0801B3F0 + Address: 0x0801B3F4 + Address: 0x0801B3F8 + Address: 0x0801B3FC + Address: 0x0801B400 + Address: 0x0801B404 + Address: 0x0801B408 + Address: 0x0801B40C + Address: 0x0801B410 + Address: 0x0801B414 + Address: 0x0801B418 + Address: 0x0801B41C + Address: 0x0801B420 + Address: 0x0801B424 + Address: 0x0801B428 + Address: 0x0801B42C + Address: 0x0801B430 + Address: 0x0801B434 + Address: 0x0801B438 + Address: 0x0801B43C + Address: 0x0801B440 + Address: 0x0801B444 + Address: 0x0801B448 + Address: 0x0801B44C + Address: 0x0801B450 + Address: 0x0801B454 + Address: 0x0801B458 + Address: 0x0801B45C + Address: 0x0801B460 + Address: 0x0801B464 + Address: 0x0801B48C + Address: 0x0801B490 + Address: 0x0801B494 + Address: 0x0801B498 + Address: 0x0801B49C + Address: 0x0801B4A0 + Address: 0x0801B4A4 + Address: 0x0801B4A8 + Address: 0x0801B4AC + Address: 0x0801B4B0 + Address: 0x0801B4B4 + Address: 0x0801B4B8 + Address: 0x0801B4BC + Address: 0x0801B4C0 + Address: 0x0801B4C4 + Address: 0x0801B4C8 + Address: 0x0801B4CC + Address: 0x0801B4D0 + Address: 0x0801B4D4 + Address: 0x0801B4D8 + Address: 0x0801B4DC + Address: 0x0801B4E0 + Address: 0x0801B4E4 + Address: 0x0801B4E8 + Address: 0x0801B4EC + Address: 0x0801B4F0 + Address: 0x0801B4F4 + Address: 0x0801B4F8 + Address: 0x0801B4FC + Address: 0x0801B500 + Address: 0x0801B504 + Address: 0x0801B508 + Address: 0x0801B50C + Address: 0x0801B510 + Address: 0x0801B514 + Address: 0x0801B518 + Address: 0x0801B51C + Address: 0x0801B520 + Address: 0x0801B548 + Address: 0x0801B54C + Address: 0x0801B550 + Address: 0x0801B554 + Address: 0x0801B558 + Address: 0x0801B55C + Address: 0x0801B560 + Address: 0x0801B564 + Address: 0x0801B568 + Address: 0x0801B56C + Address: 0x0801B570 + Address: 0x0801B574 + Address: 0x0801B578 + Address: 0x0801B57C + Address: 0x0801B580 + Address: 0x0801B584 + Address: 0x0801B588 + Address: 0x0801B58C + Address: 0x0801B590 + Address: 0x0801B594 + Address: 0x0801B598 + Address: 0x0801B59C + Address: 0x0801B5A0 + Address: 0x0801B5A4 + Address: 0x0801B5A8 + Address: 0x0801B5AC + Address: 0x0801B5B0 + Address: 0x0801B5B4 + Address: 0x0801B5B8 + Address: 0x0801B5BC + Address: 0x0801B5C0 + Address: 0x0801B5C4 + Address: 0x0801B5C8 + Address: 0x0801B5CC + Address: 0x0801B5D0 + Address: 0x0801B5D4 + Address: 0x0801B5D8 + Address: 0x0801B5FC + Address: 0x0801B600 + Address: 0x0801B604 + Address: 0x0801B608 + Address: 0x0801B60C + Address: 0x0801B610 + Address: 0x0801B614 + Address: 0x0801B618 + Address: 0x0801B61C + Address: 0x0801B620 + Address: 0x0801B624 + Address: 0x0801B628 + Address: 0x0801B62C + Address: 0x0801B630 + Address: 0x0801B634 + Address: 0x0801B638 + Address: 0x0801B63C + Address: 0x0801B640 + Address: 0x0801B644 + Address: 0x0801B648 + Address: 0x0801B654 + Address: 0x0801B658 + Address: 0x0801B65C + Address: 0x0801B660 + Address: 0x0801B664 + Address: 0x0801B668 + Address: 0x0801B66C + Address: 0x0801B670 + Address: 0x0801B674 + Address: 0x0801B678 + Address: 0x0801B67C + Address: 0x0801B680 + Address: 0x0801B684 + Address: 0x0801B688 + Address: 0x0801B68C + Address: 0x0801B690 + Address: 0x0801B694 + Address: 0x0801B698 + Address: 0x0801B6B8 + Address: 0x0801B6BC + Address: 0x0801B6C0 + Address: 0x0801B6C4 + Address: 0x0801B6C8 + Address: 0x0801B6CC + Address: 0x0801B6D0 + Address: 0x0801B6D4 + Address: 0x0801B6D8 + Address: 0x0801B6DC + Address: 0x0801B6E0 + Address: 0x0801B6E4 + Address: 0x0801B6E8 + Address: 0x0801B6EC + Address: 0x0801B6F0 + Address: 0x0801B6F4 + Address: 0x0801B6F8 + Address: 0x0801B6FC + Address: 0x0801B700 + Address: 0x0801B704 + Address: 0x0801B70C + Address: 0x0801B710 + Address: 0x0801B714 + Address: 0x0801B718 + Address: 0x0801B71C + Address: 0x0801B720 + Address: 0x0801B724 + Address: 0x0801B728 + Address: 0x0801B72C + Address: 0x0801B730 + Address: 0x0801B734 + Address: 0x0801B738 + Address: 0x0801B73C + Address: 0x0801B740 + Address: 0x0801B744 + Address: 0x0801B748 + Address: 0x0801B74C + Address: 0x0801B774 + Address: 0x0801B778 + Address: 0x0801B77C + Address: 0x0801B780 + Address: 0x0801B784 + Address: 0x0801B788 + Address: 0x0801B78C + Address: 0x0801B790 + Address: 0x0801B794 + Address: 0x0801B798 + Address: 0x0801B79C + Address: 0x0801B7A0 + Address: 0x0801B7A4 + Address: 0x0801B7A8 + Address: 0x0801B7AC + Address: 0x0801B7B0 + Address: 0x0801B7B4 + Address: 0x0801B7B8 + Address: 0x0801B7BC + Address: 0x0801B7C0 + Address: 0x0801B7C4 + Address: 0x0801B7CC + Address: 0x0801B7D0 + Address: 0x0801B7D4 + Address: 0x0801B7D8 + Address: 0x0801B7DC + Address: 0x0801B7E0 + Address: 0x0801B7E4 + Address: 0x0801B7E8 + Address: 0x0801B7EC + Address: 0x0801B7F0 + Address: 0x0801B7F4 + Address: 0x0801B7F8 + Address: 0x0801B7FC + Address: 0x0801B800 + Address: 0x0801B804 + Address: 0x0801B808 + Address: 0x0801B80C + Address: 0x0801B830 + Address: 0x0801B834 + Address: 0x0801B838 + Address: 0x0801B83C + Address: 0x0801B840 + Address: 0x0801B844 + Address: 0x0801B848 + Address: 0x0801B84C + Address: 0x0801B850 + Address: 0x0801B854 + Address: 0x0801B858 + Address: 0x0801B85C + Address: 0x0801B860 + Address: 0x0801B864 + Address: 0x0801B868 + Address: 0x0801B86C + Address: 0x0801B870 + Address: 0x0801B874 + Address: 0x0801B878 + Address: 0x0801B87C + Address: 0x0801B880 + Address: 0x0801B884 + Address: 0x0801B888 + Address: 0x0801B88C + Address: 0x0801B890 + Address: 0x0801B894 + Address: 0x0801B898 + Address: 0x0801B89C + Address: 0x0801B8A0 + Address: 0x0801B8A4 + Address: 0x0801B8A8 + Address: 0x0801B8AC + Address: 0x0801B8B0 + Address: 0x0801B8B4 + Address: 0x0801B8B8 + Address: 0x0801B8BC + Address: 0x0801B8C0 + Address: 0x0801B8E8 + Address: 0x0801B8EC + Address: 0x0801B8F0 + Address: 0x0801B8F4 + Address: 0x0801B8F8 + Address: 0x0801B8FC + Address: 0x0801B900 + Address: 0x0801B904 + Address: 0x0801B908 + Address: 0x0801B90C + Address: 0x0801B910 + Address: 0x0801B914 + Address: 0x0801B918 + Address: 0x0801B91C + Address: 0x0801B920 + Address: 0x0801B924 + Address: 0x0801B928 + Address: 0x0801B92C + Address: 0x0801B930 + Address: 0x0801B934 + Address: 0x0801B938 + Address: 0x0801B940 + Address: 0x0801B944 + Address: 0x0801B948 + Address: 0x0801B94C + Address: 0x0801B950 + Address: 0x0801B954 + Address: 0x0801B958 + Address: 0x0801B95C + Address: 0x0801B960 + Address: 0x0801B964 + Address: 0x0801B968 + Address: 0x0801B96C + Address: 0x0801B970 + Address: 0x0801B974 + Address: 0x0801B978 + Address: 0x0801B97C + Address: 0x0801B980 + Address: 0x0801B9A0 + Address: 0x0801B9A4 + Address: 0x0801B9A8 + Address: 0x0801B9AC + Address: 0x0801B9B0 + Address: 0x0801B9B4 + Address: 0x0801B9B8 + Address: 0x0801B9BC + Address: 0x0801B9C0 + Address: 0x0801B9C4 + Address: 0x0801B9C8 + Address: 0x0801B9CC + Address: 0x0801B9D0 + Address: 0x0801B9D4 + Address: 0x0801B9D8 + Address: 0x0801B9DC + Address: 0x0801B9E0 + Address: 0x0801B9E4 + Address: 0x0801B9E8 + Address: 0x0801B9EC + Address: 0x0801B9F8 + Address: 0x0801B9FC + Address: 0x0801BA00 + Address: 0x0801BA04 + Address: 0x0801BA08 + Address: 0x0801BA0C + Address: 0x0801BA10 + Address: 0x0801BA14 + Address: 0x0801BA18 + Address: 0x0801BA1C + Address: 0x0801BA20 + Address: 0x0801BA24 + Address: 0x0801BA28 + Address: 0x0801BA2C + Address: 0x0801BA30 + Address: 0x0801BA34 + Address: 0x0801BA38 + Address: 0x0801BA5C + Address: 0x0801BA60 + Address: 0x0801BA64 + Address: 0x0801BA68 + Address: 0x0801BA6C + Address: 0x0801BA70 + Address: 0x0801BA74 + Address: 0x0801BA78 + Address: 0x0801BA7C + Address: 0x0801BA80 + Address: 0x0801BA84 + Address: 0x0801BA88 + Address: 0x0801BA8C + Address: 0x0801BA90 + Address: 0x0801BA94 + Address: 0x0801BA98 + Address: 0x0801BA9C + Address: 0x0801BAA0 + Address: 0x0801BAA4 + Address: 0x0801BAA8 + Address: 0x0801BAAC + Address: 0x0801BAB4 + Address: 0x0801BAB8 + Address: 0x0801BABC + Address: 0x0801BAC0 + Address: 0x0801BAC4 + Address: 0x0801BAC8 + Address: 0x0801BACC + Address: 0x0801BAD0 + Address: 0x0801BAD4 + Address: 0x0801BAD8 + Address: 0x0801BADC + Address: 0x0801BAE0 + Address: 0x0801BAE4 + Address: 0x0801BAE8 + Address: 0x0801BAEC + Address: 0x0801BAF0 + Address: 0x0801BAF4 + Address: 0x0801BB18 + Address: 0x0801BB1C + Address: 0x0801BB20 + Address: 0x0801BB24 + Address: 0x0801BB28 + Address: 0x0801BB2C + Address: 0x0801BB30 + Address: 0x0801BB34 + Address: 0x0801BB38 + Address: 0x0801BB3C + Address: 0x0801BB40 + Address: 0x0801BB44 + Address: 0x0801BB48 + Address: 0x0801BB4C + Address: 0x0801BB50 + Address: 0x0801BB54 + Address: 0x0801BB58 + Address: 0x0801BB5C + Address: 0x0801BB60 + Address: 0x0801BB64 + Address: 0x0801BB68 + Address: 0x0801BB6C + Address: 0x0801BB70 + Address: 0x0801BB74 + Address: 0x0801BB78 + Address: 0x0801BB7C + Address: 0x0801BB80 + Address: 0x0801BB84 + Address: 0x0801BB88 + Address: 0x0801BB8C + Address: 0x0801BB90 + Address: 0x0801BB94 + Address: 0x0801BB98 + Address: 0x0801BB9C + Address: 0x0801BBA0 + Address: 0x0801BBA4 + Address: 0x0801BBA8 + Address: 0x0801BBD0 + Address: 0x0801BBD4 + Address: 0x0801BBD8 + Address: 0x0801BBDC + Address: 0x0801BBE0 + Address: 0x0801BBE4 + Address: 0x0801BBE8 + Address: 0x0801BBEC + Address: 0x0801BBF0 + Address: 0x0801BBF4 + Address: 0x0801BBF8 + Address: 0x0801BBFC + Address: 0x0801BC00 + Address: 0x0801BC04 + Address: 0x0801BC08 + Address: 0x0801BC0C + Address: 0x0801BC10 + Address: 0x0801BC14 + Address: 0x0801BC18 + Address: 0x0801BC1C + Address: 0x0801BC20 + Address: 0x0801BC2C + Address: 0x0801BC30 + Address: 0x0801BC34 + Address: 0x0801BC38 + Address: 0x0801BC3C + Address: 0x0801BC40 + Address: 0x0801BC44 + Address: 0x0801BC48 + Address: 0x0801BC4C + Address: 0x0801BC50 + Address: 0x0801BC54 + Address: 0x0801BC58 + Address: 0x0801BC5C + Address: 0x0801BC60 + Address: 0x0801BC64 + Address: 0x0801BC68 + Address: 0x0801BC6C + Address: 0x0801BC70 + Address: 0x0801BC8C + Address: 0x0801BC90 + Address: 0x0801BC94 + Address: 0x0801BC98 + Address: 0x0801BC9C + Address: 0x0801BCA0 + Address: 0x0801BCA4 + Address: 0x0801BCA8 + Address: 0x0801BCAC + Address: 0x0801BCB0 + Address: 0x0801BCB4 + Address: 0x0801BCB8 + Address: 0x0801BCBC + Address: 0x0801BCC0 + Address: 0x0801BCC4 + Address: 0x0801BCC8 + Address: 0x0801BCCC + Address: 0x0801BCD0 + Address: 0x0801BCD4 + Address: 0x0801BCD8 + Address: 0x0801BCDC + Address: 0x0801BCE0 + Address: 0x0801BCE4 + Address: 0x0801BCE8 + Address: 0x0801BCEC + Address: 0x0801BCF0 + Address: 0x0801BCF4 + Address: 0x0801BCF8 + Address: 0x0801BCFC + Address: 0x0801BD00 + Address: 0x0801BD04 + Address: 0x0801BD08 + Address: 0x0801BD0C + Address: 0x0801BD10 + Address: 0x0801BD14 + Address: 0x0801BD18 + Address: 0x0801BD1C + Address: 0x0801BD4C + Address: 0x0801BD50 + Address: 0x0801BD54 + Address: 0x0801BD58 + Address: 0x0801BD5C + Address: 0x0801BD60 + Address: 0x0801BD64 + Address: 0x0801BD68 + Address: 0x0801BD6C + Address: 0x0801BD70 + Address: 0x0801BD74 + Address: 0x0801BD78 + Address: 0x0801BD7C + Address: 0x0801BD80 + Address: 0x0801BD84 + Address: 0x0801BD88 + Address: 0x0801BD8C + Address: 0x0801BD90 + Address: 0x0801BD94 + Address: 0x0801BD98 + Address: 0x0801BD9C + Address: 0x0801BDA0 + Address: 0x0801BDA4 + Address: 0x0801BDA8 + Address: 0x0801BDAC + Address: 0x0801BDB0 + Address: 0x0801BDB4 + Address: 0x0801BDB8 + Address: 0x0801BDBC + Address: 0x0801BDC0 + Address: 0x0801BDC4 + Address: 0x0801BDC8 + Address: 0x0801BDCC + Address: 0x0801BDD0 + Address: 0x0801BDD4 + Address: 0x0801BDD8 + Address: 0x0801BDDC + Address: 0x0801BDE0 + Address: 0x0801BE00 + Address: 0x0801BE04 + Address: 0x0801BE08 + Address: 0x0801BE0C + Address: 0x0801BE10 + Address: 0x0801BE14 + Address: 0x0801BE18 + Address: 0x0801BE1C + Address: 0x0801BE20 + Address: 0x0801BE24 + Address: 0x0801BE28 + Address: 0x0801BE2C + Address: 0x0801BE30 + Address: 0x0801BE34 + Address: 0x0801BE38 + Address: 0x0801BE3C + Address: 0x0801BE40 + Address: 0x0801BE44 + Address: 0x0801BE48 + Address: 0x0801BE4C + Address: 0x0801BE54 + Address: 0x0801BE58 + Address: 0x0801BE5C + Address: 0x0801BE60 + Address: 0x0801BE64 + Address: 0x0801BE68 + Address: 0x0801BE6C + Address: 0x0801BE70 + Address: 0x0801BE74 + Address: 0x0801BE78 + Address: 0x0801BE7C + Address: 0x0801BE80 + Address: 0x0801BE84 + Address: 0x0801BE88 + Address: 0x0801BE8C + Address: 0x0801BE90 + Address: 0x0801BE94 + Address: 0x0801BEBC + Address: 0x0801BEC0 + Address: 0x0801BEC4 + Address: 0x0801BEC8 + Address: 0x0801BECC + Address: 0x0801BED0 + Address: 0x0801BED4 + Address: 0x0801BED8 + Address: 0x0801BEDC + Address: 0x0801BEE0 + Address: 0x0801BEE4 + Address: 0x0801BEE8 + Address: 0x0801BEEC + Address: 0x0801BEF0 + Address: 0x0801BEF4 + Address: 0x0801BEF8 + Address: 0x0801BEFC + Address: 0x0801BF00 + Address: 0x0801BF04 + Address: 0x0801BF08 + Address: 0x0801BF0C + Address: 0x0801BF14 + Address: 0x0801BF18 + Address: 0x0801BF1C + Address: 0x0801BF20 + Address: 0x0801BF24 + Address: 0x0801BF28 + Address: 0x0801BF2C + Address: 0x0801BF30 + Address: 0x0801BF34 + Address: 0x0801BF38 + Address: 0x0801BF3C + Address: 0x0801BF40 + Address: 0x0801BF44 + Address: 0x0801BF48 + Address: 0x0801BF4C + Address: 0x0801BF50 + Address: 0x0801BF54 + Address: 0x0801BF78 + Address: 0x0801BF7C + Address: 0x0801BF80 + Address: 0x0801BF84 + Address: 0x0801BF88 + Address: 0x0801BF8C + Address: 0x0801BF90 + Address: 0x0801BF94 + Address: 0x0801BF98 + Address: 0x0801BF9C + Address: 0x0801BFA0 + Address: 0x0801BFA4 + Address: 0x0801BFA8 + Address: 0x0801BFAC + Address: 0x0801BFB0 + Address: 0x0801BFB4 + Address: 0x0801BFB8 + Address: 0x0801BFBC + Address: 0x0801BFC0 + Address: 0x0801BFC4 + Address: 0x0801BFC8 + Address: 0x0801BFCC + Address: 0x0801BFD0 + Address: 0x0801BFD4 + Address: 0x0801BFD8 + Address: 0x0801BFDC + Address: 0x0801BFE0 + Address: 0x0801BFE4 + Address: 0x0801BFE8 + Address: 0x0801BFEC + Address: 0x0801BFF0 + Address: 0x0801BFF4 + Address: 0x0801BFF8 + Address: 0x0801BFFC + Address: 0x0801C000 + Address: 0x0801C004 + Address: 0x0801C008 + Address: 0x0801C030 + Address: 0x0801C034 + Address: 0x0801C038 + Address: 0x0801C03C + Address: 0x0801C040 + Address: 0x0801C044 + Address: 0x0801C048 + Address: 0x0801C04C + Address: 0x0801C050 + Address: 0x0801C054 + Address: 0x0801C058 + Address: 0x0801C05C + Address: 0x0801C060 + Address: 0x0801C064 + Address: 0x0801C068 + Address: 0x0801C06C + Address: 0x0801C070 + Address: 0x0801C074 + Address: 0x0801C078 + Address: 0x0801C07C + Address: 0x0801C080 + Address: 0x0801C088 + Address: 0x0801C08C + Address: 0x0801C090 + Address: 0x0801C094 + Address: 0x0801C098 + Address: 0x0801C09C + Address: 0x0801C0A0 + Address: 0x0801C0A4 + Address: 0x0801C0A8 + Address: 0x0801C0AC + Address: 0x0801C0B0 + Address: 0x0801C0B4 + Address: 0x0801C0B8 + Address: 0x0801C0BC + Address: 0x0801C0C0 + Address: 0x0801C0C4 + Address: 0x0801C0C8 + Address: 0x0801C0EC + Address: 0x0801C0F0 + Address: 0x0801C0F4 + Address: 0x0801C0F8 + Address: 0x0801C0FC + Address: 0x0801C100 + Address: 0x0801C104 + Address: 0x0801C108 + Address: 0x0801C10C + Address: 0x0801C110 + Address: 0x0801C114 + Address: 0x0801C118 + Address: 0x0801C11C + Address: 0x0801C120 + Address: 0x0801C124 + Address: 0x0801C128 + Address: 0x0801C12C + Address: 0x0801C130 + Address: 0x0801C134 + Address: 0x0801C138 + Address: 0x0801C13C + Address: 0x0801C140 + Address: 0x0801C144 + Address: 0x0801C148 + Address: 0x0801C14C + Address: 0x0801C150 + Address: 0x0801C154 + Address: 0x0801C158 + Address: 0x0801C15C + Address: 0x0801C160 + Address: 0x0801C164 + Address: 0x0801C168 + Address: 0x0801C16C + Address: 0x0801C170 + Address: 0x0801C174 + Address: 0x0801C178 + Address: 0x0801C17C + Address: 0x0801C1A8 + Address: 0x0801C1AC + Address: 0x0801C1B0 + Address: 0x0801C1B4 + Address: 0x0801C1B8 + Address: 0x0801C1BC + Address: 0x0801C1C0 + Address: 0x0801C1C4 + Address: 0x0801C1C8 + Address: 0x0801C1CC + Address: 0x0801C1D0 + Address: 0x0801C1D4 + Address: 0x0801C1D8 + Address: 0x0801C1DC + Address: 0x0801C1E0 + Address: 0x0801C1E4 + Address: 0x0801C1E8 + Address: 0x0801C1EC + Address: 0x0801C1F0 + Address: 0x0801C1F4 + Address: 0x0801C1F8 + Address: 0x0801C1FC + Address: 0x0801C200 + Address: 0x0801C204 + Address: 0x0801C208 + Address: 0x0801C20C + Address: 0x0801C210 + Address: 0x0801C214 + Address: 0x0801C218 + Address: 0x0801C21C + Address: 0x0801C220 + Address: 0x0801C224 + Address: 0x0801C228 + Address: 0x0801C22C + Address: 0x0801C230 + Address: 0x0801C234 + Address: 0x0801C238 + Address: 0x0801C23C + Address: 0x0801C25C + Address: 0x0801C260 + Address: 0x0801C264 + Address: 0x0801C268 + Address: 0x0801C26C + Address: 0x0801C270 + Address: 0x0801C274 + Address: 0x0801C278 + Address: 0x0801C27C + Address: 0x0801C280 + Address: 0x0801C284 + Address: 0x0801C288 + Address: 0x0801C28C + Address: 0x0801C290 + Address: 0x0801C294 + Address: 0x0801C298 + Address: 0x0801C29C + Address: 0x0801C2A0 + Address: 0x0801C2A4 + Address: 0x0801C2A8 + Address: 0x0801C2AC + Address: 0x0801C2B0 + Address: 0x0801C2B4 + Address: 0x0801C2B8 + Address: 0x0801C2BC + Address: 0x0801C2C0 + Address: 0x0801C2C4 + Address: 0x0801C2C8 + Address: 0x0801C2CC + Address: 0x0801C2D0 + Address: 0x0801C2D4 + Address: 0x0801C2D8 + Address: 0x0801C2DC + Address: 0x0801C2E0 + Address: 0x0801C2E4 + Address: 0x0801C2E8 + Address: 0x0801C2EC + Address: 0x0801C318 + Address: 0x0801C31C + Address: 0x0801C320 + Address: 0x0801C324 + Address: 0x0801C328 + Address: 0x0801C32C + Address: 0x0801C330 + Address: 0x0801C334 + Address: 0x0801C338 + Address: 0x0801C33C + Address: 0x0801C340 + Address: 0x0801C344 + Address: 0x0801C348 + Address: 0x0801C34C + Address: 0x0801C350 + Address: 0x0801C354 + Address: 0x0801C358 + Address: 0x0801C35C + Address: 0x0801C360 + Address: 0x0801C364 + Address: 0x0801C368 + Address: 0x0801C370 + Address: 0x0801C374 + Address: 0x0801C378 + Address: 0x0801C37C + Address: 0x0801C380 + Address: 0x0801C384 + Address: 0x0801C388 + Address: 0x0801C38C + Address: 0x0801C390 + Address: 0x0801C394 + Address: 0x0801C398 + Address: 0x0801C39C + Address: 0x0801C3A0 + Address: 0x0801C3A4 + Address: 0x0801C3A8 + Address: 0x0801C3AC + Address: 0x0801C3B0 + Address: 0x0801C3D0 + Address: 0x0801C3D4 + Address: 0x0801C3D8 + Address: 0x0801C3DC + Address: 0x0801C3E0 + Address: 0x0801C3E4 + Address: 0x0801C3E8 + Address: 0x0801C3EC + Address: 0x0801C3F0 + Address: 0x0801C3F4 + Address: 0x0801C3F8 + Address: 0x0801C3FC + Address: 0x0801C400 + Address: 0x0801C404 + Address: 0x0801C408 + Address: 0x0801C40C + Address: 0x0801C410 + Address: 0x0801C414 + Address: 0x0801C418 + Address: 0x0801C41C + Address: 0x0801C424 + Address: 0x0801C428 + Address: 0x0801C42C + Address: 0x0801C430 + Address: 0x0801C434 + Address: 0x0801C438 + Address: 0x0801C43C + Address: 0x0801C440 + Address: 0x0801C444 + Address: 0x0801C448 + Address: 0x0801C44C + Address: 0x0801C450 + Address: 0x0801C454 + Address: 0x0801C458 + Address: 0x0801C45C + Address: 0x0801C460 + Address: 0x0801C464 + Address: 0x0801C48C + Address: 0x0801C490 + Address: 0x0801C494 + Address: 0x0801C498 + Address: 0x0801C49C + Address: 0x0801C4A0 + Address: 0x0801C4A4 + Address: 0x0801C4A8 + Address: 0x0801C4AC + Address: 0x0801C4B0 + Address: 0x0801C4B4 + Address: 0x0801C4B8 + Address: 0x0801C4BC + Address: 0x0801C4C0 + Address: 0x0801C4C4 + Address: 0x0801C4C8 + Address: 0x0801C4CC + Address: 0x0801C4D0 + Address: 0x0801C4D4 + Address: 0x0801C4D8 + Address: 0x0801C4DC + Address: 0x0801C4E0 + Address: 0x0801C4E4 + Address: 0x0801C4E8 + Address: 0x0801C4EC + Address: 0x0801C4F0 + Address: 0x0801C4F4 + Address: 0x0801C4F8 + Address: 0x0801C4FC + Address: 0x0801C500 + Address: 0x0801C504 + Address: 0x0801C508 + Address: 0x0801C50C + Address: 0x0801C510 + Address: 0x0801C514 + Address: 0x0801C518 + Address: 0x0801C530 + Address: 0x0801C534 + Address: 0x0801C538 + Address: 0x0801C53C + Address: 0x0801C540 + Address: 0x0801C544 + Address: 0x0801C548 + Address: 0x0801C54C + Address: 0x0801C550 + Address: 0x0801C554 + Address: 0x0801C558 + Address: 0x0801C55C + Address: 0x0801C560 + Address: 0x0801C564 + Address: 0x0801C568 + Address: 0x0801C56C + Address: 0x0801C570 + Address: 0x0801C574 + Address: 0x0801C578 + Address: 0x0801C588 + Address: 0x0801C58C + Address: 0x0801C590 + Address: 0x0801C594 + Address: 0x0801C598 + Address: 0x0801C59C + Address: 0x0801C5A0 + Address: 0x0801C5A4 + Address: 0x0801C5A8 + Address: 0x0801C5AC + Address: 0x0801C5B0 + Address: 0x0801C5B4 + Address: 0x0801C5B8 + Address: 0x0801C5BC + Address: 0x0801C5C0 + Address: 0x0801C5C4 + Address: 0x0801C5C8 + Address: 0x0801C5CC + Address: 0x0801C5EC + Address: 0x0801C5F0 + Address: 0x0801C5F4 + Address: 0x0801C5F8 + Address: 0x0801C5FC + Address: 0x0801C600 + Address: 0x0801C604 + Address: 0x0801C608 + Address: 0x0801C60C + Address: 0x0801C610 + Address: 0x0801C614 + Address: 0x0801C618 + Address: 0x0801C61C + Address: 0x0801C620 + Address: 0x0801C624 + Address: 0x0801C628 + Address: 0x0801C62C + Address: 0x0801C630 + Address: 0x0801C634 + Address: 0x0801C638 + Address: 0x0801C648 + Address: 0x0801C64C + Address: 0x0801C650 + Address: 0x0801C654 + Address: 0x0801C658 + Address: 0x0801C65C + Address: 0x0801C660 + Address: 0x0801C664 + Address: 0x0801C668 + Address: 0x0801C66C + Address: 0x0801C670 + Address: 0x0801C674 + Address: 0x0801C678 + Address: 0x0801C67C + Address: 0x0801C680 + Address: 0x0801C684 + Address: 0x0801C688 + Address: 0x0801C68C + Address: 0x0801C6AC + Address: 0x0801C6B0 + Address: 0x0801C6B4 + Address: 0x0801C6B8 + Address: 0x0801C6BC + Address: 0x0801C6C0 + Address: 0x0801C6C4 + Address: 0x0801C6C8 + Address: 0x0801C6CC + Address: 0x0801C6D0 + Address: 0x0801C6D4 + Address: 0x0801C6D8 + Address: 0x0801C6DC + Address: 0x0801C6E0 + Address: 0x0801C6E4 + Address: 0x0801C6E8 + Address: 0x0801C6EC + Address: 0x0801C6F0 + Address: 0x0801C6F4 + Address: 0x0801C6F8 + Address: 0x0801C700 + Address: 0x0801C704 + Address: 0x0801C708 + Address: 0x0801C70C + Address: 0x0801C710 + Address: 0x0801C714 + Address: 0x0801C718 + Address: 0x0801C71C + Address: 0x0801C720 + Address: 0x0801C724 + Address: 0x0801C728 + Address: 0x0801C72C + Address: 0x0801C730 + Address: 0x0801C734 + Address: 0x0801C738 + Address: 0x0801C73C + Address: 0x0801C740 + Address: 0x0801C75C + Address: 0x0801C760 + Address: 0x0801C764 + Address: 0x0801C768 + Address: 0x0801C76C + Address: 0x0801C770 + Address: 0x0801C774 + Address: 0x0801C778 + Address: 0x0801C77C + Address: 0x0801C780 + Address: 0x0801C784 + Address: 0x0801C788 + Address: 0x0801C78C + Address: 0x0801C790 + Address: 0x0801C794 + Address: 0x0801C798 + Address: 0x0801C79C + Address: 0x0801C7A0 + Address: 0x0801C7A4 + Address: 0x0801C7A8 + Address: 0x0801C7B8 + Address: 0x0801C7BC + Address: 0x0801C7C0 + Address: 0x0801C7C4 + Address: 0x0801C7C8 + Address: 0x0801C7CC + Address: 0x0801C7D0 + Address: 0x0801C7D4 + Address: 0x0801C7D8 + Address: 0x0801C7DC + Address: 0x0801C7E0 + Address: 0x0801C7E4 + Address: 0x0801C7E8 + Address: 0x0801C7EC + Address: 0x0801C7F0 + Address: 0x0801C7F4 + Address: 0x0801C7F8 + Address: 0x0801C7FC + Address: 0x0801C81C + Address: 0x0801C820 + Address: 0x0801C824 + Address: 0x0801C828 + Address: 0x0801C82C + Address: 0x0801C830 + Address: 0x0801C834 + Address: 0x0801C838 + Address: 0x0801C83C + Address: 0x0801C840 + Address: 0x0801C844 + Address: 0x0801C848 + Address: 0x0801C84C + Address: 0x0801C850 + Address: 0x0801C854 + Address: 0x0801C858 + Address: 0x0801C85C + Address: 0x0801C860 + Address: 0x0801C864 + Address: 0x0801C868 + Address: 0x0801C874 + Address: 0x0801C878 + Address: 0x0801C87C + Address: 0x0801C880 + Address: 0x0801C884 + Address: 0x0801C888 + Address: 0x0801C88C + Address: 0x0801C890 + Address: 0x0801C894 + Address: 0x0801C898 + Address: 0x0801C89C + Address: 0x0801C8A0 + Address: 0x0801C8A4 + Address: 0x0801C8A8 + Address: 0x0801C8AC + Address: 0x0801C8B0 + Address: 0x0801C8B4 + Address: 0x0801C8D0 + Address: 0x0801C8D4 + Address: 0x0801C8D8 + Address: 0x0801C8DC + Address: 0x0801C8E0 + Address: 0x0801C8E4 + Address: 0x0801C8E8 + Address: 0x0801C8EC + Address: 0x0801C8F0 + Address: 0x0801C8F4 + Address: 0x0801C8F8 + Address: 0x0801C8FC + Address: 0x0801C900 + Address: 0x0801C904 + Address: 0x0801C908 + Address: 0x0801C90C + Address: 0x0801C910 + Address: 0x0801C914 + Address: 0x0801C918 + Address: 0x0801C91C + Address: 0x0801C930 + Address: 0x0801C934 + Address: 0x0801C938 + Address: 0x0801C93C + Address: 0x0801C940 + Address: 0x0801C944 + Address: 0x0801C948 + Address: 0x0801C94C + Address: 0x0801C950 + Address: 0x0801C954 + Address: 0x0801C958 + Address: 0x0801C95C + Address: 0x0801C960 + Address: 0x0801C964 + Address: 0x0801C968 + Address: 0x0801C96C + Address: 0x0801C970 + Address: 0x0801C974 + Address: 0x0801C994 + Address: 0x0801C998 + Address: 0x0801C99C + Address: 0x0801C9A0 + Address: 0x0801C9A4 + Address: 0x0801C9A8 + Address: 0x0801C9AC + Address: 0x0801C9B0 + Address: 0x0801C9B4 + Address: 0x0801C9B8 + Address: 0x0801C9BC + Address: 0x0801C9C0 + Address: 0x0801C9C4 + Address: 0x0801C9C8 + Address: 0x0801C9CC + Address: 0x0801C9D0 + Address: 0x0801C9D4 + Address: 0x0801C9D8 + Address: 0x0801C9DC + Address: 0x0801C9E0 + Address: 0x0801C9EC + Address: 0x0801C9F0 + Address: 0x0801C9F4 + Address: 0x0801C9F8 + Address: 0x0801C9FC + Address: 0x0801CA00 + Address: 0x0801CA04 + Address: 0x0801CA08 + Address: 0x0801CA0C + Address: 0x0801CA10 + Address: 0x0801CA14 + Address: 0x0801CA18 + Address: 0x0801CA1C + Address: 0x0801CA20 + Address: 0x0801CA24 + Address: 0x0801CA28 + Address: 0x0801CA2C + Address: 0x0801CA30 + Address: 0x0801CA48 + Address: 0x0801CA4C + Address: 0x0801CA50 + Address: 0x0801CA54 + Address: 0x0801CA58 + Address: 0x0801CA5C + Address: 0x0801CA60 + Address: 0x0801CA64 + Address: 0x0801CA68 + Address: 0x0801CA6C + Address: 0x0801CA70 + Address: 0x0801CA74 + Address: 0x0801CA78 + Address: 0x0801CA7C + Address: 0x0801CA80 + Address: 0x0801CA84 + Address: 0x0801CA88 + Address: 0x0801CA8C + Address: 0x0801CA90 + Address: 0x0801CAB0 + Address: 0x0801CAB4 + Address: 0x0801CAB8 + Address: 0x0801CABC + Address: 0x0801CAC0 + Address: 0x0801CAC4 + Address: 0x0801CAC8 + Address: 0x0801CACC + Address: 0x0801CAD0 + Address: 0x0801CAD4 + Address: 0x0801CAD8 + Address: 0x0801CADC + Address: 0x0801CAE0 + Address: 0x0801CAE4 + Address: 0x0801CAE8 + Address: 0x0801CAEC + Address: 0x0801CAF0 + Address: 0x0801CAF4 + Address: 0x0801CAF8 + Address: 0x0801CAFC + Address: 0x0801CB0C + Address: 0x0801CB10 + Address: 0x0801CB14 + Address: 0x0801CB18 + Address: 0x0801CB1C + Address: 0x0801CB20 + Address: 0x0801CB24 + Address: 0x0801CB28 + Address: 0x0801CB2C + Address: 0x0801CB30 + Address: 0x0801CB34 + Address: 0x0801CB38 + Address: 0x0801CB3C + Address: 0x0801CB40 + Address: 0x0801CB44 + Address: 0x0801CB48 + Address: 0x0801CB4C + Address: 0x0801CB50 + Address: 0x0801CB64 + Address: 0x0801CB68 + Address: 0x0801CB6C + Address: 0x0801CB70 + Address: 0x0801CB74 + Address: 0x0801CB78 + Address: 0x0801CB7C + Address: 0x0801CB80 + Address: 0x0801CB84 + Address: 0x0801CB88 + Address: 0x0801CB8C + Address: 0x0801CB90 + Address: 0x0801CB94 + Address: 0x0801CB98 + Address: 0x0801CB9C + Address: 0x0801CBA0 + Address: 0x0801CBA4 + Address: 0x0801CBA8 + Address: 0x0801CBAC + Address: 0x0801CBBC + Address: 0x0801CBC0 + Address: 0x0801CBC4 + Address: 0x0801CBC8 + Address: 0x0801CBCC + Address: 0x0801CBD0 + Address: 0x0801CBD4 + Address: 0x0801CBD8 + Address: 0x0801CBDC + Address: 0x0801CBE0 + Address: 0x0801CBE4 + Address: 0x0801CBE8 + Address: 0x0801CBEC + Address: 0x0801CBF0 + Address: 0x0801CBF4 + Address: 0x0801CBF8 + Address: 0x0801CBFC + Address: 0x0801CC00 + Address: 0x0801CC20 + Address: 0x0801CC24 + Address: 0x0801CC28 + Address: 0x0801CC2C + Address: 0x0801CC30 + Address: 0x0801CC34 + Address: 0x0801CC38 + Address: 0x0801CC3C + Address: 0x0801CC40 + Address: 0x0801CC44 + Address: 0x0801CC48 + Address: 0x0801CC4C + Address: 0x0801CC50 + Address: 0x0801CC54 + Address: 0x0801CC58 + Address: 0x0801CC5C + Address: 0x0801CC60 + Address: 0x0801CC64 + Address: 0x0801CC68 + Address: 0x0801CC6C + Address: 0x0801CC80 + Address: 0x0801CC84 + Address: 0x0801CC88 + Address: 0x0801CC8C + Address: 0x0801CC90 + Address: 0x0801CC94 + Address: 0x0801CC98 + Address: 0x0801CC9C + Address: 0x0801CCA0 + Address: 0x0801CCA4 + Address: 0x0801CCA8 + Address: 0x0801CCAC + Address: 0x0801CCB0 + Address: 0x0801CCB4 + Address: 0x0801CCB8 + Address: 0x0801CCBC + Address: 0x0801CCC0 + Address: 0x0801CCC4 + Address: 0x0801CCDC + Address: 0x0801CCE0 + Address: 0x0801CCE4 + Address: 0x0801CCE8 + Address: 0x0801CCEC + Address: 0x0801CCF0 + Address: 0x0801CCF4 + Address: 0x0801CCF8 + Address: 0x0801CCFC + Address: 0x0801CD00 + Address: 0x0801CD04 + Address: 0x0801CD08 + Address: 0x0801CD0C + Address: 0x0801CD10 + Address: 0x0801CD14 + Address: 0x0801CD18 + Address: 0x0801CD1C + Address: 0x0801CD20 + Address: 0x0801CD24 + Address: 0x0801CD34 + Address: 0x0801CD38 + Address: 0x0801CD3C + Address: 0x0801CD40 + Address: 0x0801CD44 + Address: 0x0801CD48 + Address: 0x0801CD4C + Address: 0x0801CD50 + Address: 0x0801CD54 + Address: 0x0801CD58 + Address: 0x0801CD5C + Address: 0x0801CD60 + Address: 0x0801CD64 + Address: 0x0801CD68 + Address: 0x0801CD6C + Address: 0x0801CD70 + Address: 0x0801CD74 + Address: 0x0801CD78 + Address: 0x0801CD94 + Address: 0x0801CD98 + Address: 0x0801CD9C + Address: 0x0801CDA0 + Address: 0x0801CDA4 + Address: 0x0801CDA8 + Address: 0x0801CDAC + Address: 0x0801CDB0 + Address: 0x0801CDB4 + Address: 0x0801CDB8 + Address: 0x0801CDBC + Address: 0x0801CDC0 + Address: 0x0801CDC4 + Address: 0x0801CDC8 + Address: 0x0801CDCC + Address: 0x0801CDD0 + Address: 0x0801CDD4 + Address: 0x0801CDD8 + Address: 0x0801CDDC + Address: 0x0801CDE0 + Address: 0x0801CDF0 + Address: 0x0801CDF4 + Address: 0x0801CDF8 + Address: 0x0801CDFC + Address: 0x0801CE00 + Address: 0x0801CE04 + Address: 0x0801CE08 + Address: 0x0801CE0C + Address: 0x0801CE10 + Address: 0x0801CE14 + Address: 0x0801CE18 + Address: 0x0801CE1C + Address: 0x0801CE20 + Address: 0x0801CE24 + Address: 0x0801CE28 + Address: 0x0801CE2C + Address: 0x0801CE30 + Address: 0x0801CE34 + Address: 0x0801CE4C + Address: 0x0801CE50 + Address: 0x0801CE54 + Address: 0x0801CE58 + Address: 0x0801CE5C + Address: 0x0801CE60 + Address: 0x0801CE64 + Address: 0x0801CE68 + Address: 0x0801CE6C + Address: 0x0801CE70 + Address: 0x0801CE74 + Address: 0x0801CE78 + Address: 0x0801CE7C + Address: 0x0801CE80 + Address: 0x0801CE84 + Address: 0x0801CE88 + Address: 0x0801CE8C + Address: 0x0801CE90 + Address: 0x0801CE94 + Address: 0x0801CEA4 + Address: 0x0801CEA8 + Address: 0x0801CEAC + Address: 0x0801CEB0 + Address: 0x0801CEB4 + Address: 0x0801CEB8 + Address: 0x0801CEBC + Address: 0x0801CEC0 + Address: 0x0801CEC4 + Address: 0x0801CEC8 + Address: 0x0801CECC + Address: 0x0801CED0 + Address: 0x0801CED4 + Address: 0x0801CED8 + Address: 0x0801CEDC + Address: 0x0801CEE0 + Address: 0x0801CEE4 + Address: 0x0801CEE8 + Address: 0x0801CF08 + Address: 0x0801CF0C + Address: 0x0801CF10 + Address: 0x0801CF14 + Address: 0x0801CF18 + Address: 0x0801CF1C + Address: 0x0801CF20 + Address: 0x0801CF24 + Address: 0x0801CF28 + Address: 0x0801CF2C + Address: 0x0801CF30 + Address: 0x0801CF34 + Address: 0x0801CF38 + Address: 0x0801CF3C + Address: 0x0801CF40 + Address: 0x0801CF44 + Address: 0x0801CF48 + Address: 0x0801CF4C + Address: 0x0801CF50 + Address: 0x0801CF54 + Address: 0x0801CF64 + Address: 0x0801CF68 + Address: 0x0801CF6C + Address: 0x0801CF70 + Address: 0x0801CF74 + Address: 0x0801CF78 + Address: 0x0801CF7C + Address: 0x0801CF80 + Address: 0x0801CF84 + Address: 0x0801CF88 + Address: 0x0801CF8C + Address: 0x0801CF90 + Address: 0x0801CF94 + Address: 0x0801CF98 + Address: 0x0801CF9C + Address: 0x0801CFA0 + Address: 0x0801CFA4 + Address: 0x0801CFA8 + Address: 0x0801CFC8 + Address: 0x0801CFCC + Address: 0x0801CFD0 + Address: 0x0801CFD4 + Address: 0x0801CFD8 + Address: 0x0801CFDC + Address: 0x0801CFE0 + Address: 0x0801CFE4 + Address: 0x0801CFE8 + Address: 0x0801CFEC + Address: 0x0801CFF0 + Address: 0x0801CFF4 + Address: 0x0801CFF8 + Address: 0x0801CFFC + Address: 0x0801D000 + Address: 0x0801D004 + Address: 0x0801D008 + Address: 0x0801D00C + Address: 0x0801D010 + Address: 0x0801D014 + Address: 0x0801D01C + Address: 0x0801D020 + Address: 0x0801D024 + Address: 0x0801D028 + Address: 0x0801D02C + Address: 0x0801D030 + Address: 0x0801D034 + Address: 0x0801D038 + Address: 0x0801D03C + Address: 0x0801D040 + Address: 0x0801D044 + Address: 0x0801D048 + Address: 0x0801D04C + Address: 0x0801D050 + Address: 0x0801D054 + Address: 0x0801D058 + Address: 0x0801D05C + Address: 0x0801D084 + Address: 0x0801D088 + Address: 0x0801D08C + Address: 0x0801D090 + Address: 0x0801D094 + Address: 0x0801D098 + Address: 0x0801D09C + Address: 0x0801D0A0 + Address: 0x0801D0A4 + Address: 0x0801D0A8 + Address: 0x0801D0AC + Address: 0x0801D0B0 + Address: 0x0801D0B4 + Address: 0x0801D0B8 + Address: 0x0801D0BC + Address: 0x0801D0C0 + Address: 0x0801D0C4 + Address: 0x0801D0C8 + Address: 0x0801D0CC + Address: 0x0801D0D0 + Address: 0x0801D0D4 + Address: 0x0801D0DC + Address: 0x0801D0E0 + Address: 0x0801D0E4 + Address: 0x0801D0E8 + Address: 0x0801D0EC + Address: 0x0801D0F0 + Address: 0x0801D0F4 + Address: 0x0801D0F8 + Address: 0x0801D0FC + Address: 0x0801D100 + Address: 0x0801D104 + Address: 0x0801D108 + Address: 0x0801D10C + Address: 0x0801D110 + Address: 0x0801D114 + Address: 0x0801D118 + Address: 0x0801D11C + Address: 0x0801D13C + Address: 0x0801D140 + Address: 0x0801D144 + Address: 0x0801D148 + Address: 0x0801D14C + Address: 0x0801D150 + Address: 0x0801D154 + Address: 0x0801D158 + Address: 0x0801D15C + Address: 0x0801D160 + Address: 0x0801D164 + Address: 0x0801D168 + Address: 0x0801D16C + Address: 0x0801D170 + Address: 0x0801D174 + Address: 0x0801D178 + Address: 0x0801D17C + Address: 0x0801D180 + Address: 0x0801D184 + Address: 0x0801D188 + Address: 0x0801D18C + Address: 0x0801D190 + Address: 0x0801D194 + Address: 0x0801D198 + Address: 0x0801D19C + Address: 0x0801D1A0 + Address: 0x0801D1A4 + Address: 0x0801D1A8 + Address: 0x0801D1AC + Address: 0x0801D1B0 + Address: 0x0801D1B4 + Address: 0x0801D1B8 + Address: 0x0801D1BC + Address: 0x0801D1C0 + Address: 0x0801D1C4 + Address: 0x0801D1C8 + Address: 0x0801D1CC + Address: 0x0801D1F8 + Address: 0x0801D1FC + Address: 0x0801D200 + Address: 0x0801D204 + Address: 0x0801D208 + Address: 0x0801D20C + Address: 0x0801D210 + Address: 0x0801D214 + Address: 0x0801D218 + Address: 0x0801D21C + Address: 0x0801D220 + Address: 0x0801D224 + Address: 0x0801D228 + Address: 0x0801D22C + Address: 0x0801D230 + Address: 0x0801D234 + Address: 0x0801D238 + Address: 0x0801D23C + Address: 0x0801D240 + Address: 0x0801D244 + Address: 0x0801D248 + Address: 0x0801D24C + Address: 0x0801D250 + Address: 0x0801D254 + Address: 0x0801D258 + Address: 0x0801D25C + Address: 0x0801D260 + Address: 0x0801D264 + Address: 0x0801D268 + Address: 0x0801D26C + Address: 0x0801D270 + Address: 0x0801D274 + Address: 0x0801D278 + Address: 0x0801D27C + Address: 0x0801D280 + Address: 0x0801D284 + Address: 0x0801D288 + Address: 0x0801D2B4 + Address: 0x0801D2B8 + Address: 0x0801D2BC + Address: 0x0801D2C0 + Address: 0x0801D2C4 + Address: 0x0801D2C8 + Address: 0x0801D2CC + Address: 0x0801D2D0 + Address: 0x0801D2D4 + Address: 0x0801D2D8 + Address: 0x0801D2DC + Address: 0x0801D2E0 + Address: 0x0801D2E4 + Address: 0x0801D2E8 + Address: 0x0801D2EC + Address: 0x0801D2F0 + Address: 0x0801D2F4 + Address: 0x0801D2F8 + Address: 0x0801D2FC + Address: 0x0801D300 + Address: 0x0801D304 + Address: 0x0801D308 + Address: 0x0801D30C + Address: 0x0801D310 + Address: 0x0801D314 + Address: 0x0801D318 + Address: 0x0801D31C + Address: 0x0801D320 + Address: 0x0801D324 + Address: 0x0801D328 + Address: 0x0801D32C + Address: 0x0801D330 + Address: 0x0801D334 + Address: 0x0801D338 + Address: 0x0801D33C + Address: 0x0801D340 + Address: 0x0801D344 + Address: 0x0801D364 + Address: 0x0801D368 + Address: 0x0801D36C + Address: 0x0801D370 + Address: 0x0801D374 + Address: 0x0801D378 + Address: 0x0801D37C + Address: 0x0801D380 + Address: 0x0801D384 + Address: 0x0801D388 + Address: 0x0801D38C + Address: 0x0801D390 + Address: 0x0801D394 + Address: 0x0801D398 + Address: 0x0801D39C + Address: 0x0801D3A0 + Address: 0x0801D3A4 + Address: 0x0801D3A8 + Address: 0x0801D3AC + Address: 0x0801D3B0 + Address: 0x0801D3C0 + Address: 0x0801D3C4 + Address: 0x0801D3C8 + Address: 0x0801D3CC + Address: 0x0801D3D0 + Address: 0x0801D3D4 + Address: 0x0801D3D8 + Address: 0x0801D3DC + Address: 0x0801D3E0 + Address: 0x0801D3E4 + Address: 0x0801D3E8 + Address: 0x0801D3EC + Address: 0x0801D3F0 + Address: 0x0801D3F4 + Address: 0x0801D3F8 + Address: 0x0801D3FC + Address: 0x0801D400 + Address: 0x0801D404 + Address: 0x0801D424 + Address: 0x0801D428 + Address: 0x0801D42C + Address: 0x0801D430 + Address: 0x0801D434 + Address: 0x0801D438 + Address: 0x0801D43C + Address: 0x0801D440 + Address: 0x0801D444 + Address: 0x0801D448 + Address: 0x0801D44C + Address: 0x0801D450 + Address: 0x0801D454 + Address: 0x0801D458 + Address: 0x0801D45C + Address: 0x0801D460 + Address: 0x0801D464 + Address: 0x0801D468 + Address: 0x0801D46C + Address: 0x0801D470 + Address: 0x0801D47C + Address: 0x0801D480 + Address: 0x0801D484 + Address: 0x0801D488 + Address: 0x0801D48C + Address: 0x0801D490 + Address: 0x0801D494 + Address: 0x0801D498 + Address: 0x0801D49C + Address: 0x0801D4A0 + Address: 0x0801D4A4 + Address: 0x0801D4A8 + Address: 0x0801D4AC + Address: 0x0801D4B0 + Address: 0x0801D4B4 + Address: 0x0801D4B8 + Address: 0x0801D4BC + Address: 0x0801D4C0 + Address: 0x0801D4D8 + Address: 0x0801D4DC + Address: 0x0801D4E0 + Address: 0x0801D4E4 + Address: 0x0801D4E8 + Address: 0x0801D4EC + Address: 0x0801D4F0 + Address: 0x0801D4F4 + Address: 0x0801D4F8 + Address: 0x0801D4FC + Address: 0x0801D500 + Address: 0x0801D504 + Address: 0x0801D508 + Address: 0x0801D50C + Address: 0x0801D510 + Address: 0x0801D514 + Address: 0x0801D518 + Address: 0x0801D51C + Address: 0x0801D520 + Address: 0x0801D53C + Address: 0x0801D540 + Address: 0x0801D544 + Address: 0x0801D548 + Address: 0x0801D54C + Address: 0x0801D550 + Address: 0x0801D554 + Address: 0x0801D558 + Address: 0x0801D55C + Address: 0x0801D560 + Address: 0x0801D564 + Address: 0x0801D568 + Address: 0x0801D56C + Address: 0x0801D570 + Address: 0x0801D574 + Address: 0x0801D578 + Address: 0x0801D57C + Address: 0x0801D580 + Address: 0x0801D584 + Address: 0x0801D598 + Address: 0x0801D59C + Address: 0x0801D5A0 + Address: 0x0801D5A4 + Address: 0x0801D5A8 + Address: 0x0801D5AC + Address: 0x0801D5B0 + Address: 0x0801D5B4 + Address: 0x0801D5B8 + Address: 0x0801D5BC + Address: 0x0801D5C0 + Address: 0x0801D5C4 + Address: 0x0801D5C8 + Address: 0x0801D5CC + Address: 0x0801D5D0 + Address: 0x0801D5D4 + Address: 0x0801D5D8 + Address: 0x0801D5DC + Address: 0x0801D5E0 + Address: 0x0801D5F4 + Address: 0x0801D5F8 + Address: 0x0801D5FC + Address: 0x0801D600 + Address: 0x0801D604 + Address: 0x0801D608 + Address: 0x0801D60C + Address: 0x0801D610 + Address: 0x0801D614 + Address: 0x0801D618 + Address: 0x0801D61C + Address: 0x0801D620 + Address: 0x0801D624 + Address: 0x0801D628 + Address: 0x0801D62C + Address: 0x0801D630 + Address: 0x0801D634 + Address: 0x0801D638 + Address: 0x0801D63C + Address: 0x0801D64C + Address: 0x0801D650 + Address: 0x0801D654 + Address: 0x0801D658 + Address: 0x0801D65C + Address: 0x0801D660 + Address: 0x0801D664 + Address: 0x0801D668 + Address: 0x0801D66C + Address: 0x0801D670 + Address: 0x0801D674 + Address: 0x0801D678 + Address: 0x0801D67C + Address: 0x0801D680 + Address: 0x0801D684 + Address: 0x0801D688 + Address: 0x0801D68C + Address: 0x0801D690 + Address: 0x0801D6B4 + Address: 0x0801D6B8 + Address: 0x0801D6BC + Address: 0x0801D6C0 + Address: 0x0801D6C4 + Address: 0x0801D6C8 + Address: 0x0801D6CC + Address: 0x0801D6D0 + Address: 0x0801D6D4 + Address: 0x0801D6D8 + Address: 0x0801D6DC + Address: 0x0801D6E0 + Address: 0x0801D6E4 + Address: 0x0801D6E8 + Address: 0x0801D6EC + Address: 0x0801D6F0 + Address: 0x0801D6F4 + Address: 0x0801D6F8 + Address: 0x0801D6FC + Address: 0x0801D700 + Address: 0x0801D710 + Address: 0x0801D714 + Address: 0x0801D718 + Address: 0x0801D71C + Address: 0x0801D720 + Address: 0x0801D724 + Address: 0x0801D728 + Address: 0x0801D72C + Address: 0x0801D730 + Address: 0x0801D734 + Address: 0x0801D738 + Address: 0x0801D73C + Address: 0x0801D740 + Address: 0x0801D744 + Address: 0x0801D748 + Address: 0x0801D74C + Address: 0x0801D750 + Address: 0x0801D754 + Address: 0x0801D76C + Address: 0x0801D770 + Address: 0x0801D774 + Address: 0x0801D778 + Address: 0x0801D77C + Address: 0x0801D780 + Address: 0x0801D784 + Address: 0x0801D788 + Address: 0x0801D78C + Address: 0x0801D790 + Address: 0x0801D794 + Address: 0x0801D798 + Address: 0x0801D79C + Address: 0x0801D7A0 + Address: 0x0801D7A4 + Address: 0x0801D7A8 + Address: 0x0801D7AC + Address: 0x0801D7B0 + Address: 0x0801D7B4 + Address: 0x0801D7C4 + Address: 0x0801D7C8 + Address: 0x0801D7CC + Address: 0x0801D7D0 + Address: 0x0801D7D4 + Address: 0x0801D7D8 + Address: 0x0801D7DC + Address: 0x0801D7E0 + Address: 0x0801D7E4 + Address: 0x0801D7E8 + Address: 0x0801D7EC + Address: 0x0801D7F0 + Address: 0x0801D7F4 + Address: 0x0801D7F8 + Address: 0x0801D7FC + Address: 0x0801D800 + Address: 0x0801D804 + Address: 0x0801D808 + Address: 0x0801D824 + Address: 0x0801D828 + Address: 0x0801D82C + Address: 0x0801D830 + Address: 0x0801D834 + Address: 0x0801D838 + Address: 0x0801D83C + Address: 0x0801D840 + Address: 0x0801D844 + Address: 0x0801D848 + Address: 0x0801D84C + Address: 0x0801D850 + Address: 0x0801D854 + Address: 0x0801D858 + Address: 0x0801D85C + Address: 0x0801D860 + Address: 0x0801D864 + Address: 0x0801D868 + Address: 0x0801D86C + Address: 0x0801D870 + Address: 0x0801D880 + Address: 0x0801D884 + Address: 0x0801D888 + Address: 0x0801D88C + Address: 0x0801D890 + Address: 0x0801D894 + Address: 0x0801D898 + Address: 0x0801D89C + Address: 0x0801D8A0 + Address: 0x0801D8A4 + Address: 0x0801D8A8 + Address: 0x0801D8AC + Address: 0x0801D8B0 + Address: 0x0801D8B4 + Address: 0x0801D8B8 + Address: 0x0801D8BC + Address: 0x0801D8C0 + Address: 0x0801D8C4 + Address: 0x0801D8DC + Address: 0x0801D8E0 + Address: 0x0801D8E4 + Address: 0x0801D8E8 + Address: 0x0801D8EC + Address: 0x0801D8F0 + Address: 0x0801D8F4 + Address: 0x0801D8F8 + Address: 0x0801D8FC + Address: 0x0801D900 + Address: 0x0801D904 + Address: 0x0801D908 + Address: 0x0801D90C + Address: 0x0801D910 + Address: 0x0801D914 + Address: 0x0801D918 + Address: 0x0801D91C + Address: 0x0801D920 + Address: 0x0801D924 + Address: 0x0801D934 + Address: 0x0801D938 + Address: 0x0801D93C + Address: 0x0801D940 + Address: 0x0801D944 + Address: 0x0801D948 + Address: 0x0801D94C + Address: 0x0801D950 + Address: 0x0801D954 + Address: 0x0801D958 + Address: 0x0801D95C + Address: 0x0801D960 + Address: 0x0801D964 + Address: 0x0801D968 + Address: 0x0801D96C + Address: 0x0801D970 + Address: 0x0801D974 + Address: 0x0801D978 + Address: 0x0801D99C + Address: 0x0801D9A0 + Address: 0x0801D9A4 + Address: 0x0801D9A8 + Address: 0x0801D9AC + Address: 0x0801D9B0 + Address: 0x0801D9B4 + Address: 0x0801D9B8 + Address: 0x0801D9BC + Address: 0x0801D9C0 + Address: 0x0801D9C4 + Address: 0x0801D9C8 + Address: 0x0801D9CC + Address: 0x0801D9D0 + Address: 0x0801D9D4 + Address: 0x0801D9D8 + Address: 0x0801D9DC + Address: 0x0801D9E0 + Address: 0x0801D9E4 + Address: 0x0801D9E8 + Address: 0x0801D9F4 + Address: 0x0801D9F8 + Address: 0x0801D9FC + Address: 0x0801DA00 + Address: 0x0801DA04 + Address: 0x0801DA08 + Address: 0x0801DA0C + Address: 0x0801DA10 + Address: 0x0801DA14 + Address: 0x0801DA18 + Address: 0x0801DA1C + Address: 0x0801DA20 + Address: 0x0801DA24 + Address: 0x0801DA28 + Address: 0x0801DA2C + Address: 0x0801DA30 + Address: 0x0801DA34 + Address: 0x0801DA38 + Address: 0x0801DA58 + Address: 0x0801DA5C + Address: 0x0801DA60 + Address: 0x0801DA64 + Address: 0x0801DA68 + Address: 0x0801DA6C + Address: 0x0801DA70 + Address: 0x0801DA74 + Address: 0x0801DA78 + Address: 0x0801DA7C + Address: 0x0801DA80 + Address: 0x0801DA84 + Address: 0x0801DA88 + Address: 0x0801DA8C + Address: 0x0801DA90 + Address: 0x0801DA94 + Address: 0x0801DA98 + Address: 0x0801DA9C + Address: 0x0801DAA0 + Address: 0x0801DAA4 + Address: 0x0801DAAC + Address: 0x0801DAB0 + Address: 0x0801DAB4 + Address: 0x0801DAB8 + Address: 0x0801DABC + Address: 0x0801DAC0 + Address: 0x0801DAC4 + Address: 0x0801DAC8 + Address: 0x0801DACC + Address: 0x0801DAD0 + Address: 0x0801DAD4 + Address: 0x0801DAD8 + Address: 0x0801DADC + Address: 0x0801DAE0 + Address: 0x0801DAE4 + Address: 0x0801DAE8 + Address: 0x0801DAEC + Address: 0x0801DB14 + Address: 0x0801DB18 + Address: 0x0801DB1C + Address: 0x0801DB20 + Address: 0x0801DB24 + Address: 0x0801DB28 + Address: 0x0801DB2C + Address: 0x0801DB30 + Address: 0x0801DB34 + Address: 0x0801DB38 + Address: 0x0801DB3C + Address: 0x0801DB40 + Address: 0x0801DB44 + Address: 0x0801DB48 + Address: 0x0801DB4C + Address: 0x0801DB50 + Address: 0x0801DB54 + Address: 0x0801DB58 + Address: 0x0801DB5C + Address: 0x0801DB60 + Address: 0x0801DB64 + Address: 0x0801DB6C + Address: 0x0801DB70 + Address: 0x0801DB74 + Address: 0x0801DB78 + Address: 0x0801DB7C + Address: 0x0801DB80 + Address: 0x0801DB84 + Address: 0x0801DB88 + Address: 0x0801DB8C + Address: 0x0801DB90 + Address: 0x0801DB94 + Address: 0x0801DB98 + Address: 0x0801DB9C + Address: 0x0801DBA0 + Address: 0x0801DBA4 + Address: 0x0801DBA8 + Address: 0x0801DBAC + Address: 0x0801DBCC + Address: 0x0801DBD0 + Address: 0x0801DBD4 + Address: 0x0801DBD8 + Address: 0x0801DBDC + Address: 0x0801DBE0 + Address: 0x0801DBE4 + Address: 0x0801DBE8 + Address: 0x0801DBEC + Address: 0x0801DBF0 + Address: 0x0801DBF4 + Address: 0x0801DBF8 + Address: 0x0801DBFC + Address: 0x0801DC00 + Address: 0x0801DC04 + Address: 0x0801DC08 + Address: 0x0801DC0C + Address: 0x0801DC10 + Address: 0x0801DC14 + Address: 0x0801DC18 + Address: 0x0801DC1C + Address: 0x0801DC20 + Address: 0x0801DC24 + Address: 0x0801DC28 + Address: 0x0801DC2C + Address: 0x0801DC30 + Address: 0x0801DC34 + Address: 0x0801DC38 + Address: 0x0801DC3C + Address: 0x0801DC40 + Address: 0x0801DC44 + Address: 0x0801DC48 + Address: 0x0801DC4C + Address: 0x0801DC50 + Address: 0x0801DC54 + Address: 0x0801DC58 + Address: 0x0801DC5C + Address: 0x0801DC88 + Address: 0x0801DC8C + Address: 0x0801DC90 + Address: 0x0801DC94 + Address: 0x0801DC98 + Address: 0x0801DC9C + Address: 0x0801DCA0 + Address: 0x0801DCA4 + Address: 0x0801DCA8 + Address: 0x0801DCAC + Address: 0x0801DCB0 + Address: 0x0801DCB4 + Address: 0x0801DCB8 + Address: 0x0801DCBC + Address: 0x0801DCC0 + Address: 0x0801DCC4 + Address: 0x0801DCC8 + Address: 0x0801DCCC + Address: 0x0801DCD0 + Address: 0x0801DCD4 + Address: 0x0801DCD8 + Address: 0x0801DCE0 + Address: 0x0801DCE4 + Address: 0x0801DCE8 + Address: 0x0801DCEC + Address: 0x0801DCF0 + Address: 0x0801DCF4 + Address: 0x0801DCF8 + Address: 0x0801DCFC + Address: 0x0801DD00 + Address: 0x0801DD04 + Address: 0x0801DD08 + Address: 0x0801DD0C + Address: 0x0801DD10 + Address: 0x0801DD14 + Address: 0x0801DD18 + Address: 0x0801DD1C + Address: 0x0801DD20 + Address: 0x0801DD40 + Address: 0x0801DD44 + Address: 0x0801DD48 + Address: 0x0801DD4C + Address: 0x0801DD50 + Address: 0x0801DD54 + Address: 0x0801DD58 + Address: 0x0801DD5C + Address: 0x0801DD60 + Address: 0x0801DD64 + Address: 0x0801DD68 + Address: 0x0801DD6C + Address: 0x0801DD70 + Address: 0x0801DD74 + Address: 0x0801DD78 + Address: 0x0801DD7C + Address: 0x0801DD80 + Address: 0x0801DD84 + Address: 0x0801DD88 + Address: 0x0801DD8C + Address: 0x0801DD94 + Address: 0x0801DD98 + Address: 0x0801DD9C + Address: 0x0801DDA0 + Address: 0x0801DDA4 + Address: 0x0801DDA8 + Address: 0x0801DDAC + Address: 0x0801DDB0 + Address: 0x0801DDB4 + Address: 0x0801DDB8 + Address: 0x0801DDBC + Address: 0x0801DDC0 + Address: 0x0801DDC4 + Address: 0x0801DDC8 + Address: 0x0801DDCC + Address: 0x0801DDD0 + Address: 0x0801DDD4 + Address: 0x0801DDFC + Address: 0x0801DE00 + Address: 0x0801DE04 + Address: 0x0801DE08 + Address: 0x0801DE0C + Address: 0x0801DE10 + Address: 0x0801DE14 + Address: 0x0801DE18 + Address: 0x0801DE1C + Address: 0x0801DE20 + Address: 0x0801DE24 + Address: 0x0801DE28 + Address: 0x0801DE2C + Address: 0x0801DE30 + Address: 0x0801DE34 + Address: 0x0801DE38 + Address: 0x0801DE3C + Address: 0x0801DE40 + Address: 0x0801DE44 + Address: 0x0801DE48 + Address: 0x0801DE4C + Address: 0x0801DE54 + Address: 0x0801DE58 + Address: 0x0801DE5C + Address: 0x0801DE60 + Address: 0x0801DE64 + Address: 0x0801DE68 + Address: 0x0801DE6C + Address: 0x0801DE70 + Address: 0x0801DE74 + Address: 0x0801DE78 + Address: 0x0801DE7C + Address: 0x0801DE80 + Address: 0x0801DE84 + Address: 0x0801DE88 + Address: 0x0801DE8C + Address: 0x0801DE90 + Address: 0x0801DE94 + Address: 0x0801DEB4 + Address: 0x0801DEB8 + Address: 0x0801DEBC + Address: 0x0801DEC0 + Address: 0x0801DEC4 + Address: 0x0801DEC8 + Address: 0x0801DECC + Address: 0x0801DED0 + Address: 0x0801DED4 + Address: 0x0801DED8 + Address: 0x0801DEDC + Address: 0x0801DEE0 + Address: 0x0801DEE4 + Address: 0x0801DEE8 + Address: 0x0801DEEC + Address: 0x0801DEF0 + Address: 0x0801DEF4 + Address: 0x0801DEF8 + Address: 0x0801DEFC + Address: 0x0801DF00 + Address: 0x0801DF08 + Address: 0x0801DF0C + Address: 0x0801DF10 + Address: 0x0801DF14 + Address: 0x0801DF18 + Address: 0x0801DF1C + Address: 0x0801DF20 + Address: 0x0801DF24 + Address: 0x0801DF28 + Address: 0x0801DF2C + Address: 0x0801DF30 + Address: 0x0801DF34 + Address: 0x0801DF38 + Address: 0x0801DF3C + Address: 0x0801DF40 + Address: 0x0801DF44 + Address: 0x0801DF48 + Address: 0x0801DF70 + Address: 0x0801DF74 + Address: 0x0801DF78 + Address: 0x0801DF7C + Address: 0x0801DF80 + Address: 0x0801DF84 + Address: 0x0801DF88 + Address: 0x0801DF8C + Address: 0x0801DF90 + Address: 0x0801DF94 + Address: 0x0801DF98 + Address: 0x0801DF9C + Address: 0x0801DFA0 + Address: 0x0801DFA4 + Address: 0x0801DFA8 + Address: 0x0801DFAC + Address: 0x0801DFB0 + Address: 0x0801DFB4 + Address: 0x0801DFB8 + Address: 0x0801DFBC + Address: 0x0801DFC0 + Address: 0x0801DFC8 + Address: 0x0801DFCC + Address: 0x0801DFD0 + Address: 0x0801DFD4 + Address: 0x0801DFD8 + Address: 0x0801DFDC + Address: 0x0801DFE0 + Address: 0x0801DFE4 + Address: 0x0801DFE8 + Address: 0x0801DFEC + Address: 0x0801DFF0 + Address: 0x0801DFF4 + Address: 0x0801DFF8 + Address: 0x0801DFFC + Address: 0x0801E000 + Address: 0x0801E004 + Address: 0x0801E008 + Address: 0x0801E028 + Address: 0x0801E02C + Address: 0x0801E030 + Address: 0x0801E034 + Address: 0x0801E038 + Address: 0x0801E03C + Address: 0x0801E040 + Address: 0x0801E044 + Address: 0x0801E048 + Address: 0x0801E04C + Address: 0x0801E050 + Address: 0x0801E054 + Address: 0x0801E058 + Address: 0x0801E05C + Address: 0x0801E060 + Address: 0x0801E064 + Address: 0x0801E068 + Address: 0x0801E06C + Address: 0x0801E070 + Address: 0x0801E074 + Address: 0x0801E07C + Address: 0x0801E080 + Address: 0x0801E084 + Address: 0x0801E088 + Address: 0x0801E08C + Address: 0x0801E090 + Address: 0x0801E094 + Address: 0x0801E098 + Address: 0x0801E09C + Address: 0x0801E0A0 + Address: 0x0801E0A4 + Address: 0x0801E0A8 + Address: 0x0801E0AC + Address: 0x0801E0B0 + Address: 0x0801E0B4 + Address: 0x0801E0B8 + Address: 0x0801E0BC + Address: 0x0801E0E4 + Address: 0x0801E0E8 + Address: 0x0801E0EC + Address: 0x0801E0F0 + Address: 0x0801E0F4 + Address: 0x0801E0F8 + Address: 0x0801E0FC + Address: 0x0801E100 + Address: 0x0801E104 + Address: 0x0801E108 + Address: 0x0801E10C + Address: 0x0801E110 + Address: 0x0801E114 + Address: 0x0801E118 + Address: 0x0801E11C + Address: 0x0801E120 + Address: 0x0801E124 + Address: 0x0801E128 + Address: 0x0801E12C + Address: 0x0801E130 + Address: 0x0801E134 + Address: 0x0801E13C + Address: 0x0801E140 + Address: 0x0801E144 + Address: 0x0801E148 + Address: 0x0801E14C + Address: 0x0801E150 + Address: 0x0801E154 + Address: 0x0801E158 + Address: 0x0801E15C + Address: 0x0801E160 + Address: 0x0801E164 + Address: 0x0801E168 + Address: 0x0801E16C + Address: 0x0801E170 + Address: 0x0801E174 + Address: 0x0801E178 + Address: 0x0801E17C + Address: 0x0801E1A4 + Address: 0x0801E1A8 + Address: 0x0801E1AC + Address: 0x0801E1B0 + Address: 0x0801E1B4 + Address: 0x0801E1B8 + Address: 0x0801E1BC + Address: 0x0801E1C0 + Address: 0x0801E1C4 + Address: 0x0801E1C8 + Address: 0x0801E1CC + Address: 0x0801E1D0 + Address: 0x0801E1D4 + Address: 0x0801E1D8 + Address: 0x0801E1DC + Address: 0x0801E1E0 + Address: 0x0801E1E4 + Address: 0x0801E1E8 + Address: 0x0801E1EC + Address: 0x0801E1F0 + Address: 0x0801E1F4 + Address: 0x0801E1F8 + Address: 0x0801E1FC + Address: 0x0801E200 + Address: 0x0801E204 + Address: 0x0801E208 + Address: 0x0801E20C + Address: 0x0801E210 + Address: 0x0801E214 + Address: 0x0801E218 + Address: 0x0801E21C + Address: 0x0801E220 + Address: 0x0801E224 + Address: 0x0801E228 + Address: 0x0801E22C + Address: 0x0801E230 + Address: 0x0801E234 + Address: 0x0801E258 + Address: 0x0801E25C + Address: 0x0801E260 + Address: 0x0801E264 + Address: 0x0801E268 + Address: 0x0801E26C + Address: 0x0801E270 + Address: 0x0801E274 + Address: 0x0801E278 + Address: 0x0801E27C + Address: 0x0801E280 + Address: 0x0801E284 + Address: 0x0801E288 + Address: 0x0801E28C + Address: 0x0801E290 + Address: 0x0801E294 + Address: 0x0801E298 + Address: 0x0801E29C + Address: 0x0801E2A0 + Address: 0x0801E2A4 + Address: 0x0801E2B4 + Address: 0x0801E2B8 + Address: 0x0801E2BC + Address: 0x0801E2C0 + Address: 0x0801E2C4 + Address: 0x0801E2C8 + Address: 0x0801E2CC + Address: 0x0801E2D0 + Address: 0x0801E2D4 + Address: 0x0801E2D8 + Address: 0x0801E2DC + Address: 0x0801E2E0 + Address: 0x0801E2E4 + Address: 0x0801E2E8 + Address: 0x0801E2EC + Address: 0x0801E2F0 + Address: 0x0801E2F4 + Address: 0x0801E2F8 + Address: 0x0801E318 + Address: 0x0801E31C + Address: 0x0801E320 + Address: 0x0801E324 + Address: 0x0801E328 + Address: 0x0801E32C + Address: 0x0801E330 + Address: 0x0801E334 + Address: 0x0801E338 + Address: 0x0801E33C + Address: 0x0801E340 + Address: 0x0801E344 + Address: 0x0801E348 + Address: 0x0801E34C + Address: 0x0801E350 + Address: 0x0801E354 + Address: 0x0801E358 + Address: 0x0801E35C + Address: 0x0801E360 + Address: 0x0801E364 + Address: 0x0801E370 + Address: 0x0801E374 + Address: 0x0801E378 + Address: 0x0801E37C + Address: 0x0801E380 + Address: 0x0801E384 + Address: 0x0801E388 + Address: 0x0801E38C + Address: 0x0801E390 + Address: 0x0801E394 + Address: 0x0801E398 + Address: 0x0801E39C + Address: 0x0801E3A0 + Address: 0x0801E3A4 + Address: 0x0801E3A8 + Address: 0x0801E3AC + Address: 0x0801E3B0 + Address: 0x0801E3B4 + Address: 0x0801E3CC + Address: 0x0801E3D0 + Address: 0x0801E3D4 + Address: 0x0801E3D8 + Address: 0x0801E3DC + Address: 0x0801E3E0 + Address: 0x0801E3E4 + Address: 0x0801E3E8 + Address: 0x0801E3EC + Address: 0x0801E3F0 + Address: 0x0801E3F4 + Address: 0x0801E3F8 + Address: 0x0801E3FC + Address: 0x0801E400 + Address: 0x0801E404 + Address: 0x0801E408 + Address: 0x0801E40C + Address: 0x0801E410 + Address: 0x0801E414 + Address: 0x0801E428 + Address: 0x0801E42C + Address: 0x0801E430 + Address: 0x0801E434 + Address: 0x0801E438 + Address: 0x0801E43C + Address: 0x0801E440 + Address: 0x0801E444 + Address: 0x0801E448 + Address: 0x0801E44C + Address: 0x0801E450 + Address: 0x0801E454 + Address: 0x0801E458 + Address: 0x0801E45C + Address: 0x0801E460 + Address: 0x0801E464 + Address: 0x0801E468 + Address: 0x0801E46C + Address: 0x0801E470 + Address: 0x0801E490 + Address: 0x0801E494 + Address: 0x0801E498 + Address: 0x0801E49C + Address: 0x0801E4A0 + Address: 0x0801E4A4 + Address: 0x0801E4A8 + Address: 0x0801E4AC + Address: 0x0801E4B0 + Address: 0x0801E4B4 + Address: 0x0801E4B8 + Address: 0x0801E4BC + Address: 0x0801E4C0 + Address: 0x0801E4C4 + Address: 0x0801E4C8 + Address: 0x0801E4CC + Address: 0x0801E4D0 + Address: 0x0801E4D4 + Address: 0x0801E4D8 + Address: 0x0801E4DC + Address: 0x0801E4EC + Address: 0x0801E4F0 + Address: 0x0801E4F4 + Address: 0x0801E4F8 + Address: 0x0801E4FC + Address: 0x0801E500 + Address: 0x0801E504 + Address: 0x0801E508 + Address: 0x0801E50C + Address: 0x0801E510 + Address: 0x0801E514 + Address: 0x0801E518 + Address: 0x0801E51C + Address: 0x0801E520 + Address: 0x0801E524 + Address: 0x0801E528 + Address: 0x0801E52C + Address: 0x0801E530 + Address: 0x0801E548 + Address: 0x0801E54C + Address: 0x0801E550 + Address: 0x0801E554 + Address: 0x0801E558 + Address: 0x0801E55C + Address: 0x0801E560 + Address: 0x0801E564 + Address: 0x0801E568 + Address: 0x0801E56C + Address: 0x0801E570 + Address: 0x0801E574 + Address: 0x0801E578 + Address: 0x0801E57C + Address: 0x0801E580 + Address: 0x0801E584 + Address: 0x0801E588 + Address: 0x0801E58C + Address: 0x0801E590 + Address: 0x0801E59C + Address: 0x0801E5A0 + Address: 0x0801E5A4 + Address: 0x0801E5A8 + Address: 0x0801E5AC + Address: 0x0801E5B0 + Address: 0x0801E5B4 + Address: 0x0801E5B8 + Address: 0x0801E5BC + Address: 0x0801E5C0 + Address: 0x0801E5C4 + Address: 0x0801E5C8 + Address: 0x0801E5CC + Address: 0x0801E5D0 + Address: 0x0801E5D4 + Address: 0x0801E5D8 + Address: 0x0801E5DC + Address: 0x0801E5E0 + Address: 0x0801E604 + Address: 0x0801E608 + Address: 0x0801E60C + Address: 0x0801E610 + Address: 0x0801E614 + Address: 0x0801E618 + Address: 0x0801E61C + Address: 0x0801E620 + Address: 0x0801E624 + Address: 0x0801E628 + Address: 0x0801E62C + Address: 0x0801E630 + Address: 0x0801E634 + Address: 0x0801E638 + Address: 0x0801E63C + Address: 0x0801E640 + Address: 0x0801E644 + Address: 0x0801E648 + Address: 0x0801E64C + Address: 0x0801E650 + Address: 0x0801E65C + Address: 0x0801E660 + Address: 0x0801E664 + Address: 0x0801E668 + Address: 0x0801E66C + Address: 0x0801E670 + Address: 0x0801E674 + Address: 0x0801E678 + Address: 0x0801E67C + Address: 0x0801E680 + Address: 0x0801E684 + Address: 0x0801E688 + Address: 0x0801E68C + Address: 0x0801E690 + Address: 0x0801E694 + Address: 0x0801E698 + Address: 0x0801E69C + Address: 0x0801E6A0 + Address: 0x0801E6BC + Address: 0x0801E6C0 + Address: 0x0801E6C4 + Address: 0x0801E6C8 + Address: 0x0801E6CC + Address: 0x0801E6D0 + Address: 0x0801E6D4 + Address: 0x0801E6D8 + Address: 0x0801E6DC + Address: 0x0801E6E0 + Address: 0x0801E6E4 + Address: 0x0801E6E8 + Address: 0x0801E6EC + Address: 0x0801E6F0 + Address: 0x0801E6F4 + Address: 0x0801E6F8 + Address: 0x0801E6FC + Address: 0x0801E700 + Address: 0x0801E704 + Address: 0x0801E708 + Address: 0x0801E710 + Address: 0x0801E714 + Address: 0x0801E718 + Address: 0x0801E71C + Address: 0x0801E720 + Address: 0x0801E724 + Address: 0x0801E728 + Address: 0x0801E72C + Address: 0x0801E730 + Address: 0x0801E734 + Address: 0x0801E738 + Address: 0x0801E73C + Address: 0x0801E740 + Address: 0x0801E744 + Address: 0x0801E748 + Address: 0x0801E74C + Address: 0x0801E750 + Address: 0x0801E778 + Address: 0x0801E77C + Address: 0x0801E780 + Address: 0x0801E784 + Address: 0x0801E788 + Address: 0x0801E78C + Address: 0x0801E790 + Address: 0x0801E794 + Address: 0x0801E798 + Address: 0x0801E79C + Address: 0x0801E7A0 + Address: 0x0801E7A4 + Address: 0x0801E7A8 + Address: 0x0801E7AC + Address: 0x0801E7B0 + Address: 0x0801E7B4 + Address: 0x0801E7B8 + Address: 0x0801E7BC + Address: 0x0801E7C0 + Address: 0x0801E7C4 + Address: 0x0801E7C8 + Address: 0x0801E7D0 + Address: 0x0801E7D4 + Address: 0x0801E7D8 + Address: 0x0801E7DC + Address: 0x0801E7E0 + Address: 0x0801E7E4 + Address: 0x0801E7E8 + Address: 0x0801E7EC + Address: 0x0801E7F0 + Address: 0x0801E7F4 + Address: 0x0801E7F8 + Address: 0x0801E7FC + Address: 0x0801E800 + Address: 0x0801E804 + Address: 0x0801E808 + Address: 0x0801E80C + Address: 0x0801E810 + Address: 0x0801E834 + Address: 0x0801E838 + Address: 0x0801E83C + Address: 0x0801E840 + Address: 0x0801E844 + Address: 0x0801E848 + Address: 0x0801E84C + Address: 0x0801E850 + Address: 0x0801E854 + Address: 0x0801E858 + Address: 0x0801E85C + Address: 0x0801E860 + Address: 0x0801E864 + Address: 0x0801E868 + Address: 0x0801E86C + Address: 0x0801E870 + Address: 0x0801E874 + Address: 0x0801E878 + Address: 0x0801E87C + Address: 0x0801E880 + Address: 0x0801E884 + Address: 0x0801E888 + Address: 0x0801E88C + Address: 0x0801E890 + Address: 0x0801E894 + Address: 0x0801E898 + Address: 0x0801E89C + Address: 0x0801E8A0 + Address: 0x0801E8A4 + Address: 0x0801E8A8 + Address: 0x0801E8AC + Address: 0x0801E8B0 + Address: 0x0801E8B4 + Address: 0x0801E8B8 + Address: 0x0801E8BC + Address: 0x0801E8C0 + Address: 0x0801E8C4 + Address: 0x0801E8E8 + Address: 0x0801E8EC + Address: 0x0801E8F0 + Address: 0x0801E8F4 + Address: 0x0801E8F8 + Address: 0x0801E8FC + Address: 0x0801E900 + Address: 0x0801E904 + Address: 0x0801E908 + Address: 0x0801E90C + Address: 0x0801E910 + Address: 0x0801E914 + Address: 0x0801E918 + Address: 0x0801E91C + Address: 0x0801E920 + Address: 0x0801E924 + Address: 0x0801E928 + Address: 0x0801E92C + Address: 0x0801E930 + Address: 0x0801E934 + Address: 0x0801E938 + Address: 0x0801E940 + Address: 0x0801E944 + Address: 0x0801E948 + Address: 0x0801E94C + Address: 0x0801E950 + Address: 0x0801E954 + Address: 0x0801E958 + Address: 0x0801E95C + Address: 0x0801E960 + Address: 0x0801E964 + Address: 0x0801E968 + Address: 0x0801E96C + Address: 0x0801E970 + Address: 0x0801E974 + Address: 0x0801E978 + Address: 0x0801E97C + Address: 0x0801E980 + Address: 0x0801E9A4 + Address: 0x0801E9A8 + Address: 0x0801E9AC + Address: 0x0801E9B0 + Address: 0x0801E9B4 + Address: 0x0801E9B8 + Address: 0x0801E9BC + Address: 0x0801E9C0 + Address: 0x0801E9C4 + Address: 0x0801E9C8 + Address: 0x0801E9CC + Address: 0x0801E9D0 + Address: 0x0801E9D4 + Address: 0x0801E9D8 + Address: 0x0801E9DC + Address: 0x0801E9E0 + Address: 0x0801E9E4 + Address: 0x0801E9E8 + Address: 0x0801E9EC + Address: 0x0801E9F0 + Address: 0x0801E9F4 + Address: 0x0801E9F8 + Address: 0x0801E9FC + Address: 0x0801EA00 + Address: 0x0801EA04 + Address: 0x0801EA08 + Address: 0x0801EA0C + Address: 0x0801EA10 + Address: 0x0801EA14 + Address: 0x0801EA18 + Address: 0x0801EA1C + Address: 0x0801EA20 + Address: 0x0801EA24 + Address: 0x0801EA28 + Address: 0x0801EA2C + Address: 0x0801EA30 + Address: 0x0801EA34 + Address: 0x0801EA58 + Address: 0x0801EA5C + Address: 0x0801EA60 + Address: 0x0801EA64 + Address: 0x0801EA68 + Address: 0x0801EA6C + Address: 0x0801EA70 + Address: 0x0801EA74 + Address: 0x0801EA78 + Address: 0x0801EA7C + Address: 0x0801EA80 + Address: 0x0801EA84 + Address: 0x0801EA88 + Address: 0x0801EA8C + Address: 0x0801EA90 + Address: 0x0801EA94 + Address: 0x0801EA98 + Address: 0x0801EA9C + Address: 0x0801EAA0 + Address: 0x0801EAA4 + Address: 0x0801EAA8 + Address: 0x0801EAB0 + Address: 0x0801EAB4 + Address: 0x0801EAB8 + Address: 0x0801EABC + Address: 0x0801EAC0 + Address: 0x0801EAC4 + Address: 0x0801EAC8 + Address: 0x0801EACC + Address: 0x0801EAD0 + Address: 0x0801EAD4 + Address: 0x0801EAD8 + Address: 0x0801EADC + Address: 0x0801EAE0 + Address: 0x0801EAE4 + Address: 0x0801EAE8 + Address: 0x0801EAEC + Address: 0x0801EAF0 + Address: 0x0801EB18 + Address: 0x0801EB1C + Address: 0x0801EB20 + Address: 0x0801EB24 + Address: 0x0801EB28 + Address: 0x0801EB2C + Address: 0x0801EB30 + Address: 0x0801EB34 + Address: 0x0801EB38 + Address: 0x0801EB3C + Address: 0x0801EB40 + Address: 0x0801EB44 + Address: 0x0801EB48 + Address: 0x0801EB4C + Address: 0x0801EB50 + Address: 0x0801EB54 + Address: 0x0801EB58 + Address: 0x0801EB5C + Address: 0x0801EB60 + Address: 0x0801EB64 + Address: 0x0801EB68 + Address: 0x0801EB70 + Address: 0x0801EB74 + Address: 0x0801EB78 + Address: 0x0801EB7C + Address: 0x0801EB80 + Address: 0x0801EB84 + Address: 0x0801EB88 + Address: 0x0801EB8C + Address: 0x0801EB90 + Address: 0x0801EB94 + Address: 0x0801EB98 + Address: 0x0801EB9C + Address: 0x0801EBA0 + Address: 0x0801EBA4 + Address: 0x0801EBA8 + Address: 0x0801EBAC + Address: 0x0801EBB0 + Address: 0x0801EBD0 + Address: 0x0801EBD4 + Address: 0x0801EBD8 + Address: 0x0801EBDC + Address: 0x0801EBE0 + Address: 0x0801EBE4 + Address: 0x0801EBE8 + Address: 0x0801EBEC + Address: 0x0801EBF0 + Address: 0x0801EBF4 + Address: 0x0801EBF8 + Address: 0x0801EBFC + Address: 0x0801EC00 + Address: 0x0801EC04 + Address: 0x0801EC08 + Address: 0x0801EC0C + Address: 0x0801EC10 + Address: 0x0801EC14 + Address: 0x0801EC18 + Address: 0x0801EC1C + Address: 0x0801EC2C + Address: 0x0801EC30 + Address: 0x0801EC34 + Address: 0x0801EC38 + Address: 0x0801EC3C + Address: 0x0801EC40 + Address: 0x0801EC44 + Address: 0x0801EC48 + Address: 0x0801EC4C + Address: 0x0801EC50 + Address: 0x0801EC54 + Address: 0x0801EC58 + Address: 0x0801EC5C + Address: 0x0801EC60 + Address: 0x0801EC64 + Address: 0x0801EC68 + Address: 0x0801EC6C + Address: 0x0801EC70 + Address: 0x0801EC90 + Address: 0x0801EC94 + Address: 0x0801EC98 + Address: 0x0801EC9C + Address: 0x0801ECA0 + Address: 0x0801ECA4 + Address: 0x0801ECA8 + Address: 0x0801ECAC + Address: 0x0801ECB0 + Address: 0x0801ECB4 + Address: 0x0801ECB8 + Address: 0x0801ECBC + Address: 0x0801ECC0 + Address: 0x0801ECC4 + Address: 0x0801ECC8 + Address: 0x0801ECCC + Address: 0x0801ECD0 + Address: 0x0801ECD4 + Address: 0x0801ECD8 + Address: 0x0801ECDC + Address: 0x0801ECE4 + Address: 0x0801ECE8 + Address: 0x0801ECEC + Address: 0x0801ECF0 + Address: 0x0801ECF4 + Address: 0x0801ECF8 + Address: 0x0801ECFC + Address: 0x0801ED00 + Address: 0x0801ED04 + Address: 0x0801ED08 + Address: 0x0801ED0C + Address: 0x0801ED10 + Address: 0x0801ED14 + Address: 0x0801ED18 + Address: 0x0801ED1C + Address: 0x0801ED20 + Address: 0x0801ED24 + Address: 0x0801ED48 + Address: 0x0801ED4C + Address: 0x0801ED50 + Address: 0x0801ED54 + Address: 0x0801ED58 + Address: 0x0801ED5C + Address: 0x0801ED60 + Address: 0x0801ED64 + Address: 0x0801ED68 + Address: 0x0801ED6C + Address: 0x0801ED70 + Address: 0x0801ED74 + Address: 0x0801ED78 + Address: 0x0801ED7C + Address: 0x0801ED80 + Address: 0x0801ED84 + Address: 0x0801ED88 + Address: 0x0801ED8C + Address: 0x0801ED90 + Address: 0x0801ED94 + Address: 0x0801EDA0 + Address: 0x0801EDA4 + Address: 0x0801EDA8 + Address: 0x0801EDAC + Address: 0x0801EDB0 + Address: 0x0801EDB4 + Address: 0x0801EDB8 + Address: 0x0801EDBC + Address: 0x0801EDC0 + Address: 0x0801EDC4 + Address: 0x0801EDC8 + Address: 0x0801EDCC + Address: 0x0801EDD0 + Address: 0x0801EDD4 + Address: 0x0801EDD8 + Address: 0x0801EDDC + Address: 0x0801EDE0 + Address: 0x0801EDE4 + Address: 0x0801EE04 + Address: 0x0801EE08 + Address: 0x0801EE0C + Address: 0x0801EE10 + Address: 0x0801EE14 + Address: 0x0801EE18 + Address: 0x0801EE1C + Address: 0x0801EE20 + Address: 0x0801EE24 + Address: 0x0801EE28 + Address: 0x0801EE2C + Address: 0x0801EE30 + Address: 0x0801EE34 + Address: 0x0801EE38 + Address: 0x0801EE3C + Address: 0x0801EE40 + Address: 0x0801EE44 + Address: 0x0801EE48 + Address: 0x0801EE4C + Address: 0x0801EE50 + Address: 0x0801EE54 + Address: 0x0801EE58 + Address: 0x0801EE5C + Address: 0x0801EE60 + Address: 0x0801EE64 + Address: 0x0801EE68 + Address: 0x0801EE6C + Address: 0x0801EE70 + Address: 0x0801EE74 + Address: 0x0801EE78 + Address: 0x0801EE7C + Address: 0x0801EE80 + Address: 0x0801EE84 + Address: 0x0801EE88 + Address: 0x0801EE8C + Address: 0x0801EE90 + Address: 0x0801EE94 + Address: 0x0801EEB8 + Address: 0x0801EEBC + Address: 0x0801EEC0 + Address: 0x0801EEC4 + Address: 0x0801EEC8 + Address: 0x0801EECC + Address: 0x0801EED0 + Address: 0x0801EED4 + Address: 0x0801EED8 + Address: 0x0801EEDC + Address: 0x0801EEE0 + Address: 0x0801EEE4 + Address: 0x0801EEE8 + Address: 0x0801EEEC + Address: 0x0801EEF0 + Address: 0x0801EEF4 + Address: 0x0801EEF8 + Address: 0x0801EEFC + Address: 0x0801EF00 + Address: 0x0801EF04 + Address: 0x0801EF14 + Address: 0x0801EF18 + Address: 0x0801EF1C + Address: 0x0801EF20 + Address: 0x0801EF24 + Address: 0x0801EF28 + Address: 0x0801EF2C + Address: 0x0801EF30 + Address: 0x0801EF34 + Address: 0x0801EF38 + Address: 0x0801EF3C + Address: 0x0801EF40 + Address: 0x0801EF44 + Address: 0x0801EF48 + Address: 0x0801EF4C + Address: 0x0801EF50 + Address: 0x0801EF54 + Address: 0x0801EF58 + Address: 0x0801EF78 + Address: 0x0801EF7C + Address: 0x0801EF80 + Address: 0x0801EF84 + Address: 0x0801EF88 + Address: 0x0801EF8C + Address: 0x0801EF90 + Address: 0x0801EF94 + Address: 0x0801EF98 + Address: 0x0801EF9C + Address: 0x0801EFA0 + Address: 0x0801EFA4 + Address: 0x0801EFA8 + Address: 0x0801EFAC + Address: 0x0801EFB0 + Address: 0x0801EFB4 + Address: 0x0801EFB8 + Address: 0x0801EFBC + Address: 0x0801EFC0 + Address: 0x0801EFC4 + Address: 0x0801EFCC + Address: 0x0801EFD0 + Address: 0x0801EFD4 + Address: 0x0801EFD8 + Address: 0x0801EFDC + Address: 0x0801EFE0 + Address: 0x0801EFE4 + Address: 0x0801EFE8 + Address: 0x0801EFEC + Address: 0x0801EFF0 + Address: 0x0801EFF4 + Address: 0x0801EFF8 Done! + CRCs are equal. Index: ecs_cellMon/firmware/.cproject =================================================================== --- ecs_cellMon/firmware/.cproject (revision 3) +++ ecs_cellMon/firmware/.cproject (revision 3) @@ -0,0 +1,432 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: ecs_cellMon/firmware/.mxproject =================================================================== --- ecs_cellMon/firmware/.mxproject (revision 3) +++ ecs_cellMon/firmware/.mxproject (revision 3) @@ -0,0 +1,39 @@ +[PreviousLibFiles] +LibFiles=Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ramfunc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h;Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_exti.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c;Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ramfunc.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h;Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_exti.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h;Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h;Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h;Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h;Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h;Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; + +[PreviousUsedSW4STM32Files] +SourceFiles=..\Core\Src\main.c;..\Core\Src\gpio.c;..\Core\Src\adc.c;..\Core\Src\comp.c;..\Core\Src\dac.c;..\Core\Src\dma.c;..\Core\Src\tim.c;..\Core\Src\usart.c;..\Core\Src\stm32g0xx_it.c;..\Core\Src\stm32g0xx_hal_msp.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c;..\Core\Src/system_stm32g0xx.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c;..\Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c;..\Core\Src/system_stm32g0xx.c;..\Drivers/CMSIS/Device/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c;; +HeaderPath=..\Drivers\STM32G0xx_HAL_Driver\Inc;..\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32G0xx\Include;..\Drivers\CMSIS\Include;..\Core\Inc; +CDefines=USE_HAL_DRIVER;STM32G071xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + +[PreviousGenFiles] +AdvancedFolderStructure=true +HeaderFileListSize=10 +HeaderFiles#0=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Inc/gpio.h +HeaderFiles#1=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Inc/adc.h +HeaderFiles#2=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Inc/comp.h +HeaderFiles#3=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Inc/dac.h +HeaderFiles#4=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Inc/dma.h +HeaderFiles#5=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Inc/tim.h +HeaderFiles#6=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Inc/usart.h +HeaderFiles#7=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Inc/stm32g0xx_it.h +HeaderFiles#8=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Inc/stm32g0xx_hal_conf.h +HeaderFiles#9=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Inc/main.h +HeaderFolderListSize=1 +HeaderPath#0=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Inc +HeaderFiles=; +SourceFileListSize=10 +SourceFiles#0=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Src/gpio.c +SourceFiles#1=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Src/adc.c +SourceFiles#2=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Src/comp.c +SourceFiles#3=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Src/dac.c +SourceFiles#4=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Src/dma.c +SourceFiles#5=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Src/tim.c +SourceFiles#6=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Src/usart.c +SourceFiles#7=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Src/stm32g0xx_it.c +SourceFiles#8=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Src/stm32g0xx_hal_msp.c +SourceFiles#9=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Src/main.c +SourceFolderListSize=1 +SourcePath#0=D:/projekte/ecs_lipro/branches/lipro1-6_v2/firmware/Core/Src +SourceFiles=; + Index: ecs_cellMon/firmware/.project =================================================================== --- ecs_cellMon/firmware/.project (revision 3) +++ ecs_cellMon/firmware/.project (revision 3) @@ -0,0 +1,30 @@ + + + firmware + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + fr.ac6.mcu.ide.core.MCUProjectNature + + + + + Index: ecs_cellMon/firmware/Core/Inc/adc.h =================================================================== --- ecs_cellMon/firmware/Core/Inc/adc.h (revision 3) +++ ecs_cellMon/firmware/Core/Inc/adc.h (revision 3) @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file adc.h + * @brief This file contains all the function prototypes for + * the adc.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __ADC_H__ +#define __ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern ADC_HandleTypeDef hadc1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_ADC1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Inc/comp.h =================================================================== --- ecs_cellMon/firmware/Core/Inc/comp.h (revision 3) +++ ecs_cellMon/firmware/Core/Inc/comp.h (revision 3) @@ -0,0 +1,54 @@ +/** + ****************************************************************************** + * @file comp.h + * @brief This file contains all the function prototypes for + * the comp.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __COMP_H__ +#define __COMP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern COMP_HandleTypeDef hcomp1; +extern COMP_HandleTypeDef hcomp2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_COMP1_Init(void); +void MX_COMP2_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __COMP_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Inc/dac.h =================================================================== --- ecs_cellMon/firmware/Core/Inc/dac.h (revision 3) +++ ecs_cellMon/firmware/Core/Inc/dac.h (revision 3) @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file dac.h + * @brief This file contains all the function prototypes for + * the dac.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DAC_H__ +#define __DAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern DAC_HandleTypeDef hdac1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DAC1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Inc/dma.h =================================================================== --- ecs_cellMon/firmware/Core/Inc/dma.h (revision 3) +++ ecs_cellMon/firmware/Core/Inc/dma.h (revision 3) @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file dma.h + * @brief This file contains all the function prototypes for + * the dma.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA_H__ +#define __DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* DMA memory to memory transfer handles -------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DMA_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Inc/gpio.h =================================================================== --- ecs_cellMon/firmware/Core/Inc/gpio.h (revision 3) +++ ecs_cellMon/firmware/Core/Inc/gpio.h (revision 3) @@ -0,0 +1,49 @@ +/** + ****************************************************************************** + * @file gpio.h + * @brief This file contains all the function prototypes for + * the gpio.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_GPIO_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif +#endif /*__ GPIO_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Inc/main.h =================================================================== --- ecs_cellMon/firmware/Core/Inc/main.h (revision 3) +++ ecs_cellMon/firmware/Core/Inc/main.h (revision 3) @@ -0,0 +1,99 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +#define COMP1_INP_I_SENSE_Pin GPIO_PIN_1 +#define COMP1_INP_I_SENSE_GPIO_Port GPIOA +#define COMP2_INM_U_TR_SENSE_Pin GPIO_PIN_2 +#define COMP2_INM_U_TR_SENSE_GPIO_Port GPIOA +#define COMP2_INP_U_TR_REF_Pin GPIO_PIN_3 +#define COMP2_INP_U_TR_REF_GPIO_Port GPIOA +#define DAC1_OUT1_I_CTR_TP_Pin GPIO_PIN_4 +#define DAC1_OUT1_I_CTR_TP_GPIO_Port GPIOA +#define ADC1_IN5_I_SENSE_AVG_Pin GPIO_PIN_5 +#define ADC1_IN5_I_SENSE_AVG_GPIO_Port GPIOA +#define ADC1_IN6_UIN_SENSE_Pin GPIO_PIN_6 +#define ADC1_IN6_UIN_SENSE_GPIO_Port GPIOA +#define ADC1_IN7_TEMP_SENSE_Pin GPIO_PIN_7 +#define ADC1_IN7_TEMP_SENSE_GPIO_Port GPIOA +#define COMP1_OUT_I_PEAK_Pin GPIO_PIN_11 +#define COMP1_OUT_I_PEAK_GPIO_Port GPIOA +#define LVP_Pin GPIO_PIN_0 +#define LVP_GPIO_Port GPIOD +#define OVP_Pin GPIO_PIN_1 +#define OVP_GPIO_Port GPIOD +#define LED_FUNC_Pin GPIO_PIN_2 +#define LED_FUNC_GPIO_Port GPIOD +#define LED_ERROR_Pin GPIO_PIN_3 +#define LED_ERROR_GPIO_Port GPIOD +#define BUZZER_Pin GPIO_PIN_6 +#define BUZZER_GPIO_Port GPIOC +#define COMP2_OUT_DISCHARGE_Pin GPIO_PIN_5 +#define COMP2_OUT_DISCHARGE_GPIO_Port GPIOB +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Inc/stm32g0xx_hal_conf.h =================================================================== --- ecs_cellMon/firmware/Core/Inc/stm32g0xx_hal_conf.h (revision 3) +++ ecs_cellMon/firmware/Core/Inc/stm32g0xx_hal_conf.h (revision 3) @@ -0,0 +1,352 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_CONF_H +#define STM32G0xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +/* #define HAL_CEC_MODULE_ENABLED */ +#define HAL_COMP_MODULE_ENABLED +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED +/* #define HAL_EXTI_MODULE_ENABLED */ +/* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief This is the list of modules where register callback can be used + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0u +#define USE_HAL_CEC_REGISTER_CALLBACKS 0u +#define USE_HAL_COMP_REGISTER_CALLBACKS 0u +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u +#define USE_HAL_DAC_REGISTER_CALLBACKS 0u +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0u +#define USE_HAL_HCD_REGISTER_CALLBACKS 0u +#define USE_HAL_I2C_REGISTER_CALLBACKS 0u +#define USE_HAL_I2S_REGISTER_CALLBACKS 0u +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u +#define USE_HAL_PCD_REGISTER_CALLBACKS 0u +#define USE_HAL_RNG_REGISTER_CALLBACKS 0u +#define USE_HAL_RTC_REGISTER_CALLBACKS 0u +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u +#define USE_HAL_SPI_REGISTER_CALLBACKS 0u +#define USE_HAL_TIM_REGISTER_CALLBACKS 0u +#define USE_HAL_UART_REGISTER_CALLBACKS 0u +#define USE_HAL_USART_REGISTER_CALLBACKS 0u +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) + #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ +#endif + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations +in voltage and temperature.*/ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S1 peripheral + * This value is used by the RCC HAL module to compute the I2S1 clock source + * frequency. + */ +#if !defined (EXTERNAL_I2S1_CLOCK_VALUE) +#define EXTERNAL_I2S1_CLOCK_VALUE (48000UL) /*!< Value of the I2S1 External clock source in Hz*/ +#endif /* EXTERNAL_I2S1_CLOCK_VALUE */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief External clock source for I2S2 peripheral + * This value is used by the RCC HAL module to compute the I2S2 clock source + * frequency. + */ +#if !defined (EXTERNAL_I2S2_CLOCK_VALUE) + #define EXTERNAL_I2S2_CLOCK_VALUE 48000U /*!< Value of the I2S2 External clock source in Hz*/ +#endif /* EXTERNAL_I2S2_CLOCK_VALUE */ +#endif + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define INSTRUCTION_CACHE_ENABLE 1U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ + #define USE_FULL_ASSERT 1U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include modules header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32g0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32g0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32g0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32g0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32g0xx_hal_adc.h" +#include "stm32g0xx_hal_adc_ex.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED +#include "stm32g0xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32g0xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32g0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32g0xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32g0xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32g0xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32g0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32g0xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32g0xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32g0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32g0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32g0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32g0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32g0xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32g0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32g0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32g0xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32g0xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32g0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32g0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32g0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32g0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32g0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32g0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32g0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for functions parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Inc/stm32g0xx_it.h =================================================================== --- ecs_cellMon/firmware/Core/Inc/stm32g0xx_it.h (revision 3) +++ ecs_cellMon/firmware/Core/Inc/stm32g0xx_it.h (revision 3) @@ -0,0 +1,68 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32G0xx_IT_H +#define __STM32G0xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void DMA1_Channel1_IRQHandler(void); +void ADC1_COMP_IRQHandler(void); +void USART1_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32G0xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Inc/tim.h =================================================================== --- ecs_cellMon/firmware/Core/Inc/tim.h (revision 3) +++ ecs_cellMon/firmware/Core/Inc/tim.h (revision 3) @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file tim.h + * @brief This file contains all the function prototypes for + * the tim.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIM_H__ +#define __TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern TIM_HandleTypeDef htim1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_TIM1_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Inc/usart.h =================================================================== --- ecs_cellMon/firmware/Core/Inc/usart.h (revision 3) +++ ecs_cellMon/firmware/Core/Inc/usart.h (revision 3) @@ -0,0 +1,52 @@ +/** + ****************************************************************************** + * @file usart.h + * @brief This file contains all the function prototypes for + * the usart.c file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USART_H__ +#define __USART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern UART_HandleTypeDef huart1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_USART1_UART_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USART_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Src/adc.c =================================================================== --- ecs_cellMon/firmware/Core/Src/adc.c (revision 3) +++ ecs_cellMon/firmware/Core/Src/adc.c (revision 3) @@ -0,0 +1,203 @@ +/** + ****************************************************************************** + * @file adc.c + * @brief This file provides code for the configuration + * of the ADC instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "adc.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +ADC_HandleTypeDef hadc1; +DMA_HandleTypeDef hdma_adc1; + +/* ADC1 init function */ +void MX_ADC1_Init(void) +{ + + /* USER CODE BEGIN ADC1_Init 0 */ + + /* USER CODE END ADC1_Init 0 */ + + ADC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN ADC1_Init 1 */ + + /* USER CODE END ADC1_Init 1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV8; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; + hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; + hadc1.Init.LowPowerAutoWait = DISABLE; + hadc1.Init.LowPowerAutoPowerOff = DISABLE; + hadc1.Init.ContinuousConvMode = ENABLE; + hadc1.Init.NbrOfConversion = 4; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.DMAContinuousRequests = ENABLE; + hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; + hadc1.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_160CYCLES_5; + hadc1.Init.SamplingTimeCommon2 = ADC_SAMPLETIME_160CYCLES_5; + hadc1.Init.OversamplingMode = ENABLE; + hadc1.Init.Oversampling.Ratio = ADC_OVERSAMPLING_RATIO_16; + hadc1.Init.Oversampling.RightBitShift = ADC_RIGHTBITSHIFT_NONE; + hadc1.Init.Oversampling.TriggeredMode = ADC_TRIGGEREDMODE_SINGLE_TRIGGER; + hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_LOW; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_5; + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_1; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_6; + sConfig.Rank = ADC_REGULAR_RANK_2; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_7; + sConfig.Rank = ADC_REGULAR_RANK_3; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /** Configure Regular Channel + */ + sConfig.Channel = ADC_CHANNEL_8; + sConfig.Rank = ADC_REGULAR_RANK_4; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ + +} + +void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(adcHandle->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* ADC1 clock enable */ + __HAL_RCC_ADC_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 + PA6 ------> ADC1_IN6 + PA7 ------> ADC1_IN7 + PB0 ------> ADC1_IN8 + */ + GPIO_InitStruct.Pin = ADC1_IN5_I_SENSE_AVG_Pin|ADC1_IN6_UIN_SENSE_Pin|ADC1_IN7_TEMP_SENSE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_0; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* ADC1 DMA Init */ + /* ADC1 Init */ + hdma_adc1.Instance = DMA1_Channel1; + hdma_adc1.Init.Request = DMA_REQUEST_ADC1; + hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; + hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_adc1.Init.Mode = DMA_CIRCULAR; + hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; + if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); + + /* ADC1 interrupt Init */ + HAL_NVIC_SetPriority(ADC1_COMP_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(ADC1_COMP_IRQn); + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } +} + +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) +{ + + if(adcHandle->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PA5 ------> ADC1_IN5 + PA6 ------> ADC1_IN6 + PA7 ------> ADC1_IN7 + PB0 ------> ADC1_IN8 + */ + HAL_GPIO_DeInit(GPIOA, ADC1_IN5_I_SENSE_AVG_Pin|ADC1_IN6_UIN_SENSE_Pin|ADC1_IN7_TEMP_SENSE_Pin); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0); + + /* ADC1 DMA DeInit */ + HAL_DMA_DeInit(adcHandle->DMA_Handle); + + /* ADC1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(ADC1_COMP_IRQn); + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Src/comp.c =================================================================== --- ecs_cellMon/firmware/Core/Src/comp.c (revision 3) +++ ecs_cellMon/firmware/Core/Src/comp.c (revision 3) @@ -0,0 +1,196 @@ +/** + ****************************************************************************** + * @file comp.c + * @brief This file provides code for the configuration + * of the COMP instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "comp.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +COMP_HandleTypeDef hcomp1; +COMP_HandleTypeDef hcomp2; + +/* COMP1 init function */ +void MX_COMP1_Init(void) +{ + + /* USER CODE BEGIN COMP1_Init 0 */ + + /* USER CODE END COMP1_Init 0 */ + + /* USER CODE BEGIN COMP1_Init 1 */ + + /* USER CODE END COMP1_Init 1 */ + hcomp1.Instance = COMP1; + hcomp1.Init.InputPlus = COMP_INPUT_PLUS_IO3; + hcomp1.Init.InputMinus = COMP_INPUT_MINUS_DAC1_CH1; + hcomp1.Init.OutputPol = COMP_OUTPUTPOL_INVERTED; + hcomp1.Init.WindowOutput = COMP_WINDOWOUTPUT_EACH_COMP; + hcomp1.Init.Hysteresis = COMP_HYSTERESIS_HIGH; + hcomp1.Init.BlankingSrce = COMP_BLANKINGSRC_NONE; + hcomp1.Init.Mode = COMP_POWERMODE_HIGHSPEED; + hcomp1.Init.WindowMode = COMP_WINDOWMODE_DISABLE; + hcomp1.Init.TriggerMode = COMP_TRIGGERMODE_NONE; + if (HAL_COMP_Init(&hcomp1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN COMP1_Init 2 */ + + /* USER CODE END COMP1_Init 2 */ + +} +/* COMP2 init function */ +void MX_COMP2_Init(void) +{ + + /* USER CODE BEGIN COMP2_Init 0 */ + + /* USER CODE END COMP2_Init 0 */ + + /* USER CODE BEGIN COMP2_Init 1 */ + + /* USER CODE END COMP2_Init 1 */ + hcomp2.Instance = COMP2; + hcomp2.Init.InputPlus = COMP_INPUT_PLUS_IO3; + hcomp2.Init.InputMinus = COMP_INPUT_MINUS_IO3; + hcomp2.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED; + hcomp2.Init.WindowOutput = COMP_WINDOWOUTPUT_EACH_COMP; + hcomp2.Init.Hysteresis = COMP_HYSTERESIS_HIGH; + hcomp2.Init.BlankingSrce = COMP_BLANKINGSRC_NONE; + hcomp2.Init.Mode = COMP_POWERMODE_HIGHSPEED; + hcomp2.Init.WindowMode = COMP_WINDOWMODE_DISABLE; + hcomp2.Init.TriggerMode = COMP_TRIGGERMODE_NONE; + if (HAL_COMP_Init(&hcomp2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN COMP2_Init 2 */ + + /* USER CODE END COMP2_Init 2 */ + +} + +void HAL_COMP_MspInit(COMP_HandleTypeDef* compHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(compHandle->Instance==COMP1) + { + /* USER CODE BEGIN COMP1_MspInit 0 */ + + /* USER CODE END COMP1_MspInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**COMP1 GPIO Configuration + PA1 ------> COMP1_INP + PA11 [PA9] ------> COMP1_OUT + */ + GPIO_InitStruct.Pin = COMP1_INP_I_SENSE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(COMP1_INP_I_SENSE_GPIO_Port, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = COMP1_OUT_I_PEAK_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_COMP1; + HAL_GPIO_Init(COMP1_OUT_I_PEAK_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN COMP1_MspInit 1 */ + + /* USER CODE END COMP1_MspInit 1 */ + } + else if(compHandle->Instance==COMP2) + { + /* USER CODE BEGIN COMP2_MspInit 0 */ + /* USER CODE END COMP2_MspInit 0 */ + + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**COMP2 GPIO Configuration + PA2 ------> COMP2_INM + PA3 ------> COMP2_INP + PB5 ------> COMP2_OUT + */ + GPIO_InitStruct.Pin = COMP2_INM_U_TR_SENSE_Pin|COMP2_INP_U_TR_REF_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = COMP2_OUT_DISCHARGE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_COMP2; + HAL_GPIO_Init(COMP2_OUT_DISCHARGE_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN COMP2_MspInit 1 */ + + /* USER CODE END COMP2_MspInit 1 */ + } +} + +void HAL_COMP_MspDeInit(COMP_HandleTypeDef* compHandle) +{ + + if(compHandle->Instance==COMP1) + { + /* USER CODE BEGIN COMP1_MspDeInit 0 */ + + /* USER CODE END COMP1_MspDeInit 0 */ + + /**COMP1 GPIO Configuration + PA1 ------> COMP1_INP + PA11 [PA9] ------> COMP1_OUT + */ + HAL_GPIO_DeInit(GPIOA, COMP1_INP_I_SENSE_Pin|COMP1_OUT_I_PEAK_Pin); + + /* USER CODE BEGIN COMP1_MspDeInit 1 */ + + /* USER CODE END COMP1_MspDeInit 1 */ + } + else if(compHandle->Instance==COMP2) + { + /* USER CODE BEGIN COMP2_MspDeInit 0 */ + + /* USER CODE END COMP2_MspDeInit 0 */ + + /**COMP2 GPIO Configuration + PA2 ------> COMP2_INM + PA3 ------> COMP2_INP + PB5 ------> COMP2_OUT + */ + HAL_GPIO_DeInit(GPIOA, COMP2_INM_U_TR_SENSE_Pin|COMP2_INP_U_TR_REF_Pin); + + HAL_GPIO_DeInit(COMP2_OUT_DISCHARGE_GPIO_Port, COMP2_OUT_DISCHARGE_Pin); + + /* USER CODE BEGIN COMP2_MspDeInit 1 */ + + /* USER CODE END COMP2_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Src/dac.c =================================================================== --- ecs_cellMon/firmware/Core/Src/dac.c (revision 3) +++ ecs_cellMon/firmware/Core/Src/dac.c (revision 3) @@ -0,0 +1,119 @@ +/** + ****************************************************************************** + * @file dac.c + * @brief This file provides code for the configuration + * of the DAC instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "dac.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +DAC_HandleTypeDef hdac1; + +/* DAC1 init function */ +void MX_DAC1_Init(void) +{ + + /* USER CODE BEGIN DAC1_Init 0 */ + + /* USER CODE END DAC1_Init 0 */ + + DAC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN DAC1_Init 1 */ + + /* USER CODE END DAC1_Init 1 */ + /** DAC Initialization + */ + hdac1.Instance = DAC1; + if (HAL_DAC_Init(&hdac1) != HAL_OK) + { + Error_Handler(); + } + /** DAC channel OUT1 config + */ + sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; + sConfig.DAC_Trigger = DAC_TRIGGER_NONE; + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; + sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE; + sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY; + if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN DAC1_Init 2 */ + + /* USER CODE END DAC1_Init 2 */ + +} + +void HAL_DAC_MspInit(DAC_HandleTypeDef* dacHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(dacHandle->Instance==DAC1) + { + /* USER CODE BEGIN DAC1_MspInit 0 */ + + /* USER CODE END DAC1_MspInit 0 */ + /* DAC1 clock enable */ + __HAL_RCC_DAC1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 + */ + GPIO_InitStruct.Pin = DAC1_OUT1_I_CTR_TP_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(DAC1_OUT1_I_CTR_TP_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN DAC1_MspInit 1 */ + + /* USER CODE END DAC1_MspInit 1 */ + } +} + +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* dacHandle) +{ + + if(dacHandle->Instance==DAC1) + { + /* USER CODE BEGIN DAC1_MspDeInit 0 */ + + /* USER CODE END DAC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_DAC1_CLK_DISABLE(); + + /**DAC1 GPIO Configuration + PA4 ------> DAC1_OUT1 + */ + HAL_GPIO_DeInit(DAC1_OUT1_I_CTR_TP_GPIO_Port, DAC1_OUT1_I_CTR_TP_Pin); + + /* USER CODE BEGIN DAC1_MspDeInit 1 */ + + /* USER CODE END DAC1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Src/dma.c =================================================================== --- ecs_cellMon/firmware/Core/Src/dma.c (revision 3) +++ ecs_cellMon/firmware/Core/Src/dma.c (revision 3) @@ -0,0 +1,55 @@ +/** + ****************************************************************************** + * @file dma.c + * @brief This file provides code for the configuration + * of all the requested memory to memory DMA transfers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure DMA */ +/*----------------------------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA1_Channel1_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Src/gpio.c =================================================================== --- ecs_cellMon/firmware/Core/Src/gpio.c (revision 3) +++ ecs_cellMon/firmware/Core/Src/gpio.c (revision 3) @@ -0,0 +1,114 @@ +/** + ****************************************************************************** + * @file gpio.c + * @brief This file provides code for the configuration + * of all used GPIO pins. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "gpio.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure GPIO */ +/*----------------------------------------------------------------------------*/ +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** Configure pins as + * Analog + * Input + * Output + * EVENT_OUT + * EXTI + * Free pins are configured automatically as Analog (this feature is enabled through + * the Code Generation settings) +*/ +void MX_GPIO_Init(void) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOD, LVP_Pin|OVP_Pin|LED_FUNC_Pin|LED_ERROR_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : PC13 PC14 PC15 PC6 + PC7 */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15|GPIO_PIN_6 + |GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pin : PF2 */ + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /*Configure GPIO pins : PA0 PA15 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pins : PB1 PB2 PB10 PB11 + PB12 PB13 PB14 PB15 + PB4 PB6 PB7 + PB8 PB9 */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 + |GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_7 + |GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : PB3 */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /*Configure GPIO pins : PDPin PDPin PDPin PDPin */ + GPIO_InitStruct.Pin = LVP_Pin|OVP_Pin|LED_FUNC_Pin|LED_ERROR_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + HAL_GPIO_WritePin(GPIOC, BUZZER_Pin, GPIO_PIN_RESET); + GPIO_InitStruct.Pin = BUZZER_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Src/main.c =================================================================== --- ecs_cellMon/firmware/Core/Src/main.c (revision 3) +++ ecs_cellMon/firmware/Core/Src/main.c (revision 3) @@ -0,0 +1,461 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "adc.h" +#include "comp.h" +#include "dac.h" +#include "dma.h" +#include "tim.h" +#include "usart.h" +#include "gpio.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "led.h" +#include "output.h" +#include "meas.h" +#include "sysdata.h" +#include "balancer.h" +#include "modbus.h" +#include "eeprom.h" +#include "bms.h" +#include +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ +#define LED_INTERVALL 1 +#define BALANCER_EXEC_INTERVALL 1 +#define COMMUNICATION_TIMEOUT (300000) //in ms --> 5 Minuten +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ + +/* USER CODE BEGIN PV */ +modbus_t modbusData; +uint32_t communicationTimeoutCounter = 0; +uint16_t keyAccepted=0; +uint16_t savedLockKey; + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +/* USER CODE BEGIN PFP */ +bool SetFlashReadProtection(bool state); +bool SetBootFromFlashAndReadOutProtection(void); +void applyMBParameter(void); +void resetCounters(void); +void resetMinMaxValues(void); +void mb_save_lock_key(void); +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + uint32_t ledExecTime = 0; + // uint32_t balancerCheckTime = 0; + uint32_t balancerExecTime = 0; + uint32_t oldTime=0; + + + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_DMA_Init(); + MX_ADC1_Init(); + MX_COMP1_Init(); + MX_COMP2_Init(); + MX_DAC1_Init(); + MX_TIM1_Init(); + MX_USART1_UART_Init(); + /* USER CODE BEGIN 2 */ + HAL_Delay(100); + SYSDATA_Init(); + if(EEPROM_isFirstStart()) + { + // zurücksetzen aller Werte + printf("full restore...\n"); + EEPROM_fullRestore(&sysData,false); + EEPROM_ResetLogData(); + } + + if(HAL_GPIO_ReadPin(GPIOB,GPIO_PIN_3) == GPIO_PIN_RESET) + { + // zurücksetzen auf Werkseinsellung + printf("factore restore (Pin)...\n"); + EEPROM_fullRestore(&sysData,true); + } + + // Lade gespeicherte Einstellungen + printf("read config...\n"); + EEPROM_readConfig(&sysData); + EEPROM_readLogData(); + + + //Display Address with Error LED blinks + int n; + for (n=0; n= (ledExecTime + LED_INTERVALL)) + { + LED_Exec(); + ledExecTime = HAL_GetTick(); + } + + + if (HAL_GetTick() >= (balancerExecTime + BALANCER_EXEC_INTERVALL)) + { + + balancerExecTime = HAL_GetTick(); + MEAS_Exec(); + BMS_Exec(); + BALANCER_Exec(); + } + + + + if (HAL_GetTick() > oldTime) + { + //1ms Intervall + oldTime = HAL_GetTick(); + + if (communicationTimeoutCounter) + { + communicationTimeoutCounter--; + if (communicationTimeoutCounter==0) + { + sysData.s.masterMode=0; + } + + } + } + + if (sysData.s.command != 0) + { + if (modbusData.current_query == MB_QUERY_NOTHING) + { + //printf("CMD = %d\n", sys_data.s.parameter.command); + switch (sysData.s.command ) + { + case CMD_SAVE_PARAMETER_TO_EEPROM: + printf("EXE: Store parameter\n"); + EEPROM_storeConfig(&sysData,0,false); + break; + case CMD_RESET_FACTORY: + printf("EXEC: Factory Restore\n"); + EEPROM_fullRestore(&sysData,1); + break; + case CMD_SAVE_SN: + printf("EXEC: Store with sn\n"); + EEPROM_storeConfig(&sysData,1,false); + break; + case CMD_RESET: + printf("EXEC: RESTART\n"); + NVIC_SystemReset(); + break; + case CMD_APPLY_MB_PARAMETER: + printf("EXEC: Apply MB Parameter\n"); + applyMBParameter(); + break; + case CMD_RESET_COUNTERS: + printf("EXEC: Reset Counters\n"); + resetCounters(); + break; + case CMD_RESET_MIN_MAX_VALUES: + printf("EXEC: Reset Min and Max Values\n"); + resetMinMaxValues(); + break; + case CMD_SAVE_LOCK_KEY: + printf("EXEC: Save lock key\n"); + mb_save_lock_key(); + break; + default: + printf("UNKNOWN COMMAND\n"); + + } + sysData.s.command = 0; + } + else + { + //printf("wait with execution till modbus communnikation finished\n"); + } + } + + + + // Modbus Kommunikation + if (mbGetFrameComplete(&modbusData) == true) + { + //printf("RX frame complete\n"); + if (mbSlaveCheckModbusRtuQuery(&modbusData) == RESPOND_TO_QUERY) + { + //printf("->send response...\n"); + mbSlaveProcessRtuQuery(&modbusData); + + //Prüfe KEY + if (sysData.s.lockKey == savedLockKey) + { + sysData.s.keyAccepted = 1; + keyAccepted = 1; + } + else + { + sysData.s.keyAccepted = 0; + keyAccepted = 0; + } + + //Wenn Ausgleichsspannungsregister von einem Mastergerät geändert wird. In den Master Modus gehen + if (sysData.s.balancerVoltageRemote != 0) + { + communicationTimeoutCounter = COMMUNICATION_TIMEOUT; + sysData.s.masterMode = 1; + sysData.s.balancerVoltage = sysData.s.balancerVoltageRemote; + } + + } + else + { + //printf("->don't respond...\n"); + modbusData.uart->RxState = HAL_UART_STATE_BUSY_RX; + } + } + else + { + if (sysData.s.balancerPower == 0) + { + // HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON,PWR_SLEEPENTRY_WFI); + } + } + + + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the peripherals clocks + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_ADC + |RCC_PERIPHCLK_TIM1; + PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1; + PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK; + PeriphClkInit.Tim1ClockSelection = RCC_TIM1CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } +} + +/* USER CODE BEGIN 4 */ +void mb_save_lock_key() +{ + if (sysData.s.lockKey == savedLockKey) + { + EEPROM_storeConfig(&sysData,false,true); + savedLockKey = sysData.s.newLockKey; + sysData.s.lockKey = savedLockKey; + } + + if (savedLockKey != 0) + { + sysData.s.writeLocked = 1; + } + else + { + sysData.s.writeLocked = 0; + } +} + +void applyMBParameter() +{ + HAL_UART_DeInit(&huart1); + mbInit(&modbusData, sysData.s.baudrate, sysData.s.parityMode, &huart1, accessModeTable, &keyAccepted); +} + +void resetCounters() +{ + if (sysData.s.lockKey == savedLockKey) + { + sysData.s.criticalOverTempTime = 0; + sysData.s.criticalUnderTempTime = 0; + sysData.s.criticalOverVoltageTime = 0; + sysData.s.criticalUnderVoltageTime = 0; + sysData.s.cycleCounter = 0; + EEPROM_storeLogData(); + } + else + { + printf("not allowed, paramter locked!\n"); + } +} + +void resetMinMaxValues() +{ + if (sysData.s.lockKey == savedLockKey) + { + sysData.s.minTemperature = sysData.s.cellTemperature; + sysData.s.maxTemperature = sysData.s.cellTemperature; + sysData.s.minVoltage = sysData.s.cellVoltage; + sysData.s.maxVoltage = sysData.s.cellVoltage; + EEPROM_storeLogData(); + } + else + { + printf("not allowed, paramter locked!\n"); + } +} + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + printf("Wrong parameters value: file %s on line %d\r\n", file, line); + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Src/stm32g0xx_hal_msp.c =================================================================== --- ecs_cellMon/firmware/Core/Src/stm32g0xx_hal_msp.c (revision 3) +++ ecs_cellMon/firmware/Core/Src/stm32g0xx_hal_msp.c (revision 3) @@ -0,0 +1,88 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + + /** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral + */ + HAL_SYSCFG_StrobeDBattpinsConfig(SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Src/stm32g0xx_it.c =================================================================== --- ecs_cellMon/firmware/Core/Src/stm32g0xx_it.c (revision 3) +++ ecs_cellMon/firmware/Core/Src/stm32g0xx_it.c (revision 3) @@ -0,0 +1,215 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32g0xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32g0xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "modbus.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern DMA_HandleTypeDef hdma_adc1; +extern ADC_HandleTypeDef hadc1; +extern UART_HandleTypeDef huart1; +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M0+ Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + /* USER CODE BEGIN SVC_IRQn 0 */ + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + /* USER CODE BEGIN PendSV_IRQn 0 */ + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32G0xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32g0xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles DMA1 channel 1 interrupt. + */ +void DMA1_Channel1_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ + + /* USER CODE END DMA1_Channel1_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_adc1); + /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ + + /* USER CODE END DMA1_Channel1_IRQn 1 */ +} + +/** + * @brief This function handles ADC1, COMP1 and COMP2 interrupts (COMP interrupts through EXTI lines 17 and 18). + */ +void ADC1_COMP_IRQHandler(void) +{ + /* USER CODE BEGIN ADC1_COMP_IRQn 0 */ + + /* USER CODE END ADC1_COMP_IRQn 0 */ + HAL_ADC_IRQHandler(&hadc1); + /* USER CODE BEGIN ADC1_COMP_IRQn 1 */ + + /* USER CODE END ADC1_COMP_IRQn 1 */ +} + +/** + * @brief This function handles USART1 global interrupt / USART1 wake-up interrupt through EXTI line 25. + */ +void USART1_IRQHandler(void) +{ + /* USER CODE BEGIN USART1_IRQn 0 */ + //Umleitung auf unseren eigenen IRQ Handler + MODBUS_UART_IRQHandler(&huart1); + return; + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + + +//Cube IRQ Handler namen stimmen nicht mit Segger IRQ Namen überein---> Redirecting +void DMA_Channel1_IRQHandler(void) +{ + DMA1_Channel1_IRQHandler(); +} + +void ADC_COMP_IRQHandler(void) +{ + ADC1_COMP_IRQHandler(); +} + + + +void USART3_USART4_LPUART1_IRQHandler(void) +{ + MODBUS_UART_IRQHandler(&huart1); + +} + + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Src/syscalls.c =================================================================== --- ecs_cellMon/firmware/Core/Src/syscalls.c (revision 3) +++ ecs_cellMon/firmware/Core/Src/syscalls.c (revision 3) @@ -0,0 +1,207 @@ +/** +***************************************************************************** +** +** File : syscalls.c +** +** Author : Auto-generated by System workbench for STM32 +** +** Abstract : System Workbench Minimal System calls file +** +** For more information about which c-functions +** need which of these lowlevel functions +** please consult the Newlib libc-manual +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +//#undef errno +extern int errno; +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + +register char * stack_ptr asm("sp"); + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + +return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +caddr_t _sbrk(int incr) +{ + extern char end asm("end"); + static char *heap_end; + char *prev_heap_end; + + if (heap_end == 0) + heap_end = &end; + + prev_heap_end = heap_end; + if (heap_end + incr > stack_ptr) + { +// write(1, "Heap and stack collision\n", 25); +// abort(); + errno = ENOMEM; + return (caddr_t) -1; + } + + heap_end += incr; + + return (caddr_t) prev_heap_end; +} + +int _close(int file) +{ + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +int _open(char *path, int flags, ...) +{ + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + return -1; +} + +int _stat(char *file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + errno = ENOMEM; + return -1; +} Index: ecs_cellMon/firmware/Core/Src/system_stm32g0xx.c =================================================================== --- ecs_cellMon/firmware/Core/Src/system_stm32g0xx.c (revision 3) +++ ecs_cellMon/firmware/Core/Src/system_stm32g0xx.c (revision 3) @@ -0,0 +1,290 @@ +/** + ****************************************************************************** + * @file system_stm32g0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB Prescaler | 1 + *----------------------------------------------------------------------------- + * HSI Division factor | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Apache License, Version 2.0, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/Apache-2.0 + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx_system + * @{ + */ + +/** @addtogroup STM32G0xx_System_Private_Includes + * @{ + */ + +#include "stm32g0xx.h" + +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ +#endif /* LSE_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000UL; + + const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL}; + const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE + * + * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp; + uint32_t pllvco; + uint32_t pllr; + uint32_t pllsource; + uint32_t pllm; + uint32_t hsidiv; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_0: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + + case (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0): /* LSI used as system clock */ + SystemCoreClock = LSI_VALUE; + break; + + case RCC_CFGR_SWS_2: /* LSE used as system clock */ + SystemCoreClock = LSE_VALUE; + break; + + case RCC_CFGR_SWS_1: /* PLL used as system clock */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL; + + if(pllsource == 0x03UL) /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + else /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); + + SystemCoreClock = pllvco/pllr; + break; + + case 0x00000000U: /* HSI used as system clock */ + default: /* HSI used as system clock */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos)); + SystemCoreClock = (HSI_VALUE/hsidiv); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Src/tim.c =================================================================== --- ecs_cellMon/firmware/Core/Src/tim.c (revision 3) +++ ecs_cellMon/firmware/Core/Src/tim.c (revision 3) @@ -0,0 +1,162 @@ +/** + ****************************************************************************** + * @file tim.c + * @brief This file provides code for the configuration + * of the TIM instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tim.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +TIM_HandleTypeDef htim1; + +/* TIM1 init function */ +void MX_TIM1_Init(void) +{ + + /* USER CODE BEGIN TIM1_Init 0 */ + + /* USER CODE END TIM1_Init 0 */ + + TIM_ClockConfigTypeDef sClockSourceConfig = {0}; + TIM_SlaveConfigTypeDef sSlaveConfig = {0}; + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_IC_InitTypeDef sConfigIC = {0}; + + /* USER CODE BEGIN TIM1_Init 1 */ + + /* USER CODE END TIM1_Init 1 */ + htim1.Instance = TIM1; + htim1.Init.Prescaler = 0; + htim1.Init.CounterMode = TIM_COUNTERMODE_UP; + htim1.Init.Period = 65535; + htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim1.Init.RepetitionCounter = 0; + htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim1) != HAL_OK) + { + Error_Handler(); + } + sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; + if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_IC_Init(&htim1) != HAL_OK) + { + Error_Handler(); + } + sSlaveConfig.SlaveMode = TIM_SLAVEMODE_RESET; + sSlaveConfig.InputTrigger = TIM_TS_TI1FP1; + sSlaveConfig.TriggerPolarity = TIM_INPUTCHANNELPOLARITY_FALLING; + sSlaveConfig.TriggerFilter = 0; + if (HAL_TIM_SlaveConfigSynchro(&htim1, &sSlaveConfig) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_FALLING; + sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; + sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; + sConfigIC.ICFilter = 0; + if (HAL_TIM_IC_ConfigChannel(&htim1, &sConfigIC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIMEx_TISelection(&htim1, TIM_TIM1_TI1_COMP1, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; + if (HAL_TIM_IC_ConfigChannel(&htim1, &sConfigIC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIMEx_TISelection(&htim1, TIM_TIM1_TI2_COMP2, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM1_Init 2 */ + + /* USER CODE END TIM1_Init 2 */ + +} + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(tim_baseHandle->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspInit 0 */ + + /* USER CODE END TIM1_MspInit 0 */ + /* TIM1 clock enable */ + __HAL_RCC_TIM1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**TIM1 GPIO Configuration + PA8 ------> TIM1_CH1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_8; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM1_MspInit 1 */ + + /* USER CODE END TIM1_MspInit 1 */ + } +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM1) + { + /* USER CODE BEGIN TIM1_MspDeInit 0 */ + + /* USER CODE END TIM1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM1_CLK_DISABLE(); + + /**TIM1 GPIO Configuration + PA8 ------> TIM1_CH1 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8); + + /* USER CODE BEGIN TIM1_MspDeInit 1 */ + + /* USER CODE END TIM1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Core/Src/usart.c =================================================================== --- ecs_cellMon/firmware/Core/Src/usart.c (revision 3) +++ ecs_cellMon/firmware/Core/Src/usart.c (revision 3) @@ -0,0 +1,145 @@ +/** + ****************************************************************************** + * @file usart.c + * @brief This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +UART_HandleTypeDef huart1; + +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 19200; + huart1.Init.WordLength = UART_WORDLENGTH_9B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_EVEN; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_RS485Ex_Init(&huart1, UART_DE_POLARITY_HIGH, 0, 0) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* USART1 clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + PA12 [PA10] ------> USART1_DE + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USART1 interrupt Init */ + HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + + if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + PA12 [PA10] ------> USART1_DE + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_12); + + /* USART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Debug Internal/Cortex_M_Startup.d =================================================================== --- ecs_cellMon/firmware/Debug Internal/Cortex_M_Startup.d (revision 3) +++ ecs_cellMon/firmware/Debug Internal/Cortex_M_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Debug\ Internal/Cortex_M_Startup.o: \ + C\:/Program\ Files/SEGGER/SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40/samples/Cortex_M_Startup.s Index: ecs_cellMon/firmware/Debug Internal/Cortex_M_Startup_PP.s =================================================================== --- ecs_cellMon/firmware/Debug Internal/Cortex_M_Startup_PP.s (revision 3) +++ ecs_cellMon/firmware/Debug Internal/Cortex_M_Startup_PP.s (revision 3) @@ -0,0 +1,140 @@ +# 1 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/Cortex_M_Startup.s" +# 1 "" +# 1 "" +# 1 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/Cortex_M_Startup.s" +# 57 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/Cortex_M_Startup.s" + .syntax unified +# 68 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/Cortex_M_Startup.s" +.macro VECTOR Name= + .section .vectors, "a" + .word \Name +.endm + + + +.macro ISR_HANDLER Name= + + + + .section .vectors, "a" + .word \Name + + + + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b + END_FUNC \Name +.endm + + + + +.macro ISR_RESERVED + .section .vectors, "a" + .word 0 +.endm + + + + +.macro END_FUNC name + .size \name,.-\name +.endm +# 119 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/Cortex_M_Startup.s" + .section .vectors, "a" + .code 16 + .balign 4 + .global _vectors +_vectors: + VECTOR __stack_end__ + VECTOR Reset_Handler + ISR_HANDLER NMI_Handler + VECTOR HardFault_Handler + ISR_HANDLER MemManage_Handler + ISR_HANDLER BusFault_Handler + ISR_HANDLER UsageFault_Handler + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_HANDLER SVC_Handler + ISR_HANDLER DebugMon_Handler + ISR_RESERVED + ISR_HANDLER PendSV_Handler + ISR_HANDLER SysTick_Handler +# 149 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/Cortex_M_Startup.s" + .section .vectors, "a" + .size _vectors, .-_vectors +_vectors_end: +# 174 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/Cortex_M_Startup.s" + .global reset_handler + .global Reset_Handler + .equ reset_handler, Reset_Handler + .section .init.Reset_Handler, "ax" + .balign 2 + .thumb_func +Reset_Handler: + + + + + bl SystemInit +# 200 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/Cortex_M_Startup.s" + bl _start +END_FUNC Reset_Handler + + + + + + .weak SystemInit +# 229 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/Cortex_M_Startup.s" + .weak HardFault_Handler + .section .init.HardFault_Handler, "ax" + .balign 2 + .thumb_func +HardFault_Handler: + + + + ldr R1, =0xE000ED2C + ldr R2, [R1] + cmp R2, #0 + +.LHardFault_Handler_hfLoop: + bmi .LHardFault_Handler_hfLoop + + + + + movs R0, #4 + mov R1, LR + tst R0, R1 + bne .LHardFault_Handler_Uses_PSP + mrs R0, MSP + b .LHardFault_Handler_Pass_StackPtr +.LHardFault_Handler_Uses_PSP: + mrs R0, PSP +.LHardFault_Handler_Pass_StackPtr: +# 266 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/Cortex_M_Startup.s" + movs R3, #1 + lsls R3, R3, #31 + orrs R2, R3 + str R2, [R1] + + + + + + + + ldr R1, [R0, #24] + adds R1, #2 + str R1, [R0, #24] + + bx LR +END_FUNC HardFault_Handler Index: ecs_cellMon/firmware/Debug Internal/SEGGER_THUMB_Startup.d =================================================================== --- ecs_cellMon/firmware/Debug Internal/SEGGER_THUMB_Startup.d (revision 3) +++ ecs_cellMon/firmware/Debug Internal/SEGGER_THUMB_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Debug\ Internal/SEGGER_THUMB_Startup.o: \ + C\:/Program\ Files/SEGGER/SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40/samples/SEGGER_THUMB_Startup.s Index: ecs_cellMon/firmware/Debug Internal/SEGGER_THUMB_Startup_PP.s =================================================================== --- ecs_cellMon/firmware/Debug Internal/SEGGER_THUMB_Startup_PP.s (revision 3) +++ ecs_cellMon/firmware/Debug Internal/SEGGER_THUMB_Startup_PP.s (revision 3) @@ -0,0 +1,84 @@ +# 1 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/SEGGER_THUMB_Startup.s" +# 1 "" +# 1 "" +# 1 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/SEGGER_THUMB_Startup.s" +# 62 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/SEGGER_THUMB_Startup.s" + .syntax unified +# 88 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/SEGGER_THUMB_Startup.s" +.macro MARK_FUNC Name + .global \Name + .thumb_func + .code 16 +\Name: +.endm + + + + +.macro START_FUNC Name + .section .init.\Name, "ax" + .global \Name + .balign 2 + .thumb_func + .code 16 +\Name: +.endm + + + + +.macro WEAK_FUNC Name + .section .init.\Name, "ax", %progbits + .global \Name + .weak \Name + .balign 2 + .thumb_func + .code 16 +\Name: +.endm + + + + +.macro END_FUNC name + .size \name,.-\name +.endm + + + + + + + + .extern main +# 163 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/SEGGER_THUMB_Startup.s" +START_FUNC _start + + + + + + + ldr R4, =__SEGGER_init_table__ +.L_start_RunInit: + ldr R0, [R4] + adds R4, R4, #4 + blx R0 + b .L_start_RunInit + +MARK_FUNC __SEGGER_init_done +# 187 "C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 5.40/samples/SEGGER_THUMB_Startup.s" + bl main + +END_FUNC _start + + + + +MARK_FUNC exit + + + + + b . + .size exit,.-exit Index: ecs_cellMon/firmware/Debug Internal/startup_stm32g071xx.d =================================================================== --- ecs_cellMon/firmware/Debug Internal/startup_stm32g071xx.d (revision 3) +++ ecs_cellMon/firmware/Debug Internal/startup_stm32g071xx.d (revision 3) @@ -0,0 +1,2 @@ +Debug\ Internal/startup_stm32g071xx.o: \ + D\:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\startup\startup_stm32g071xx.s Index: ecs_cellMon/firmware/Debug Internal/startup_stm32g071xx_PP.s =================================================================== --- ecs_cellMon/firmware/Debug Internal/startup_stm32g071xx_PP.s (revision 3) +++ ecs_cellMon/firmware/Debug Internal/startup_stm32g071xx_PP.s (revision 3) @@ -0,0 +1,242 @@ +# 1 "D:\\projekte\\ecs_lipro\\branches\\lipro1-6_v2\\firmware\\startup\\startup_stm32g071xx.s" +# 1 "" +# 1 "" +# 1 "D:\\projekte\\ecs_lipro\\branches\\lipro1-6_v2\\firmware\\startup\\startup_stm32g071xx.s" +# 27 "D:\\projekte\\ecs_lipro\\branches\\lipro1-6_v2\\firmware\\startup\\startup_stm32g071xx.s" +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + + + +.word _sidata + +.word _sdata + +.word _edata + +.word _sbss + +.word _ebss +# 56 "D:\\projekte\\ecs_lipro\\branches\\lipro1-6_v2\\firmware\\startup\\startup_stm32g071xx.s" + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 + + + bl SystemInit + + + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + + + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + + + bl __libc_init_array + + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler +# 115 "D:\\projekte\\ecs_lipro\\branches\\lipro1-6_v2\\firmware\\startup\\startup_stm32g071xx.s" + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +# 128 "D:\\projekte\\ecs_lipro\\branches\\lipro1-6_v2\\firmware\\startup\\startup_stm32g071xx.s" + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_TAMP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_1_IRQHandler + .word EXTI2_3_IRQHandler + .word EXTI4_15_IRQHandler + .word UCPD1_2_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_3_IRQHandler + .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + .word ADC1_COMP_IRQHandler + .word TIM1_BRK_UP_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM6_DAC_LPTIM1_IRQHandler + .word TIM7_LPTIM2_IRQHandler + .word TIM14_IRQHandler + .word TIM15_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word I2C1_IRQHandler + .word I2C2_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_4_LPUART1_IRQHandler + .word CEC_IRQHandler +# 189 "D:\\projekte\\ecs_lipro\\branches\\lipro1-6_v2\\firmware\\startup\\startup_stm32g071xx.s" + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak UCPD1_2_IRQHandler + .thumb_set UCPD1_2_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_LPTIM1_IRQHandler + .thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler + + .weak TIM7_LPTIM2_IRQHandler + .thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_4_LPUART1_IRQHandler + .thumb_set USART3_4_LPUART1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler Index: ecs_cellMon/firmware/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g071xx.h (revision 3) @@ -0,0 +1,9143 @@ +/** + ****************************************************************************** + * @file stm32g071xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32g071xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Apache License, Version 2.0, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/Apache-2.0 + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g071xx + * @{ + */ + +#ifndef STM32G071xx_H +#define STM32G071xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1U /*!< STM32G0xx provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2U /*!< STM32G0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32g071xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI line 16 */ + RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + UCPD1_2_IRQn = 8, /*!< UCPD1 and UCPD2 global Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts (combined with EXTI 17 & 18) */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM6_DAC_LPTIM1_IRQn = 17, /*!< TIM6, DAC and LPTIM1 global Interrupts */ + TIM7_LPTIM2_IRQn = 18, /*!< TIM7 and LPTIM2 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + USART3_4_LPUART1_IRQn = 29, /*!< USART3, USART4 and LPUART1 globlal Interrupts (combined with EXTI 28) */ + CEC_IRQn = 30, /*!< CEC Interrupt(combined with EXTI 27) */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32g0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief HDMI-CEC + */ +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED8[17];/*!< Reserved8, Address offset: 0x3C--0x7C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ +} LPTIM_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ + __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */ + uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ +} TAMP_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[25]; /*!< Reserved 0x1C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ + +} UCPD_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ +#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */ + +#define FLASH_SIZE (((*((uint32_t *)FLASHSIZE_BASE)) & (0x00FFU)) << 10U) + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM2_BASE (APBPERIPH_BASE + 0UL) +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) +#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define DAC1_BASE (APBPERIPH_BASE + 0x00007400UL) +#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL) /* Kept for legacy purpose */ +#define CEC_BASE (APBPERIPH_BASE + 0x00007800UL) +#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL) +#define LPUART1_BASE (APBPERIPH_BASE + 0x00008000UL) +#define LPTIM2_BASE (APBPERIPH_BASE + 0x00009400UL) +#define UCPD1_BASE (APBPERIPH_BASE + 0x0000A000UL) +#define UCPD2_BASE (APBPERIPH_BASE + 0x0000A400UL) +#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define VREFBUF_BASE (APBPERIPH_BASE + 0x00010030UL) +#define COMP1_BASE (SYSCFG_BASE + 0x0200UL) +#define COMP2_BASE (SYSCFG_BASE + 0x0204UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART4 ((USART_TypeDef *) USART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) +#define UCPD2 ((UCPD_TypeDef *) UCPD2_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ +#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ +#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ +#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ +#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ +#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ +#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ +#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ +#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ +#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ +#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ +#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ +#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/* Legacy */ +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */ + +/******************************************************************************/ +/* */ +/* HDMI-CEC (CEC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CEC_CR register *********************/ +#define CEC_CR_CECEN_Pos (0U) +#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */ +#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */ +#define CEC_CR_TXSOM_Pos (1U) +#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */ +#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */ +#define CEC_CR_TXEOM_Pos (2U) +#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */ +#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */ + +/******************* Bit definition for CEC_CFGR register *******************/ +#define CEC_CFGR_SFT_Pos (0U) +#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */ +#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */ +#define CEC_CFGR_RXTOL_Pos (3U) +#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */ +#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */ +#define CEC_CFGR_BRESTP_Pos (4U) +#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */ +#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */ +#define CEC_CFGR_BREGEN_Pos (5U) +#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */ +#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */ +#define CEC_CFGR_LBPEGEN_Pos (6U) +#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */ +#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */ +#define CEC_CFGR_BRDNOGEN_Pos (7U) +#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */ +#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */ +#define CEC_CFGR_SFTOPT_Pos (8U) +#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */ +#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */ +#define CEC_CFGR_OAR_Pos (16U) +#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */ +#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */ +#define CEC_CFGR_LSTN_Pos (31U) +#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */ +#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */ + +/******************* Bit definition for CEC_TXDR register *******************/ +#define CEC_TXDR_TXD_Pos (0U) +#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */ +#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ + +/******************* Bit definition for CEC_RXDR register *******************/ +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ + +/******************* Bit definition for CEC_ISR register ********************/ +#define CEC_ISR_RXBR_Pos (0U) +#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ +#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */ +#define CEC_ISR_RXEND_Pos (1U) +#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */ +#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */ +#define CEC_ISR_RXOVR_Pos (2U) +#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */ +#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */ +#define CEC_ISR_BRE_Pos (3U) +#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */ +#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */ +#define CEC_ISR_SBPE_Pos (4U) +#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */ +#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */ +#define CEC_ISR_LBPE_Pos (5U) +#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */ +#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */ +#define CEC_ISR_RXACKE_Pos (6U) +#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */ +#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */ +#define CEC_ISR_ARBLST_Pos (7U) +#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */ +#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */ +#define CEC_ISR_TXBR_Pos (8U) +#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */ +#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */ +#define CEC_ISR_TXEND_Pos (9U) +#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */ +#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */ +#define CEC_ISR_TXUDR_Pos (10U) +#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */ +#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */ +#define CEC_ISR_TXERR_Pos (11U) +#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */ +#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */ +#define CEC_ISR_TXACKE_Pos (12U) +#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */ +#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */ + +/******************* Bit definition for CEC_IER register ********************/ +#define CEC_IER_RXBRIE_Pos (0U) +#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */ +#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */ +#define CEC_IER_RXENDIE_Pos (1U) +#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */ +#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */ +#define CEC_IER_RXOVRIE_Pos (2U) +#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */ +#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */ +#define CEC_IER_BREIE_Pos (3U) +#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */ +#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */ +#define CEC_IER_SBPEIE_Pos (4U) +#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */ +#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/ +#define CEC_IER_LBPEIE_Pos (5U) +#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */ +#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */ +#define CEC_IER_RXACKEIE_Pos (6U) +#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */ +#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */ +#define CEC_IER_ARBLSTIE_Pos (7U) +#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */ +#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */ +#define CEC_IER_TXBRIE_Pos (8U) +#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */ +#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */ +#define CEC_IER_TXENDIE_Pos (9U) +#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */ +#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */ +#define CEC_IER_TXUDRIE_Pos (10U) +#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */ +#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */ +#define CEC_IER_TXERRIE_Pos (11U) +#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */ +#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */ +#define CEC_IER_TXACKEIE_Pos (12U) +#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */ +#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ +#define DAC_ADDITIONAL_TRIGGERS_SUPPORT + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_OUT2EN_Pos (31U) +#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ +#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */ +#define RTC_CR_TAMPALRM_TYPE_Pos (30U) +#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ +#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */ +#define RTC_CR_TAMPALRM_PU_Pos (29U) +#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ +#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */ +#define RTC_CR_TAMPOE_Pos (26U) +#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ +#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */ +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk + +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */ +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */ +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */ +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U +#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U +#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFLT_0 0x00000008U +#define TAMP_FLTCR_TAMPFLT_1 0x00000010U +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U +#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk + +/******************** Bits definition for TAMP_SR register ******************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ***************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ***************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ***************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ***************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G0 series) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[16] Interrupt */ +#define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U) +#define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk /*!< TAMPER -> exti[21] interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_Pos (1U) +#define SYSCFG_ITLINE2_SR_RTC_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE2_SR_RTC SYSCFG_ITLINE2_SR_RTC_Msk /*!< RTC -> exti[19] interrupt .... */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U) +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U) +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */ +#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) +#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ +#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) +#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ +#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) +#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ +#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) +#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ +#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) +#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */ +#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) +#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */ +#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) +#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */ +#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) +#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */ +#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) +#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */ +#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) +#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */ +#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) +#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ +#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */ +#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) +#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ +#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */ +#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) +#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ +#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */ +#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) +#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ +#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */ +#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) +#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ +#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */ +#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) +#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ +#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */ +#define SYSCFG_ITLINE8_SR_UCPD1_Pos (0U) +#define SYSCFG_ITLINE8_SR_UCPD1_Msk (0x1UL << SYSCFG_ITLINE8_SR_UCPD1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE8_SR_UCPD1 SYSCFG_ITLINE8_SR_UCPD1_Msk /*!< UCPD1 -> exti[32] Interrupt */ +#define SYSCFG_ITLINE8_SR_UCPD2_Pos (1U) +#define SYSCFG_ITLINE8_SR_UCPD2_Msk (0x1UL << SYSCFG_ITLINE8_SR_UCPD2_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE8_SR_UCPD2 SYSCFG_ITLINE8_SR_UCPD2_Msk /*!< UCPD2 -> exti[33] Interrupt */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U) +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (3U) +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (4U) +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */ +#define SYSCFG_ITLINE12_SR_ADC_Pos (0U) +#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ +#define SYSCFG_ITLINE12_SR_COMP1_Pos (1U) +#define SYSCFG_ITLINE12_SR_COMP1_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE12_SR_COMP1 SYSCFG_ITLINE12_SR_COMP1_Msk /*!< COMP1 Interrupt -> exti[17] */ +#define SYSCFG_ITLINE12_SR_COMP2_Pos (2U) +#define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[18] */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ +#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB SYSCFG_ITLINE15_SR_TIM2_GLB_Msk /*!< TIM2 GLB Interrupt */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_DAC_Pos (1U) +#define SYSCFG_ITLINE17_SR_DAC_Msk (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos (2U) +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk /*!< LPTIM1 -> exti[29] Interrupt */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */ +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos (1U) +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk /*!< LPTIM2 -> exti[30] Interrupt */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt -> exti[22]*/ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ +#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U) +#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos (2U) +#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE29_SR_LPUART1_GLB SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk /*!< LPUART1 GLB Interrupt -> exti[28] */ +#define SYSCFG_ITLINE30_SR_CEC_Pos (0U) +#define SYSCFG_ITLINE30_SR_CEC_Msk (0x1UL << SYSCFG_ITLINE30_SR_CEC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE30_SR_CEC SYSCFG_ITLINE30_SR_CEC_Msk /*!< CEC Interrupt-> exti[27] */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under Apache License, Version 2.0, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/Apache-2.0 + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx + * @{ + */ + +#ifndef STM32G0xx_H +#define STM32G0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32G0) +#define STM32G0 +#endif /* STM32G0 */ + +/* Uncomment the line below according to the target STM32G0 device used in your + application + */ + +#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \ + && !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \ + && !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \ + && !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx) + /* #define STM32G0B0xx */ /*!< STM32G0B0xx Devices */ + /* #define STM32G0B1xx */ /*!< STM32G0B1xx Devices */ + /* #define STM32G0C1xx */ /*!< STM32G0C1xx Devices */ + /* #define STM32G070xx */ /*!< STM32G070xx Devices */ + /* #define STM32G071xx */ /*!< STM32G071xx Devices */ + /* #define STM32G081xx */ /*!< STM32G081xx Devices */ + /* #define STM32G050xx */ /*!< STM32G050xx Devices */ + /* #define STM32G051xx */ /*!< STM32G051xx Devices */ + /* #define STM32G061xx */ /*!< STM32G061xx Devices */ + /* #define STM32G030xx */ /*!< STM32G030xx Devices */ + /* #define STM32G031xx */ /*!< STM32G031xx Devices */ + /* #define STM32G041xx */ /*!< STM32G041xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number $VERSION$ + */ +#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32G0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\ + |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32G0_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32G0B1xx) + #include "stm32g0b1xx.h" +#elif defined(STM32G0C1xx) + #include "stm32g0c1xx.h" +#elif defined(STM32G0B0xx) + #include "stm32g0b0xx.h" +#elif defined(STM32G071xx) + #include "stm32g071xx.h" +#elif defined(STM32G081xx) + #include "stm32g081xx.h" +#elif defined(STM32G070xx) + #include "stm32g070xx.h" +#elif defined(STM32G031xx) + #include "stm32g031xx.h" +#elif defined(STM32G041xx) + #include "stm32g041xx.h" +#elif defined(STM32G030xx) + #include "stm32g030xx.h" +#elif defined(STM32G051xx) + #include "stm32g051xx.h" +#elif defined(STM32G061xx) + #include "stm32g061xx.h" +#elif defined(STM32G050xx) + #include "stm32g050xx.h" +#else + #error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/ +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32g0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32G0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Device/ST/STM32G0xx/Include/system_stm32g0xx.h (revision 3) @@ -0,0 +1,106 @@ +/** + ****************************************************************************** + * @file system_stm32g0xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device System Source File for STM32G0xx devices. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Apache License, Version 2.0, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/Apache-2.0 + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef SYSTEM_STM32G0XX_H +#define SYSTEM_STM32G0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32G0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32G0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*SYSTEM_STM32G0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_armcc.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_armcc.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_armcc.h (revision 3) @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_armclang.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_armclang.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_armclang.h (revision 3) @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_armclang_ltm.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_armclang_ltm.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_armclang_ltm.h (revision 3) @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_compiler.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_compiler.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_compiler.h (revision 3) @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_gcc.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_gcc.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_gcc.h (revision 3) @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_iccarm.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_iccarm.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_iccarm.h (revision 3) @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_version.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_version.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/cmsis_version.h (revision 3) @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_armv81mml.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_armv81mml.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_armv81mml.h (revision 3) @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_armv8mbl.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_armv8mbl.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_armv8mbl.h (revision 3) @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_armv8mml.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_armv8mml.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_armv8mml.h (revision 3) @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm0.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm0.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm0.h (revision 3) @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm0plus.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm0plus.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm0plus.h (revision 3) @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm1.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm1.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm1.h (revision 3) @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm23.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm23.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm23.h (revision 3) @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm3.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm3.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm3.h (revision 3) @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm33.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm33.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm33.h (revision 3) @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm35p.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm35p.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm35p.h (revision 3) @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm4.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm4.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm4.h (revision 3) @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm7.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm7.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_cm7.h (revision 3) @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_sc000.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_sc000.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_sc000.h (revision 3) @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/core_sc300.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/core_sc300.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/core_sc300.h (revision 3) @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/mpu_armv7.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/mpu_armv7.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/mpu_armv7.h (revision 3) @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/mpu_armv8.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/mpu_armv8.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/mpu_armv8.h (revision 3) @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + Index: ecs_cellMon/firmware/Drivers/CMSIS/Include/tz_context.h =================================================================== --- ecs_cellMon/firmware/Drivers/CMSIS/Include/tz_context.h (revision 3) +++ ecs_cellMon/firmware/Drivers/CMSIS/Include/tz_context.h (revision 3) @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h (revision 3) @@ -0,0 +1,3783 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ + +#if defined(STM32L1) + #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) + #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW + #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM + #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the events that can be selected to configure the + * set/reset crossbar of a timer output + */ +#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) +#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) +#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) +#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) +#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) +#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) +#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) +#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) +#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) + +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) + +/** @brief Constants defining the event filtering applied to external events + * by a timer + */ +#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) +#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) +#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) + #define I2S_IT_TXE I2S_IT_TXP + #define I2S_IT_RXNE I2S_IT_RXP + + #define I2S_FLAG_TXE I2S_FLAG_TXP + #define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) + #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT + +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL +#endif /* STM32H7 */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + + #define SPI_FLAG_TXE SPI_FLAG_TXP + #define SPI_FLAG_RXNE SPI_FLAG_RXP + + #define SPI_IT_TXE SPI_IT_TXP + #define SPI_IT_RXNE SPI_IT_RXP + + #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET + #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET + #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET + #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + + /** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ + /** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + + /** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else + #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG + #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG + #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG + #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) + #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h (revision 3) @@ -0,0 +1,839 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_H +#define STM32G0xx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_conf.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_BootMode Boot Mode + * @{ + */ +#define SYSCFG_BOOT_MAINFLASH 0x00000000U /*!< Main Flash memory mapped at 0x0000 0000 */ +#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x0000 0000 */ +#define SYSCFG_BOOT_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x0000 0000 */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Break Break + * @{ + */ +#define SYSCFG_BREAK_SP SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM Parity error signal with Break Input of TIM1/15/16/17 */ +#if defined(SYSCFG_CFGR2_PVDL) +#define SYSCFG_BREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#endif /* SYSCFG_CFGR2_PVDL */ +#define SYSCFG_BREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/15/16/17 */ +#define SYSCFG_BREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC of CortexM0+ with Break Input of TIM1/15/16/17 */ +/** + * @} + */ + +#if defined(SYSCFG_CDEN_SUPPORT) +/** @defgroup SYSCFG_ClampingDiode Clamping Diode + * @{ + */ +#define SYSCFG_CDEN_PA1 SYSCFG_CFGR2_PA1_CDEN /*!< Enables Clamping Diode on PA1 */ +#define SYSCFG_CDEN_PA3 SYSCFG_CFGR2_PA3_CDEN /*!< Enables Clamping Diode on PA3 */ +#define SYSCFG_CDEN_PA5 SYSCFG_CFGR2_PA5_CDEN /*!< Enables Clamping Diode on PA5 */ +#define SYSCFG_CDEN_PA6 SYSCFG_CFGR2_PA6_CDEN /*!< Enables Clamping Diode on PA6 */ +#define SYSCFG_CDEN_PA13 SYSCFG_CFGR2_PA13_CDEN /*!< Enables Clamping Diode on PA13 */ +#define SYSCFG_CDEN_PB0 SYSCFG_CFGR2_PB0_CDEN /*!< Enables Clamping Diode on PB0 */ +#define SYSCFG_CDEN_PB1 SYSCFG_CFGR2_PB1_CDEN /*!< Enables Clamping Diode on PB1 */ +#define SYSCFG_CDEN_PB2 SYSCFG_CFGR2_PB2_CDEN /*!< Enables Clamping Diode on PB2 */ + +/** + * @} + */ +#endif /* SYSCFG_CDEN_SUPPORT */ + +/** @defgroup HAL_Pin_remapping Pin remapping + * @{ + */ +/* Only available on cut2.0 */ +#define SYSCFG_REMAP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves digitally as PA9 GPIO pin */ +#define SYSCFG_REMAP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves digitally as PA10 GPIO pin */ +/** + * @} + */ + +/** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection + * @{ + */ +#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IR Modulation envelope source */ +#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */ +#if defined(USART4) +#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART4 is selected as IR Modulation envelope source */ +#else +#define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */ +#endif /* USART4 */ + +/** + * @} + */ + +/** @defgroup HAL_IR_POL_SEL IR output polarity selection + * @{ + */ +#define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED 0x00000000U /*!< 00: IR output polarity not inverted */ +#define HAL_SYSCFG_IRDA_POLARITY_INVERTED SYSCFG_CFGR1_IR_POL /*!< 01: IR output polarity inverted */ + +/** + * @} + */ + +#if defined(VREFBUF) +/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale + * @{ + */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0: VREF_OUT1 around 2.048 V. + This requires VDDA equal to or higher than 2.4 V. */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1: VREF_OUT1 around 2.5 V. + This requires VDDA equal to or higher than 2.8 V. */ + +/** + * @} + */ + +/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance + * @{ + */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ + +/** + * @} + */ +#endif /* VREFBUF */ + +/** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO + * @{ + */ + +/** @brief Fast mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast mode Plus on PB6 */ +#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast mode Plus on PB7 */ +#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast mode Plus on PB8 */ +#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast mode Plus on PB9 */ +#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast mode Plus on PA9 */ +#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */ + +/** + * @} + */ + +/** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx + * @{ + */ + +/** @brief Fast mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */ +#define SYSCFG_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast mode Plus on I2C2 */ +#if defined (I2C3) +#define SYSCFG_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast mode Plus on I2C3 */ +#endif /* I2C3 */ + +/** + * @} + */ +#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) +/** @defgroup SYSCFG_UCPDx_STROBE SYSCFG Dead Battery feature configuration + * @{ + */ +#define SYSCFG_UCPD1_STROBE SYSCFG_CFGR1_UCPD1_STROBE /*!< UCPD1 Dead battery sw configuration */ +#define SYSCFG_UCPD2_STROBE SYSCFG_CFGR1_UCPD2_STROBE /*!< UCPD2 Dead battery sw configuration */ +/** + * @} + */ +#endif /* SYSCFG_CFGR1_UCPD1_STROBE) || SYSCFG_CFGR1_UCPD2_STROBE */ + +/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper + * @brief ISR Wrapper + * @{ + */ +#define HAL_SYSCFG_ITLINE0 0x00000000U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE1 0x00000001U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE2 0x00000002U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE3 0x00000003U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE4 0x00000004U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE5 0x00000005U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE6 0x00000006U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE7 0x00000007U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE8 0x00000008U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE9 0x00000009U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE10 0x0000000AU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE11 0x0000000BU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE12 0x0000000CU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE13 0x0000000DU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE14 0x0000000EU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE15 0x0000000FU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE16 0x00000010U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE17 0x00000011U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE18 0x00000012U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE19 0x00000013U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE20 0x00000014U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE21 0x00000015U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE22 0x00000016U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE23 0x00000017U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE24 0x00000018U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE25 0x00000019U /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE26 0x0000001AU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE27 0x0000001BU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE28 0x0000001CU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE29 0x0000001DU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE30 0x0000001EU /*!< Internal define for macro handling */ +#define HAL_SYSCFG_ITLINE31 0x0000001FU /*!< Internal define for macro handling */ + +#define HAL_ITLINE_WWDG ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG) /*!< WWDG has expired .... */ +#if defined (PWR_PVD_SUPPORT) +#define HAL_ITLINE_PVDOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT) /*!< Power voltage detection Interrupt .... */ +#endif /* PWR_PVD_SUPPORT */ +#if defined (PWR_PVM_SUPPORT) +#define HAL_ITLINE_PVMOUT ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVMOUT) /*!< Power voltage monitor Interrupt .... */ +#endif /* PWR_PVM_SUPPORT */ +#define HAL_ITLINE_RTC ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC) /*!< RTC -> exti[19] Interrupt */ +#define HAL_ITLINE_TAMPER ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_TAMPER) /*!< TAMPER -> exti[21] interrupt .... */ +#define HAL_ITLINE_FLASH_ECC ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ECC) /*!< Flash ECC Interrupt */ +#define HAL_ITLINE_FLASH_ITF ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF) /*!< Flash ITF Interrupt */ +#define HAL_ITLINE_CLK_CTRL ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL) /*!< CLK Control Interrupt */ +#if defined (CRS) +#define HAL_ITLINE_CRS ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS) /*!< CRS Interrupt */ +#endif /*CRS */ +#define HAL_ITLINE_EXTI0 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0) /*!< External Interrupt 0 */ +#define HAL_ITLINE_EXTI1 ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1) /*!< External Interrupt 1 */ +#define HAL_ITLINE_EXTI2 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2) /*!< External Interrupt 2 */ +#define HAL_ITLINE_EXTI3 ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3) /*!< External Interrupt 3 */ +#define HAL_ITLINE_EXTI4 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4) /*!< EXTI4 Interrupt */ +#define HAL_ITLINE_EXTI5 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5) /*!< EXTI5 Interrupt */ +#define HAL_ITLINE_EXTI6 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6) /*!< EXTI6 Interrupt */ +#define HAL_ITLINE_EXTI7 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7) /*!< EXTI7 Interrupt */ +#define HAL_ITLINE_EXTI8 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8) /*!< EXTI8 Interrupt */ +#define HAL_ITLINE_EXTI9 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9) /*!< EXTI9 Interrupt */ +#define HAL_ITLINE_EXTI10 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10) /*!< EXTI10 Interrupt */ +#define HAL_ITLINE_EXTI11 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11) /*!< EXTI11 Interrupt */ +#define HAL_ITLINE_EXTI12 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12) /*!< EXTI12 Interrupt */ +#define HAL_ITLINE_EXTI13 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13) /*!< EXTI13 Interrupt */ +#define HAL_ITLINE_EXTI14 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14) /*!< EXTI14 Interrupt */ +#define HAL_ITLINE_EXTI15 ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15) /*!< EXTI15 Interrupt */ +#if defined (UCPD1) +#define HAL_ITLINE_UCPD1 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD1) /*!< UCPD1 Interrupt */ +#endif /* UCPD1 */ +#if defined (UCPD2) +#define HAL_ITLINE_UCPD2 ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD2) /*!< UCPD2 Interrupt */ +#endif /* UCPD2 */ +#if defined (STM32G0C1xx) || defined (STM32G0B1xx) || defined (STM32G0B0xx) +#define HAL_ITLINE_USB ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB) /*!< USB Interrupt */ +#endif /* STM32G0C1xx) || STM32G0B1xx) || STM32G0B0xx */ +#define HAL_ITLINE_DMA1_CH1 ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1) /*!< DMA1 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA1_CH2 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2) /*!< DMA1 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA1_CH3 ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3) /*!< DMA1 Channel 3 Interrupt */ +#define HAL_ITLINE_DMAMUX1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX1) /*!< DMAMUX1 Interrupt */ +#define HAL_ITLINE_DMA1_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4) /*!< DMA1 Channel 4 Interrupt */ +#define HAL_ITLINE_DMA1_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5) /*!< DMA1 Channel 5 Interrupt */ +#if defined(DMA1_Channel7) +#define HAL_ITLINE_DMA1_CH6 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6) /*!< DMA1 Channel 6 Interrupt */ +#define HAL_ITLINE_DMA1_CH7 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7) /*!< DMA1 Channel 7 Interrupt */ +#endif /* DMA1_Channel7 */ +#if defined (DMA2) +#define HAL_ITLINE_DMA2_CH1 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH1) /*!< DMA2 Channel 1 Interrupt */ +#define HAL_ITLINE_DMA2_CH2 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH2) /*!< DMA2 Channel 2 Interrupt */ +#define HAL_ITLINE_DMA2_CH3 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3) /*!< DMA2 Channel 3 Interrupt */ +#define HAL_ITLINE_DMA2_CH4 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4) /*!< DMA2 Channel 4 Interrupt */ +#define HAL_ITLINE_DMA2_CH5 ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5) /*!< DMA2 Channel 5 Interrupt */ +#endif /* DMA2 */ +#define HAL_ITLINE_ADC ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC) /*!< ADC Interrupt */ +#if defined (COMP1) +#define HAL_ITLINE_COMP1 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1) /*!< COMP1 Interrupt -> exti[17] */ +#endif /* COMP1 */ +#if defined (COMP2) +#define HAL_ITLINE_COMP2 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2) /*!< COMP2 Interrupt -> exti[18] */ +#endif /* COMP2 */ +#if defined (COMP3) +#define HAL_ITLINE_COMP3 ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP3) /*!< COMP3 Interrupt -> exti[1x] */ +#endif /* COMP3 */ +#define HAL_ITLINE_TIM1_BRK ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK) /*!< TIM1 BRK Interrupt */ +#define HAL_ITLINE_TIM1_UPD ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD) /*!< TIM1 UPD Interrupt */ +#define HAL_ITLINE_TIM1_TRG ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG) /*!< TIM1 TRG Interrupt */ +#define HAL_ITLINE_TIM1_CCU ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU) /*!< TIM1 CCU Interrupt */ +#define HAL_ITLINE_TIM1_CC ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC) /*!< TIM1 CC Interrupt */ +#if defined (TIM2) +#define HAL_ITLINE_TIM2 ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB) /*!< TIM2 Interrupt */ +#endif /* TIM2 */ +#define HAL_ITLINE_TIM3 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB) /*!< TIM3 Interrupt */ +#if defined (TIM4) +#define HAL_ITLINE_TIM4 ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM4_GLB) /*!< TIM4 Interrupt */ +#endif /* TIM4 */ +#if defined(TIM6) +#define HAL_ITLINE_TIM6 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB) /*!< TIM6 Interrupt */ +#endif /* TIM6 */ +#if defined(DAC1) +#define HAL_ITLINE_DAC ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC) /*!< DAC Interrupt */ +#endif /* DAC1 */ +#if defined(LPTIM1) +#define HAL_ITLINE_LPTIM1 ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM1_GLB) /*!< LPTIM1 Interrupt -> exti[29] */ +#endif /* LPTIM1 */ +#if defined(TIM7) +#define HAL_ITLINE_TIM7 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB) /*!< TIM7 Interrupt */ +#endif /* TIM7 */ +#if defined(LPTIM2) +#define HAL_ITLINE_LPTIM2 ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_LPTIM2_GLB) /*!< LPTIM2 Interrupt -> exti[30] */ +#endif /* LPTIM2 */ +#define HAL_ITLINE_TIM14 ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB) /*!< TIM14 Interrupt */ +#if defined(TIM15) +#define HAL_ITLINE_TIM15 ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB) /*!< TIM15 Interrupt */ +#endif /* TIM15 */ +#define HAL_ITLINE_TIM16 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB) /*!< TIM16 Interrupt */ +#if defined (FDCAN1) || defined (FDCAN2) +#define HAL_ITLINE_FDCAN1_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN1_IT0) /*!< FDCAN1_IT0 Interrupt */ +#define HAL_ITLINE_FDCAN2_IT0 ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN2_IT0) /*!< FDCAN2_IT0 Interrupt */ +#endif /* FDCAN1 || FDCAN2 */ +#define HAL_ITLINE_TIM17 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB) /*!< TIM17 Interrupt */ +#if defined (FDCAN1) || defined (FDCAN2) +#define HAL_ITLINE_FDCAN1_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN1_IT1) /*!< FDCAN1_IT1 Interrupt */ +#define HAL_ITLINE_FDCAN2_IT1 ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN2_IT1) /*!< FDCAN2_IT1 Interrupt */ +#endif /* FDCAN1 || FDCAN2 */ +#define HAL_ITLINE_I2C1 ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB) /*!< I2C1 Interrupt -> exti[23] */ +#define HAL_ITLINE_I2C2 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB) /*!< I2C2 Interrupt -> exti[24] */ +#if defined (I2C3) +#define HAL_ITLINE_I2C3 ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C3_GLB) /*!< I2C3 Interrupt -> exti[22] */ +#endif /* I2C3 */ +#define HAL_ITLINE_SPI1 ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1) /*!< SPI1 Interrupt */ +#define HAL_ITLINE_SPI2 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2) /*!< SPI2 Interrupt */ +#if defined (SPI3) +#define HAL_ITLINE_SPI3 ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI3) /*!< SPI3 Interrupt */ +#endif /* SPI3 */ +#define HAL_ITLINE_USART1 ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB) /*!< USART1 GLB Interrupt -> exti[25] */ +#define HAL_ITLINE_USART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB) /*!< USART2 GLB Interrupt -> exti[26] */ +#if defined (LPUART2) +#define HAL_ITLINE_LPUART2 ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_LPUART2_GLB) /*!< LPUART2 GLB Interrupt -> exti[26] */ +#endif /* LPUART2 */ +#if defined(USART3) +#define HAL_ITLINE_USART3 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB) /*!< USART3 Interrupt .... */ +#endif /* USART3 */ +#if defined(USART4) +#define HAL_ITLINE_USART4 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB) /*!< USART4 Interrupt .... */ +#endif /* USART4 */ +#if defined (LPUART1) +#define HAL_ITLINE_LPUART1 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART1_GLB) /*!< LPUART1 Interrupt -> exti[28]*/ +#endif /* LPUART1 */ +#if defined (USART5) +#define HAL_ITLINE_USART5 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB) /*!< USART5 Interrupt .... */ +#endif /* USART5 */ +#if defined (USART6) +#define HAL_ITLINE_USART6 ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB) /*!< USART6 Interrupt .... */ +#endif /* USART6 */ +#if defined (CEC) +#define HAL_ITLINE_CEC ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC) /*!< CEC Interrupt -> exti[27] */ +#endif /* CEC */ +#if defined (RNG) +#define HAL_ITLINE_RNG ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_RNG) /*!< RNG Interrupt */ +#endif /* RNG */ +#if defined (AES) +#define HAL_ITLINE_AES ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_AES) /*!< AES Interrupt */ +#endif /* AES */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @defgroup DBG_Exported_Macros DBG Exported Macros + * @{ + */ + +/** @brief Freeze and Unfreeze Peripherals in Debug mode + */ +#if defined(DBG_APB_FZ1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP) +#endif /* DBG_APB_FZ1_DBG_TIM2_STOP */ + +#if defined(DBG_APB_FZ1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP) +#endif /* DBG_APB_FZ1_DBG_TIM3_STOP */ + +#if defined(DBG_APB_FZ1_DBG_TIM4_STOP) +#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP) +#endif /* DBG_APB_FZ1_DBG_TIM4_STOP */ + +#if defined(DBG_APB_FZ1_DBG_TIM6_STOP) +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP) +#endif /* DBG_APB_FZ1_DBG_TIM6_STOP */ + +#if defined(DBG_APB_FZ1_DBG_TIM7_STOP) +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP) +#endif /* DBG_APB_FZ1_DBG_TIM7_STOP */ + +#if defined(DBG_APB_FZ1_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP) +#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP) +#endif /* DBG_APB_FZ1_DBG_RTC_STOP */ + +#if defined(DBG_APB_FZ1_DBG_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP) +#endif /* DBG_APB_FZ1_DBG_WWDG_STOP */ + +#if defined(DBG_APB_FZ1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP) +#endif /* DBG_APB_FZ1_DBG_IWDG_STOP */ + +#if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP) +#endif /* DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP */ + +#if defined(DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP) +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP) +#endif /* DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP */ + +#if defined(DBG_APB_FZ1_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP) +#endif /* DBG_APB_FZ1_DBG_LPTIM1_STOP */ + +#if defined(DBG_APB_FZ1_DBG_LPTIM2_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP) +#endif /* DBG_APB_FZ1_DBG_LPTIM2_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM1_STOP) +#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM1_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM14_STOP) +#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM14_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM15_STOP) +#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM15_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM16_STOP) +#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM16_STOP */ + +#if defined(DBG_APB_FZ2_DBG_TIM17_STOP) +#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP) +#endif /* DBG_APB_FZ2_DBG_TIM17_STOP */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros + * @{ + */ + +/** + * @brief ISR wrapper check + * @note Allow to determine interrupt source per line. + */ +#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF)) + +/** @brief Main Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) + +/** @brief System Flash memory mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) + +/** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() \ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0)) + +/** + * @brief Return the boot mode as configured by user. + * @retval The boot mode as configured by user. The returned value can be one + * of the following values @ref SYSCFG_BootMode + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) + +/** @brief SYSCFG Break ECC lock. + * Enable and lock the connection of Flash ECC error connection to TIM1 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) + + +/** @brief SYSCFG Break Cortex-M0+ Lockup lock. + * Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/15/16/17 Break input + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) + +#if defined(SYSCFG_CFGR2_PVDL) +/** @brief SYSCFG Break PVD lock. + * Enables and locks the PVD connection with Timer1/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register + * @note The selected configuration is locked and can be unlocked only by system reset + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) +#endif /* SYSCFG_CFGR2_PVDL */ + +/** @brief SYSCFG Break SRAM PARITY lock + * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/15/16/17 + * @note The selected configuration is locked and can only be unlocked by system reset + */ +#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL) + +/** @brief Parity check on RAM disable macro + * @note Disabling the parity check on RAM locks the configuration bit. + * To re-enable the parity check on RAM perform a system reset. + */ +#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF) + +/** @brief Set the PEF bit to clear the SRAM Parity Error Flag. + */ +#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) + +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0U) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0U) + +#if defined(SYSCFG_CDEN_SUPPORT) +/** @brief Clamping Diode on specific pins enable/disable macros + * @param __PIN__ This parameter can be a combination of values @ref SYSCFG_ClampingDiode + */ +#define __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\ + SET_BIT(SYSCFG->CFGR2, (__PIN__));\ + }while(0U) + +#define __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\ + CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\ + }while(0U) +#endif /* SYSCFG_CDEN_SUPPORT */ + +/** @brief ISR wrapper check + * @note Allow to determine interrupt source per line. + */ +#define __HAL_SYSCFG_GET_PENDING_IT(__SOURCE__) \ + (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFFU)) + +/** @brief selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register + * @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL + */ +#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\ + SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\ + }while(0U) + +#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0U) + +/** @brief IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register + * @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL + */ +#define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__) do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\ + SET_BIT(SYSCFG->CFGR1,(__SEL__));\ + }while(0U) + +/** + * @brief Return the IROut Polarity mode as configured by user. + * @retval The IROut polarity as configured by user. The returned value can be one + * of @ref HAL_IR_POL_SEL + */ +#define __HAL_SYSCFG_GET_POLARITY() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL) + +/** @brief Break input to TIM1/15/16/17 capability enable/disable macros + * @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break + */ +#define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ + SET_BIT(SYSCFG->CFGR2, (__BREAK__));\ + }while(0U) + +#define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__) do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\ + CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\ + }while(0U) + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros + * @{ + */ +#if defined (PWR_PVD_SUPPORT) +#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP) || \ + ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ + ((__CONFIG__) == SYSCFG_BREAK_ECC) || \ + ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) +#else +#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP) || \ + ((__CONFIG__) == SYSCFG_BREAK_ECC) || \ + ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) +#endif /* PWR_PVD_SUPPORT */ + +#if defined(SYSCFG_CDEN_SUPPORT) +#define IS_SYSCFG_CLAMPINGDIODE(__PIN__) ((((__PIN__) & SYSCFG_CDEN_PA1) == SYSCFG_CDEN_PA1) || \ + (((__PIN__) & SYSCFG_CDEN_PA3) == SYSCFG_CDEN_PA3) || \ + (((__PIN__) & SYSCFG_CDEN_PA5) == SYSCFG_CDEN_PA5) || \ + (((__PIN__) & SYSCFG_CDEN_PA6) == SYSCFG_CDEN_PA6) || \ + (((__PIN__) & SYSCFG_CDEN_PA13) == SYSCFG_CDEN_PA13) || \ + (((__PIN__) & SYSCFG_CDEN_PB0) == SYSCFG_CDEN_PB0) || \ + (((__PIN__) & SYSCFG_CDEN_PB1) == SYSCFG_CDEN_PB1) || \ + (((__PIN__) & SYSCFG_CDEN_PB2) == SYSCFG_CDEN_PB2)) +#endif /* SYSCFG_CDEN_SUPPORT */ + +#if defined (USART4) +#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) +#else +#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ + ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2)) +#endif /* USART4 */ +#define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \ + ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED)) + +#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) +#define IS_SYSCFG_DBATT_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_UCPD1_STROBE) || \ + ((__CONFIG__) == SYSCFG_UCPD2_STROBE) || \ + ((__CONFIG__) == (SYSCFG_UCPD1_STROBE | SYSCFG_UCPD2_STROBE))) +#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */ +#if defined(VREFBUF) +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ + ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) + +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ + ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) + +#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) +#endif /* VREFBUF */ + +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ + (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) + +#define IS_HAL_REMAP_PIN(RMP) (((RMP) == SYSCFG_REMAP_PA11) || \ + ((RMP) == SYSCFG_REMAP_PA12) || \ + ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12))) +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions + * @{ + */ + +/* Initialization and Configuration functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions + * @{ + */ + +/* DBGMCU Peripheral Control functions *****************************************/ +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); + +/** + * @} + */ + +/* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions + * @{ + */ + +/* SYSCFG Control functions ****************************************************/ + +#if defined(VREFBUF) +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); +void HAL_SYSCFG_DisableVREFBUF(void); +#endif /* VREFBUF */ + +void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); +void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); +void HAL_SYSCFG_EnableRemap(uint32_t PinRemap); +void HAL_SYSCFG_DisableRemap(uint32_t PinRemap); +#if defined(SYSCFG_CDEN_SUPPORT) +void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig); +void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig); +#endif /* SYSCFG_CDEN_SUPPORT */ +#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) +void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery); +#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h (revision 3) @@ -0,0 +1,1756 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_adc.h + * @author MCD Application Team + * @brief Header file of ADC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_ADC_H +#define STM32G0xx_HAL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/* Include low level driver */ +#include "stm32g0xx_ll_adc.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief ADC group regular oversampling structure definition + */ +typedef struct +{ + uint32_t Ratio; /*!< Configures the oversampling ratio. + This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ + + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. + This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ + + uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. + This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ + +} ADC_OversamplingTypeDef; + +/** + * @brief Structure definition of ADC instance and ADC group regular. + * @note Parameters of this structure are shared within 2 scopes: + * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, + * ScanConvMode, EOCSelection, LowPowerAutoWait. + * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, + * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. + * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behavior in case of intended action to update another parameter + * (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. + This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. + Note: The ADC clock configuration is common to all ADC instances. + Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only + if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC + must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. + Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. + Note: This parameter can be modified only if all ADC instances are disabled. */ + + uint32_t Resolution; /*!< Configure the ADC resolution. + This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ + + uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). + Refer to reference manual for alignments formats versus resolutions. + This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ + + uint32_t ScanConvMode; /*!< Configure the sequencer of ADC group regular. + On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are + available: + - sequencer configured to fully configurable: + sequencer length and each rank affectation to a channel are configurable. + - Sequence length: Set number of ranks in the scan sequence. + - Sequence direction: Unless specified in parameters, sequencer + scan direction is forward (from rank 1 to rank n). + - sequencer configured to not fully configurable: + sequencer length and each rank affectation to a channel are fixed by channel HW number. + - Sequence length: Number of ranks in the scan sequence is + defined by number of channels set in the sequence, + rank of each channel is fixed by channel HW number. + (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + - Sequence direction: Unless specified in parameters, sequencer + scan direction is forward (from lowest channel number to + highest channel number). + This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. + Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): + If only 1 channel is set: Conversion is performed in single mode. + If several channels are set: Conversions are performed in sequence mode. + This parameter can be a value of @ref ADC_Scan_mode */ + + uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. + This parameter can be a value of @ref ADC_EOCSelection. */ + + FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous + conversion (for ADC group regular) has been retrieved by user software, + using function HAL_ADC_GetValue(). + This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun + for low frequency applications. + This parameter can be set to ENABLE or DISABLE. + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). + Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: + use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */ + + FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). + This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). + This parameter can be set to ENABLE or DISABLE. + Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ + + FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, + after the first ADC conversion start trigger occurred (software start or external trigger). + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. + This parameter is dependent on ScanConvMode: + - sequencer configured to fully configurable: + Number of ranks in the scan sequence is configurable using this parameter. + Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. + Afterwards, when all needed sequencer ranks are set, parameter 'NbrOfConversion' can be updated without modifying configuration of sequencer ranks + (sequencer ranks above 'NbrOfConversion' are discarded). + - sequencer configured to not fully configurable: + Number of ranks in the scan sequence is defined by number of channels set in the sequence. This parameter is discarded. + This parameter must be a number between Min_Data = 1 and Max_Data = 8. + Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ + + FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence + (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. + Note: On this STM32 series, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */ + + uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. + If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. + This parameter can be a value of @ref ADC_regular_external_trigger_source. + Caution: external trigger source is common to all ADC instances. */ + + uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. + If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. + This parameter can be a value of @ref ADC_regular_external_trigger_edge */ + + FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) + or in continuous mode (DMA transfer unlimited, whatever number of conversions). + This parameter can be set to ENABLE or DISABLE. + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ + + uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). + This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. + Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear + end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function + HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). + Note: Error reporting with respect to the conversion mode: + - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data + overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. + - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ + + uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */ + + uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */ + + FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */ + + ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. + Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ + + uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode. + This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ. + Note: ADC trigger frequency mode must be set to low frequency when + a duration is exceeded before ADC conversion start trigger event + (between ADC enable and ADC conversion start trigger event + or between two ADC conversion start trigger event). + Duration value: Refer to device datasheet, parameter "tIdle". + Note: When ADC trigger frequency mode is set to low frequency, + some rearm cycles are inserted before performing ADC conversion + start, inducing a delay of 2 ADC clock cycles. */ + +} ADC_InitTypeDef; + +/** + * @brief Structure definition of ADC channel for regular group + * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled or enabled without conversion on going on regular group. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) + * on the fly). + */ +typedef struct +{ + uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL + Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ + + uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its conversion rank. + This parameter is dependent on ScanConvMode: + - sequencer configured to fully configurable: + Channels ordering into each rank of scan sequence: + whatever channel can be placed into whatever rank. + - sequencer configured to not fully configurable: + rank of each channel is fixed by channel HW number. + (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. + This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */ + + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time + (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON + Note: On this STM32 family, two different sampling time settings are available (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), each channel can use one of these two settings. + + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values. */ + +} ADC_ChannelConfTypeDef; + +/** + * @brief Structure definition of ADC analog watchdog + * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular. + * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular. + */ +typedef struct +{ + uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. + For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') + For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) + This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ + + uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. + For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular. + For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. + This parameter can be a value of @ref ADC_analog_watchdog_mode. */ + + uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. + For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). + For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ + + FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number + between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits + the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [15:4] (12 most significant bits). */ + + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number + between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits + the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [15:4] (12 most significant bits). */ +} ADC_AnalogWDGConfTypeDef; + +/** @defgroup ADC_States ADC States + * @{ + */ + +/** + * @brief HAL ADC state machine: ADC states definition (bitfields) + * @note ADC state machine is managed by bitfields, state must be compared + * with bit by bit. + * For example: + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " + */ +/* States of ADC global scope */ +#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ + +/* States of ADC errors */ +#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ + +/* States of ADC group regular */ +#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ + +/* States of ADC group injected */ +#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group injected is ongoing or can occur (either by auto-injection mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))*/ +#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow occurrence */ + +/* States of ADC analog watchdogs */ +#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ + +/* States of ADC multi-mode */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave state, controlled by another ADC master (when feature available) */ + + +/** + * @} + */ + +/** + * @brief ADC handle Structure definition + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +typedef struct __ADC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +{ + ADC_TypeDef *Instance; /*!< Register base address */ + ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + HAL_LockTypeDef Lock; /*!< ADC locking object */ + __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ + __IO uint32_t ErrorCode; /*!< ADC Error code */ + + uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ + void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ + void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ + void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ + void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ + void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ + void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ + void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} ADC_HandleTypeDef; + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ADC Callback ID enumeration definition + */ +typedef enum +{ + HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ + HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ + HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ + HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ + HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ + HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ +} HAL_ADC_CallbackIDTypeDef; + +/** + * @brief HAL ADC Callback pointer definition + */ +typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_Error_Code ADC Error Code + * @{ + */ +#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, + enable/disable, erroneous state, ...) */ +#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + * @{ + */ +#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */ +#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ +#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ + +#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ +#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ +#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ +#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ +#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ +#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ +#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ +#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ +#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ +#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ +#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ +#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ +#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ +#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ +#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment + * @{ + */ +#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_Scan_mode ADC sequencer scan mode + * @{ + */ +/* Note: On this STM32 family, ADC group regular sequencer both modes */ +/* "fully configurable" or "not fully configurable" are */ +/* available. */ +/* Scan mode values must be compatible with other STM32 devices having */ +/* a configurable sequencer. */ +/* Scan direction setting values are defined by taking in account */ +/* already defined values for other STM32 devices: */ +/* ADC_SCAN_DISABLE (0x00000000UL) */ +/* ADC_SCAN_ENABLE (0x00000001UL) */ +/* Sequencer fully configurable with only rank 1 enabled is considered */ +/* as default setting equivalent to scan enable. */ +/* In case of migration from another STM32 device, the user will be */ +/* warned of change of setting choices with assert check. */ +#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */ +#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */ + +#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */ +#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */ + +#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */ +#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */ +/** + * @} + */ + +/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source + * @{ + */ +/* ADC group regular trigger sources for all ADC instances */ +#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#if defined(TIM2) +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#endif +#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#if defined(TIM4) +#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#endif +#if defined(TIM6) +#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#endif +#if defined(TIM15) +#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ +#endif +#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +/** + * @} + */ + +/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) + * @{ + */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ +#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions + * @{ + */ +#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ +#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data + * @{ + */ +#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ +#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ +#define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */ + +#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ +#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ +#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ +#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ +#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ +#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ +#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ +#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels + * @{ + */ +#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */ +#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ +#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ +#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ +#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ +#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ +#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ +#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ +#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ +#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ +#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ +#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ +#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ +#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ +#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ +#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ +#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ +#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ +#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ +#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ +#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ +#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ +#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ +#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ +#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ +#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ +#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ +#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */ +#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ +#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ +#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode + * @{ + */ +#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ +#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio + * @{ + */ +#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift + * @{ + */ +#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ +#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + * @{ + */ +#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ +#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode + * @{ + */ +#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ +#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ +/** + * @} + */ + +/** @defgroup ADC_Event_type ADC Event type + * @{ + */ +#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ +#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ +#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ +#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ +#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ +/** + * @} + */ +#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ + +/** @defgroup ADC_interrupts_definition ADC interrupts definition + * @{ + */ +#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ +#define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */ +#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ +#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ +#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ +#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ +#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC flags definition + * @{ + */ +#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ +#define ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC channel configuration ready flag */ +#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ +#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ +#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ +#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag */ +#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag */ +#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Test if conversion trigger of regular group is software start + * or external trigger. + * @param __HANDLE__ ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL) + +/** + * @brief Return resolution bits in CFGR1 register RES[1:0] field. + * @param __HANDLE__ ADC handle + * @retval Value of bitfield RES in CFGR1 register. + */ +#define ADC_GET_RESOLUTION(__HANDLE__) \ + (LL_ADC_GetResolution((__HANDLE__)->Instance)) + +/** + * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) + +/** + * @brief Simultaneously clear and set specific bits of the handle State. + * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), + * the first parameter is the ADC handle State, the second parameter is the + * bit field to clear, the third and last parameter is the bit field to set. + * @retval None + */ +#define ADC_STATE_CLR_SET MODIFY_REG + +/** + * @brief Enable ADC discontinuous conversion mode for regular group + * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. + * @retval None + */ +#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ + ((_REG_DISCONTINUOUS_MODE_) << 16U) + +/** + * @brief Enable the ADC auto off mode. + * @param _AUTOOFF_ Auto off bit enable or disable. + * @retval None + */ +#define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ + ((_AUTOOFF_) << 15U) + +/** + * @brief Enable the ADC auto delay mode. + * @param _AUTOWAIT_ Auto delay bit enable or disable. + * @retval None + */ +#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ + ((_AUTOWAIT_) << 14U) + +/** + * @brief Enable ADC continuous conversion mode. + * @param _CONTINUOUS_MODE_ Continuous mode. + * @retval None + */ +#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ + ((_CONTINUOUS_MODE_) << 13U) + +/** + * @brief Enable ADC overrun mode. + * @param _OVERRUN_MODE_ Overrun mode. + * @retval Overrun bit setting to be programmed into CFGR register + */ +/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ +/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ +/* as the default case to be compliant with other STM32 devices. */ +#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ + ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ + )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \ + ) + +/** + * @brief Set ADC scan mode with differentiation of sequencer setting + * fixed or configurable + * @param _SCAN_MODE_ Scan conversion mode. + * @retval None + */ +/* Note: Scan mode set using this macro (instead of parameter direct set) */ +/* due to different modes on other STM32 devices: */ +/* if scan mode is disabled, sequencer is set to fully configurable */ +/* with setting of only rank 1 enabled afterwards. */ +#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \ + ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \ + )? \ + ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \ + : \ + (ADC_CFGR1_CHSELRMOD) \ + ) + +/** + * @brief Enable the ADC DMA continuous request. + * @param _DMACONTREQ_MODE_: DMA continuous request mode. + * @retval None + */ +#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ + ((_DMACONTREQ_MODE_) << 1U) + +/** + * @brief Shift the AWD threshold in function of the selected ADC resolution. + * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. + * If resolution 12 bits, no shift. + * If resolution 10 bits, shift of 2 ranks on the left. + * If resolution 8 bits, shift of 4 ranks on the left. + * If resolution 6 bits, shift of 6 ranks on the left. + * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) + * @param __HANDLE__ ADC handle + * @param _Threshold_ Value to be shifted + * @retval None + */ +#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ + ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U)) + +#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256)) + +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ + ((RESOLUTION) == ADC_RESOLUTION_10B) || \ + ((RESOLUTION) == ADC_RESOLUTION_8B) || \ + ((RESOLUTION) == ADC_RESOLUTION_6B) ) + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ + ((ALIGN) == ADC_DATAALIGN_LEFT) ) + +#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ + ((SCAN_MODE) == ADC_SCAN_ENABLE) || \ + ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED) || \ + ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD) ) + +#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) + +#if defined(TIM15) && defined(TIM6) && defined(TIM2) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T6_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T15_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \ + ((REGTRIG) == ADC_SOFTWARE_START) ) +#elif defined(TIM15) && defined(TIM6) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T6_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T15_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \ + ((REGTRIG) == ADC_SOFTWARE_START) ) +#elif defined(TIM2) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \ + ((REGTRIG) == ADC_SOFTWARE_START) ) +#else +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \ + ((REGTRIG) == ADC_SOFTWARE_START) ) +#endif + +#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ + ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)) + +#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ + ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) + +#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \ + ((RANK) == ADC_RANK_NONE) ) + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \ + ((RANK) == ADC_REGULAR_RANK_2 ) || \ + ((RANK) == ADC_REGULAR_RANK_3 ) || \ + ((RANK) == ADC_REGULAR_RANK_4 ) || \ + ((RANK) == ADC_REGULAR_RANK_5 ) || \ + ((RANK) == ADC_REGULAR_RANK_6 ) || \ + ((RANK) == ADC_REGULAR_RANK_7 ) || \ + ((RANK) == ADC_REGULAR_RANK_8 ) ) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_16) || \ + ((CHANNEL) == ADC_CHANNEL_17) || \ + ((CHANNEL) == ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ + ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ + ((CHANNEL) == ADC_CHANNEL_VBAT) ) + +#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \ + ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) ) + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ + ((TIME) == ADC_SAMPLETIME_3CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_12CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_39CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_79CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_160CYCLES_5) ) + +#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) ) + +#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) + +#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \ + ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) ) + +#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \ + ((EVENT) == ADC_AWD1_EVENT) || \ + ((EVENT) == ADC_AWD2_EVENT) || \ + ((EVENT) == ADC_AWD3_EVENT) || \ + ((EVENT) == ADC_OVR_EVENT) ) + +/** + * @brief Verify that a given value is aligned with the ADC resolution range. + * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). + * @param __ADC_VALUE__ value checked against the resolution. + * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) + */ +#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ + ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) + +/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification + * @{ + */ +#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL)) +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ + +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + +/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ +#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) + +#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ + +/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. + * @{ + */ + +/** @brief Reset ADC handle state. + * @param __HANDLE__ ADC handle + * @retval None + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @brief Enable ADC interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable ADC interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** @brief Checks if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC interrupt source to check + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @retval State of interruption (SET or RESET) + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Check whether the specified ADC flag is set or not. + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag + * This parameter can be one of the following values: + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) + * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) + * @retval State of flag (TRUE or FALSE). + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified ADC flag. + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag + * This parameter can be one of the following values: + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) + * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) + * @retval None + */ +/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (((__HANDLE__)->Instance->ISR) = (__FLAG__)) + +/** + * @} + */ + +/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals ADC_CHANNEL_x. + * @note Example: + * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (1) + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT + * @arg @ref ADC_CHANNEL_TEMPSENSOR + * @arg @ref ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) + +/** + * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "ADC_CHANNEL_4". + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (1) + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT (2) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref ADC_CHANNEL_VBAT (2) + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * ADC_CHANNEL_1, ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (1) + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT + * @arg @ref ADC_CHANNEL_TEMPSENSOR + * @arg @ref ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 (1) + * @arg @ref ADC_CHANNEL_16 (1) + * @arg @ref ADC_CHANNEL_17 (1) + * @arg @ref ADC_CHANNEL_18 + * @arg @ref ADC_CHANNEL_VREFINT + * @arg @ref ADC_CHANNEL_TEMPSENSOR + * @arg @ref ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_14 + * @arg @ref ADC_CHANNEL_15 + * @arg @ref ADC_CHANNEL_16 + * @arg @ref ADC_CHANNEL_17 + * @arg @ref ADC_CHANNEL_18 + */ +#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_VREFINT + * @arg @ref ADC_CHANNEL_TEMPSENSOR + * @arg @ref ADC_CHANNEL_VBAT + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ + __LL_ADC_COMMON_INSTANCE((__ADCx__)) + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data full-scale digital value + */ +#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ + __ADC_RESOLUTION_CURRENT__,\ + __ADC_RESOLUTION_TARGET__) \ +__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ + (__ADC_RESOLUTION_CURRENT__),\ + (__ADC_RESOLUTION_TARGET__)) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ + (__ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 series, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note On this STM32 series, calibration data of temperature sensor + * corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * temperature sensor. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature + * sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * On STM32G0, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32G0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ + (__TEMPSENSOR_TYP_CALX_V__),\ + (__TEMPSENSOR_CALX_TEMP__),\ + (__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include ADC HAL Extended module */ +#include "stm32g0xx_hal_adc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group2 + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); + +/* Non-blocking mode: Interruption */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); + +/* Non-blocking mode: DMA */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); + +/* ADC retrieve conversion value intended to be used with polling or interruption */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); + +/** + * @} + */ + +/* Peripheral State functions *************************************************/ +/** @addtogroup ADC_Exported_Functions_Group4 + * @{ + */ +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32G0xx_HAL_ADC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc_ex.h (revision 3) @@ -0,0 +1,189 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_adc_ex.h + * @author MCD Application Team + * @brief Header file of ADC HAL extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_ADC_EX_H +#define STM32G0xx_HAL_ADC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types + * @{ + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants + * @{ + */ + +/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Check whether or not ADC is independent. + * @param __HANDLE__ ADC handle. + * @note When multimode feature is not available, the macro always returns SET. + * @retval SET (ADC is independent) or RESET (ADC is not). + */ +#define ADC_IS_INDEPENDENT(__HANDLE__) (SET) + + +/** + * @brief Calibration factor size verification (7 bits maximum). + * @param __CALIBRATION_FACTOR__ Calibration factor value. + * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) + */ +#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) + +/** + * @brief Verify the ADC oversampling ratio. + * @param __RATIO__ programmed ADC oversampling ratio. + * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) + */ +#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) + +/** + * @brief Verify the ADC oversampling shift. + * @param __SHIFT__ programmed ADC oversampling shift. + * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) + */ +#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) + +/** + * @brief Verify the ADC oversampling triggered mode. + * @param __MODE__ programmed ADC oversampling triggered mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ + ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) + + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADCEx_Exported_Functions + * @{ + */ + +/** @addtogroup ADCEx_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ + +/* ADC calibration */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ +void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** @addtogroup ADCEx_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_ADC_EX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h (revision 3) @@ -0,0 +1,884 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_comp.h + * @author MCD Application Team + * @brief Header file of COMP HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_COMP_H +#define STM32G0xx_HAL_COMP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" +#include "stm32g0xx_ll_exti.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ +#if defined (COMP1) || defined (COMP2) + +/** @addtogroup COMP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup COMP_Exported_Types COMP Exported Types + * @{ + */ + +/** + * @brief COMP Init structure definition + */ +typedef struct +{ + + uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances + (2 consecutive instances odd and even COMP and COMP). + Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode, except for window mode with COMP2 and COMP3 (for devices featuring COMP3): it must be set from COMP3 instance. + This parameter can be a value of @ref COMP_WindowMode */ + + uint32_t WindowOutput; /*!< Set window mode output. + This parameter can be a value of @ref COMP_WindowOutput */ + + uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed. + Note: For the characteristics of comparator power modes + (propagation delay and power consumption), refer to device datasheet. + This parameter can be a value of @ref COMP_PowerMode */ + + uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). + This parameter can be a value of @ref COMP_InputPlus */ + + uint32_t InputMinus; /*!< Set comparator input minus (inverting input). + This parameter can be a value of @ref COMP_InputMinus */ + + uint32_t Hysteresis; /*!< Set comparator hysteresis mode of the input minus. + This parameter can be a value of @ref COMP_Hysteresis */ + + uint32_t OutputPol; /*!< Set comparator output polarity. + This parameter can be a value of @ref COMP_OutputPolarity */ + + uint32_t BlankingSrce; /*!< Set comparator blanking source. + This parameter can be a value of @ref COMP_BlankingSrce */ + + uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI). + This parameter can be a value of @ref COMP_EXTI_TriggerMode */ + +} COMP_InitTypeDef; + +/** + * @brief HAL COMP state machine: HAL COMP states definition + */ +#define COMP_STATE_BITFIELD_LOCK (0x10U) +typedef enum +{ + HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized */ + HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */ + HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */ + HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */ + HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */ + HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */ +} HAL_COMP_StateTypeDef; + +/** + * @brief COMP Handle Structure definition + */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +typedef struct __COMP_HandleTypeDef +#else +typedef struct +#endif +{ + COMP_TypeDef *Instance; /*!< Register base address */ + COMP_InitTypeDef Init; /*!< COMP required parameters */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */ + __IO uint32_t ErrorCode; /*!< COMP error code */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */ + void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */ + void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */ +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ +} COMP_HandleTypeDef; + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/** + * @brief HAL COMP Callback ID enumeration definition + */ +typedef enum +{ + HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */ + HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */ + HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */ +} HAL_COMP_CallbackIDTypeDef; + +/** + * @brief HAL COMP Callback pointer definition + */ +typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */ + +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup COMP_Exported_Constants COMP Exported Constants + * @{ + */ + +/** @defgroup COMP_Error_Code COMP Error Code + * @{ + */ +#define HAL_COMP_ERROR_NONE (0x00UL) /*!< No error */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL) /*!< Invalid Callback error */ +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup COMP_WindowMode COMP Window Mode + * @{ + */ +#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ +#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ +#define COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | COMP_WINDOWMODE_COMP2) /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible). If used from COMP3 instance (when available), comparators instances pair COMP2 and COMP3 have their input plus connected together, the common input is COMP2 input plus (COMP3 input plus is no more accessible). */ +/** + * @} + */ + +/** @defgroup COMP_WindowOutput COMP Window output + * @{ + */ +#define COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. */ +#define COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT) /*!< Window output synthetized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */ +#define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | COMP_WINDOWMODE_COMP2) /*!< Window output synthetized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */ +#if defined(COMP3) +#define COMP_WINDOWOUTPUT_COMP3 (COMP_CSR_WINOUT) /*!< Window output synthetized on COMP3 output: COMP3 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). */ +#endif +#define COMP_WINDOWOUTPUT_BOTH (0x00000001UL) /*!< Window output synthetized on both comparators output of pair of comparator selected (COMP1 and COMP2, or COMP2 and COMP3 for devices featuring COMP3 instance): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */ +/** + * @} + */ + +/** @defgroup COMP_PowerMode COMP power mode + * @{ + */ +/* Note: For the characteristics of comparator power modes */ +/* (propagation delay and power consumption), */ +/* refer to device datasheet. */ +#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */ +#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */ +/** + * @} + */ + +/** @defgroup COMP_InputPlus COMP input plus (non-inverting input) + * @{ + */ +#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2, pin PB0 for COMP3 (for devices featuring COMP3 instance)) */ +#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2, pin PC1 for COMP3 (for devices featuring COMP3 instance)) */ +#define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2, pin PE7 for COMP3 (for devices featuring COMP3 instance)) */ +/** + * @} + */ + +/** @defgroup COMP_InputMinus COMP input minus (inverting input) + * @{ + */ +#define COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL) /*!< Comparator input minus connected to 1/4 VrefInt */ +#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */ +#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */ +#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */ +#define COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */ +#define COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ +#define COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2, pin PB2 for COMP3 (for devices featuring COMP3 instance)) */ +#define COMP_INPUT_MINUS_IO2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2, pin PC0 for COMP3 (for devices featuring COMP3 instance)) */ +#define COMP_INPUT_MINUS_IO3 (COMP_CSR_INMSEL_3 ) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2, pin PE8 for COMP3 (for devices featuring COMP3 instance)) */ +/** + * @} + */ + +/** @defgroup COMP_Hysteresis COMP hysteresis + * @{ + */ +#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */ +#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ +#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ +#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ +/** + * @} + */ + +/** @defgroup COMP_OutputPolarity COMP output Polarity + * @{ + */ +#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */ +#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */ +/** + * @} + */ + +/** @defgroup COMP_BlankingSrce COMP blanking source + * @{ + */ +#define COMP_BLANKINGSRC_NONE (0x00000000UL) /*!State = HAL_COMP_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) +#endif + +/** + * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE"). + * @param __HANDLE__ COMP handle + * @retval None + */ +#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE) + +/** + * @brief Enable the specified comparator. + * @param __HANDLE__ COMP handle + * @retval None + */ +#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) + +/** + * @brief Disable the specified comparator. + * @param __HANDLE__ COMP handle + * @retval None + */ +#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) + +/** + * @brief Lock the specified comparator configuration. + * @note Using this macro induce HAL COMP handle state machine being no + * more in line with COMP instance state. + * To keep HAL COMP handle state machine updated, it is recommended + * to use function "HAL_COMP_Lock')". + * @param __HANDLE__ COMP handle + * @retval None + */ +#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) + +/** + * @brief Check whether the specified comparator is locked. + * @param __HANDLE__ COMP handle + * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked + */ +#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK) + +/** + * @} + */ + +/** @defgroup COMP_Exti_Management COMP external interrupt line management + * @{ + */ + +/** + * @brief Enable the COMP1 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + } while(0) + +/** + * @brief Disable the COMP1 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + } while(0) + +/** + * @brief Enable the COMP1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Generate a software interrupt on the COMP1 EXTI line. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Check whether the COMP1 EXTI line rising flag is set. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP1_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Clear the COMP1 EXTI rising flag. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Check whether the COMP1 EXTI line falling flag is set. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Clear the COMP1 EXTI falling flag. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP2 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + } while(0) + +/** + * @brief Disable the COMP2 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + } while(0) + +/** + * @brief Enable the COMP2 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Generate a software interrupt on the COMP2 EXTI line. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Check whether the COMP2 EXTI line rising flag is set. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Clear the COMP2 EXTI rising flag. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Check whether the COMP2 EXTI line falling flag is set. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP2_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Clear the COMP2 EXTI falling flag. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP3 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @brief Disable the COMP3 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @brief Enable the COMP3 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @brief Disable the COMP3 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @brief Enable the COMP3 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + } while(0) + +/** + * @brief Disable the COMP3 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + } while(0) + +/** + * @brief Enable the COMP3 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @brief Disable the COMP3 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @brief Generate a software interrupt on the COMP3 EXTI line. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @brief Enable the COMP3 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @brief Disable the COMP3 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @brief Check whether the COMP3 EXTI line rising flag is set. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP3_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @brief Clear the COMP3 EXTI rising flag. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @brief Check whether the COMP3 EXTI line falling flag is set. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP3_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @brief Clear the COMP3 EXTI falling flag. + * @retval None + */ +#define __HAL_COMP_COMP3_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP3) + +/** + * @} + */ + +/** + * @} + */ + + +/* Private types -------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup COMP_Private_Constants COMP Private Constants + * @{ + */ + +/** @defgroup COMP_WindowMode_Instance_Differentiator COMP window mode instance differentiator + * @{ + */ +#define COMP_WINDOWMODE_COMP2 0x00001000U /*!< COMP window mode using common input of COMP instance: COMP2 */ +/** + * @} + */ + +/** @defgroup COMP_ExtiLine COMP EXTI Lines + * @{ + */ +#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM17) /*!< EXTI line 17 connected to COMP1 output */ +#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM18) /*!< EXTI line 18 connected to COMP2 output */ +#if defined(COMP3) +#define COMP_EXTI_LINE_COMP3 (EXTI_IMR1_IM20) /*!< EXTI line 20 connected to COMP3 output */ +#endif +/** + * @} + */ + +/** @defgroup COMP_ExtiLine COMP EXTI Lines + * @{ + */ +#define COMP_EXTI_IT (0x00000001UL) /*!< EXTI line event with interruption */ +#define COMP_EXTI_EVENT (0x00000002UL) /*!< EXTI line event only (without interruption) */ +#define COMP_EXTI_RISING (0x00000010UL) /*!< EXTI line event on rising edge */ +#define COMP_EXTI_FALLING (0x00000020UL) /*!< EXTI line event on falling edge */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup COMP_Private_Macros COMP Private Macros + * @{ + */ + +/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators + * @{ + */ +/** + * @brief Get the specified EXTI line for a comparator instance. + * @param __INSTANCE__ specifies the COMP instance. + * @retval value of @ref COMP_ExtiLine + */ +#if defined(COMP3) +#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ + :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \ + : COMP_EXTI_LINE_COMP3) +#else +#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ + : COMP_EXTI_LINE_COMP2) +#endif +/** + * @} + */ + +/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters + * @{ + */ +#if defined(COMP3) +#define IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__) \ +(((__INSTANCE__) == COMP3) \ + ? \ + (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) \ + :\ + (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) \ +) +#else +#define IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__) \ +(((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) +#endif + +#define IS_COMP_WINDOWOUTPUT(__WINDOWOUTPUT__) (((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_EACH_COMP) || \ + ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP1) || \ + ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP2) || \ + ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_BOTH) ) + +#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \ + ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) ) + +#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \ + ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \ + ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3)) + +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3)) + +#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \ + ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \ + ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \ + ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH)) + +#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \ + ((__POL__) == COMP_OUTPUTPOL_INVERTED)) + +#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ + ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC4) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2) \ + ) + +/* Note: Output blanking source common to all COMP instances */ +/* Macro kept for compatibility with other STM32 series */ +#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)) + + +#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ + ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \ + ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \ + ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \ + ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \ + ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \ + ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING)) + +#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \ + ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH)) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup COMP_Exported_Functions + * @{ + */ + +/** @addtogroup COMP_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp); +void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); +void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, + pCOMP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup COMP_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp); +void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @addtogroup COMP_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); +/* Callback in interrupt mode */ +void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/* Peripheral State functions **************************************************/ +/** @addtogroup COMP_Exported_Functions_Group4 + * @{ + */ +HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* COMP1 || COMP2 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_COMP_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cortex.h (revision 3) @@ -0,0 +1,387 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_CORTEX_H +#define STM32G0xx_HAL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types CORTEX Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. + */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +} MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U +#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) +#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01) +#define MPU_REGION_DISABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and Configuration functions *****************************/ +void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ +/* Peripheral Control functions *************************************************/ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1U) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_CORTEX_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h (revision 3) @@ -0,0 +1,533 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_dac.h + * @author MCD Application Team + * @brief Header file of DAC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_DAC_H +#define STM32G0xx_HAL_DAC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +#if defined(DAC1) + +/** @addtogroup DAC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Types DAC Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ + HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ + +} HAL_DAC_StateTypeDef; + +/** + * @brief DAC handle Structure definition + */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +typedef struct __DAC_HandleTypeDef +#else +typedef struct +#endif +{ + DAC_TypeDef *Instance; /*!< Register base address */ + + __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ + + HAL_LockTypeDef Lock; /*!< DAC locking object */ + + DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ + + DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ + + __IO uint32_t ErrorCode; /*!< DAC Error code */ + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + + void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +} DAC_HandleTypeDef; + +/** + * @brief DAC Configuration sample and hold Channel structure definition + */ +typedef struct +{ + uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ + + uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ + + uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel + This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. + This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ +} DAC_SampleAndHoldConfTypeDef; + +/** + * @brief DAC Configuration regular Channel structure definition + */ +typedef struct +{ + uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. + This parameter can be a value of @ref DAC_SampleAndHold */ + + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ + + uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . + This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ + + uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode + This parameter must be a value of @ref DAC_UserTrimming + DAC_UserTrimming is either factory or user trimming */ + + uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value + i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + + DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ + +} DAC_ChannelConfTypeDef; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DAC Callback ID enumeration definition + */ +typedef enum +{ + HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ + HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ + HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ + HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ + HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ + HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ + HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ + HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ + HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ + HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ + HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ +} HAL_DAC_CallbackIDTypeDef; + +/** + * @brief HAL DAC Callback pointer definition + */ +typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Constants DAC Exported Constants + * @{ + */ + +/** @defgroup DAC_Error_Code DAC Error Code + * @{ + */ +#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ +#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ +#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup DAC_trigger_selection DAC trigger selection + * @{ + */ +#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ +#define DAC_TRIGGER_SOFTWARE (DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1_OUT selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2_OUT selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ + +/** + * @} + */ + +/** @defgroup DAC_output_buffer DAC output buffer + * @{ + */ +#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U +#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1) + +/** + * @} + */ + +/** @defgroup DAC_Channel_selection DAC Channel selection + * @{ + */ +#define DAC_CHANNEL_1 0x00000000U +#define DAC_CHANNEL_2 0x00000010U +/** + * @} + */ + +/** @defgroup DAC_data_alignment DAC data alignment + * @{ + */ +#define DAC_ALIGN_12B_R 0x00000000U +#define DAC_ALIGN_12B_L 0x00000004U +#define DAC_ALIGN_8B_R 0x00000008U + +/** + * @} + */ + +/** @defgroup DAC_flags_definition DAC flags definition + * @{ + */ +#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) +#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) + +/** + * @} + */ + +/** @defgroup DAC_IT_definition DAC IT definition + * @{ + */ +#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) +#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) + +/** + * @} + */ + +/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral + * @{ + */ +#define DAC_CHIPCONNECT_DISABLE 0x00000000U +#define DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0) + +/** + * @} + */ + +/** @defgroup DAC_UserTrimming DAC User Trimming + * @{ + */ +#define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */ +#define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */ + +/** + * @} + */ +/** @defgroup DAC_SampleAndHold DAC power mode + * @{ + */ +#define DAC_SAMPLEANDHOLD_DISABLE 0x00000000U +#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) + +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Macros DAC Exported Macros + * @{ + */ + +/** @brief Reset DAC handle state. + * @param __HANDLE__ specifies the DAC handle. + * @retval None + */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** @brief Enable the DAC channel. + * @param __HANDLE__ specifies the DAC handle. + * @param __DAC_Channel__ specifies the DAC channel + * @retval None + */ +#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ + ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) + +/** @brief Disable the DAC channel. + * @param __HANDLE__ specifies the DAC handle + * @param __DAC_Channel__ specifies the DAC channel. + * @retval None + */ +#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ + ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) + +/** @brief Set DHR12R1 alignment. + * @param __ALIGNMENT__ specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__)) + +/** @brief Set DHR12R2 alignment. + * @param __ALIGNMENT__ specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__)) + +/** @brief Set DHR12RD alignment. + * @param __ALIGNMENT__ specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__)) + +/** @brief Enable the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt + * @retval None + */ +#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) + +/** @brief Disable the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt + * @retval None + */ +#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) + +/** @brief Check whether the specified DAC interrupt source is enabled or not. + * @param __HANDLE__ DAC handle + * @param __INTERRUPT__ DAC interrupt source to check + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt + * @retval State of interruption (SET or RESET) + */ +#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Get the selected DAC's flag status. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to get. + * This parameter can be any combination of the following values: + * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag + * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag + * @retval None + */ +#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the DAC's flag. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to clear. + * This parameter can be any combination of the following values: + * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag + * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag + * @retval None + */ +#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup DAC_Private_Macros DAC Private Macros + * @{ + */ +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ + ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ + ((CHANNEL) == DAC_CHANNEL_2)) + +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ + ((ALIGN) == DAC_ALIGN_12B_L) || \ + ((ALIGN) == DAC_ALIGN_8B_R)) + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) + +#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFU) + +/** + * @} + */ + +/* Include DAC HAL Extended module */ +#include "stm32g0xx_hal_dac_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac); +void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); +void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, + uint32_t Alignment); +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); + +void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); + +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); + +void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/* DAC callback registering/unregistering */ +HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, + pDAC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); + +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); +uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Functions DAC Private Functions + * @{ + */ +void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); +void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); +void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /*STM32G0xx_HAL_DAC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h (revision 3) @@ -0,0 +1,231 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_dac_ex.h + * @author MCD Application Team + * @brief Header file of DAC HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_DAC_EX_H +#define STM32G0xx_HAL_DAC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +#if defined(DAC1) + +/** @addtogroup DACEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL State structures definition + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DACEx_Exported_Constants DACEx Exported Constants + * @{ + */ + +/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude + * @{ + */ +#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup DACEx_Private_Macros DACEx Private Macros + * @{ + */ +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \ + ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \ + ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9)) + + +#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU) + +#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU) + +#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \ + ((MODE) == DAC_SAMPLEANDHOLD_ENABLE)) + +#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) + +#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU) + +#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \ + ((CONNECT) == DAC_CHIPCONNECT_ENABLE)) + +#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \ + ((TRIMMING) == DAC_TRIMMING_USER)) + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/* Extended features functions ***********************************************/ + +/** @addtogroup DACEx_Exported_Functions + * @{ + */ + +/** @addtogroup DACEx_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ + +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); + +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac); + +void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac); +void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac); +void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac); +void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac); + + +/** + * @} + */ + +/** @addtogroup DACEx_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ + +HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, + uint32_t NewTrimmingValue); +uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel); + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DACEx_Private_Functions + * @{ + */ + +/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */ +/* are called by HAL_DAC_Start_DMA */ +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*STM32G0xx_HAL_DAC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_def.h (revision 3) @@ -0,0 +1,214 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_DEF +#define STM32G0xx_HAL_DEF + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx.h" +#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macros -----------------------------------------------------------*/ + +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0U) + +/** @brief Reset the Handles State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handles "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handles "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) +/* Reserved for future use */ +#error " USE_RTOS should be 0 in the current HAL release " +#else +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #ifndef __weak + #define __weak __attribute__((weak)) + #endif + #ifndef __packed + #define __packed __attribute__((packed)) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +/* GNU Compiler */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif +#elif defined (__GNUC__) && !defined (__CC_ARM) /* GNU Compiler */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4U))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#else +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +/* ARM Compiler */ +#if defined (__CC_ARM) /* ARM Compiler V5 */ +#define __ALIGN_BEGIN __align(4U) +/* IAR Compiler */ +#elif defined (__ICCARM__) +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_DEF */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h (revision 3) @@ -0,0 +1,803 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_DMA_H +#define STM32G0xx_HAL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" +#include "stm32g0xx_ll_dma.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Types DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the request selected for the specified channel. + This parameter can be a value of @ref DMA_request */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ +} DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ +} HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ +} HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ + +} HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */ + + void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + +#if defined(DMA2) + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + +#endif + uint32_t ChannelIndex; /*!< DMA Channel Index */ + + DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ + + DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ + + uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ + + DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ + + DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ + + uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ +} DMA_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ +#define HAL_DMA_ERROR_BUSY 0x00000080U /*!< DMA Busy error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ +#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ + +/** + * @} + */ + +/** @defgroup DMA_request DMA request + * @{ + */ +#define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */ +#define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */ +#define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */ +#define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */ +#define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */ +#define DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1 /*!< DMAMUX ADC1 request */ +#if defined(AES) +#define DMA_REQUEST_AES_IN LL_DMAMUX_REQ_AES_IN /*!< DMAMUX AES_IN request */ +#define DMA_REQUEST_AES_OUT LL_DMAMUX_REQ_AES_OUT /*!< DMAMUX AES_OUT request */ +#endif +#if defined(DAC1) +#define DMA_REQUEST_DAC1_CH1 LL_DMAMUX_REQ_DAC1_CH1 /*!< DMAMUX DAC_CH1 request */ +#define DMA_REQUEST_DAC1_CH2 LL_DMAMUX_REQ_DAC1_CH2 /*!< DMAMUX DAC_CH2 request */ +#endif +#define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */ +#define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */ +#define DMA_REQUEST_I2C2_RX LL_DMAMUX_REQ_I2C2_RX /*!< DMAMUX I2C2 RX request */ +#define DMA_REQUEST_I2C2_TX LL_DMAMUX_REQ_I2C2_TX /*!< DMAMUX I2C2 TX request */ +#if defined(LPUART1) +#define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LPUART1 RX request */ +#define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LPUART1 TX request */ +#endif +#define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */ +#define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */ +#define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */ +#define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */ +#define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */ +#define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */ +#define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */ +#define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */ +#define DMA_REQUEST_TIM1_TRIG_COM LL_DMAMUX_REQ_TIM1_TRIG_COM /*!< DMAMUX TIM1 TRIG COM request */ +#define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */ +#if defined(TIM2) +#define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */ +#define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */ +#define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */ +#define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */ +#define DMA_REQUEST_TIM2_TRIG LL_DMAMUX_REQ_TIM2_TRIG /*!< DMAMUX TIM2 TRIG request */ +#define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */ +#endif +#define DMA_REQUEST_TIM3_CH1 LL_DMAMUX_REQ_TIM3_CH1 /*!< DMAMUX TIM3 CH1 request */ +#define DMA_REQUEST_TIM3_CH2 LL_DMAMUX_REQ_TIM3_CH2 /*!< DMAMUX TIM3 CH2 request */ +#define DMA_REQUEST_TIM3_CH3 LL_DMAMUX_REQ_TIM3_CH3 /*!< DMAMUX TIM3 CH3 request */ +#define DMA_REQUEST_TIM3_CH4 LL_DMAMUX_REQ_TIM3_CH4 /*!< DMAMUX TIM3 CH4 request */ +#define DMA_REQUEST_TIM3_TRIG LL_DMAMUX_REQ_TIM3_TRIG /*!< DMAMUX TIM3 TRIG request */ +#define DMA_REQUEST_TIM3_UP LL_DMAMUX_REQ_TIM3_UP /*!< DMAMUX TIM3 UP request */ +#if defined(TIM6) +#define DMA_REQUEST_TIM6_UP LL_DMAMUX_REQ_TIM6_UP /*!< DMAMUX TIM6 UP request */ +#endif +#if defined(TIM7) +#define DMA_REQUEST_TIM7_UP LL_DMAMUX_REQ_TIM7_UP /*!< DMAMUX TIM7 UP request */ +#endif +#if defined(TIM15) +#define DMA_REQUEST_TIM15_CH1 LL_DMAMUX_REQ_TIM15_CH1 /*!< DMAMUX TIM15 CH1 request */ +#define DMA_REQUEST_TIM15_CH2 LL_DMAMUX_REQ_TIM15_CH2 /*!< DMAMUX TIM15 CH2 request */ +#define DMA_REQUEST_TIM15_TRIG_COM LL_DMAMUX_REQ_TIM15_TRIG_COM /*!< DMAMUX TIM15 TRIG COM request */ +#define DMA_REQUEST_TIM15_UP LL_DMAMUX_REQ_TIM15_UP /*!< DMAMUX TIM15 UP request */ +#endif +#define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */ +#define DMA_REQUEST_TIM16_COM LL_DMAMUX_REQ_TIM16_COM /*!< DMAMUX TIM16 COM request */ +#define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */ +#define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */ +#define DMA_REQUEST_TIM17_COM LL_DMAMUX_REQ_TIM17_COM /*!< DMAMUX TIM17 COM request */ +#define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */ +#define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */ +#define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */ +#define DMA_REQUEST_USART2_RX LL_DMAMUX_REQ_USART2_RX /*!< DMAMUX USART2 RX request */ +#define DMA_REQUEST_USART2_TX LL_DMAMUX_REQ_USART2_TX /*!< DMAMUX USART2 TX request */ +#if defined(USART3) +#define DMA_REQUEST_USART3_RX LL_DMAMUX_REQ_USART3_RX /*!< DMAMUX USART3 RX request */ +#define DMA_REQUEST_USART3_TX LL_DMAMUX_REQ_USART3_TX /*!< DMAMUX USART3 TX request */ +#endif +#if defined(USART4) +#define DMA_REQUEST_USART4_RX LL_DMAMUX_REQ_USART4_RX /*!< DMAMUX USART4 RX request */ +#define DMA_REQUEST_USART4_TX LL_DMAMUX_REQ_USART4_TX /*!< DMAMUX USART4 TX request */ +#endif +#if defined(UCPD1) +#define DMA_REQUEST_UCPD1_RX LL_DMAMUX_REQ_UCPD1_RX /*!< DMAMUX UCPD1 RX request */ +#define DMA_REQUEST_UCPD1_TX LL_DMAMUX_REQ_UCPD1_TX /*!< DMAMUX UCPD1 TX request */ +#endif +#if defined(UCPD2) +#define DMA_REQUEST_UCPD2_RX LL_DMAMUX_REQ_UCPD2_RX /*!< DMAMUX UCPD2 RX request */ +#define DMA_REQUEST_UCPD2_TX LL_DMAMUX_REQ_UCPD2_TX /*!< DMAMUX UCPD2 TX request */ +#endif + +#if defined(I2C3) +#define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */ +#define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */ +#endif + +#if defined(LPUART2) +#define DMA_REQUEST_LPUART2_RX LL_DMAMUX_REQ_LPUART2_RX /*!< DMAMUX LPUART2 RX request */ +#define DMA_REQUEST_LPUART2_TX LL_DMAMUX_REQ_LPUART2_TX /*!< DMAMUX LPUART2 TX request */ +#endif + +#if defined(SPI3) +#define DMA_REQUEST_SPI3_RX LL_DMAMUX_REQ_SPI3_RX /*!< DMAMUX SPI3 RX request */ +#define DMA_REQUEST_SPI3_TX LL_DMAMUX_REQ_SPI3_TX /*!< DMAMUX SPI3 TX request */ +#endif + +#if defined(TIM4) +#define DMA_REQUEST_TIM4_CH1 LL_DMAMUX_REQ_TIM4_CH1 /*!< DMAMUX TIM4 CH1 request */ +#define DMA_REQUEST_TIM4_CH2 LL_DMAMUX_REQ_TIM4_CH2 /*!< DMAMUX TIM4 CH2 request */ +#define DMA_REQUEST_TIM4_CH3 LL_DMAMUX_REQ_TIM4_CH3 /*!< DMAMUX TIM4 CH3 request */ +#define DMA_REQUEST_TIM4_CH4 LL_DMAMUX_REQ_TIM4_CH4 /*!< DMAMUX TIM4 CH4 request */ +#define DMA_REQUEST_TIM4_TRIG LL_DMAMUX_REQ_TIM4_TRIG /*!< DMAMUX TIM4 TRIG request */ +#define DMA_REQUEST_TIM4_UP LL_DMAMUX_REQ_TIM4_UP /*!< DMAMUX TIM4 UP request */ +#endif + +#if defined(USART5) +#define DMA_REQUEST_USART5_RX LL_DMAMUX_REQ_USART5_RX /*!< DMAMUX USART5 RX request */ +#define DMA_REQUEST_USART5_TX LL_DMAMUX_REQ_USART5_TX /*!< DMAMUX USART5 TX request */ +#endif + +#if defined(USART6) +#define DMA_REQUEST_USART6_RX LL_DMAMUX_REQ_USART6_RX /*!< DMAMUX USART6 RX request */ +#define DMA_REQUEST_USART6_TX LL_DMAMUX_REQ_USART6_TX /*!< DMAMUX USART6 TX request */ +#endif + + +#define DMA_MAX_REQUEST LL_DMAMUX_MAX_REQ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */ + +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */ +#define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */ +#define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */ +#define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */ +#define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @{ + */ +#define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */ +#define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @{ + */ +#define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */ +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @{ + */ +#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer Complete interrupt */ +#define DMA_IT_HT DMA_CCR_HTIE /*!< Half Transfer Complete interrupt */ +#define DMA_IT_TE DMA_CCR_TEIE /*!< Transfer Error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @{ + */ + +#define DMA_FLAG_GI1 DMA_ISR_GIF1 /*!< Global Interrupt flag for Channel 1 */ +#define DMA_FLAG_TC1 DMA_ISR_TCIF1 /*!< Transfer Complete flag for Channel 1 */ +#define DMA_FLAG_HT1 DMA_ISR_HTIF1 /*!< Half Transfer flag for Channel 1 */ +#define DMA_FLAG_TE1 DMA_ISR_TEIF1 /*!< Transfer Error flag for Channel 1 */ +#define DMA_FLAG_GI2 DMA_ISR_GIF2 /*!< Global Interrupt flag for Channel 2 */ +#define DMA_FLAG_TC2 DMA_ISR_TCIF2 /*!< Transfer Complete flag for Channel 2 */ +#define DMA_FLAG_HT2 DMA_ISR_HTIF2 /*!< Half Transfer flag for Channel 2 */ +#define DMA_FLAG_TE2 DMA_ISR_TEIF2 /*!< Transfer Error flag for Channel 2 */ +#define DMA_FLAG_GI3 DMA_ISR_GIF3 /*!< Global Interrupt flag for Channel 3 */ +#define DMA_FLAG_TC3 DMA_ISR_TCIF3 /*!< Transfer Complete flag for Channel 3 */ +#define DMA_FLAG_HT3 DMA_ISR_HTIF3 /*!< Half Transfer flag for Channel 3 */ +#define DMA_FLAG_TE3 DMA_ISR_TEIF3 /*!< Transfer Error flag for Channel 3 */ +#define DMA_FLAG_GI4 DMA_ISR_GIF4 /*!< Global Interrupt flag for Channel 4 */ +#define DMA_FLAG_TC4 DMA_ISR_TCIF4 /*!< Transfer Complete flag for Channel 4 */ +#define DMA_FLAG_HT4 DMA_ISR_HTIF4 /*!< Half Transfer flag for Channel 4 */ +#define DMA_FLAG_TE4 DMA_ISR_TEIF4 /*!< Transfer Error flag for Channel 4 */ +#define DMA_FLAG_GI5 DMA_ISR_GIF5 /*!< Global Interrupt flag for Channel 5 */ +#define DMA_FLAG_TC5 DMA_ISR_TCIF5 /*!< Transfer Complete flag for Channel 5 */ +#define DMA_FLAG_HT5 DMA_ISR_HTIF5 /*!< Half Transfer flag for Channel 5 */ +#define DMA_FLAG_TE5 DMA_ISR_TEIF5 /*!< Transfer Error for Channel 5 */ +#if defined(DMA1_Channel6) +#define DMA_FLAG_GI6 DMA_ISR_GIF6 /*!< Global Interrupt flag for Channel 6 */ +#define DMA_FLAG_TC6 DMA_ISR_TCIF6 /*!< Transfer Complete flag for Channel 6 */ +#define DMA_FLAG_HT6 DMA_ISR_HTIF6 /*!< Half Transfer flag for Channel 6 */ +#define DMA_FLAG_TE6 DMA_ISR_TEIF6 /*!< Transfer Error flag for Channel 6 */ +#endif +#if defined(DMA1_Channel7) +#define DMA_FLAG_GI7 DMA_ISR_GIF7 /*!< Global Interrupt flag for Channel 7 */ +#define DMA_FLAG_TC7 DMA_ISR_TCIF7 /*!< Transfer Complete flag for Channel 7 */ +#define DMA_FLAG_HT7 DMA_ISR_HTIF7 /*!< Half Transfer flag for Channel 7 */ +#define DMA_FLAG_TE7 DMA_ISR_TEIF7 /*!< Transfer Error flag for Channel 7 */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) + +/** + * @brief Return the current DMA Channel transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#if defined(DMA2) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ + DMA_FLAG_TC7) +#else +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ + DMA_FLAG_TC5) +#endif +#endif /* DMA2 */ + +/** + * @brief Return the current DMA Channel half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#if defined(DMA2) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ + DMA_FLAG_HT7) +#else +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ + DMA_FLAG_HT5) +#endif +#endif /* DMA2 */ + +/** + * @brief Return the current DMA Channel transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#if defined(DMA2) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ + DMA_FLAG_TE7) +#else +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ + DMA_FLAG_TE5) +#endif +#endif /* DMA2 */ + +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#if defined(DMA2) +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ + DMA_FLAG_GI7) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\ + DMA_FLAG_GI7) +#else +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\ + DMA_FLAG_GI5) +#endif +#endif /* DMA2 */ + +/** + * @brief Get the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GIx: Global interrupt flag + * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. + * @retval The state of FLAG (SET or RESET). + */ +#if defined(DMA2) +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ + (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) +#else /* DMA1 */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) +#endif /* DMA2 */ + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCx: Transfer complete flag + * @arg DMA_FLAG_HTx: Half transfer complete flag + * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GIx: Global interrupt flag + * Where x can be 1 to max Channel supported by the product to select the DMA Channel flag. + * @retval None + */ +#if defined(DMA2) +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ + (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) +#else /* DMA1 */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR |= (__FLAG__)) +#endif /* DMA2 */ + +/** + * @brief Enable the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified DMA Channel interrupt is enabled or disabled. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer complete interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Returns the number of remaining data units in the current DMA Channel transfer. + * @param __HANDLE__ DMA handle + * @retval The number of remaining data units in the current DMA Channel transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) + +/** + * @} + */ + +/* Include DMA HAL Extension module */ +#include "stm32g0xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @{ + */ + +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_MAX_REQUEST) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma_ex.h (revision 3) @@ -0,0 +1,280 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_DMA_EX_H +#define STM32G0xx_HAL_DMA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" +#include "stm32g0xx_ll_dmamux.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @{ + */ + +/** + * @brief HAL DMAMUX Synchronization configuration structure definition + */ +typedef struct +{ + uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ + + uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. + This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ + + FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled + This parameter can take the value ENABLE or DISABLE */ + + FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. + This parameter can take the value ENABLE or DISABLE */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + + +} HAL_DMA_MuxSyncConfigTypeDef; + + +/** + * @brief HAL DMAMUX request generator parameters structure definition + */ +typedef struct +{ + uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator + This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ + + uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. + This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ + + uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event + This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ + +} HAL_DMA_MuxRequestGeneratorConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @{ + */ + +/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection + * @{ + */ +#define HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0 /*!< Synchronization signal from EXTI Line0 */ +#define HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1 /*!< Synchronization signal from EXTI Line1 */ +#define HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2 /*!< Synchronization signal from EXTI Line2 */ +#define HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3 /*!< Synchronization signal from EXTI Line3 */ +#define HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4 /*!< Synchronization signal from EXTI Line4 */ +#define HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5 /*!< Synchronization signal from EXTI Line5 */ +#define HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6 /*!< Synchronization signal from EXTI Line6 */ +#define HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7 /*!< Synchronization signal from EXTI Line7 */ +#define HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8 /*!< Synchronization signal from EXTI Line8 */ +#define HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9 /*!< Synchronization signal from EXTI Line9 */ +#define HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10 /*!< Synchronization signal from EXTI Line10 */ +#define HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11 /*!< Synchronization signal from EXTI Line11 */ +#define HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12 /*!< Synchronization signal from EXTI Line12 */ +#define HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13 /*!< Synchronization signal from EXTI Line1 3 */ +#define HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14 /*!< Synchronization signal from EXTI Line1 4 */ +#define HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15 /*!< Synchronization signal from EXTI Line1 5 */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0 /*!< Synchronization signal from DMAMUX channel0 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1 /*!< Synchronization signal from DMAMUX channel1 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT LL_DMAMUX_SYNC_DMAMUX_CH2 /*!< Synchronization signal from DMAMUX channel2 Event */ +#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT LL_DMAMUX_SYNC_DMAMUX_CH3 /*!< Synchronization signal from DMAMUX channel3 Event */ +#if defined(LPTIM1) +#define HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT /*!< Synchronization signal from LPTIM1 Output */ +#endif +#if defined(LPTIM2) +#define HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT /*!< Synchronization signal from LPTIM2 Output */ +#endif +#define HAL_DMAMUX1_SYNC_TIM14_OC LL_DMAMUX_SYNC_TIM14_OC /*!< Synchronization signal from TIM14 OC */ + +#define HAL_DMAMUX1_MAX_SYNC HAL_DMAMUX1_SYNC_TIM14_OC +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection + * @{ + */ +#define HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT /*!< block synchronization events */ +#define HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING /*!< synchronize with rising edge events */ +#define HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING /*!< synchronize with falling edge events */ +#define HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING /*!< synchronize with rising and falling edge events */ + +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection + * @{ + */ +#define HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0 /*!< Request signal generation from EXTI Line0 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1 /*!< Request signal generation from EXTI Line1 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2 /*!< Request signal generation from EXTI Line2 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3 /*!< Request signal generation from EXTI Line3 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4 /*!< Request signal generation from EXTI Line4 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5 /*!< Request signal generation from EXTI Line5 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6 /*!< Request signal generation from EXTI Line6 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7 /*!< Request signal generation from EXTI Line7 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8 /*!< Request signal generation from EXTI Line8 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9 /*!< Request signal generation from EXTI Line9 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10 /*!< Request signal generation from EXTI Line10 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11 /*!< Request signal generation from EXTI Line11 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12 /*!< Request signal generation from EXTI Line12 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13 /*!< Request signal generation from EXTI Line13 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14 /*!< Request signal generation from EXTI Line14 */ +#define HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15 /*!< Request signal generation from EXTI Line15 */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0 /*!< Request signal generation from DMAMUX channel0 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1 /*!< Request signal generation from DMAMUX channel1 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH2 /*!< Request signal generation from DMAMUX channel2 Event */ +#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH3 /*!< Request signal generation from DMAMUX channel3 Event */ +#if defined(LPTIM1) +#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT /*!< Request signal generation from LPTIM1 Output */ +#endif +#if defined(LPTIM2) +#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT /*!< Request signal generation from LPTIM2 Output */ +#endif +#define HAL_DMAMUX1_REQ_GEN_TIM14_OC LL_DMAMUX_REQ_GEN_TIM14_OC /*!< Request signal generation from TIM14 OC */ + +#define HAL_DMAMUX1_MAX_REQ_GEN HAL_DMAMUX1_REQ_GEN_TIM14_OC +/** + * @} + */ + +/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection + * @{ + */ +#define HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT /*!< block request generator events */ +#define HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING /*!< generate request on rising edge events */ +#define HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING /*!< generate request on falling edge events */ +#define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING /*!< generate request on rising and falling edge events */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup DMAEx_Exported_Functions_Group1 + * @{ + */ + +/* ------------------------- REQUEST -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, + HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma); +/* -------------------------------------------------------------------------- */ + +/* ------------------------- SYNCHRO -----------------------------------------*/ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); +/* -------------------------------------------------------------------------- */ + +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMAEx Private Macros + * @brief DMAEx private macros + * @{ + */ + +#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_SYNC_EXTI0) || \ + (((SIGNAL_ID) >= HAL_DMAMUX1_SYNC_EXTI1) && \ + ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_SYNC))) + +#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) + +#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) + +#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ + ((EVENT) == ENABLE)) + +#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_REQ_GEN_EXTI0) || \ + (((SIGNAL_ID) >= HAL_DMAMUX1_REQ_GEN_EXTI1) && \ + ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_REQ_GEN))) + +#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) + +#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)|| \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ + ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_DMA_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_exti.h (revision 3) @@ -0,0 +1,389 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_EXTI_H +#define STM32G0xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, + HAL_EXTI_RISING_CB_ID = 0x01U, + HAL_EXTI_FALLING_CB_ID = 0x02U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* RisingCallback)(void); /*!< Exti rising callback */ + void (* FallingCallback)(void); /*!< Exti falling callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u) +#if defined(COMP1) +#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u) +#else +#define EXTI_LINE_17 (EXTI_RESERVED | EXTI_REG1 | 0x11u) +#endif +#if defined(COMP2) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12u) +#else +#define EXTI_LINE_18 (EXTI_RESERVED | EXTI_REG1 | 0x12u) +#endif +#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13u) +#if defined(COMP3) +#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u) +#else +#define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u) +#endif +#define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15u) +#if defined(RCC_CCIPR_I2C2SEL) +#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u) +#else +#define EXTI_LINE_22 (EXTI_RESERVED | EXTI_REG1 | 0x16u) +#endif +#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) +#if defined(RCC_CCIPR_USART3SEL) +#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) +#else +#define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u) +#endif +#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) +#if defined(RCC_CCIPR_USART2SEL) +#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au) +#else +#define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au) +#endif +#if defined(CEC) +#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu) +#else +#define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu) +#endif +#if defined(LPUART1) +#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) +#else +#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu) +#endif +#if defined(LPTIM1) +#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du) +#else +#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Du) +#endif +#if defined(LPTIM2) +#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu) +#else +#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu) +#endif +#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1Fu) +#if defined(UCPD1) +#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00u) +#else +#define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u) +#endif +#if defined(UCPD2) +#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01u) +#else +#define EXTI_LINE_33 (EXTI_RESERVED | EXTI_REG2 | 0x01u) +#endif +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define EXTI_LINE_34 (EXTI_CONFIG | EXTI_REG2 | 0x02u) +#else +#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) +#endif +#if defined(LPUART2) +#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u) +#else +#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) +#endif +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u) +#endif +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#if defined(GPIOE) +#define EXTI_GPIOE 0x00000004u +#endif +#define EXTI_GPIOF 0x00000005u +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16u +#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define EXTI_LINE_NB 37uL +#elif defined(STM32G0B0xx) +#define EXTI_LINE_NB 37uL +#elif defined(STM32G081xx) || defined(STM32G071xx) +#define EXTI_LINE_NB 34uL +#elif defined(STM32G070xx) +#define EXTI_LINE_NB 34uL +#elif defined(STM32G041xx) || defined(STM32G031xx) +#define EXTI_LINE_NB 32uL +#else +#define EXTI_LINE_NB 32uL +#endif + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) + +#define IS_EXTI_MODE(__MODE__) ((((__MODE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__MODE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING)) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) + +#if defined(GPIOE) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOF)) +#endif + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash.h (revision 3) @@ -0,0 +1,1025 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_FLASH_H +#define STM32G0xx_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or page erase. + This parameter can be a value of @ref FLASH_Type_Erase */ + uint32_t Banks; /*!< Select bank to erase. + This parameter must be a value of @ref FLASH_Banks + (FLASH_BANK_BOTH should be used only for mass erase) */ + uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled + This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */ + uint32_t NbPages; /*!< Number of pages to be erased. + This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/ +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a combination of the values of @ref FLASH_OB_Type */ + uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). + Only one WRP area could be programmed at the same time. + This parameter can be value of @ref FLASH_OB_WRP_Area */ + uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). + This parameter must be a value between 0 and [FLASH_PAGE_NB - 1]*/ + uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). + This parameter must be a value between WRPStartOffset and [FLASH_PAGE_NB - 1] */ + uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). + This parameter can be a value of @ref FLASH_OB_Read_Protection */ + uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_Type */ + uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). + This parameter can be a combination of + @ref FLASH_OB_USER_BOR_ENABLE(*), + @ref FLASH_OB_USER_BOR_LEVEL(*), + @ref FLASH_OB_USER_RESET_CONFIG(*), + @ref FLASH_OB_USER_nRST_STOP, + @ref FLASH_OB_USER_nRST_STANDBY, + @ref FLASH_OB_USER_nRST_SHUTDOWN(*), + @ref FLASH_OB_USER_IWDG_SW, + @ref FLASH_OB_USER_IWDG_STOP, + @ref FLASH_OB_USER_IWDG_STANDBY, + @ref FLASH_OB_USER_WWDG_SW, + @ref FLASH_OB_USER_SRAM_PARITY, + @ref FLASH_OB_USER_BANK_SWAP(*), + @ref FLASH_OB_USER_DUAL_BANK(*), + @ref FLASH_OB_USER_nBOOT_SEL, + @ref FLASH_OB_USER_nBOOT1, + @ref FLASH_OB_USER_nBOOT0, + @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*) + @note (*) availability depends on devices */ +#if defined(FLASH_PCROP_SUPPORT) + uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP). + This parameter must be a combination of @ref FLASH_OB_PCROP_ZONE + and @ref FLASH_OB_PCROP_RDP. Note that once set, Pcrop erase on RDP level 1 regression + (PCROP_RDP bit) can not be reset. It will be reset by mass erase */ + uint32_t PCROP1AStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ + uint32_t PCROP1AEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ + uint32_t PCROP1BStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ + uint32_t PCROP1BEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ +#if defined(FLASH_DBANK_SUPPORT) + uint32_t PCROP2AStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ + uint32_t PCROP2AEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ + uint32_t PCROP2BStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). It represents first address of start block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ + uint32_t PCROP2BEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). It represents first address of end block + to protect. Make sure this parameter is multiple of PCROP granularity: 512 Bytes.*/ +#endif +#endif +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) + uint32_t BootEntryPoint; /*!< Allow to force a unique boot entry point to Flash or system Flash */ + uint32_t SecSize; /*!< This parameter defines securable memory area width in number of pages starting from Flash base address. + This parameter must be a value between [0] and [FLASH_PAGE_NB], + [0] meaning no secure area defined, [1] meaning first page only protected, etc... */ +#if defined(FLASH_DBANK_SUPPORT) + uint32_t SecSize2; /*!< This parameter defines securable memory area width in number of pages starting from 2nd Bank start address. + This parameter must be a value between [0] and [FLASH_PAGE_NB], + [0] meaning no secure area defined, [1] meaning first page only protected, etc... */ +#endif +#endif +} FLASH_OBProgramInitTypeDef; + +/** +* @brief FLASH handle Structure definition +*/ +typedef struct +{ + HAL_LockTypeDef Lock; /* FLASH locking object */ + uint32_t ErrorCode; /* FLASH error code */ + uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ + uint32_t Address; /* Internal variable to save address selected for program in IT context */ + uint32_t Banks; /* Internal variable to save current bank selected during erase in IT context */ + uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */ + uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define FLASH_KEY1 0x45670123U /*!< Flash key1 */ +#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1 + to unlock the FLASH registers access */ +#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */ +#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1 + to allow option bytes operations */ +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 0x00000000UL /*!< FLASH Zero wait state */ +#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */ +#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ +/** + * @} + */ + +/** @defgroup FLASH_Flags FLASH Flags Definition + * @{ + */ +#define FLASH_FLAG_EOP ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_EOP_Pos) /*!< FLASH End of operation flag */ +#define FLASH_FLAG_OPERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_OPERR_Pos) /*!< FLASH Operation error flag */ +#define FLASH_FLAG_PROGERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PROGERR_Pos) /*!< FLASH Programming error flag */ +#define FLASH_FLAG_WRPERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_WRPERR_Pos) /*!< FLASH Write protection error flag */ +#define FLASH_FLAG_PGAERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PGAERR_Pos) /*!< FLASH Programming alignment error flag */ +#define FLASH_FLAG_SIZERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_SIZERR_Pos) /*!< FLASH Size error flag */ +#define FLASH_FLAG_PGSERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PGSERR_Pos) /*!< FLASH Programming sequence error flag */ +#define FLASH_FLAG_MISERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_MISERR_Pos) /*!< FLASH Fast programming data miss error flag */ +#define FLASH_FLAG_FASTERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_FASTERR_Pos) /*!< FLASH Fast programming error flag */ +#if defined(FLASH_PCROP_SUPPORT) +#define FLASH_FLAG_RDERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_RDERR_Pos) /*!< FLASH PCROP read error flag */ +#endif /* FLASH_PCROP_SUPPORT */ +#define FLASH_FLAG_OPTVERR ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_OPTVERR_Pos) /*!< FLASH Option validity error flag */ +#define FLASH_FLAG_BSY1 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY1_Pos) /*!< FLASH Operation Busy flag for Bank 1 */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_FLAG_BSY2 ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_BSY2_Pos) /*!< FLASH Operation Busy flag for Bank 2 */ +#endif +#define FLASH_FLAG_BSY FLASH_FLAG_BSY1 /*!< FLASH Operation Busy flag - legacy name for single bank */ +#define FLASH_FLAG_CFGBSY ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_CFGBSY_Pos) /*!< FLASH Configuration Busy flag */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_FLAG_PESD ((FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS) | FLASH_SR_PESD_Pos) /*!< FLASH Programming/erase operation suspended */ +#endif +#define FLASH_FLAG_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCC_Pos) /*!< FLASH ECC correction on bank 1 */ +#define FLASH_FLAG_ECCD1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCD_Pos) /*!< FLASH ECC detection on bank 1 */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_FLAG_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCC_Pos) /*!< FLASH ECC correction on bank 2 */ +#define FLASH_FLAG_ECCD2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCD_Pos) /*!< FLASH ECC detection on bank 2 */ +#endif +#define FLASH_FLAG_ECCC FLASH_FLAG_ECCC1 /*!< FLASH ECC correction - legacy name for single bank */ +#define FLASH_FLAG_ECCD FLASH_FLAG_ECCD1 /*!< FLASH ECC detection - legacy name for single bank */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_EOPIE_Pos) /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_OPERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_ERRIE_Pos) /*!< Error Interrupt source */ +#if defined(FLASH_PCROP_SUPPORT) +#define FLASH_IT_RDERR ((FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS) | FLASH_CR_RDERRIE_Pos) /*!< PCROP Read Error Interrupt source*/ +#endif +#define FLASH_IT_ECCC1 ((FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS) | FLASH_ECCR_ECCCIE_Pos) /*!< ECC Correction on Bank 1 Interrupt source */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_IT_ECCC2 ((FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS) | FLASH_ECC2R_ECCCIE_Pos) /*!< ECC Correction on Bank 2 Interrupt source */ +#endif +#define FLASH_IT_ECCC FLASH_IT_ECCC1 /*!< ECC Correction - legacy name for single bank */ +/** + * @} + */ + +/** @defgroup FLASH_Error FLASH Error + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U +#define HAL_FLASH_ERROR_OP FLASH_SR_EOP +#define HAL_FLASH_ERROR_PROG FLASH_SR_PROGERR +#define HAL_FLASH_ERROR_WRP FLASH_SR_WRPERR +#define HAL_FLASH_ERROR_PGA FLASH_SR_PGAERR +#define HAL_FLASH_ERROR_SIZ FLASH_SR_SIZERR +#define HAL_FLASH_ERROR_PGS FLASH_SR_PGSERR +#define HAL_FLASH_ERROR_MIS FLASH_SR_MISERR +#define HAL_FLASH_ERROR_FAST FLASH_SR_FASTERR +#if defined(FLASH_PCROP_SUPPORT) +#define HAL_FLASH_ERROR_RD FLASH_SR_RDERR +#endif +#define HAL_FLASH_ERROR_OPTV FLASH_SR_OPTVERR +#define HAL_FLASH_ERROR_ECCD FLASH_ECCR_ECCD +/** + * @} + */ + +/** @defgroup FLASH_Type_Erase FLASH Erase Type + * @{ + */ +#define FLASH_TYPEERASE_PAGES FLASH_CR_PER /*!< Pages erase only */ +#define FLASH_TYPEERASE_MASS FLASH_CR_MER1 /*!< Flash mass erase activation */ +/** + * @} + */ + +/** @defgroup FLASH_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 FLASH_CR_MER1 /*!< Bank 1 */ +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_BANK_2 FLASH_CR_MER2 /*!< Bank 2 */ +#endif +/** + * @} + */ + + +/** @defgroup FLASH_Type_Program FLASH Program Type + * @{ + */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG /*!< Program a double-word (64-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG /*!< Fast program a 32 row double-word (64-bit) at a specified address */ +/** + * @} + */ + +/** @defgroup FLASH_OB_Type FLASH Option Bytes Type + * @{ + */ +#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER 0x00000004U /*!< USER option byte configuration */ +#if defined(FLASH_PCROP_SUPPORT) +#define OPTIONBYTE_PCROP 0x00000008U /*!< PCROP option byte configuration */ +#endif +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +#define OPTIONBYTE_SEC 0x00000010U /*!< SEC option byte configuration */ +#endif + +#if defined(FLASH_PCROP_SUPPORT) && defined(FLASH_SECURABLE_MEMORY_SUPPORT) +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ + OPTIONBYTE_PCROP | OPTIONBYTE_SEC) /*!< All option byte configuration */ +#else +#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER) /*!< All option byte configuration */ +#endif +/** + * @} + */ + +/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area + * @{ + */ +#define OB_WRPAREA_ZONE_A 0x00000001U /*!< Flash Zone A */ +#define OB_WRPAREA_ZONE_B 0x00000002U /*!< Flash Zone B */ +#if defined(FLASH_DBANK_SUPPORT) +#define OB_WRPAREA_ZONE2_A 0x00000004U /*!< Flash Bank 2 Zone A */ +#define OB_WRPAREA_ZONE2_B 0x00000008U /*!< Flash Bank 2 Zone B */ +#endif +/** + * @} + */ + +/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 0x000000AAU +#define OB_RDP_LEVEL_1 0x000000BBU +#define OB_RDP_LEVEL_2 0x000000CCU /*!< Warning: When enabling read protection level 2 + it is no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type + * @{ + */ +#if defined(PWR_BOR_SUPPORT) +#define OB_USER_BOR_EN FLASH_OPTR_BOR_EN /*!< BOR reset enable */ +#define OB_USER_BOR_LEV (FLASH_OPTR_BORF_LEV | FLASH_OPTR_BORR_LEV) /*!< BOR reset Level */ +#endif +#define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */ +#define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */ +#if defined(PWR_SHDW_SUPPORT) +#define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */ +#endif +#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */ +#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */ +#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */ +#define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */ +#if defined(FLASH_DBANK_SUPPORT) +#define OB_USER_BANK_SWAP FLASH_OPTR_nSWAP_BANK /*!< Swap bank memory addresses */ +#define OB_USER_DUAL_BANK FLASH_OPTR_DUAL_BANK /*!< Select single or dual bank (depending of device memory size) */ +#endif +#define OB_USER_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK /*!< Sram parity check control */ +#define OB_USER_nBOOT_SEL FLASH_OPTR_nBOOT_SEL /*!< Boot Selection */ +#define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1 /*!< nBoot1 configuration */ +#define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBoot0 configuration */ +#if defined(GPIO_NRST_CONFIG_SUPPORT) +#define OB_USER_NRST_MODE FLASH_OPTR_NRST_MODE /*!< Reset pin configuration */ +#endif +#if defined(FLASH_OPTR_IRHEN) +#define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /*!< Internal reset holder enable */ +#endif + +#if defined(FLASH_DBANK_SUPPORT) +#if defined(PWR_BOR_SUPPORT) && defined(PWR_SHDW_SUPPORT) && defined(GPIO_NRST_CONFIG_SUPPORT) +#define OB_USER_ALL (OB_USER_BOR_EN | OB_USER_BOR_LEV | OB_USER_nRST_STOP | \ + OB_USER_nRST_STDBY | OB_USER_nRST_SHDW | OB_USER_IWDG_SW | \ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ + OB_USER_BANK_SWAP | OB_USER_DUAL_BANK | \ + OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ + OB_USER_nBOOT0 | OB_USER_NRST_MODE | OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */ +#else +#define OB_USER_ALL ( OB_USER_nRST_STOP | \ + OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ + OB_USER_BANK_SWAP | OB_USER_DUAL_BANK | \ + OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ + OB_USER_nBOOT0) /*!< all option bits */ +#endif +#else +#if defined(PWR_BOR_SUPPORT) && defined(PWR_SHDW_SUPPORT) && defined(GPIO_NRST_CONFIG_SUPPORT) +#define OB_USER_ALL (OB_USER_BOR_EN | OB_USER_BOR_LEV | OB_USER_nRST_STOP | \ + OB_USER_nRST_STDBY | OB_USER_nRST_SHDW | OB_USER_IWDG_SW | \ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ + OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ + OB_USER_nBOOT0 | OB_USER_NRST_MODE | OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */ +#else +#define OB_USER_ALL ( OB_USER_nRST_STOP | \ + OB_USER_nRST_STDBY | OB_USER_IWDG_SW | \ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | \ + OB_USER_RAM_PARITY_CHECK | OB_USER_nBOOT_SEL | OB_USER_nBOOT1 | \ + OB_USER_nBOOT0) /*!< all option bits */ +#endif +#endif +/** + * @} + */ + +#if defined(PWR_BOR_SUPPORT) +/** @defgroup FLASH_OB_USER_BOR_ENABLE FLASH Option Bytes User BOR enable + * @{ + */ +#define OB_BOR_DISABLE 0x00000000U /*!< BOR Reset set to default */ +#define OB_BOR_ENABLE FLASH_OPTR_BOR_EN /*!< Use option byte to define BOR thresholds */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level + * @{ + */ +#define OB_BOR_LEVEL_FALLING_0 0x00000000U /*!< BOR falling level 1 with threshold around 2.0V */ +#define OB_BOR_LEVEL_FALLING_1 FLASH_OPTR_BORF_LEV_0 /*!< BOR falling level 2 with threshold around 2.2V */ +#define OB_BOR_LEVEL_FALLING_2 FLASH_OPTR_BORF_LEV_1 /*!< BOR falling level 3 with threshold around 2.5V */ +#define OB_BOR_LEVEL_FALLING_3 (FLASH_OPTR_BORF_LEV_0 | FLASH_OPTR_BORF_LEV_1) /*!< BOR falling level 4 with threshold around 2.8V */ +#define OB_BOR_LEVEL_RISING_0 0x00000000U /*!< BOR rising level 1 with threshold around 2.1V */ +#define OB_BOR_LEVEL_RISING_1 FLASH_OPTR_BORR_LEV_0 /*!< BOR rising level 2 with threshold around 2.3V */ +#define OB_BOR_LEVEL_RISING_2 FLASH_OPTR_BORR_LEV_1 /*!< BOR rising level 3 with threshold around 2.6V */ +#define OB_BOR_LEVEL_RISING_3 (FLASH_OPTR_BORR_LEV_0 | FLASH_OPTR_BORR_LEV_1) /*!< BOR rising level 4 with threshold around 2.9V */ +/** + * @} + */ +#endif + +/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop + * @{ + */ +#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ +#define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby + * @{ + */ +#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ +#define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */ +/** + * @} + */ + +#if defined(PWR_SHDW_SUPPORT) +/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown + * @{ + */ +#define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ +#define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */ +/** + * @} + */ +#endif + +/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type + * @{ + */ +#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ +#define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop + * @{ + */ +#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ +#define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby + * @{ + */ +#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ +#define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type + * @{ + */ +#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ +#define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */ +/** + * @} + */ + +#if defined(FLASH_DBANK_SUPPORT) +/** @defgroup FLASH_OB_USER_BANK_SWAP FLASH Option Bytes User bank swap Type + * @{ + */ +#define OB_USER_DUALBANK_SWAP_ENABLE 0x00000000U /*!< Enable bank swap */ +#define OB_USER_DUALBANK_SWAP_DISABLE FLASH_OPTR_nSWAP_BANK /*!< Disable bank swap */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_DUAL_BANK FLASH Option Bytes User dual bank enable Type + * @{ + */ +#define OB_USER_DUALBANK_DISABLE 0x00000000U /*!< Disable dual bank */ +#define OB_USER_DUALBANK_ENABLE FLASH_OPTR_DUAL_BANK /*!< Enable dual bank */ +/** + * @} + */ +#endif + +/** @defgroup FLASH_OB_USER_SRAM_PARITY FLASH Option Bytes User SRAM parity + * @{ + */ +#define OB_SRAM_PARITY_ENABLE 0x00000000U /*!< Sram parity enable */ +#define OB_SRAM_PARITY_DISABLE FLASH_OPTR_RAM_PARITY_CHECK /*!< Sram parity disable */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nBOOT_SEL FLASH Option Bytes User Boot0 Selection + * @{ + */ +#define OB_BOOT0_FROM_PIN 0x00000000U /*!< BOOT0 signal is defined by PA14/BOOT0 pin value */ +#define OB_BOOT0_FROM_OB FLASH_OPTR_nBOOT_SEL /*!< BOOT0 signal is defined by nBOOT0 option bit */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type + * @{ + */ +#define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM is selected as boot space (if nBOOT0=0 or BOOT0_pin=1) */ +#define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if nBOOT0=0 or BOOT0_pin=1) */ +/** + * @} + */ + +/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit + * @{ + */ +#define OB_nBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */ +#define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */ +/** + * @} + */ + +#if defined(GPIO_NRST_CONFIG_SUPPORT) +/** @defgroup FLASH_OB_USER_RESET_CONFIG FLASH Option Bytes User reset config bit + * @{ + */ +#define OB_RESET_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0 /*!< Reset pin is in Reset input mode only */ +#define OB_RESET_MODE_GPIO FLASH_OPTR_NRST_MODE_1 /*!< Reset pin is in GPIO mode mode only */ +#define OB_RESET_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE /*!< Reset pin is in reset input and output mode */ +/** + * @} + */ +#endif + +#if defined(FLASH_OPTR_IRHEN) +/** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit + * @{ + */ +#define OB_IRH_ENABLE 0x00000000U /*!< Internal Reset handler enable */ +#define OB_IRH_DISABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler disable */ +/** + * @} + */ +#endif + +#if defined(FLASH_PCROP_SUPPORT) +/** @defgroup FLASH_OB_PCROP_ZONE FLASH Option Bytes PCROP ZONE + * @{ + */ +#define OB_PCROP_ZONE_A 0x00000001U /*!< PCROP Zone A */ +#define OB_PCROP_ZONE_B 0x00000002U /*!< PCROP Zone B */ +#if defined(FLASH_DBANK_SUPPORT) +#define OB_PCROP_ZONE2_A 0x00000004U /*!< PCROP Bank 2 Zone A */ +#define OB_PCROP_ZONE2_B 0x00000008U /*!< PCROP Bank 2 Zone B */ +#endif +/** + * @} + */ + +/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type + * @{ + */ +#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level + is decreased from Level 1 to Level 0 */ +#define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP /*!< PCROP area is erased when the RDP level is + decreased from Level 1 to Level 0 (full mass erase). + Once this bit is set only, it will be reset by mass erase */ +/** + * @} + */ +#endif + +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +/** @defgroup FLASH_OB_SEC_BOOT_LOCK FLASH Option Bytes Secure boot lock + * @{ + */ +#define OB_BOOT_ENTRY_FORCED_NONE 0x00000000U /*!< Boot entry is free */ +#define OB_BOOT_ENTRY_FORCED_FLASH FLASH_SECR_BOOT_LOCK /*!< Boot entry is forced to Flash or System Flash */ +/** + * @} + */ +#endif + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @brief macros to control FLASH features + * @{ + */ + +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * This parameter can be one of the following values : + * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state + * @arg @ref FLASH_LATENCY_1 FLASH One wait state + * @arg @ref FLASH_LATENCY_2 FLASH Two wait states + * @retval None + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * Returned value can be one of the following values : + * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state + * @arg @ref FLASH_LATENCY_1 FLASH One wait state + * @arg @ref FLASH_LATENCY_2 FLASH Two wait states + */ +#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Enable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN) + +/** + * @brief Disable the FLASH instruction cache. + * @retval none + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN) + +/** + * @brief Reset the FLASH instruction Cache. + * @note This function must be used only when the Instruction Cache is disabled. + * @retval None + */ +#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \ + } while (0U) +/** + * @} + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupts Macros + * @brief macros to handle FLASH interrupts + * @{ + */ + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be one of the following values : + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt(*) + * @arg @ref FLASH_IT_ECCC1 ECC Correction Interrupt on bank 1 + * @arg @ref FLASH_IT_ECCC2 ECC Correction Interrupt on bank 2(*) + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt - legacy name for single bank + * @note (*) availability depends on devices + * @retval none + */ +#if defined(FLASH_DBANK_SUPPORT) +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECC2R, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + } while(0U) +#else +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { SET_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + } while(0U) +#endif + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be one of the following values : + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt(*) + * @arg @ref FLASH_IT_ECCC1 ECC Correction Interrupt on bank 1 + * @arg @ref FLASH_IT_ECCC2 ECC Correction Interrupt on bank 2(*) + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt - legacy name for single bank + * @note (*) availability depends on devices + * @retval none + */ +#if defined(FLASH_DBANK_SUPPORT) +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECC2R, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + } while(0U) +#else +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & (FLASH_FLAG_CR_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->CR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + else if(((__INTERRUPT__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { CLEAR_BIT(FLASH->ECCR, (1uL << ((__INTERRUPT__) & 0x1Fu))); } \ + } while(0U) +#endif + +/** + * @brief Check whether the specified FLASH flag is set or not. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values : + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag + * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag + * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag(*) + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag + * @arg @ref FLASH_FLAG_BSY1 FLASH bank 1 write/erase operations in progress flag + * @arg @ref FLASH_FLAG_BSY2 FLASH bank 2 write/erase operations in progress flag(*) + * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag - legacy name for single bank + * @arg @ref FLASH_FLAG_CFGBSY FLASH configuration is busy : program or erase setting are used. + * @arg @ref FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD1 FLASH two ECC errors have been detected on bank 1 + * @arg @ref FLASH_FLAG_ECCC2 FLASH one ECC error has been detected and corrected on bank 2(*) + * @arg @ref FLASH_FLAG_ECCD2 FLASH two ECC errors have been detected on bank 2(*) + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected - legacy name for single bank + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected - legacy name for single bank + * @note (*) availability depends on devices + * @retval The state of FLASH_FLAG (SET or RESET). + */ +#if defined(FLASH_DBANK_SUPPORT) +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ? \ + (READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \ + ((((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \ + (READ_BIT(FLASH->ECC2R, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u))) +#else +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) ? \ + (READ_BIT(FLASH->SR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u) : \ + (READ_BIT(FLASH->ECCR, (1uL << ((__FLAG__) & 0x1Fu))) != 0x00u)) +#endif + +/** + * @brief Clear the FLASH pending flags. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be one of the following values : + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag + * @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag + * @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag + * @arg @ref FLASH_FLAG_ECCC1 FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD1 FLASH two ECC errors have been detected on bank 1 + * @arg @ref FLASH_FLAG_ECCC2 FLASH one ECC error has been detected and corrected on bank 2(*) + * @arg @ref FLASH_FLAG_ECCD2 FLASH two ECC errors have been detected on bank 2(*) + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected - legacy name for single bank + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected - legacy name for single bank + * @note (*) availability depends on devices + * @retval None + */ +#if defined(FLASH_DBANK_SUPPORT) +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); } \ + else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR = (1uL << ((__FLAG__) & 0x1Fu)); } \ + else if(((__FLAG__) & (FLASH_FLAG_ECCR2_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECC2R = (1uL << ((__FLAG__) & 0x1Fu)); } \ + } while(0U) +#else +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_SR_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->SR = (1uL << ((__FLAG__) & 0x1Fu)); } \ + else if(((__FLAG__) & (FLASH_FLAG_ECCR1_ID << FLASH_FLAG_REG_POS)) != 0U) { FLASH->ECCR = (1uL << ((__FLAG__) & 0x1Fu)); } \ + } while(0U) +#endif +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32g0xx_hal_flash_ex.h" +/* Exported variables --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Variables FLASH Exported Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/* Program operation functions ***********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +uint32_t HAL_FLASH_GetError(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types --------------------------------------------------------*/ +/** @defgroup FLASH_Private_types FLASH Private Types + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE + +#if defined(FLASH_DBANK_SUPPORT) +#define OB_DUAL_BANK_BASE (FLASH_R_BASE + 0x20U) /*!< Not use cmsis FLASH alias to avoid iar warning about volatile reading sequence */ +#define FLASH_SALES_TYPE_Pos (24U) +#define FLASH_SALES_TYPE (0x3UL << FLASH_SALES_TYPE_Pos) /*!< 0x000001E0 */ +#define FLASH_SALES_TYPE_0 (0x1UL << FLASH_SALES_TYPE_Pos) /*!< 0x01000000 */ +#define FLASH_SALES_TYPE_1 (0x2UL << FLASH_SALES_TYPE_Pos) /*!< 0x02000000 */ +#define FLASH_SALES_VALUE ((*((uint32_t *)PACKAGE_BASE)) & (FLASH_SALES_TYPE)) +#define OB_DUAL_BANK_VALUE ((*((uint32_t *)OB_DUAL_BANK_BASE)) & (FLASH_OPTR_DUAL_BANK)) +#define FLASH_BANK_NB (((FLASH_SALES_VALUE == 0U) || ((FLASH_SALES_VALUE == FLASH_SALES_TYPE_0) && (OB_DUAL_BANK_VALUE == 0U)))?1U:2U) +#define FLASH_BANK_SIZE ((FLASH_BANK_NB==1U)?(FLASH_SIZE):(FLASH_SIZE >> 1U)) /*!< FLASH Bank Size. Divided by 2 if 2 Banks */ +#else /* FLASH_DBANK_SUPPORT */ +#define FLASH_BANK_SIZE (FLASH_SIZE) /*!< FLASH Bank Size */ +#endif /* FLASH_DBANK_SUPPORT */ + +#define FLASH_PAGE_SIZE 0x00000800U /*!< FLASH Page Size, 2 KBytes */ +#define FLASH_PAGE_NB (FLASH_BANK_SIZE/FLASH_PAGE_SIZE) /* Number of pages per bank */ +#define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */ +#define FLASH_TYPENONE 0x00000000U /*!< No programming Procedure On Going */ + +#if defined(FLASH_PCROP_SUPPORT) +#define FLASH_SR_ERRORS (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR | \ + FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | \ + FLASH_SR_MISERR | FLASH_SR_FASTERR | FLASH_SR_RDERR | \ + FLASH_SR_OPTVERR) /*!< All SR error flags */ +#else +#define FLASH_SR_ERRORS (FLASH_SR_OPERR | FLASH_SR_PROGERR | FLASH_SR_WRPERR | \ + FLASH_SR_PGAERR | FLASH_SR_SIZERR | FLASH_SR_PGSERR | \ + FLASH_SR_MISERR | FLASH_SR_FASTERR | \ + FLASH_SR_OPTVERR) /*!< All SR error flags */ +#endif + +#if defined(FLASH_DBANK_SUPPORT) +#define FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP | FLASH_SR_PESD) +#else +#define FLASH_SR_CLEAR (FLASH_SR_ERRORS | FLASH_SR_EOP) +#endif + +/* Internal defines for HAL macro usage */ +#define FLASH_FLAG_REG_POS 16u +#define FLASH_FLAG_SR_ID 1u +#define FLASH_FLAG_CR_ID 2u +#define FLASH_FLAG_ECCR1_ID 4u +#define FLASH_FLAG_ECCR2_ID 8u + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#define IS_FLASH_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) + +#define IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_BANK_SIZE - 1UL))) +#if defined(FLASH_DBANK_SUPPORT) +#define IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE + FLASH_BANK_SIZE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) +#endif + +#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 8UL))) + +#define IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= 0x1FFF7000U) && ((__ADDRESS__) <= (0x1FFF7400U - 8UL))) + +#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) ((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__ADDRESS__)) || (IS_FLASH_PROGRAM_OTP_ADDRESS(__ADDRESS__))) + +#define IS_FLASH_FAST_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= (FLASH_BASE)) && ((__ADDRESS__) <= (FLASH_BASE + FLASH_SIZE - 256UL))) + +#define IS_FLASH_PAGE(__PAGE__) ((__PAGE__) < FLASH_PAGE_NB) + +#if defined(FLASH_DBANK_SUPPORT) +#define IS_FLASH_BANK(__BANK__) \ + ((FLASH_BANK_NB == 2U) ? \ + (((__BANK__) == FLASH_BANK_1) || \ + ((__BANK__) == FLASH_BANK_2) || \ + ((__BANK__) == (FLASH_BANK_2 | FLASH_BANK_1))): \ + ((__BANK__) == FLASH_BANK_1)) +#else +#define IS_FLASH_BANK(__BANK__) ((__BANK__) == FLASH_BANK_1) +#endif + +#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \ + ((__VALUE__) == FLASH_TYPEERASE_MASS)) + +#define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ + ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) + +#define IS_OPTIONBYTE(__VALUE__) ((((__VALUE__) & OPTIONBYTE_ALL) != 0x00U) && \ + (((__VALUE__) & ~OPTIONBYTE_ALL) == 0x00U)) + +#if defined(FLASH_DBANK_SUPPORT) +#define IS_OB_WRPAREA(__VALUE__) \ + ((FLASH_BANK_NB == 2U) ? \ + (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B) || \ + ((__VALUE__) == OB_WRPAREA_ZONE2_A) || ((__VALUE__) == OB_WRPAREA_ZONE2_B)) : \ + (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B))) +#else +#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_ZONE_A) || ((__VALUE__) == OB_WRPAREA_ZONE_B)) +#endif + +#define IS_OB_RDP_LEVEL(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\ + ((__LEVEL__) == OB_RDP_LEVEL_1) ||\ + ((__LEVEL__) == OB_RDP_LEVEL_2)) + +#define IS_OB_USER_TYPE(__TYPE__) ((((__TYPE__) & OB_USER_ALL) != 0x00U) && \ + (((__TYPE__) & ~OB_USER_ALL) == 0x00U)) + +#define IS_OB_USER_CONFIG(__TYPE__,__CONFIG__) ((~(__TYPE__) & (__CONFIG__)) == 0x00U) + +#if defined(FLASH_PCROP_SUPPORT) +#if defined(FLASH_DBANK_SUPPORT) +#define IS_OB_PCROP_CONFIG(__CONFIG__) \ + ((FLASH_BANK_NB == 2U) ? \ + (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | \ + OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B | OB_PCROP_RDP_ERASE)) == 0x00U): \ + (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U)) +#else +#define IS_OB_PCROP_CONFIG(__CONFIG__) (((__CONFIG__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0x00U) +#endif +#endif + +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +#define IS_OB_SEC_BOOT_LOCK(__VALUE__) (((__VALUE__) == OB_BOOT_ENTRY_FORCED_NONE) || ((__VALUE__) == OB_BOOT_ENTRY_FORCED_FLASH)) + +#define IS_OB_SEC_SIZE(__VALUE__) ((__VALUE__) < (FLASH_PAGE_NB + 1U)) +#endif + +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1) || \ + ((__LATENCY__) == FLASH_LATENCY_2)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_FLASH_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h (revision 3) @@ -0,0 +1,119 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_FLASH_EX_H +#define STM32G0xx_HAL_FLASH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ +/** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check + * @{ + */ +#define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */ +#define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY /*!< 1st location in Flash is empty */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/* Extended Program operation functions *************************************/ +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +void HAL_FLASHEx_EnableDebugger(void); +void HAL_FLASHEx_DisableDebugger(void); +uint32_t HAL_FLASHEx_FlashEmptyCheck(void); +void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty); +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +void HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks); +#endif +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + * @{ + */ +#define FLASH_PCROP_GRANULARITY_OFFSET 9u /*!< FLASH Code Readout Protection granularity offset */ +#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 512 Bytes */ +/** + * @} + */ + + +/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + * @{ + */ +#define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY)) +void FLASH_PageErase(uint32_t Banks, uint32_t Page); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_FLASH_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h (revision 3) @@ -0,0 +1,340 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_GPIO_H +#define STM32G0xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0xX0yz00YZ + * - X : GPIO mode or EXTI Mode + * - y : External IT or Event trigger detection + * - z : IO configuration on External IT or Event + * - Y : Output type (Push Pull or Open Drain) + * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @{ + */ +#define GPIO_MODE_INPUT (0x00000000u) /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (0x00000001u) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (0x00000011u) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (0x00000002u) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (0x00000012u) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG (0x00000003u) /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (0x10110000u) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (0x10210000u) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (0x10310000u) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (0x10120000u) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (0x10220000u) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (0x10320000u) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW (0x00000000u) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM (0x00000001u) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH (0x00000002u) /*!< High speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003u) /*!< Very high speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL (0x00000000u) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP (0x00000001u) /*!< Pull-up activation */ +#define GPIO_PULLDOWN (0x00000002u) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line is rising edge asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI line rising pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is falling edge asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI line falling pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \ + __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) \ + do { \ + __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__); \ + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__); \ + } while(0) + + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) + +/** + * @brief Clear the EXTI line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Include GPIO HAL Extended module */ +#include "stm32g0xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @brief GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h (revision 3) @@ -0,0 +1,838 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_GPIO_EX_H +#define STM32G0xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ +#if defined (STM32G0C1xx) || defined (STM32G0B1xx) +/*------------------------- STM32G0C1xx / STM32G0B1xx ------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< CEC Alternate Function mapping */ +#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< CRS Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< USART4 Alternate Function mapping */ +#define GPIO_AF0_UCPD1 ((uint8_t)0x00) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF0_UCPD2 ((uint8_t)0x00) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< CEC Alternate Function mapping */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_LPTIM2 ((uint8_t)0x01) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF1_LPUART1 ((uint8_t)0x01) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF1_LPUART2 ((uint8_t)0x01) /*!< LPUART2 Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF1_USART4 ((uint8_t)0x01) /*!< USART4 Alternate Function mapping */ +#define GPIO_AF1_UCPD1 ((uint8_t)0x01) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF1_UCPD2 ((uint8_t)0x01) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02) /*!< USB Alternate Function mapping */ + + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_FDCAN1 ((uint8_t)0x03) /*!< FDCAN1 Alternate Function mapping */ +#define GPIO_AF3_FDCAN2 ((uint8_t)0x03) /*!< FDCAN2 Alternate Function mapping */ +#define GPIO_AF3_LPUART2 ((uint8_t)0x03) /*!< LPUART2 Alternate Function mapping */ +#define GPIO_AF3_USART5 ((uint8_t)0x03) /*!< USART5 Alternate Function mapping */ +#define GPIO_AF3_USART6 ((uint8_t)0x03) /*!< USART6 Alternate Function mapping */ +#define GPIO_AF3_MCO2 ((uint8_t)0x03) /*!< MCO2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< CRS Alternate Function mapping */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_SPI3 ((uint8_t)0x04) /*!< SPI3 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< USART4 Alternate Function mapping */ +#define GPIO_AF4_USART6 ((uint8_t)0x04) /*!< USART6 Alternate Function mapping */ +#define GPIO_AF4_UCPD1 ((uint8_t)0x04) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF4_UCPD2 ((uint8_t)0x04) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF5_LPTIM2 ((uint8_t)0x05) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF5_USART3 ((uint8_t)0x05) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF6_UCPD1 ((uint8_t)0x06) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF6_UCPD2 ((uint8_t)0x06) /*!< UCPD2 Alternate Function mapping */ +#define GPIO_AF6_USB ((uint8_t)0x06) /*!< USB Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF7_COMP3 ((uint8_t)0x07) /*!< COMP3 Alternate Function mapping */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_I2C2 ((uint8_t)0x08) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF8_USART5 ((uint8_t)0x08) /*!< USART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /*!< USART5 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF9_SPI3 ((uint8_t)0x09) /*!< SPI3 Alternate Function mapping */ +#define GPIO_AF9_TIM4 ((uint8_t)0x09) /*!< TIM4 Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_LPUART2 ((uint8_t)0x0A) /*!< LPUART2 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0A) + +#endif + +#if defined (STM32G0B0xx) +/*------------------------- STM32G0B0xx ------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_CRS ((uint8_t)0x00) /*!< CRS Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_TIM15 ((uint8_t)0x00) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF0_TIM16 ((uint8_t)0x00) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF0_TIM17 ((uint8_t)0x00) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF0_USART4 ((uint8_t)0x00) /*!< USART4 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_EVENTOUT ((uint8_t)0x01) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF1_USART4 ((uint8_t)0x01) /*!< USART4 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02) /*!< USB Alternate Function mapping */ + + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_USART5 ((uint8_t)0x03) /*!< USART5 Alternate Function mapping */ +#define GPIO_AF3_USART6 ((uint8_t)0x03) /*!< USART6 Alternate Function mapping */ +#define GPIO_AF3_MCO2 ((uint8_t)0x03) /*!< MCO2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_CRS ((uint8_t)0x04) /*!< CRS Alternate Function mapping */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_SPI3 ((uint8_t)0x04) /*!< SPI3 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< USART4 Alternate Function mapping */ +#define GPIO_AF4_USART6 ((uint8_t)0x04) /*!< USART6 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF5_USART3 ((uint8_t)0x05) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF6_USB ((uint8_t)0x06) /*!< USB Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_I2C2 ((uint8_t)0x08) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF8_USART5 ((uint8_t)0x08) /*!< USART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08) /*!< USART5 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_I2C3 ((uint8_t)0x09) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF9_SPI3 ((uint8_t)0x09) /*!< SPI3 Alternate Function mapping */ +#define GPIO_AF9_TIM4 ((uint8_t)0x09) /*!< TIM4 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x09) + +#endif + + +#if defined (STM32G081xx) || defined (STM32G071xx) +/*------------------------- STM32G081xx / STM32G071xx ------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_CEC ((uint8_t)0x00) /*!< CEC Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF0_UCPD1 ((uint8_t)0x00) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF0_UCPD2 ((uint8_t)0x00) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_CEC ((uint8_t)0x01) /*!< CEC Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_LPUART1 ((uint8_t)0x01) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF1_USART4 ((uint8_t)0x01) /*!< USART4 Alternate Function mapping */ +#define GPIO_AF1_UCPD1 ((uint8_t)0x01) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF1_UCPD2 ((uint8_t)0x01) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_UCPD1 ((uint8_t)0x03) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF3_UCPD2 ((uint8_t)0x03) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< USART4 Alternate Function mapping */ +#define GPIO_AF4_UCPD1 ((uint8_t)0x04) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF4_UCPD2 ((uint8_t)0x04) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF5_LPTIM2 ((uint8_t)0x05) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF5_USART3 ((uint8_t)0x05) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF6_UCPD1 ((uint8_t)0x06) /*!< UCPD1 Alternate Function mapping */ +#define GPIO_AF6_UCPD2 ((uint8_t)0x06) /*!< UCPD2 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G081xx || STM32G071xx */ + +#if defined (STM32G070xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF0_USART3 ((uint8_t)0x00) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF1_USART4 ((uint8_t)0x01) /*!< USART4 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF4_USART3 ((uint8_t)0x04) /*!< USART3 Alternate Function mapping */ +#define GPIO_AF4_USART4 ((uint8_t)0x04) /*!< USART4 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ +#define GPIO_AF5_USART3 ((uint8_t)0x05) /*!< USART3 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G070xx */ + +#if defined (STM32G051xx) || defined (STM32G061xx) +/*------------------------- STM32G061xx / STM32G051xx ------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_LPUART1 ((uint8_t)0x01) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF5_LPTIM2 ((uint8_t)0x05) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /*!< LPUART1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /*!< COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /*!< COMP2 Alternate Function mapping */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G051xx || STM32G061xx */ + +#if defined (STM32G050xx) +/*------------------------- STM32G050xx --------------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM15 ((uint8_t)0x02) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_TIM15 ((uint8_t)0x04) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM15 ((uint8_t)0x05) /*!< TIM15 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G050xx */ + +#if defined (STM32G031xx) || defined (STM32G041xx) +/*------------------------- STM32G041xx / STM32G031xx ------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_LPUART1 ((uint8_t)0x01) /*!< LPUART1 Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF5_LPTIM2 ((uint8_t)0x05) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /*!< LPUART1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G031xx || STM32G041xx */ + +#if defined (STM32G030xx) +/*------------------------- STM32G030xx --------------------------------------*/ +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1) Alternate Function mapping */ +#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ +#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */ +#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ +#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07) + +#endif /* STM32G030xx */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index +* @{ + */ +#if defined(GPIOE) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL :\ + ((__GPIOx__) == (GPIOE))? 4uL : 5uL) +#else +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ + ((__GPIOx__) == (GPIOB))? 1uL :\ + ((__GPIOx__) == (GPIOC))? 2uL :\ + ((__GPIOx__) == (GPIOD))? 3uL : 5uL) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_GPIO_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr.h (revision 3) @@ -0,0 +1,328 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_PWR_H +#define STM32G0xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_WakeUp_Pins PWR WakeUp pins + * @{ + */ +#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level detection) */ +#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level detection) */ +#if defined(PWR_CR3_EWUP3) +#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level detection) */ +#endif +#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level detection) */ +#if defined(PWR_CR3_EWUP5) +#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level detection) */ +#endif +#define PWR_WAKEUP_PIN6 PWR_CR3_EWUP6 /*!< Wakeup pin 6 (with high level detection) */ +#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level detection) */ +#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level detection) */ +#if defined(PWR_CR3_EWUP3) +#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level detection) */ +#endif +#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level detection) */ +#if defined(PWR_CR3_EWUP5) +#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level detection) */ +#endif +#define PWR_WAKEUP_PIN6_HIGH PWR_CR3_EWUP6 /*!< Wakeup pin 6 (with high level detection) */ +#define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level detection) */ +#define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level detection) */ +#if defined(PWR_CR3_EWUP3) +#define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level detection) */ +#endif +#define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level detection) */ +#if defined(PWR_CR3_EWUP5) +#define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level detection) */ +#endif +#define PWR_WAKEUP_PIN6_LOW ((PWR_CR4_WP6 << PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP6) /*!< Wakeup pin 6 (with low level detection) */ +/** + * @} + */ + +/** @defgroup PWR_Low_Power_Mode_Selection PWR Low Power Mode Selection + * @{ + */ +#define PWR_LOWPOWERMODE_STOP0 (0x00000000u) /*!< Stop 0: stop mode with main regulator */ +#define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0) /*!< Stop 1: stop mode with low power regulator */ +#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */ +#if defined(PWR_SHDW_SUPPORT) +#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2) /*!< Shutdown mode */ +#endif +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0x00000000u) /*!< Regulator in main mode */ +#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */ +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01u) /*!< Wait For Interruption instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02u) /*!< Wait For Event instruction to enter Sleep mode */ +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01u) /*!< Wait For Interruption instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE ((uint8_t)0x02u) /*!< Wait For Event instruction to enter Stop mode */ +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Status Flags + * @brief Elements values convention: 0000 00XX 000Y YYYYb + * - Y YYYY : Flag position in the XX register (5 bits) + * - XX : Status register (2 bits) + * - 01: SR1 register + * - 10: SR2 register + * The only exception is PWR_FLAG_WU, encompassing all + * wake-up flags and set to PWR_SR1_WUF. + * @{ + */ +#define PWR_FLAG_WUF1 (0x00010000u | PWR_SR1_WUF1) /*!< Wakeup event on wakeup pin 1 */ +#define PWR_FLAG_WUF2 (0x00010000u | PWR_SR1_WUF2) /*!< Wakeup event on wakeup pin 2 */ +#if defined(PWR_CR3_EWUP3) +#define PWR_FLAG_WUF3 (0x00010000u | PWR_SR1_WUF3) /*!< Wakeup event on wakeup pin 3 */ +#endif +#define PWR_FLAG_WUF4 (0x00010000u | PWR_SR1_WUF4) /*!< Wakeup event on wakeup pin 4 */ +#if defined(PWR_CR3_EWUP5) +#define PWR_FLAG_WUF5 (0x00010000u | PWR_SR1_WUF5) /*!< Wakeup event on wakeup pin 5 */ +#endif +#define PWR_FLAG_WUF6 (0x00010000u | PWR_SR1_WUF6) /*!< Wakeup event on wakeup pin 6 */ +#define PWR_FLAG_WUF (0x00010000u | PWR_SR1_WUF) /*!< Wakeup event on all wakeup pin */ +#define PWR_FLAG_SB (0x00010000u | PWR_SR1_SBF) /*!< Standby flag */ +#define PWR_FLAG_WUFI (0x00010000u | PWR_SR1_WUFI) /*!< Wakeup on internal wakeup line */ +#define PWR_FLAG_FLASH_READY (0x00020000u | PWR_SR2_FLASH_RDY) /*!< Flash ready */ +#define PWR_FLAG_REGLPS (0x00020000u | PWR_SR2_REGLPS) /*!< Regulator Low Power started */ +#define PWR_FLAG_REGLPF (0x00020000u | PWR_SR2_REGLPF) /*!< Regulator Low Power flag */ +#if defined(PWR_PVD_SUPPORT) +#define PWR_FLAG_PVDO (0x00020000u | PWR_SR2_PVDO) /*!< Power Voltage Detector output */ +#endif +#if defined(PWR_PVM_SUPPORT) +#define PWR_FLAG_PVMO_USB (0x00020000u | PWR_SR2_PVMO_USB) /*!< Power Voltage Monitoring output */ +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macros PWR Exported Macros + * @{ + */ +/** @brief Check whether or not a specific PWR flag is set. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one a combination of following values: + * @arg PWR_FLAG_WUF1: Wake Up Flag 1. Indicates that a wakeup event + * was received from the WKUP pin 1. + * @arg PWR_FLAG_WUF2: Wake Up Flag 2. Indicates that a wakeup event + * was received from the WKUP pin 2. + * @arg PWR_FLAG_WUF3: Wake Up Flag 3. Indicates that a wakeup event + * was received from the WKUP pin 3. (*) + * @arg PWR_FLAG_WUF4: Wake Up Flag 4. Indicates that a wakeup event + * was received from the WKUP pin 4. + * @arg PWR_FLAG_WUF5: Wake Up Flag 5. Indicates that a wakeup event + * was received from the WKUP pin 5. (*) + * @arg PWR_FLAG_WUF6: Wake Up Flag 6. Indicates that a wakeup event + * was received from the WKUP pin 6. + * @arg PWR_FLAG_SB: StandBy Flag. Indicates that the system + * entered StandBy mode. + * @arg PWR_FLAG_WUFI: Wake-Up Flag Internal. Set when a wakeup is + * detected on the internal wakeup line. + * OR a combination of following values: + * @arg PWR_FLAG_FLASH_READY: Flash is ready. Indicates whether flash + * can be used or not + * @arg PWR_FLAG_REGLPS: Low Power Regulator Started. Indicates whether + * or not the low-power regulator is ready. + * @arg PWR_FLAG_REGLPF: Low Power Regulator Flag. Indicates whether the + * regulator is ready in main mode or is in low-power mode. + * @if defined(STM32G081xx) + * @arg PWR_FLAG_PVDO: Power Voltage Detector Output. Indicates whether + * VDD voltage is below or above the selected PVD threshold. + * @endif + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) (((__FLAG__) & 0x00010000u) ?\ + ((PWR->SR1 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u)) :\ + ((PWR->SR2 & ((__FLAG__) & ~0x00030000u)) == ((__FLAG__) & ~0x00030000u))) + +/** @brief Clear a specific PWR flag. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be a combination of following values: + * @arg PWR_FLAG_WUF1: Wake Up Flag 1. Indicates that a wakeup event + * was received from the WKUP pin 1. + * @arg PWR_FLAG_WUF2: Wake Up Flag 2. Indicates that a wakeup event + * was received from the WKUP pin 2. + * @arg PWR_FLAG_WUF3: Wake Up Flag 3. Indicates that a wakeup event + * was received from the WKUP pin 3. (*) + * @arg PWR_FLAG_WUF4: Wake Up Flag 4. Indicates that a wakeup event + * was received from the WKUP pin 4. + * @arg PWR_FLAG_WUF5: Wake Up Flag 5. Indicates that a wakeup event + * was received from the WKUP pin 5. (*) + * @arg PWR_FLAG_WUF6: Wake Up Flag 6. Indicates that a wakeup event + * was received from the WKUP pin 6. + * @arg PWR_FLAG_WUF: Encompasses all Wake Up Flags. + * @arg PWR_FLAG_SB: Standby Flag. Indicates that the system + * entered Standby mode. + * @retval None + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->SCR = (__FLAG__)) + +/** + * @} + */ + +/* Private constants-------------------------------------------------------*/ +/** @defgroup PWR_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants + * @{ + */ +#define PWR_WUP_POLARITY_SHIFT 0x08u /*!< Internal constant used to retrieve wakeup pin polariry */ +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +#define IS_PWR_WAKEUP_PIN(PIN) ((((PIN) & ((PWR_CR4_WP << 8U) | (PWR_CR3_EWUP))) != 0x00000000u) && \ + (((PIN) & ~((PWR_CR4_WP << 8U) | (PWR_CR3_EWUP))) == 0x00000000u)) + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) + +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || \ + ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || \ + ((ENTRY) == PWR_STOPENTRY_WFE)) +/** + * @} + */ + +/* Include PWR HAL Extended module */ +#include "stm32g0xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions *******************************/ +void HAL_PWR_DeInit(void); +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); + +/* WakeUp pins configuration functions ****************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes configuration functions ************************************/ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSTANDBYMode(void); +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32G0xx_HAL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_pwr_ex.h (revision 3) @@ -0,0 +1,643 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_PWR_EX_H +#define STM32G0xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Types PWR Extended Exported Types + * @{ + */ + +#if defined(PWR_PVM_SUPPORT) +/** + * @brief PWR PVM configuration structure definition + */ +typedef struct +{ + uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold. + This parameter can be a value of @ref PWREx_PVM_Type. + @arg @ref PWR_PVM_USB Peripheral Voltage Monitoring USB enable */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWREx_PVM_Mode. */ +}PWR_PVMTypeDef; +#endif + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value or a combination of + @ref PWR_PVD_detection_level. */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode. */ +}PWR_PVDTypeDef; +#endif + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants + * @{ + */ +#if defined(PWR_PVD_SUPPORT) +/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels + * @note see datasheet for selection voltage value + * @{ + */ +#define PWR_PVDLEVEL_RISING_0 (0x00000000u) /*!< PVD threshold level 0 for rising detection */ +#define PWR_PVDLEVEL_RISING_1 (PWR_CR2_PVDRT_0) /*!< PVD threshold level 1 for rising detection */ +#define PWR_PVDLEVEL_RISING_2 (PWR_CR2_PVDRT_1) /*!< PVD threshold level 2 for rising detection */ +#define PWR_PVDLEVEL_RISING_3 (PWR_CR2_PVDRT_0 | PWR_CR2_PVDRT_1) /*!< PVD threshold level 3 for rising detection */ +#define PWR_PVDLEVEL_RISING_4 (PWR_CR2_PVDRT_2) /*!< PVD threshold level 4 for rising detection */ +#define PWR_PVDLEVEL_RISING_5 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_0) /*!< PVD threshold level 5 for rising detection */ +#define PWR_PVDLEVEL_RISING_6 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1) /*!< PVD threshold level 6 for rising detection */ +#define PWR_PVDLEVEL_FALLING_0 (0x00000000u) /*!< PVD threshold level 0 for falling detection */ +#define PWR_PVDLEVEL_FALLING_1 (PWR_CR2_PVDFT_0) /*!< PVD threshold level 1 for falling detection */ +#define PWR_PVDLEVEL_FALLING_2 (PWR_CR2_PVDFT_1) /*!< PVD threshold level 2 for falling detection */ +#define PWR_PVDLEVEL_FALLING_3 (PWR_CR2_PVDFT_0 | PWR_CR2_PVDFT_1) /*!< PVD threshold level 3 for falling detection */ +#define PWR_PVDLEVEL_FALLING_4 (PWR_CR2_PVDFT_2) /*!< PVD threshold level 4 for falling detection */ +#define PWR_PVDLEVEL_FALLING_5 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_0) /*!< PVD threshold level 5 for falling detection */ +#define PWR_PVDLEVEL_FALLING_6 (PWR_CR2_PVDFT_2 | PWR_CR2_PVDFT_1) /*!< PVD threshold level 6 for falling detection */ +#define PWR_PVDLEVEL_0 (PWR_PVDLEVEL_RISING_0 | PWR_PVDLEVEL_FALLING_0) /*!< same PVD threshold level 0 on rising & falling */ +#define PWR_PVDLEVEL_1 (PWR_PVDLEVEL_RISING_1 | PWR_PVDLEVEL_FALLING_1) /*!< same PVD threshold level 1 on rising & falling */ +#define PWR_PVDLEVEL_2 (PWR_PVDLEVEL_RISING_2 | PWR_PVDLEVEL_FALLING_2) /*!< same PVD threshold level 2 on rising & falling */ +#define PWR_PVDLEVEL_3 (PWR_PVDLEVEL_RISING_3 | PWR_PVDLEVEL_FALLING_3) /*!< same PVD threshold level 3 on rising & falling */ +#define PWR_PVDLEVEL_4 (PWR_PVDLEVEL_RISING_4 | PWR_PVDLEVEL_FALLING_4) /*!< same PVD threshold level 4 on rising & falling */ +#define PWR_PVDLEVEL_5 (PWR_PVDLEVEL_RISING_5 | PWR_PVDLEVEL_FALLING_5) /*!< same PVD threshold level 5 on rising & falling */ +#define PWR_PVDLEVEL_6 (PWR_PVDLEVEL_RISING_6 | PWR_PVDLEVEL_FALLING_6) /*!< same PVD threshold level 6 on rising & falling */ +#define PWR_PVDLEVEL_7 (PWR_CR2_PVDRT_2 | PWR_CR2_PVDRT_1 | PWR_CR2_PVDRT_0) /*!< External input analog voltage (compared internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00000000u) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x00010001u) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x00010002u) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003u) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x00020001u) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x00020002u) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003u) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line + * @{ + */ +#define PWR_EXTI_LINE_PVD (EXTI_IMR1_IM16) /*!< External interrupt line 16 connected to PVD */ +/** + * @} + */ + +/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line + * @{ + */ +#define PWR_EVENT_LINE_PVD (EXTI_EMR1_EM16) /*!< Event line 16 connected to PVD */ +/** + * @} + */ +#endif + +#if defined(PWR_PVM_SUPPORT) +/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type + * @{ + */ +#define PWR_PVM_USB PWR_CR2_PVMEN_USB /*!< Peripheral Voltage Monitoring enable for USB peripheral: Enable to keep the USB peripheral voltage monitoring under control (power domain Vddio2) */ +/** + * @} + */ +/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode + * @{ + */ +#define PWR_PVM_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ +#define PWR_PVM_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVM_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVM_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVM_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVM_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVM_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ +/** @defgroup PWR_PVM_EXTI_LINE PWR PVM external interrupt line + * @{ + */ +#define PWR_EXTI_LINE_PVM (EXTI_IMR2_IM34) /*!< External interrupt line 34 connected to PVM */ +/** + * @} + */ + +/** @defgroup PWR_PVM_EVENT_LINE PWR PVM event line + * @{ + */ +#define PWR_EVENT_LINE_PVM (EXTI_EMR2_EM34) /*!< Event line 34 connected to PVM */ +/** + * @} + */ +#endif + +/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection + * @{ + */ +#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000u) /*!< VBAT charging through a 5 kOhms resistor */ +#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ +/** + * @} + */ + +/** @defgroup PWREx_GPIO_Bit_Number GPIO bit position + * @brief for I/O pull up/down setting in standby/shutdown mode + * @{ + */ +#define PWR_GPIO_BIT_0 PWR_PUCRB_PU0 /*!< GPIO port I/O pin 0 */ +#define PWR_GPIO_BIT_1 PWR_PUCRB_PU1 /*!< GPIO port I/O pin 1 */ +#define PWR_GPIO_BIT_2 PWR_PUCRB_PU2 /*!< GPIO port I/O pin 2 */ +#define PWR_GPIO_BIT_3 PWR_PUCRB_PU3 /*!< GPIO port I/O pin 3 */ +#define PWR_GPIO_BIT_4 PWR_PUCRB_PU4 /*!< GPIO port I/O pin 4 */ +#define PWR_GPIO_BIT_5 PWR_PUCRB_PU5 /*!< GPIO port I/O pin 5 */ +#define PWR_GPIO_BIT_6 PWR_PUCRB_PU6 /*!< GPIO port I/O pin 6 */ +#define PWR_GPIO_BIT_7 PWR_PUCRB_PU7 /*!< GPIO port I/O pin 7 */ +#define PWR_GPIO_BIT_8 PWR_PUCRB_PU8 /*!< GPIO port I/O pin 8 */ +#define PWR_GPIO_BIT_9 PWR_PUCRB_PU9 /*!< GPIO port I/O pin 9 */ +#define PWR_GPIO_BIT_10 PWR_PUCRB_PU10 /*!< GPIO port I/O pin 10 */ +#define PWR_GPIO_BIT_11 PWR_PUCRB_PU11 /*!< GPIO port I/O pin 11 */ +#define PWR_GPIO_BIT_12 PWR_PUCRB_PU12 /*!< GPIO port I/O pin 12 */ +#define PWR_GPIO_BIT_13 PWR_PUCRB_PU13 /*!< GPIO port I/O pin 13 */ +#define PWR_GPIO_BIT_14 PWR_PUCRB_PU14 /*!< GPIO port I/O pin 14 */ +#define PWR_GPIO_BIT_15 PWR_PUCRB_PU15 /*!< GPIO port I/O pin 15 */ +/** + * @} + */ + +/** @defgroup PWREx_GPIO_Port GPIO Port + * @{ + */ +#define PWR_GPIO_A (0x00000000u) /*!< GPIO port A */ +#define PWR_GPIO_B (0x00000001u) /*!< GPIO port B */ +#define PWR_GPIO_C (0x00000002u) /*!< GPIO port C */ +#define PWR_GPIO_D (0x00000003u) /*!< GPIO port D */ +#if defined (GPIOE) +#define PWR_GPIO_E (0x00000004u) /*!< GPIO port E */ +#endif +#define PWR_GPIO_F (0x00000005u) /*!< GPIO port F */ +/** + * @} + */ + +/** @defgroup PWREx_Flash_PowerDown Flash Power Down modes + * @{ + */ +#define PWR_FLASHPD_LPRUN PWR_CR1_FPD_LPRUN /*!< Enable Flash power down in low power run mode */ +#define PWR_FLASHPD_LPSLEEP PWR_CR1_FPD_LPSLP /*!< Enable Flash power down in low power sleep mode */ +#define PWR_FLASHPD_STOP PWR_CR1_FPD_STOP /*!< Enable Flash power down in stop mode */ +/** + * @} + */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale + * @{ + */ +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Voltage scaling range 1 */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Voltage scaling range 2 */ +/** + * @} + */ + +/** @addtogroup PWR_Flag PWR Status Flags + * @brief Elements values convention: 0000 00XX 000Y YYYYb + * - Y YYYY : Flag position in the XX register (5 bits) + * - XX : Status register (2 bits) + * - 01: SR1 register + * - 10: SR2 register + * The only exception is PWR_FLAG_WU, encompassing all + * wake-up flags and set to PWR_SR1_WUF. + * @{ + */ +#if defined(PWR_PVM_SUPPORT) +#define PWR_FLAG_PVMOUSB (0x00020000u | PWR_SR2_PVMO_USB) /*!< USB Peripheral Voltage Monitoring output */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Macros PWR Extended Exported Macros + * @{ + */ +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Enable the PVD Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Event Line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) + +/** + * @brief Disable the PVD Event Line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether or not the PVD EXTI interrupt Rising flag is set. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG() (EXTI->RPR1 & PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether or not the PVD EXTI interrupt Falling flag is set. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() (EXTI->FPR1 & PWR_EXTI_LINE_PVD) + +/** + * @brief Clear the PVD EXTI interrupt Rising flag. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Clear the PVD EXTI interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD) +#endif + +#if defined(PWR_PVM_SUPPORT) +/** + * @brief Enable the PVM Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Disable the PVM Extended Interrupt Line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Enable the PVM Event Line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM) + +/** + * @brief Disable the PVM Event Line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM) + +/** + * @brief Enable the PVM Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Disable the PVM Extended Interrupt Rising Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Enable the PVM Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Disable the PVM Extended Interrupt Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Enable the PVM Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Disable the PVM Extended Interrupt Rising & Falling Trigger. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do { \ + __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM) + +/** + * @brief Check whether or not the PVM EXTI interrupt Rising flag is set. + * @retval EXTI PVM Line Status. + */ +#define __HAL_PWR_PVM_EXTI_GET_RISING_FLAG() (EXTI->RPR2 & PWR_EXTI_LINE_PVM) + +/** + * @brief Check whether or not the PVM EXTI interrupt Falling flag is set. + * @retval EXTI PVM Line Status. + */ +#define __HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() (EXTI->FPR2 & PWR_EXTI_LINE_PVM) + +/** + * @brief Clear the PVM EXTI interrupt Rising flag. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR2, PWR_EXTI_LINE_PVM) + +/** + * @brief Clear the PVM EXTI interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR2, PWR_EXTI_LINE_PVM) +#endif +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines + * @{ + */ + +/** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask + * @{ + */ +#define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */ +#define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */ +#define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */ +#define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros + * @{ + */ + +#define IS_PWR_BATTERY_RESISTOR_SELECT(__RESISTOR__) (((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_5) || \ + ((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) + +#define IS_PWR_GPIO_BIT_NUMBER(__BIT_NUMBER__) ((((__BIT_NUMBER__) & 0x0000FFFFu) != 0x00u) && \ + (((__BIT_NUMBER__) & 0xFFFF0000u) == 0x00u)) +#if defined (GPIOE) +#define IS_PWR_GPIO(__GPIO__) (((__GPIO__) == PWR_GPIO_A) || \ + ((__GPIO__) == PWR_GPIO_B) || \ + ((__GPIO__) == PWR_GPIO_C) || \ + ((__GPIO__) == PWR_GPIO_D) || \ + ((__GPIO__) == PWR_GPIO_E) || \ + ((__GPIO__) == PWR_GPIO_F)) +#else +#define IS_PWR_GPIO(__GPIO__) (((__GPIO__) == PWR_GPIO_A) || \ + ((__GPIO__) == PWR_GPIO_B) || \ + ((__GPIO__) == PWR_GPIO_C) || \ + ((__GPIO__) == PWR_GPIO_D) || \ + ((__GPIO__) == PWR_GPIO_F)) +#endif + +#define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) != 0x00u) && \ + (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP | PWR_FLASHPD_STOP)) == 0x00u)) + +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) + +#if defined(PWR_PVD_SUPPORT) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) & ~(PWR_CR2_PVDRT | PWR_CR2_PVDFT)) == 0x00000000u) + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING) || \ + ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) +#endif + +#if defined(PWR_PVM_SUPPORT) +#define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_USB) + +#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ + ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) +#endif +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions **********************************************/ +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection); +void HAL_PWREx_DisableBatteryCharging(void); +#if defined(PWR_CR3_ENB_ULP) +void HAL_PWREx_EnablePORMonitorSampling(void); +void HAL_PWREx_DisablePORMonitorSampling(void); +#endif +void HAL_PWREx_EnableInternalWakeUpLine(void); +void HAL_PWREx_DisableInternalWakeUpLine(void); +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber); +void HAL_PWREx_EnablePullUpPullDownConfig(void); +void HAL_PWREx_DisablePullUpPullDownConfig(void); +#if defined(PWR_CR3_RRS) +void HAL_PWREx_EnableSRAMRetention(void); +void HAL_PWREx_DisableSRAMRetention(void); +#endif +void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode); +void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode); +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); +#if defined(PWR_PVD_SUPPORT) +/* Power voltage detection configuration functions ****************************/ +HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWREx_EnablePVD(void); +void HAL_PWREx_DisablePVD(void); +#endif +#if defined(PWR_PVM_SUPPORT) +/* Power voltage monitoring configuration functions ***************************/ +void HAL_PWREx_EnableVddIO2(void); +void HAL_PWREx_DisableVddIO2(void); +void HAL_PWREx_EnableVddUSB(void); +void HAL_PWREx_DisableVddUSB(void); +void HAL_PWREx_EnablePVMUSB(void); +void HAL_PWREx_DisablePVMUSB(void); +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); +#endif + +/* Low Power modes configuration functions ************************************/ +void HAL_PWREx_EnableLowPowerRunMode(void); +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); +#if defined(PWR_SHDW_SUPPORT) +void HAL_PWREx_EnterSHUTDOWNMode(void); +#endif + +#if defined(PWR_PVD_SUPPORT) && defined(PWR_PVM_SUPPORT) +void HAL_PWREx_PVD_PVM_IRQHandler(void); +void HAL_PWREx_PVD_PVM_Rising_Callback(void); +void HAL_PWREx_PVD_PVM_Falling_Callback(void); +#elif defined(PWR_PVD_SUPPORT) +void HAL_PWREx_PVD_IRQHandler(void); +void HAL_PWREx_PVD_Rising_Callback(void); +void HAL_PWREx_PVD_Falling_Callback(void); +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32G0xx_HAL_PWR_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h (revision 3) @@ -0,0 +1,3111 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_RCC_H +#define STM32G0xx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" +#include "stm32g0xx_ll_rcc.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RCC_Private_Constants + * @{ + */ +/* Defines used for Flags */ +#define CR_REG_INDEX 1U +#define BDCR_REG_INDEX 2U +#define CSR_REG_INDEX 3U +#if defined(RCC_HSI48_SUPPORT) +#define CRRCR_REG_INDEX 4U +#endif /* RCC_HSI48_SUPPORT */ + +#define RCC_FLAG_MASK 0x1FU + +/* Define used for IS_RCC_CLOCKTYPE() */ +#define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1) /*!< All clocktype to configure */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros + * @{ + */ + +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ + (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#else +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) \ + (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#endif /* RCC_HSI48_SUPPORT */ + +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) + +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) + +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) + +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) +#endif /* RCC_HSI48_SUPPORT */ + +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U) + +#define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1) || ((__DIV__) == RCC_HSI_DIV2) || \ + ((__DIV__) == RCC_HSI_DIV4) || ((__DIV__) == RCC_HSI_DIV8) || \ + ((__DIV__) == RCC_HSI_DIV16) || ((__DIV__) == RCC_HSI_DIV32)|| \ + ((__DIV__) == RCC_HSI_DIV64) || ((__DIV__) == RCC_HSI_DIV128)) + +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) + +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_PLLM_VALUE(__VALUE__) ((__VALUE__) <= RCC_PLLM_DIV8) + +#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) + +#define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) + +#if defined(RCC_PLLQ_SUPPORT) +#define IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) +#endif /* RCC_PLLQ_SUPPORT */ + +#define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) + +#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) + +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) + +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) + +#if defined(RCC_MCO2_SUPPORT) +#define IS_RCC_MCO(__MCOX__) ( ((__MCOX__) == RCC_MCO1) || ((__MCOX__) == RCC_MCO2) ) +#else +#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) +#endif /* RCC_MCO2_SUPPORT */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI48) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_RTCCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WKUP)) +#elif defined(STM32G0B0xx) +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_RTCCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_RTC_WKUP)) +#else +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) +#endif /* STM32G0C1xx || STM32G0B1xx */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16) || ((__DIV__) == RCC_MCODIV_32) || \ + ((__DIV__) == RCC_MCODIV_64) || ((__DIV__) == RCC_MCODIV_128) || \ + ((__DIV__) == RCC_MCODIV_256)|| ((__DIV__) == RCC_MCODIV_512) || \ + ((__DIV__) == RCC_MCODIV_1024)) +#else +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16) || ((__DIV__) == RCC_MCODIV_32) || \ + ((__DIV__) == RCC_MCODIV_64) || ((__DIV__) == RCC_MCODIV_128)) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(RCC_MCO2_SUPPORT) +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSI48) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_PLLPCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_PLLQCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_RTCCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WKUP)) +#else +#define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_PLLPCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_PLLQCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_RTCCLK) || \ + ((__SOURCE__) == RCC_MCO2SOURCE_RTC_WKUP)) +#endif /* RCC_HSI48_SUPPORT */ +#define IS_RCC_MCO2DIV(__DIV__) (((__DIV__) == RCC_MCO2DIV_1) || ((__DIV__) == RCC_MCO2DIV_2) || \ + ((__DIV__) == RCC_MCO2DIV_4) || ((__DIV__) == RCC_MCO2DIV_8) || \ + ((__DIV__) == RCC_MCO2DIV_16) || ((__DIV__) == RCC_MCO2DIV_32) || \ + ((__DIV__) == RCC_MCO2DIV_64) || ((__DIV__) == RCC_MCO2DIV_128)|| \ + ((__DIV__) == RCC_MCO2DIV_256)|| ((__DIV__) == RCC_MCO2DIV_512)|| \ + ((__DIV__) == RCC_MCO2DIV_1024)) + +#endif /* RCC_MCO2_SUPPORT */ + +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a value of @ref RCC_PLLM_Clock_Divider */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ + + uint32_t PLLP; /*!< PLLP: PLL Division factor. + User have to set the PLLQ parameter correctly to not exceed max frequency 64MHZ. + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + +#if defined(RCC_PLLQ_SUPPORT) + uint32_t PLLQ; /*!< PLLQ: PLL Division factor. + User have to set the PLLQ parameter correctly to not exceed max frequency 64MHZ. + This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ +#endif /* RCC_PLLQ_SUPPORT */ + + uint32_t PLLR; /*!< PLLR: PLL Division for the main system clock. + User have to set the PLLR parameter correctly to not exceed max frequency 64MHZ. + This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ + +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSIDiv; /*!< The division factor of the HSI16. + This parameter can be a value of @ref RCC_HSI_Div */ + + uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + +#if defined(RCC_HSI48_SUPPORT) + uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32G0C1xx/STM32G0B1xx/STM32G0B0xx devices). + This parameter can be a value of @ref RCC_HSI48_Config */ + +#endif /* RCC_HSI48_SUPPORT */ + + RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a combination of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_Clock_Source */ + + +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Timeout_Value Timeout Values + * @{ + */ +#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */ +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ +#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ +#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ +#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */ +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT 64U /*!< Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Div HSI Div + * @{ + */ +#define RCC_HSI_DIV1 0x00000000U /*!< HSI clock is not divided */ +#define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock is divided by 2 */ +#define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock is divided by 4 */ +#define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 8 */ +#define RCC_HSI_DIV16 RCC_CR_HSIDIV_2 /*!< HSI clock is divided by 16 */ +#define RCC_HSI_DIV32 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 32 */ +#define RCC_HSI_DIV64 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1) /*!< HSI clock is divided by 64 */ +#define RCC_HSI_DIV128 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_HSI48_Config HSI48 Config + * @{ + */ +#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ +#define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ +/** + * @} + */ +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_PLL_Config PLL Config + * @{ + */ +#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */ +#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ +#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ +/** + * @} + */ + +/** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider + * @{ + */ +#define RCC_PLLM_DIV1 0x00000000U /*!< PLLM division factor = 8 */ +#define RCC_PLLM_DIV2 RCC_PLLCFGR_PLLM_0 /*!< PLLM division factor = 2 */ +#define RCC_PLLM_DIV3 RCC_PLLCFGR_PLLM_1 /*!< PLLM division factor = 3 */ +#define RCC_PLLM_DIV4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 4 */ +#define RCC_PLLM_DIV5 RCC_PLLCFGR_PLLM_2 /*!< PLLM division factor = 5 */ +#define RCC_PLLM_DIV6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 6 */ +#define RCC_PLLM_DIV7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLLM division factor = 7 */ +#define RCC_PLLM_DIV8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1| RCC_PLLCFGR_PLLM_0) /*!< PLLM division factor = 8 */ +/** + * @} + */ + +/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider + * @{ + */ +#define RCC_PLLP_DIV2 RCC_PLLCFGR_PLLP_0 /*!< PLLP division factor = 2 */ +#define RCC_PLLP_DIV3 RCC_PLLCFGR_PLLP_1 /*!< PLLP division factor = 3 */ +#define RCC_PLLP_DIV4 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 4 */ +#define RCC_PLLP_DIV5 RCC_PLLCFGR_PLLP_2 /*!< PLLP division factor = 5 */ +#define RCC_PLLP_DIV6 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 6 */ +#define RCC_PLLP_DIV7 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 7 */ +#define RCC_PLLP_DIV8 (RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 8 */ +#define RCC_PLLP_DIV9 RCC_PLLCFGR_PLLP_3 /*!< PLLP division factor = 9 */ +#define RCC_PLLP_DIV10 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 10 */ +#define RCC_PLLP_DIV11 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 11 */ +#define RCC_PLLP_DIV12 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 12 */ +#define RCC_PLLP_DIV13 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 13 */ +#define RCC_PLLP_DIV14 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 14 */ +#define RCC_PLLP_DIV15 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 15 */ +#define RCC_PLLP_DIV16 (RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 16 */ +#define RCC_PLLP_DIV17 RCC_PLLCFGR_PLLP_4 /*!< PLLP division factor = 17 */ +#define RCC_PLLP_DIV18 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 18 */ +#define RCC_PLLP_DIV19 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 19 */ +#define RCC_PLLP_DIV20 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 20 */ +#define RCC_PLLP_DIV21 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 21 */ +#define RCC_PLLP_DIV22 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 22 */ +#define RCC_PLLP_DIV23 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 23 */ +#define RCC_PLLP_DIV24 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 24 */ +#define RCC_PLLP_DIV25 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3) /*!< PLLP division factor = 25 */ +#define RCC_PLLP_DIV26 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 26 */ +#define RCC_PLLP_DIV27 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 27 */ +#define RCC_PLLP_DIV28 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 28 */ +#define RCC_PLLP_DIV29 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2) /*!< PLLP division factor = 29 */ +#define RCC_PLLP_DIV30 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 30 */ +#define RCC_PLLP_DIV31 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1) /*!< PLLP division factor = 31 */ +#define RCC_PLLP_DIV32 (RCC_PLLCFGR_PLLP_4 | RCC_PLLCFGR_PLLP_3 | RCC_PLLCFGR_PLLP_2 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< PLLP division factor = 32 */ +/** + * @} + */ + +#if defined(RCC_PLLQ_SUPPORT) +/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider + * @{ + */ +#define RCC_PLLQ_DIV2 RCC_PLLCFGR_PLLQ_0 /*!< PLLQ division factor = 2 */ +#define RCC_PLLQ_DIV3 RCC_PLLCFGR_PLLQ_1 /*!< PLLQ division factor = 3 */ +#define RCC_PLLQ_DIV4 (RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 4 */ +#define RCC_PLLQ_DIV5 RCC_PLLCFGR_PLLQ_2 /*!< PLLQ division factor = 5 */ +#define RCC_PLLQ_DIV6 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 6 */ +#define RCC_PLLQ_DIV7 (RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_1) /*!< PLLQ division factor = 7 */ +#define RCC_PLLQ_DIV8 (RCC_PLLCFGR_PLLQ_2 |RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_0) /*!< PLLQ division factor = 8 */ +/** * @} + */ +#endif /* RCC_PLLQ_SUPPORT */ + +/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider + * @{ + */ +#define RCC_PLLR_DIV2 RCC_PLLCFGR_PLLR_0 /*!< PLLR division factor = 2 */ +#define RCC_PLLR_DIV3 RCC_PLLCFGR_PLLR_1 /*!< PLLR division factor = 3 */ +#define RCC_PLLR_DIV4 (RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 4 */ +#define RCC_PLLR_DIV5 RCC_PLLCFGR_PLLR_2 /*!< PLLR division factor = 5 */ +#define RCC_PLLR_DIV6 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 6 */ +#define RCC_PLLR_DIV7 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1) /*!< PLLR division factor = 7 */ +#define RCC_PLLR_DIV8 (RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_0) /*!< PLLR division factor = 8 */ +/** * @} + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Output PLL Clock Output + * @{ + */ +#define RCC_PLLPCLK RCC_PLLCFGR_PLLPEN /*!< PLLPCLK selection from main PLL */ +#if defined(RCC_PLLQ_SUPPORT) +#define RCC_PLLQCLK RCC_PLLCFGR_PLLQEN /*!< PLLQCLK selection from main PLL */ +#endif /* RCC_PLLQ_SUPPORT */ +#define RCC_PLLRCLK RCC_PLLCFGR_PLLREN /*!< PLLRCLK selection from main PLL */ + +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_1 /*!< PLL selection as system clock */ +#define RCC_SYSCLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection as system clock */ +#define RCC_SYSCLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_1 /*!< PLL used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ +#define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ +#define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ +#define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ +#define RCC_SYSCLK_DIV512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Source APB Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock configured for RTC */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 0x00000000U +#if defined(RCC_MCO2_SUPPORT) +#define RCC_MCO2 0x00000001U /*!< MCO2 index */ +#endif /* RCC_MCO2_SUPPORT */ + +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ +#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1 /*!< HSI48 selection as MCO1 source */ +#endif /* RCC_HSI48_SUPPORT */ +#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ +#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ +#if defined(RCC_CFGR_MCOSEL_3) +#define RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3 /*!< PLLPCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0) /*!< PLLQCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1) /*!< RTCCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0) /*!< RTC_Wakeup selection as MCO1 source */ +#endif /* RCC_CFGR_MCOSEL_3 */ +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Prescaler MCO1 Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 0x00000000U /*!< MCO not divided */ +#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */ +#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */ +#define RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */ +#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */ +#define RCC_MCODIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 32 */ +#define RCC_MCODIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 64 */ +#define RCC_MCODIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 128 */ +#if defined(RCC_CFGR_MCOPRE_3) +#define RCC_MCODIV_256 RCC_CFGR_MCOPRE_3 /*!< MCO divided by 256 */ +#define RCC_MCODIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 512 */ +#define RCC_MCODIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 1024 */ +#endif /* RCC_CFGR_MCOSEL_3 */ +/** + * @} + */ + +#if defined(RCC_MCO2_SUPPORT) +/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO2 output disabled, no clock on MCO2 */ +#define RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1 /*!< HSI48 selection as MCO2 source */ +#endif /* RCC_HSI48_SUPPORT */ +#define RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1| RCC_CFGR_MCO2SEL_0) /*!< HSI selection as MCO2 source */ +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */ +#define RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_0) /*!< PLLCLK selection as MCO2 source */ +#define RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1) /*!< LSI selection as MCO2 source */ +#define RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< LSE selection as MCO2 source */ +#define RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3 /*!< PLLPCLK selection as MCO2 source */ +#define RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_0) /*!< PLLQCLK selection as MCO2 source */ +#define RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1) /*!< RTCCLK selection as MCO2 source */ +#define RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_0) /*!< RTC_Wakeup selection as MCO2 source */ +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Prescaler MCO2 Clock Prescaler + * @{ + */ +#define RCC_MCO2DIV_1 0x00000000U /*!< MCO2 not divided */ +#define RCC_MCO2DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO2 divided by 2 */ +#define RCC_MCO2DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO2 divided by 4 */ +#define RCC_MCO2DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 8 */ +#define RCC_MCO2DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO2 divided by 16 */ +#define RCC_MCO2DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 32 */ +#define RCC_MCO2DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 64 */ +#define RCC_MCO2DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */ +#define RCC_MCO2DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO2 divided by 256 */ +#define RCC_MCO2DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 512 */ +#define RCC_MCO2DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 1024 */ +/** + * @} + */ +#endif /* RCC_MCO2_SUPPORT */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define RCC_IT_CSS RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ +#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: BDCR register + * - 011: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ +#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */ + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */ +#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */ +#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ +#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ +#define RCC_FLAG_PWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PWRRSTF_Pos) /*!< BOR or POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ + +#if defined(RCC_HSI48_SUPPORT) +/* Flags in the CRRCR register */ +#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_RC48RDY_Pos) /*!< HSI48 Ready flag */ +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Config LSE Drive Configuration + * @{ + */ +#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable + * @brief Enable or disable the AHB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(DMA2) +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#endif /* DMA2 */ + + +#define __HAL_RCC_FLASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(RNG) +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* RNG */ + +#if defined(AES) +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* AES */ + +#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) +#if defined(DMA2) +#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) +#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) +#if defined(RNG) +#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) +#endif /* AES */ +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Clock Enable Disable + * @brief Enable or disable the IO Ports clock. + * @note After reset, the IO ports clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* GPIOE */ + +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) +#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) +#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) +#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* TIM2 */ + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* TIM4 */ + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(CRS) +#define __HAL_RCC_CRS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* CRS */ + +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \ + UNUSED(tmpreg); \ + } while(0U) +#if defined(SPI3) +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* SPI3 */ + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(USART5) +#define __HAL_RCC_USART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* USART5 */ + +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* USART6 */ + +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* LPUART1 */ + +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* LPUART2 */ + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(I2C3) +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* I2C3 */ + +#if defined(CEC) +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* CEC */ + +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* UCPD1 */ + +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* UCPD2 */ + +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ + +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* FDCAN1 || FDCAN2 */ + +#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(DAC1) +#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* DAC1 */ + +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* LPTIM2 */ + +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* LPTIM1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN); \ + UNUSED(tmpreg); \ + } while(0U) +#endif /* TIM15 */ + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ + UNUSED(tmpreg); \ + } while(0U) + +#define __HAL_RCC_ADC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ + UNUSED(tmpreg); \ + } while(0U) + +#if defined(TIM2) +#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) +#endif /* TIM4 */ +#if defined(TIM6) +#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) +#endif /* TIM6 */ +#if defined(TIM7) +#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) +#endif /* TIM7 */ +#if defined(CRS) +#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) +#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) +#if defined(SPI3) +#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) +#if defined(USART3) +#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) +#endif /* USART4 */ +#if defined(USART5) +#define __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) +#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) +#if defined(I2C3) +#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) +#endif /* FDCAN1 || FDCAN2 */ +#define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) +#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) +#if defined(DAC1) +#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) +#endif /* DAC1 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) +#endif /* LPTIM1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) +#endif /* LPTIM2 */ +#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) +#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) +#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) +#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) +#define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) +#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) +#define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Peripheral_Clock_Enabled_Disabled_Status AHB Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET) +#if defined(DMA2) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) != RESET) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != RESET) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET) +#if defined(RNG) +#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) != RESET) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) != RESET) +#endif /* AES */ + +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == RESET) +#if defined(DMA2) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN) == RESET) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == RESET) +#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET) +#if defined(RNG) +#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_RNGEN) == RESET) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN) == RESET) +#endif /* AES */ +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Clock_Enabled_Disabled_Status IOPORT Clock Enabled or Disabled Status + * @brief Check whether the IO Port clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != RESET) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) != RESET) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) != RESET) + + +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == RESET) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN) == RESET) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enabled_Disabled_Status APB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#if defined(TIM2) +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U) +#if defined(TIM4) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) != 0U) +#endif /* TIM4 */ +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) != 0U) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) != 0U) +#if defined(CRS) +#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U) +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U) +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) != 0U) +#endif /* FDCAN1 || FDCAN2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) != 0U) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) != 0U) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) != 0U) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) != 0U) +#define __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) != 0U) +#if defined(USART5) +#define __HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) != 0U) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) != 0U) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)!= 0U) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)!= 0U) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) != 0U) +#if defined(I2C3) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) != 0U) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) != 0U) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) != 0U) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) != 0U) +#endif /* UCPD2 */ +#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) != 0U) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) != 0U) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) != 0U) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) != 0U) +#endif /* LPTIM1 */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U) +#if defined(TIM4) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) == 0U) +#endif /* TIM4 */ +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) == 0U) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) == 0U) +#if defined(CRS) +#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U) +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U) +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) == 0U) +#endif /* FDCAN1 || FDCAN2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) == 0U) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) == 0U) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) == 0U) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) == 0U) +#define __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) == 0U) +#if defined(USART5) +#define __HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) == 0U) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) == 0U) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)== 0U) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)== 0U) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) == 0U) +#if defined(I2C3) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) == 0U) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) == 0U) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) == 0U) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) == 0U) +#endif /* UCPD2 */ +#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) == 0U) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) == 0U) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) == 0U) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) == 0U) +#endif /* LPTIM1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enabled_Disabled_Status APB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock is enabled or not. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U) +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) != 0U) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) != 0U) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) != 0U) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) != 0U) +#define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U) + +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U) +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) == 0U) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM15EN) == 0U) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) == 0U) +#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) == 0U) +#define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB_FORCE_RESET() WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU) +#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) +#if defined(DMA2) +#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) +#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) +#if defined(RNG) +#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST) +#endif /* AES */ + +#define __HAL_RCC_AHB_RELEASE_RESET() WRITE_REG(RCC->AHBRSTR, 0x00000000U) +#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) +#if defined(DMA2) +#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA2RST) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) +#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) +#if defined(RNG) +#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_RNGRST) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_AESRST) +#endif /* AES */ +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Force Release Reset + * @brief Force or release IO Port reset. + * @{ + */ +#define __HAL_RCC_IOP_FORCE_RESET() WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU) +#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) +#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) +#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) + +#define __HAL_RCC_IOP_RELEASE_RESET() WRITE_REG(RCC->IOPRSTR, 0x00000000U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) +#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) +#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOERST) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU) + +#if defined(TIM2) +#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) +#if defined(TIM4) +#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST) +#endif /* TIM4 */ +#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST) +#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST) +#if defined(CRS) +#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) +#endif /* CRS */ +#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) +#if defined(SPI3) +#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) +#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST) +#define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST) +#if defined(USART5) +#define __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) +#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) +#if defined(I2C3) +#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST) +#endif /* FDCAN1 || FDCAN2 */ +#define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST) +#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) +#if defined(DAC1) +#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST) +#endif /* LPTIM1 */ +#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APBRSTR1, 0x00000000U) +#if defined(TIM2) +#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM2RST) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) +#if defined(TIM4) +#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM4RST) +#endif /* TIM4 */ +#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM6RST) +#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM7RST) +#if defined(CRS) +#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CRSRST) +#endif /* CRS */ +#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI2RST) +#if defined(SPI3) +#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_SPI3RST) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) +#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART3RST) +#define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART4RST) +#if defined(USART5) +#define __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART5RST) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART6RST) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART1RST) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPUART2RST) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) +#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C2RST) +#if defined(I2C3) +#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C3RST) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_CECRST) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD1RST) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_UCPD2RST) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USBRST) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_FDCANRST) +#endif /* FDCAN1 || FDCAN2 */ +#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST) +#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) +#if defined(DAC1) +#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DAC1RST) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM2RST) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_LPTIM1RST) +#endif /* LPTIM1 */ +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) +#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) +#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) +#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) +#define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) +#if defined(TIM15) +#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) +#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) +#define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) + +#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APBRSTR2, 0x00U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) +#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) +#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) +#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) +#define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) +#if defined(TIM15) +#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM15RST) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) +#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) +#define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripherals Clock Sleep Enable Disable + * @brief Enable or disable the AHB peripherals clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) +#if defined(DMA2) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) +#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) +#if defined(RNG) +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) +#endif /* AES */ +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) +#if defined(DMA2) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) +#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) +#if defined(RNG) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) +#endif /* AES */ + +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Clock Sleep Enable Disable + * @brief Enable or disable the IOPORT clock during Low Power (Sleep) mode. + * @note IOPORT clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) +#endif /* TIM4 */ +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) +#if defined(CRS) +#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) +#if defined(SPI3) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) +#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) +#if defined(USART5) +#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) +#if defined(I2C3) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) +#endif /* FDCAN1 || FDCAN2 */ +#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) +#if defined(DAC1) +#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) +#endif /* LPTIM1 */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) +#if defined(TIM4) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) +#endif /* TIM4 */ +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) +#if defined(CRS) +#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) +#if defined(SPI3) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) +#endif /* TIM2 */ +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) +#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) +#if defined(USART5) +#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) +#if defined(I2C3) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) +#endif /* FDCAN1) || FDCAN2 */ +#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) +#if defined(DAC1) +#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) +#endif /* LPTIM1 */ +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) +#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) +#if defined(TIM15) +#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) +#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Sleep_Enabled_Disabled_Status AHB Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET) +#if defined(DMA2) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) != RESET) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)!= RESET) +#define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET) +#if defined(RNG) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) != RESET) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) != RESET) +#endif /* AES */ +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET) +#if defined(DMA2) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA2SMEN) == RESET) +#endif /* DMA2 */ +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) == RESET) +#define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET) +#if defined(RNG) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_RNGSMEN) == RESET) +#endif /* RNG */ +#if defined(AES) +#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_AESSMEN) == RESET) +#endif /* AES */ + +/** + * @} + */ + +/** @defgroup RCC_IOPORT_Clock_Sleep_Enabled_Disabled_Status IOPORT Clock Sleep Enabled or Disabled Status + * @brief Check whether the IOPORT clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)!= RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)!= RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)!= RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)!= RESET) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN)!= RESET) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)!= RESET) + + + +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET) +#if defined(GPIOE) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOESMEN) == RESET) +#endif /* GPIOE */ +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) == RESET) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enabled_Disabled_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) != RESET) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) != RESET) +#if defined(TIM4) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) != RESET) +#endif /* TIM4 */ +#if defined(TIM6) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) != RESET) +#endif /* TIM6 */ +#if defined(TIM7) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) != RESET) +#endif /* TIM7 */ +#if defined(CRS) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) != RESET) +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) != RESET) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) != RESET) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) != RESET) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) != RESET) +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) != RESET) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) != RESET) +#endif /* USART4 */ +#if defined(USART5) +#define __HAL_RCC_USART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) != RESET) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) != RESET) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)!= RESET) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)!= RESET) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) != RESET) +#if defined(I2C3) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) != RESET) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) != RESET) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) != RESET) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) != RESET) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) != RESET) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) != RESET) +#endif /* FDCAN1 || FDCAN2 */ +#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) != RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) != RESET) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) != RESET) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) != RESET) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) != RESET) +#endif /* LPTIM1 */ +#if defined(TIM2) +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM2SMEN) == RESET) +#endif /* TIM2 */ +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) == RESET) +#if defined(TIM4) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM4SMEN) == RESET) +#endif /* TIM4 */ +#if defined(TIM6) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM6SMEN) == RESET) +#endif /* TIM6 */ +#if defined(TIM7) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM7SMEN) == RESET) +#endif /* TIM7 */ +#if defined(CRS) +#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CRSSMEN) == RESET) +#endif /* CRS */ +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) == RESET) +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI2SMEN) == RESET) +#if defined(SPI3) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_SPI3SMEN) == RESET) +#endif /* SPI3 */ +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) == RESET) +#if defined(USART3) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART3SMEN) == RESET) +#endif /* USART3 */ +#if defined(USART4) +#define __HAL_RCC_USART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART4SMEN) == RESET) +#endif /* USART4 */ +#if defined(USART5) +#define __HAL_RCC_USART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART5SMEN) == RESET) +#endif /* USART5 */ +#if defined(USART6) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART6SMEN) == RESET) +#endif /* USART6 */ +#if defined(LPUART1) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART1SMEN)== RESET) +#endif /* LPUART1 */ +#if defined(LPUART2) +#define __HAL_RCC_LPUART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPUART2SMEN)== RESET) +#endif /* LPUART2 */ +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C2SMEN) == RESET) +#if defined(I2C3) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C3SMEN) == RESET) +#endif /* I2C3 */ +#if defined(CEC) +#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_CECSMEN) == RESET) +#endif /* CEC */ +#if defined(UCPD1) +#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD1SMEN) == RESET) +#endif /* UCPD1 */ +#if defined(UCPD2) +#define __HAL_RCC_UCPD2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_UCPD2SMEN) == RESET) +#endif /* UCPD2 */ +#if defined(STM32G0B0xx) || defined(STM32G0B1xx) || defined (STM32G0C1xx) +#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USBSMEN) == RESET) +#endif /* STM32G0B0xx || STM32G0B1xx || STM32G0C1xx */ +#if defined(FDCAN1) || defined(FDCAN2) +#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_FDCANSMEN) == RESET) +#endif /* FDCAN1 || FDCAN2 */ +#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) == RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) == RESET) +#if defined(DAC1) +#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DAC1SMEN) == RESET) +#endif /* DAC1 */ +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM2SMEN) == RESET) +#endif /* LPTIM2 */ +#if defined(LPTIM1) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_LPTIM1SMEN) == RESET) +#endif /* LPTIM1 */ + +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enabled_Disabled_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) != RESET) +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) != RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) != RESET) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) != RESET) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) != RESET) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) != RESET) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) != RESET) + + +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) == RESET) +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) == RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) == RESET) +#if defined(TIM15) +#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM15SMEN) == RESET) +#endif /* TIM15 */ +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) == RESET) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) == RESET) +#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) == RESET) + + +/** + * @} + */ + +/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset + * @{ + */ + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + * @retval None + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) + +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note As the RTC is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the RTC + * (to be done once after reset). + * @note These macros must be used after the RTC clock source was selected. + * @retval None + */ +#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) + +/** + * @} + */ + +/** @defgroup RCC_Clock_Configuration RCC Clock Configuration + * @{ + */ + +/** @brief Macros to enable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macros to disable the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 127. + * @retval None + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) + +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI startup time. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) + +#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) + +/** @brief Macro to configure the HSISYS clock. + * @param __HSIDIV__ specifies the HSI16 division factor. + * This parameter can be one of the following values: + * @arg @ref RCC_HSI_DIV1 HSI clock source is divided by 1 + * @arg @ref RCC_HSI_DIV2 HSI clock source is divided by 2 + * @arg @ref RCC_HSI_DIV4 HSI clock source is divided by 4 + * @arg @ref RCC_HSI_DIV8 HSI clock source is divided by 8 + * @arg @ref RCC_HSI_DIV16 HSI clock source is divided by 16 + * @arg @ref RCC_HSI_DIV32 HSI clock source is divided by 32 + * @arg @ref RCC_HSI_DIV64 HSI clock source is divided by 64 + * @arg @ref RCC_HSI_DIV128 HSI clock source is divided by 128 + */ +#define __HAL_RCC_HSI_CONFIG(__HSIDIV__) \ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__)) + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) + +#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. + * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. + * @retval None + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) do { \ + if((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0U) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + * @retval None + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0U) + +#if defined(RCC_HSI48_SUPPORT) +/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @note After enabling the HSI48, the application software should wait on HSI48RDY + * flag to be set indicating that HSI48 clock is stable. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) + +#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) + +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +/** @addtogroup RCC_RTC_Clock_Configuration + * @{ + */ + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__ specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + * @retval None + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ + MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + + +/** @brief Macro to get the RTC clock source. + * @retval The returned value can be one of the following: + * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + */ +#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + * @retval None + */ + +/** + * @} + */ + +/** @addtogroup RCC_Clock_Configuration + * @{ + */ + +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) + +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to configure the PLL clock source. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * @retval None + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) + +/** @brief Macro to configure the PLL multiplication factor. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a value of RCC_PLLM_Clock_Divider. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency + * of 16 MHz to limit PLL jitter. + * @retval None + * + */ +#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) + +/** + * @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry + * + * @param __PLLM__ specifies the division factor for PLL VCO input clock. + * This parameter must be a value of RCC_PLLM_Clock_Divider. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency + * of 16 MHz to limit PLL jitter. + * + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock. + * This parameter must be a number between 8 and 86. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 64 and 344 MHz. + * + * @param __PLLP__ specifies the division factor for ADC clock. + * This parameter must be a value of @ref RCC_PLLP_Clock_Divider. + * + * @param __PLLQ__ specifies the division factor for RBG & HS Timers clocks.(1) + * This parameter must be a value of @ref RCC_PLLQ_Clock_Divider + * @note (1)__PLLQ__ parameter availability depends on devices + * @note If the USB FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the RNG needs a frequency lower than or equal to 48 MHz to work + * correctly. + * + * @param __PLLR__ specifies the division factor for the main system clock. + * This parameter must be a value of RCC_PLLR_Clock_Divider + * @note You have to set the PLL parameters correctly to not exceed 64MHZ. + * @retval None + */ +#if defined(RCC_PLLQ_SUPPORT) +#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ + MODIFY_REG(RCC->PLLCFGR, \ + (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ + RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR), \ + ((uint32_t) (__PLLSOURCE__) | \ + (uint32_t) (__PLLM__) | \ + (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + (uint32_t) (__PLLP__) | \ + (uint32_t) (__PLLQ__) | \ + (uint32_t) (__PLLR__))) +#else +#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLR__ ) \ + MODIFY_REG(RCC->PLLCFGR, \ + (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ + RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLR), \ + ((uint32_t) (__PLLSOURCE__) | \ + (uint32_t) (__PLLM__) | \ + (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + (uint32_t) (__PLLP__) | \ + (uint32_t) (__PLLR__))) +#endif /* RCC_PLLQ_SUPPORT */ +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source. + * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) + +/** + * @brief Enable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK) + * @note Enabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK(*) can be done at anytime + * without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot + * be stopped if used as System Clock. + * @note (*) RCC_PLLQCLK availability depends on devices + * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. + * This parameter can be one or a combination of the following values: + * @arg @ref RCC_PLLPCLK This clock is used to generate the clock for the ADC. + * @if defined(STM32G081xx) + * @arg @ref RCC_PLLQCLK This Clock is used to generate the clock for the High Speed Timers, + * and the random analog generator (<=48 MHz). + * @endif + * @arg @ref RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz) + * @retval None + */ +#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) + +/** + * @brief Disable each clock output (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK) + * @note Disabling clock outputs RCC_PLLPCLK and RCC_PLLQCLK(*) can be done at anytime + * without the need to stop the PLL in order to save power. But RCC_PLLRCLK cannot + * be stopped if used as System Clock. + * @note (*) RCC_PLLQCLK availability depends on devices + * @param __PLLCLOCKOUT__ specifies the PLL clock to be output. + * This parameter can be one or a combination of the following values: + * @arg @ref RCC_PLLPCLK This clock may be used to generate the clock for the ADC, I2S1. + * @if defined(STM32G081xx) + * @arg @ref RCC_PLLQCLK This Clock may be used to generate the clock for the High Speed Timers, + * and RNG (<=48 MHz). + * @endif + * @arg @ref RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz) + * @retval None + */ +#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) + +/** + * @brief Get clock output enable status (RCC_PLLRCLK, RCC_PLLQCLK(*), RCC_PLLPCLK) + * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked. + * This parameter can be one of the following values: + * @arg RCC_PLLPCLK This clock may be used to generate the clock for ADC, I2S1. + * @if defined(STM32G081xx) + * @arg RCC_PLLQCLK This Clock may be used to generate the clock for the HS Timers, + * the RNG (<=48 MHz). + * @endif + * @arg @ref RCC_PLLRCLK This Clock is used to generate the high speed system clock (up to 64MHz) + * @retval SET / RESET + * @note (*) RCC_PLLQCLK availability depends on devices + */ +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_LSI LSI oscillator is used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_LSE LSE oscillator is used as system clock source. + * @retval None + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSI LSI used as system clock source. + * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSE LSE used as system clock source. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) + +/** @brief Macro to configure the Microcontroller output clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLPCLK PLLP output clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLQCLK PLLQ output clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO source + @if STM32G0C1xx + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 + @endif + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 + * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 128 + * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 256 + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +#if defined(RCC_MCO2_SUPPORT) +/** @brief Macro to configure the Microcontroller output clock 2. + * @param __MCOCLKSOURCE__ specifies the MCO2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled + * @arg @ref RCC_MCO2SOURCE_SYSCLK System clock selected as MCO source + * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 sourcee + * @arg @ref RCC_MCO2SOURCE_PLLCLK Main PLL clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_PLLPCLK PLLP output clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_PLLQCLK PLLQ output clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_RTCCLK RTC clock selected as MCO2 source + * @arg @ref RCC_MCO2SOURCE_RTC_WKUP RTC_WKUP clock selected as MCO2 source + @if STM32G0C1xx + * @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices with HSI48 + @endif + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO2DIV_1 MCO2 clock source is divided by 1 + * @arg @ref RCC_MCO2DIV_2 MCO2 clock source is divided by 2 + * @arg @ref RCC_MCO2DIV_4 MCO2 clock source is divided by 4 + * @arg @ref RCC_MCO2DIV_8 MCO2 clock source is divided by 8 + * @arg @ref RCC_MCO2DIV_16 MCO2 clock source is divided by 16 + * @arg @ref RCC_MCO2DIV_32 MCO2 clock source is divided by 32 + * @arg @ref RCC_MCO2DIV_64 MCO2 clock source is divided by 64 + * @arg @ref RCC_MCO2DIV_128 MCO2 clock source is divided by 128 + * @arg @ref RCC_MCO2DIV_256 MCO2 clock source is divided by 256 + * @arg @ref RCC_MCO2DIV_512 MCO2 clock source is divided by 512 + * @arg @ref RCC_MCO2DIV_1024 MCO2 clock source is divided by 1024 + */ +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) +#endif /* RCC_MCO2_SUPPORT */ + +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + @if STM32G0C1xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + @endif + * @retval None + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Disable RCC interrupt. + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + @if STM32G0C1xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + @endif + * @retval None + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** @brief Clear RCC interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + * @arg @ref RCC_IT_CSS HSE Clock security system interrupt + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt + @if STM32G0C1xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + @endif + * @retval None + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) + +/** @brief Check whether the RCC interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSIRDY LSI ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt + * @arg @ref RCC_IT_CSS HSE Clock security system interrupt + * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt + @if STM32G0C1xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + @endif + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PWRRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + * @retval None + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check whether the selected RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready + * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready + * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection + * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready + @if STM32G0C1xx + * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 + @endif + * @arg @ref RCC_FLAG_PWRRST BOR or POR/PDR reset + * @arg @ref RCC_FLAG_OBLRST OBLRST reset + * @arg @ref RCC_FLAG_PINRST Pin reset + * @arg @ref RCC_FLAG_SFTRST Software reset + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset + * @arg @ref RCC_FLAG_LPWRRST Low Power reset + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#if defined(RCC_HSI48_SUPPORT) +#define __HAL_RCC_GET_FLAG(__FLAG__) \ + (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ + ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \ + ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \ + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) +#else +#define __HAL_RCC_GET_FLAG(__FLAG__) \ + (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ + ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \ + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1U : 0U) +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extended module */ +#include "stm32g0xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_EnableLSECSS(void); +void HAL_RCC_DisableLSECSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); +/* LSE & HSE CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +void HAL_RCC_LSECSSCallback(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h (revision 3) @@ -0,0 +1,1593 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_RCC_EX_H +#define STM32G0xx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ +#if defined(RCC_CCIPR_USART2SEL) + uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ +#endif /* RCC_CCIPR_USART2SEL */ + +#if defined(RCC_CCIPR_USART3SEL) + uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(LPUART1) + uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source + This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ +#endif /* LPUART1 */ + +#if defined(LPUART2) + uint32_t Lpuart2ClockSelection; /*!< Specifies LPUART2 clock source + This parameter can be a value of @ref RCCEx_LPUART2_Clock_Source */ +#endif /* LPUART2 */ + + uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source + This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ + +#if defined(RCC_CCIPR_I2C2SEL) + uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ +#endif /* RCC_CCIPR_I2C2SEL */ + + uint32_t I2s1ClockSelection; /*!< Specifies I2S1 clock source + This parameter can be a value of @ref RCCEx_I2S1_Clock_Source */ +#if defined(RCC_CCIPR2_I2S2SEL) + uint32_t I2s2ClockSelection; /*!< Specifies I2S2 clock source + This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */ +#endif /* RCC_CCIPR2_I2S2SEL */ +#if defined(RCC_CCIPR_LPTIM1SEL) + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ +#endif /* RCC_CCIPR_LPTIM1SEL */ +#if defined(RCC_CCIPR_LPTIM2SEL) + uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source + This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ +#endif /* RCC_CCIPR_LPTIM2SEL */ +#if defined(RNG) + uint32_t RngClockSelection; /*!< Specifies RNG clock source + This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ +#endif /* RNG */ + uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source + This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ +#if defined(CEC) + uint32_t CecClockSelection; /*!< Specifies CEC Clock clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ +#endif /* CEC */ +#if defined(RCC_CCIPR_TIM1SEL) + uint32_t Tim1ClockSelection; /*!< Specifies TIM1 Clock clock source + This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ +#endif /* RCC_CCIPR_TIM1SEL */ +#if defined(RCC_CCIPR_TIM15SEL) + uint32_t Tim15ClockSelection; /*!< Specifies TIM15 Clock clock source + This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ +#endif /* RCC_CCIPR_TIM15SEL */ + uint32_t RTCClockSelection; /*!< Specifies RTC clock source. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ +#if defined(RCC_CCIPR2_USBSEL) + uint32_t UsbClockSelection; /*!< Specifies USB Clock clock source + This parameter can be a value of @ref RCCEx_USB_Clock_Source */ +#endif /* RCC_CCIPR2_USBSEL */ +#if defined(FDCAN1) || defined(FDCAN2) + uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source + This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */ +#endif /* FDCAN1 || FDCAN2 */ +} RCC_PeriphCLKInitTypeDef; + +#if defined(CRS) + +/** + * @brief RCC_CRS Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. + This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ + + uint32_t Source; /*!< Specifies the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ + + uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. + This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ + + uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event. + It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) + This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/ + + uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. + This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */ + + uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. + This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */ + +} RCC_CRSInitTypeDef; + +/** + * @brief RCC_CRS Synchronization structure definition + */ +typedef struct +{ + uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. + This parameter must be a number between 0 and 0x7F */ + + uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter + value latched in the time of the last SYNC event. + This parameter must be a number between 0 and 0xFFFF */ + + uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the + frequency error counter latched in the time of the last SYNC event. + It shows whether the actual frequency is below or above the target. + This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ + +} RCC_CRSSynchroInfoTypeDef; + +#endif /* CRS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source + * @{ + */ +#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ +/** + * @} + */ + +/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_USART1 0x00000001U +#if defined(RCC_CCIPR_USART2SEL) +#define RCC_PERIPHCLK_USART2 0x00000002U +#endif /* RCC_CCIPR_USART2SEL */ +#if defined(RCC_CCIPR_USART3SEL) +#define RCC_PERIPHCLK_USART3 0x00000004U +#endif /* RCC_CCIPR_USART3SEL */ +#if defined(LPUART1) +#define RCC_PERIPHCLK_LPUART1 0x00000010U +#endif /* LPUART1 */ +#define RCC_PERIPHCLK_I2C1 0x00000020U +#if defined(RCC_CCIPR_I2C2SEL) +#define RCC_PERIPHCLK_I2C2 0x00000040U +#endif /* RCC_CCIPR_I2C2SEL */ +#if defined(RCC_CCIPR_LPTIM1SEL) +#define RCC_PERIPHCLK_LPTIM1 0x00000200U +#endif /* RCC_CCIPR_LPTIM1SEL */ +#if defined(RCC_CCIPR_LPTIM2SEL) +#define RCC_PERIPHCLK_LPTIM2 0x00000400U +#endif /* RCC_CCIPR_LPTIM2SEL */ +#define RCC_PERIPHCLK_I2S1 0x00000800U +#if defined(LPUART2) +#define RCC_PERIPHCLK_LPUART2 0x00001000U +#endif /* LPUART2 */ +#if defined(RCC_CCIPR2_I2S2SEL) +#define RCC_PERIPHCLK_I2S2 0x00002000U +#endif /* RCC_CCIPR2_I2S2SEL */ +#define RCC_PERIPHCLK_ADC 0x00004000U +#define RCC_PERIPHCLK_RTC 0x00020000U +#if defined(RCC_CCIPR_RNGSEL) +#define RCC_PERIPHCLK_RNG 0x00040000U +#endif /* RCC_CCIPR_RNGSEL */ +#if defined(RCC_CCIPR_CECSEL) +#define RCC_PERIPHCLK_CEC 0x00080000U +#endif /* RCC_CCIPR_CECSEL */ +#if defined(RCC_CCIPR_TIM1SEL) +#define RCC_PERIPHCLK_TIM1 0x00200000U +#endif /* RCC_CCIPR_TIM1SEL */ +#if defined(RCC_CCIPR_TIM15SEL) +#define RCC_PERIPHCLK_TIM15 0x00400000U +#endif /* RCC_CCIPR_TIM15SEL */ +#if defined(RCC_CCIPR2_USBSEL) +#define RCC_PERIPHCLK_USB 0x01000000U +#endif /* RCC_CCIPR2_USBSEL */ +#if defined(FDCAN1) || defined(FDCAN2) +#define RCC_PERIPHCLK_FDCAN 0x02000000U +#endif /* FDCAN1 || FDCAN2 */ +/** + * @} + */ + + +/** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as USART1 clock */ +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 /*!< SYSCLK clock selected as USART1 clock */ +#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 /*!< HSI clock selected as USART1 clock */ +#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) /*!< LSE clock selected as USART1 clock */ +/** + * @} + */ + +#if defined(RCC_CCIPR_USART2SEL) +/** @defgroup RCCEx_USART2_Clock_Source RCC USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as USART2 clock */ +#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 /*!< SYSCLK clock selected as USART2 clock */ +#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 /*!< HSI clock selected as USART2 clock */ +#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) /*!< LSE clock selected as USART2 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR_USART2SEL */ +#if defined(RCC_CCIPR_USART3SEL) +/** @defgroup RCCEx_USART3_Clock_Source RCC USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as USART3 clock */ +#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 /*!< SYSCLK clock selected as USART3 clock */ +#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 /*!< HSI clock selected as USART3 clock */ +#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) /*!< LSE clock selected as USART3 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(LPUART1) +/** @defgroup RCCEx_LPUART1_Clock_Source RCC LPUART1 Clock Source + * @{ + */ +#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as LPUART1 clock */ +#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock selected as LPUART1 clock */ +#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock selected as LPUART1 clock */ +#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) /*!< LSE clock selected as LPUART1 clock */ +/** + * @} + */ +#endif /* LPUART1 */ + +#if defined(LPUART2) +/** @defgroup RCCEx_LPUART2_Clock_Source RCC LPUART2 Clock Source + * @{ + */ +#define RCC_LPUART2CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as LPUART2 clock */ +#define RCC_LPUART2CLKSOURCE_SYSCLK RCC_CCIPR_LPUART2SEL_0 /*!< SYSCLK clock selected as LPUART2 clock */ +#define RCC_LPUART2CLKSOURCE_HSI RCC_CCIPR_LPUART2SEL_1 /*!< HSI clock selected as LPUART2 clock */ +#define RCC_LPUART2CLKSOURCE_LSE (RCC_CCIPR_LPUART2SEL_0 | RCC_CCIPR_LPUART2SEL_1) /*!< LSE clock selected as LPUART2 clock */ +/** + * @} + */ +#endif /* LPUART2 */ + +/** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as I2C1 clock */ +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 /*!< SYSCLK clock selected as I2C1 clock */ +#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 /*!< HSI clock selected as I2C1 clock */ +/** + * @} + */ + +#if defined(RCC_CCIPR_I2C2SEL) +/** @defgroup RCCEx_I2C2_Clock_Source RCC I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as I2C2 clock */ +#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 /*!< SYSCLK clock selected as I2C2 clock */ +#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 /*!< HSI clock selected as I2C2 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR_I2C2SEL */ + +/** @defgroup RCCEx_I2S1_Clock_Source RCC I2S1 Clock Source + * @{ + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define RCC_I2S1CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_PLL RCC_CCIPR2_I2S1SEL_0 /*!< PLL "P" selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_HSI RCC_CCIPR2_I2S1SEL_1 /*!< HSI clock selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_EXT RCC_CCIPR2_I2S1SEL /*!< External I2S clock source selected as I2S1 clock */ +#else +#define RCC_I2S1CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_PLL RCC_CCIPR_I2S1SEL_0 /*!< PLL "P" selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_HSI RCC_CCIPR_I2S1SEL_1 /*!< HSI clock selected as I2S1 clock */ +#define RCC_I2S1CLKSOURCE_EXT RCC_CCIPR_I2S1SEL /*!< External I2S clock source selected as I2S1 clock */ +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +/** + * @} + */ + +#if defined(RCC_CCIPR2_I2S2SEL) +/** @defgroup RCCEx_I2S2_Clock_Source RCC I2S2 Clock Source + * @{ + */ +#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock selected as I2S2 clock */ +#define RCC_I2S2CLKSOURCE_PLL RCC_CCIPR2_I2S2SEL_0 /*!< PLL "P" selected as I2S2 clock */ +#define RCC_I2S2CLKSOURCE_HSI RCC_CCIPR2_I2S2SEL_1 /*!< HSI clock selected as I2S2 clock */ +#define RCC_I2S2CLKSOURCE_EXT RCC_CCIPR2_I2S2SEL /*!< External I2S clock source selected as I2S2 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(RCC_CCIPR_LPTIM1SEL) +/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as LPTimer 1 clock */ +#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 /*!< LSI clock selected as LPTimer 1 clock */ +#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 /*!< HSI clock selected as LPTimer 1 clock */ +#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL /*!< LSE clock selected as LPTimer 1 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR_LPTIM1SEL */ + +#if defined(RCC_CCIPR_LPTIM2SEL) +/** @defgroup RCCEx_LPTIM2_Clock_Source RCC LPTIM2 Clock Source + * @{ + */ +#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as LPTimer 2 clock */ +#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 /*!< LSI clock selected as LPTimer 2 clock */ +#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 /*!< HSI clock selected as LPTimer 2 clock */ +#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL /*!< LSE clock selected as LPTimer 2 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR_LPTIM2SEL */ + +#if defined(RNG) +/** @defgroup RCCEx_RNG_Clock_Source RCC RNG Clock Source + * @{ + */ +#define RCC_RNGCLKSOURCE_NONE 0x00000000U /*!< No clock selected */ +#define RCC_RNGCLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0 /*!< HSI oscillator divided by 8 clock selected as RNG clock */ +#define RCC_RNGCLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1 /*!< SYSCLK selected as RNG clock */ +#define RCC_RNGCLKSOURCE_PLL (RCC_CCIPR_RNGSEL_0|RCC_CCIPR_RNGSEL_1) /*!< PLL "Q" selected as RNG clock */ + +/** + * @} + */ + +/** @defgroup RCCEx_RNG_Division_factor RCC RNG Division factor + * @{ + */ +#define RCC_RNGCLK_DIV1 0x00000000U /*!< RNG clock not divided */ +#define RCC_RNGCLK_DIV2 RCC_CCIPR_RNGDIV_0 /*!< RNG clock divided by 2 */ +#define RCC_RNGCLK_DIV4 RCC_CCIPR_RNGDIV_1 /*!< RNG clock divided by 4 */ +#define RCC_RNGCLK_DIV8 (RCC_CCIPR_RNGDIV_0|RCC_CCIPR_RNGDIV_1) /*!< RNG clock divided by 8 */ + +/** + * @} + */ +#endif /* RNG */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @defgroup RCCEx_FDCAN_Clock_Source RCC FDCAN Clock Source + * @{ + */ +#define RCC_FDCANCLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as FDCAN clock */ +#define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0 /*!< PLL "Q" selected as FDCAN clock */ +#define RCC_FDCANCLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1 /*!< HSE oscillator clock selected as FDCAN clock */ + +/** + * @} + */ +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(RCC_CCIPR2_USBSEL) +/** @defgroup RCCEx_USB_Clock_Source USB Clock Source + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) +#define RCC_USBCLKSOURCE_HSI48 0x00000000U /*!< HSI48 oscillator clock selected as USB clock */ +#endif /* RCC_HSI48_SUPPORT */ +#define RCC_USBCLKSOURCE_HSE RCC_CCIPR2_USBSEL_0 /*!< HSE oscillator clock selected as USB clock */ +#define RCC_USBCLKSOURCE_PLL RCC_CCIPR2_USBSEL_1 /*!< PLL "Q" selected as USB clock */ +/** + * @} + */ +#endif /* RCC_CCIPR2_USBSEL */ + +/** @defgroup RCCEx_ADC_Clock_Source RCC ADC Clock Source + * @{ + */ + +#define RCC_ADCCLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */ +#define RCC_ADCCLKSOURCE_PLLADC RCC_CCIPR_ADCSEL_0 /*!< PLL "P" (PLLADC) used as ADC clock */ +#define RCC_ADCCLKSOURCE_HSI RCC_CCIPR_ADCSEL_1 /*!< HSI used as ADC clock */ +/** + * @} + */ + +#if defined(CEC) +/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as default CEC clock */ +#define RCC_CECCLKSOURCE_LSE RCC_CCIPR_CECSEL /*!< LSE oscillator clock used as CEC clock */ +/** + * @} + */ +#endif /* CEC */ + +#if defined(RCC_CCIPR_TIM1SEL) +/** @defgroup RCCEx_TIM1_Clock_Source RCC TIM1 Clock Source + * @{ + */ +#define RCC_TIM1CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as Timer 1 clock */ +#define RCC_TIM1CLKSOURCE_PLL RCC_CCIPR_TIM1SEL /*!< PLL "Q" clock selected as Timer 1 clock */ +/** + * @} + */ +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) +/** @defgroup RCCEx_TIM15_Clock_Source RCC TIM15 Clock Source + * @{ + */ +#define RCC_TIM15CLKSOURCE_PCLK1 0x00000000U /*!< APB clock selected as Timer 15 clock */ +#define RCC_TIM15CLKSOURCE_PLL RCC_CCIPR_TIM15SEL /*!< PLL "Q" clock selected as Timer 15 clock */ + +/** + * @} + */ +#endif /* RCC_CCIPR_TIM15SEL */ + +#if defined(CRS) + +/** @defgroup RCCEx_CRS_Status RCCEx CRS Status + * @{ + */ +#define RCC_CRS_NONE 0x00000000U +#define RCC_CRS_TIMEOUT 0x00000001U +#define RCC_CRS_SYNCOK 0x00000002U +#define RCC_CRS_SYNCWARN 0x00000004U +#define RCC_CRS_SYNCERR 0x00000008U +#define RCC_CRS_SYNCMISS 0x00000010U +#define RCC_CRS_TRIMOVF 0x00000020U +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource + * @{ + */ +#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider + * @{ + */ +#define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */ +#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity + * @{ + */ +#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ +#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault + * @{ + */ +#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds + to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault + * @{ + */ +#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault + * @{ + */ +#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /*!< The default value is 64, which corresponds to the middle of the trimming interval. + The trimming step is specified in the product datasheet. A higher TRIM value + corresponds to a higher output frequency */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection + * @{ + */ +#define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ +#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources + * @{ + */ +#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */ +#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */ +#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */ +#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */ +#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */ +#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */ +#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags + * @{ + */ +#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */ +#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */ +#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */ +#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */ +#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ +#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) + +#if defined(RCC_CCIPR_I2C2SEL) +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * + * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock + * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))) +#endif /* RCC_CCIPR_I2C2SEL */ + +/** @brief Macro to configure the I2S1 clock (I2S1CLK). + * + * @param __I2S1_CLKSOURCE__ specifies the I2S1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_PLL PLLP Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_HSI HSI Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) +#else +#define __HAL_RCC_I2S1_CONFIG(__I2S1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, (uint32_t)(__I2S1_CLKSOURCE__)) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +/** @brief Macro to get the I2S1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2S1CLKSOURCE_SYSCLK System Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_PLL PLLP Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_HSI HSI Clock selected as I2S1 clock + * @arg @ref RCC_I2S1CLKSOURCE_EXT External clock selected as I2S1 clock + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S1SEL))) +#else +#define __HAL_RCC_GET_I2S1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S1SEL))) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(RCC_CCIPR2_I2S2SEL) +/** @brief Macro to configure the I2S2 clock (I2S2CLK). + * + * @param __I2S2_CLKSOURCE__ specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK System Clock selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_PLL PLLP Clock selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_HSI HSI Clock selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_EXT External clock selected as I2S2 clock + */ +#define __HAL_RCC_I2S2_CONFIG(__I2S2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL, (uint32_t)(__I2S2_CLKSOURCE__)) + +/** @brief Macro to get the I2S2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK System Clock selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_PLL PLLP Clock selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_HSI HSI Clock selected as I2S2 clock + * @arg @ref RCC_I2S2CLKSOURCE_EXT External clock selected as I2S2 clock + */ +#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2S2SEL))) +#endif /* RCC_CCIPR2_I2S2SEL */ + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) + +#if defined(RCC_CCIPR_USART2SEL) +/** @brief Macro to configure the USART2 clock (USART2CLK). + * + * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) +#endif /* RCC_CCIPR_USART2SEL */ + +#if defined(RCC_CCIPR_USART3SEL) +/** @brief Macro to configure the USART3 clock (USART3CLK). + * + * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) + +/** @brief Macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock + * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))) +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(RCC_CCIPR_LPUART1SEL) +/** @brief Macro to configure the LPUART1 clock (LPUART1CLK). + * + * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) + +/** @brief Macro to get the LPUART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) +#endif /* RCC_CCIPR_LPUART1SEL */ + +#if defined(RCC_CCIPR_LPUART2SEL) +/** @brief Macro to configure the LPUART2 clock (LPUART2CLK). + * + * @param __LPUART2_CLKSOURCE__ specifies the LPUART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPUART2CLKSOURCE_PCLK1 PCLK1 selected as LPUART2 clock + * @arg @ref RCC_LPUART2CLKSOURCE_HSI HSI selected as LPUART2 clock + * @arg @ref RCC_LPUART2CLKSOURCE_SYSCLK System Clock selected as LPUART2 clock + * @arg @ref RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock + */ +#define __HAL_RCC_LPUART2_CONFIG(__LPUART2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART2SEL, (uint32_t)(__LPUART2_CLKSOURCE__)) + +/** @brief Macro to get the LPUART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPUART2CLKSOURCE_PCLK1 PCLK1 selected as LPUART2 clock + * @arg @ref RCC_LPUART2CLKSOURCE_HSI HSI selected as LPUART2 clock + * @arg @ref RCC_LPUART2CLKSOURCE_SYSCLK System Clock selected as LPUART2 clock + * @arg @ref RCC_LPUART2CLKSOURCE_LSE LSE selected as LPUART2 clock + */ +#define __HAL_RCC_GET_LPUART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART2SEL))) +#endif /* RCC_CCIPR_LPUART2SEL */ + +#if defined(RCC_CCIPR_LPTIM1SEL) +/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). + * + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) +#endif /* RCC_CCIPR_LPTIM1SEL */ + +#if defined(RCC_CCIPR_LPTIM2SEL) +/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). + * + * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock + */ +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock + */ +#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))) +#endif /* RCC_CCIPR_LPTIM2SEL */ + +#if defined(CEC) +/** @brief Macro to configure the CEC clock (CECCLK). + * + * @param __CEC_CLKSOURCE__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_CECCLKSOURCE_HSI_DIV488 HSI_DIV_488 selected as CEC clock + * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) + +/** @brief Macro to get the CEC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_CECCLKSOURCE_HSI_DIV488 HSI_DIV_488 Clock selected as CEC clock + * @arg @ref RCC_CECCLKSOURCE_LSE LSE selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CECSEL))) +#endif /* CEC */ + +#if defined(RNG) +/** @brief Macro to configure the RNG clock. + * + * + * @param __RNG_CLKSOURCE__ specifies the RNG clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_HSI_DIV8 HSI Clock divided by 8 selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_SYSCLK System Clock selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_PLL PLLQ Output Clock selected as RNG clock + */ +#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, (uint32_t)(__RNG_CLKSOURCE__)) + +/** @brief Macro to get the RNG clock. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_HSI_DIV8 HSI Clock divide by 8 selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_SYSCLK System clock selected as RNG clock + * @arg @ref RCC_RNGCLKSOURCE_PLL PLLQ Output Clock selected as RNG clock + */ +#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGSEL))) + +/** @brief Macro to configure the RNG clock. + * + * + * @param __RNG_CLKDIV__ specifies the RNG clock division factor. + * This parameter can be one of the following values: + * @arg @ref RCC_RNGCLK_DIV1 RNG Clock not divided + * @arg @ref RCC_RNGCLK_DIV2 RNG Clock divided by 2 + * @arg @ref RCC_RNGCLK_DIV4 RNG Clock divided by 4 + * @arg @ref RCC_RNGCLK_DIV8 RNG Clock divided by 8 + */ +#define __HAL_RCC_RNGDIV_CONFIG(__RNG_CLKDIV__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, (uint32_t)(__RNG_CLKDIV__)) + +/** @brief Macro to get the RNG clock division factor. + * @retval The division factor can be one of the following values: + * @arg @ref RCC_RNGCLK_DIV1 RNG Clock not divided + * @arg @ref RCC_RNGCLK_DIV2 RNG Clock divided by 2 + * @arg @ref RCC_RNGCLK_DIV4 RNG Clock divided by 4 + * @arg @ref RCC_RNGCLK_DIV8 RNG Clock divided by 8 + */ +#define __HAL_RCC_GET_RNG_DIV() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV))) +#endif /* RNG */ + +/** @brief Macro to configure the ADC interface clock + * @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADCCLKSOURCE_PLLADC PLL "P" (PLLADC) Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock + */ +#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) + +/** @brief Macro to get the ADC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADCCLKSOURCE_PLLADC PLL "P" (PLLADC) Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock + * @arg @ref RCC_ADCCLKSOURCE_HSI HSI Clock selected as ADC clock + */ +#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) + +#if defined(RCC_CCIPR_TIM1SEL) +/** @brief Macro to configure the TIM1 interface clock + * @param __TIM1_CLKSOURCE__ specifies the TIM1 digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_TIM1CLKSOURCE_PLL PLLQ Output Clock selected as TIM1 clock + * @arg @ref RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock + */ +#define __HAL_RCC_TIM1_CONFIG(__TIM1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__)) + +/** @brief Macro to get the TIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM1CLKSOURCE_PLL PLLQ Output Clock selected as TIM1 clock + * @arg @ref RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock + */ +#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL))) +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) +/** @brief Macro to configure the TIM15 interface clock + * @param __TIM15_CLKSOURCE__ specifies the TIM15 digital interface clock source. + * This parameter can be one of the following values: + * @arg RCC_TIM15CLKSOURCE_PLL PLLQ Output Clock selected as TIM15 clock + * @arg RCC_TIM15CLKSOURCE_PCLK1 System Clock selected as TIM15 clock + */ +#define __HAL_RCC_TIM15_CONFIG(__TIM15_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM15SEL, (uint32_t)(__TIM15_CLKSOURCE__)) + +/** @brief Macro to get the TIM15 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_TIM15CLKSOURCE_PLL PLLQ Output Clock selected as TIM15 clock + * @arg @ref RCC_TIM15CLKSOURCE_PCLK1 System Clock selected as TIM15 clock + */ +#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL))) +#endif /* RCC_CCIPR_TIM15SEL */ + +#if defined(RCC_CCIPR2_USBSEL) +/** @brief Macro to configure the USB interface clock + * @param __USB_CLKSOURCE__ specifies the USB digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_PLL PLLQ Output Clock selected as USB clock (*) + * @arg @ref RCC_USBCLKSOURCE_HSE HSE Output Clock selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 Clock selected as USB clock (*) + * (*) Feature not available on all devices + */ +#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, (uint32_t)(__USB_CLKSOURCE__)) + +/** @brief Macro to get the USB clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 Clock selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_HSE HSE Output Clock selected as USB clock + * @arg @ref RCC_USBCLKSOURCE_PLL PLLQ Output Clock selected as USB clock + */ +#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL))) +#endif /* RCC_CCIPR2_USBSEL */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @brief Macro to configure the FDCAN interface clock + * @param __FDCAN_CLKSOURCE__ specifies the FDCAN digital interface clock source. + * This parameter can be one of the following values: + * @arg RCC_FDCANCLKSOURCE_PLL PLLQ Output Clock selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_PCLK1 System Clock selected as FDCAN clock + * @arg RCC_FDCANCLKSOURCE_HSE HSE Clock selected as FDCAN clock + */ +#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) + +/** @brief Macro to get the FDCAN clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_FDCANCLKSOURCE_PLL PLLQ Output Clock selected as FDCAN clock + * @arg @ref RCC_FDCANCLKSOURCE_PCLK1 System Clock selected as FDCAN clock + * @arg @ref RCC_FDCANCLKSOURCE_HSE HSE Clock selected as FDCAN clock + */ +#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL))) +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(CRS) + +/** + * @brief Enable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) + +/** + * @brief Disable the specified CRS interrupts. + * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval None + */ +#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) + +/** @brief Check whether the CRS interrupt has occurred or not. + * @param __INTERRUPT__ specifies the CRS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET) + +/** @brief Clear the CRS interrupt pending bits + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt + * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt + * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt + * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt + * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt + * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt + * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt + */ +/* CRS IT Error Mask */ +#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS) + +#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0) + +/** + * @brief Check whether the specified CRS flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @retval The new state of _FLAG_ (TRUE or FALSE). + */ +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the CRS specified FLAG. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK + * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning + * @arg @ref RCC_CRS_FLAG_ERR Error + * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC + * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow + * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error + * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed + * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR + * @retval None + */ + +/* CRS Flag Error Mask */ +#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS) + +#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0) + +#endif /* CRS */ + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ +/** + * @brief Enable the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Disable the oscillator clock for frequency error counter. + * @retval None + */ +#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) + +/** + * @brief Enable the automatic hardware adjustment of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Enable or disable the automatic hardware adjustment of TRIM bits. + * @retval None + */ +#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency + * of the synchronization source after prescaling. It is then decreased by one in order to + * reach the expected synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval None + */ +#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +#endif /* CRS */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); + +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); +void HAL_RCCEx_DisableLSCO(void); + +/** + * @} + */ + +#if defined(CRS) + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ + +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_CRS_IRQHandler(void); +void HAL_RCCEx_CRS_SyncOkCallback(void); +void HAL_RCCEx_CRS_SyncWarnCallback(void); +void HAL_RCCEx_CRS_ExpectedSyncCallback(void); +void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ + +#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) + +#if defined(STM32G0C1xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + +#elif defined(STM32G0B1xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + +#elif defined(STM32G0B0xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)) + +#elif defined(STM32G081xx) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) +#elif defined(STM32G071xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + +#elif defined(STM32G070xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + +#elif defined(STM32G061xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + +#elif defined(STM32G051xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)) + +#elif defined(STM32G041xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)) + +#elif defined(STM32G031xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)) + +#elif defined(STM32G030xx) || defined(STM32G050xx) + +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#endif /* STM32G0C1xx */ + +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) + +#if defined(RCC_CCIPR_USART2SEL) +#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) +#endif /* RCC_CCIPR_USART2SEL */ + +#if defined(RCC_CCIPR_USART3SEL) +#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(LPUART1) +#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) +#endif /* LPUART1 */ + +#if defined(LPUART2) +#define IS_RCC_LPUART2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPUART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPUART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_LPUART2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART2CLKSOURCE_HSI)) +#endif /* LPUART2 */ + +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) + +#if defined(RCC_CCIPR_I2C2SEL) +#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) + +#endif /* RCC_CCIPR_I2C2SEL */ + +#define IS_RCC_I2S1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2S1CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2S1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_I2S1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2S1CLKSOURCE_EXT)) + +#if defined(RCC_CCIPR2_I2S2SEL) +#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_I2S2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_I2S2CLKSOURCE_EXT)) +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(RCC_CCIPR_LPTIM1SEL) +#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1)|| \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) +#endif /* RCC_CCIPR_LPTIM1SEL */ + +#if defined(RCC_CCIPR_LPTIM2SEL) +#define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1)|| \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) +#endif /* RCC_CCIPR_LPTIM2SEL */ + +#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_ADCCLKSOURCE_PLLADC) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI)) + +#if defined(RNG) +#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI_DIV8) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)) +#define IS_RCC_RNGDIV(__DIV__) \ + (((__DIV__) == RCC_RNGCLK_DIV1) || \ + ((__DIV__) == RCC_RNGCLK_DIV2) || \ + ((__DIV__) == RCC_RNGCLK_DIV4) || \ + ((__DIV__) == RCC_RNGCLK_DIV8)) +#endif /* RNG */ + +#if defined(CEC) +#define IS_RCC_CECCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_CECCLKSOURCE_HSI_DIV488)|| \ + ((__SOURCE__) == RCC_CECCLKSOURCE_LSE)) +#endif /* CEC */ + +#if defined(FDCAN1) || defined(FDCAN2) +#define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)|| \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)|| \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1)) + +#endif /* FDCAN1 */ + +#if defined(RCC_HSI48_SUPPORT) +#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48)|| \ + ((__SOURCE__) == RCC_USBCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) +#else +#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_USBCLKSOURCE_HSE)|| \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL)) +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_CCIPR_TIM1SEL) +#define IS_RCC_TIM1CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_TIM1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_TIM1CLKSOURCE_PCLK1)) +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) +#define IS_RCC_TIM15CLKSOURCE(__SOURCE__) \ + (((__SOURCE__) == RCC_TIM15CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_TIM15CLKSOURCE_PCLK1)) +#endif /* RCC_CCIPR_TIM15SEL */ + +#if defined(CRS) + +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) + +#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) + +#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) + +#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) + +#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) + +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) + +#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ + ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) + +#endif /* CRS */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_RCC_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim.h (revision 3) @@ -0,0 +1,2425 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_TIM_H +#define STM32G0xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + * @note Advanced timers provide TRGO2 internal line which is redirected + * to the ADC + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + uint32_t LockLevel; /*!< TIM Lock level + This parameter can be a value of @ref TIM_Lock_level */ + uint32_t DeadTime; /*!< TIM dead Time + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint32_t BreakState; /*!< TIM Break State + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + uint32_t BreakPolarity; /*!< TIM Break input polarity + This parameter can be a value of @ref TIM_Break_Polarity */ + uint32_t BreakFilter; /*!< Specifies the break input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. + This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + uint32_t Break2State; /*!< TIM Break2 State + This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + uint32_t Break2Polarity; /*!< TIM Break2 input polarity + This parameter can be a value of @ref TIM_Break2_Polarity */ + uint32_t Break2Filter; /*!< TIM break2 input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. + This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x10000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x20000000U /*!< OCREF_CLR is connected to ETRF input */ +#if defined(COMP1) && defined(COMP2) && defined(COMP3) +#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ +#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_OR1_OCREF_CLR_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ +#define TIM_CLEARINPUTSOURCE_COMP3 TIM1_OR1_OCREF_CLR_1 /*!< OCREF_CLR_INT is connected to COMP3 output */ +#elif defined(COMP1) && defined(COMP2) +#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ +#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_OR1_OCREF_CLR /*!< OCREF_CLR_INT is connected to COMP2 output */ +#endif /* COMP1 && COMP2 && COMP3 */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +#define TIM_DMABASE_OR1 0x00000014U +#define TIM_DMABASE_CCMR3 0x00000015U +#define TIM_DMABASE_CCR5 0x00000016U +#define TIM_DMABASE_CCR6 0x00000017U +#define TIM_DMABASE_AF1 0x00000018U +#define TIM_DMABASE_AF2 0x00000019U +#define TIM_DMABASE_TISEL 0x0000001AU +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#if defined(USB_BASE) +#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ +#endif /* USB_BASE */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ +#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable + * @{ + */ +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity + * @{ + */ +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ +#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event + (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#if defined(USB_BASE) +#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ +#endif /* USB_BASE */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_System TIM Break System + * @{ + */ +#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/15/16/17 */ +#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/15/16/17 */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder +mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value + * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#if defined(COMP1) && defined(COMP2) && defined(COMP3) +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#elif defined(COMP1) && defined(COMP2) +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#else +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) +#endif /* COMP1 && COMP2 && COMP3 */ + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2) || \ + ((__BASE__) == TIM_DMABASE_TISEL)) + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENALE)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_5) || \ + ((__CHANNEL__) == TIM_CHANNEL_6) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) + + +#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ + ((__STATE__) == TIM_BREAK2_DISABLE)) + +#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) + +#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ + ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO2_OC1) || \ + ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) + +#if defined(USB_BASE) +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) +#else +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) +#endif /* USB_BASE */ + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#if defined(PWR_PVD_SUPPORT) +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) +#else +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) +#endif /* PWR_PVD_SUPPORT */ + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32g0xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_TIM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h (revision 3) @@ -0,0 +1,496 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_TIM_EX_H +#define STM32G0xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; + +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct +{ + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ + uint32_t Polarity; /*!< Specifies the break input source polarity. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ +} +TIMEx_BreakInputConfigTypeDef; + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ +#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /* !< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ +#if defined(COMP3) +#define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to COMP3 output */ +#endif +#if defined(TIM2) +#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ +#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ +#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */ +#define TIM_TIM2_ETR_LSE (TIM2_AF1_ETRSEL_1 | TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to LSE */ +#if defined(COMP3) +#define TIM_TIM2_ETR_MCO TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to MCO */ +#define TIM_TIM2_ETR_MCO2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to MCO2 */ +#define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP3 output */ +#endif +#endif /* TIM2 */ +#if defined(TIM3) +#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 output */ +#define TIM_TIM3_ETR_COMP2 TIM3_AF1_ETRSEL_1 /* !< TIM3_ETR is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +#if defined(COMP3) +#define TIM_TIM3_ETR_COMP3 (TIM3_AF1_ETRSEL_1 | TIM3_AF1_ETRSEL_0) /* !< TIM3_ETR is connected to COMP3 output */ +#endif /* COMP3 */ +#endif /* TIM3 */ +#if defined(TIM4) +#define TIM_TIM4_ETR_GPIO 0x00000000U /* !< TIM4_ETR is connected to GPIO */ +#if defined(COMP1) && defined(COMP2) +#define TIM_TIM4_ETR_COMP1 TIM4_AF1_ETRSEL_0 /* !< TIM4_ETR is connected to COMP1 output */ +#define TIM_TIM4_ETR_COMP2 TIM4_AF1_ETRSEL_1 /* !< TIM4_ETR is connected to COMP2 output */ +#endif /* COMP1 && COMP2 */ +#if defined(COMP3) +#define TIM_TIM4_ETR_COMP3 (TIM4_AF1_ETRSEL_1 | TIM4_AF1_ETRSEL_0) /* !< TIM4_ETR is connected to COMP3 output */ +#endif /* COMP3 */ +#endif /* TIM4 */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ +#if defined(COMP1) && defined(COMP2) +#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ +#endif /* COMP1 && COMP2 */ +#if defined(COMP3) +#define TIM_BREAKINPUTSOURCE_COMP3 0x00000008U /* !< The COMP3 output is connected to the break input */ +#endif /* COMP3 */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity + * @{ + */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */ +/** + * @} + */ + +/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection + * @{ + */ +#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */ +#if defined(COMP1) +#define TIM_TIM1_TI1_COMP1 0x00000001U /* !< TIM1_TI1 is connected to COMP1 OUT */ +#endif /* COMP1 */ + +#define TIM_TIM1_TI2_GPIO 0x00000000U /* !< TIM1_TI2 is connected to GPIO */ +#if defined(COMP2) +#define TIM_TIM1_TI2_COMP2 0x00000100U /* !< TIM1_TI2 is connected to COMP2 OUT */ +#endif /* COMP2 */ + +#define TIM_TIM1_TI3_GPIO 0x00000000U /* !< TIM1_TI3 is connected to GPIO */ +#if defined(COMP3) +#define TIM_TIM1_TI3_COMP3 0x00010000U /* !< TIM1_TI3 is connected to COMP3 OUT */ +#endif /* COMP3 */ + +#if defined(TIM2) +#define TIM_TIM2_TI1_GPIO 0x00000000U /* !< TIM2_TI1 is connected to GPIO */ +#define TIM_TIM2_TI1_COMP1 0x00000001U /* !< TIM2_TI1 is connected to COMP1 OUT */ + +#define TIM_TIM2_TI2_GPIO 0x00000000U /* !< TIM2_TI2 is connected to GPIO */ +#define TIM_TIM2_TI2_COMP2 0x00000100U /* !< TIM2_TI2 is connected to COMP2 OUT */ + +#define TIM_TIM2_TI3_GPIO 0x00000000U /* !< TIM2_TI3 is connected to GPIO */ +#if defined(COMP3) +#define TIM_TIM2_TI3_COMP3 0x00010000U /* !< TIM2_TI3 is connected to COMP3 OUT */ +#endif /* COMP3 */ +#endif /* TIM2 */ + +#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */ +#if defined(COMP1) +#define TIM_TIM3_TI1_COMP1 0x00000001U /* !< TIM3_TI1 is connected to COMP1 OUT */ +#endif /* COMP1 */ + +#define TIM_TIM3_TI2_GPIO 0x00000000U /* !< TIM3_TI2 is connected to GPIO */ +#if defined(COMP2) +#define TIM_TIM3_TI2_COMP2 0x00000100U /* !< TIM3_TI2 is connected to COMP2 OUT */ +#endif /* COMP2 */ + +#define TIM_TIM3_TI3_GPIO 0x00000000U /* !< TIM3_TI3 is connected to GPIO */ +#if defined(COMP3) +#define TIM_TIM3_TI3_COMP3 0x00010000U /* !< TIM3_TI3 is connected to COMP3 OUT */ +#endif /* COMP3 */ + +#if defined(TIM4) +#define TIM_TIM4_TI1_GPIO 0x00000000U /* !< TIM4_TI1 is connected to GPIO */ +#if defined(COMP1) +#define TIM_TIM4_TI1_COMP1 0x00000001U /* !< TIM4_TI1 is connected to COMP1 OUT */ +#endif /* COMP1 */ + +#define TIM_TIM4_TI2_GPIO 0x00000000U /* !< TIM4_TI2 is connected to GPIO */ +#if defined(COMP2) +#define TIM_TIM4_TI2_COMP2 0x00000100U /* !< TIM4_TI2 is connected to COMP2 OUT */ +#endif /* COMP2 */ + +#define TIM_TIM4_TI3_GPIO 0x00000000U /* !< TIM4_TI3 is connected to GPIO */ +#if defined(COMP3) +#define TIM_TIM4_TI3_COMP3 0x00010000U /* !< TIM4_TI3 is connected to COMP3 OUT */ +#endif /* COMP3 */ +#endif /* TIM4 */ + +#define TIM_TIM14_TI1_GPIO 0x00000000U /* !< TIM14_TI1 is connected to GPIO */ +#define TIM_TIM14_TI1_RTC 0x00000001U /* !< TIM14_TI1 is connected to RTC clock */ +#define TIM_TIM14_TI1_HSE_32 0x00000002U /* !< TIM14_TI1 is connected to HSE div 32 */ +#define TIM_TIM14_TI1_MCO 0x00000003U /* !< TIM14_TI1 is connected to MCO */ +#if defined(RCC_MCO2_SUPPORT) +#define TIM_TIM14_TI1_MCO2 0x00000004U /* !< TIM14_TI1 is connected to MCO2 */ +#endif + +#if defined(TIM15) +#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */ +#define TIM_TIM15_TI1_TIM2_CH1 0x00000001U /* !< TIM15_TI1 is connected to TIM2 CH1 */ +#define TIM_TIM15_TI1_TIM3_CH1 0x00000002U /* !< TIM15_TI1 is connected to TIM3 CH1 */ + +#define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */ +#define TIM_TIM15_TI2_TIM2_CH2 0x00000100U /* !< TIM15_TI2 is connected to TIM2 CH2 */ +#define TIM_TIM15_TI2_TIM3_CH2 0x00000200U /* !< TIM15_TI2 is connected to TIM3 CH2 */ +#endif /* TIM15 */ + +#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to GPIO */ +#define TIM_TIM16_TI1_LSI 0x00000001U /* !< TIM16_TI1 is connected to LSI */ +#define TIM_TIM16_TI1_LSE 0x00000002U /* !< TIM16_TI1 is connected to LSE */ +#define TIM_TIM16_TI1_RTC_WAKEUP 0x00000003U /* !< TIM16_TI1 is connected to TRC wakeup interrupt */ +#if defined(RCC_MCO2_SUPPORT) +#define TIM_TIM16_TI1_MCO2 0x00000004U /* !< TIM16_TI1 is connected to MCO2 */ +#endif + +#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to GPIO */ +#if defined(RCC_HSI48_SUPPORT) +#define TIM_TIM17_TI1_HSI48 0x00000001U /* !< TIM17_TI1 is connected to HSI48/256 */ +#endif +#define TIM_TIM17_TI1_HSE_32 0x00000002U /* !< TIM17_TI1 is connected to HSE div 32 */ +#define TIM_TIM17_TI1_MCO 0x00000003U /* !< TIM17_TI1 is connected to MCO */ +#if defined(RCC_MCO2_SUPPORT) +#define TIM_TIM17_TI1_MCO2 0x00000004U /* !< TIM17_TI1 is connected to MCO2 */ +#endif +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) + +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#if defined(COMP1) && defined(COMP2) && defined(COMP3) +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3)) +#elif defined(COMP1) && defined(COMP2) +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) +#else +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) ((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) +#endif /* COMP1 && COMP2 && COMP3 */ + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) + +#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); + +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32G0xx_HAL_TIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h (revision 3) @@ -0,0 +1,1718 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_UART_H +#define STM32G0xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + LPUART: + ======= + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler + UART: + ===== + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ + +} UART_InitTypeDef; + +/** + * @brief UART Advanced Features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv. */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv. */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv. */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable. */ + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ + + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First. */ +} UART_AdvFeatureInitTypeDef; + +/** + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_UART_StateTypeDef; + +/** + * @brief UART clock sources definition + */ +typedef enum +{ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ +} UART_ClockSourceTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * It is expected to admit following values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + + uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + uint16_t Mask; /*!< UART Rx RDR register mask */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref UARTEx_FIFO_mode. */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ + HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +/** @defgroup UART_ClockPrescaler UART Clock Prescaler + * @{ + */ +#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ + +/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ +/** + * @} + */ + +/** @defgroup UART_LIN UART Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ +/** + * @} + */ + +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ +/** + * @} + */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UART Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +/** + * @} + */ + +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ +/** + * @} + */ + +/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ +/** + * @} + */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +/** + * @} + */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ +/** + * @} + */ + +/** @defgroup UART_Flags UART Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ +#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ +#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ +#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ +#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ +#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +/** + * @} + */ + +/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle states. + * @param __HANDLE__ UART handle. + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flush the UART Data registers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + +/** @brief Clear the UART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) + +/** @brief Check whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref UART_FLAG_RXFF RXFIFO Full flag + * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref UART_FLAG_WUF Wake up from stop mode flag + * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_CTS CTS Change flag + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) + +/** @brief Check whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) + +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +/** @brief Get UART clok division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval UART clock division factor + */ +#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + +/** @brief BRR division operation to set BRR register with LPUART. + * @param __PCLK__ LPUART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \ + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \ + ) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief Check whether or not UART instance is Low Power UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) + */ +#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) + +/** @brief Check UART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on G0 (i.e. 64 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 8000001U) + +/** @brief Check UART assertion time. + * @param __TIME__ 5-bit value assertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param __TIME__ 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__ UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that LPUART frame number of stop bits is valid. + * @param __STOPBITS__ LPUART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__ UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__ UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__ UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__ UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__ UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__ UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__ UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__ UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__ UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__ UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) + +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__ UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__ UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__ UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__ UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__ UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__ UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__ UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__ UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__ UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__ UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__ UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__ UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__ UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__ UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__ UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__ UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__ UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) + +/** + * @brief Ensure that UART Prescaler is valid. + * @param __CLOCKPRESCALER__ UART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) + +/** + * @} + */ + +/* Include UART HAL Extended module */ +#include "stm32g0xx_hal_uart_ex.h" + + +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_UART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h (revision 3) @@ -0,0 +1,770 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_uart_ex.h + * @author MCD Application Team + * @brief Header file of UART HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_HAL_UART_EX_H +#define STM32G0xx_HAL_UART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal_def.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ + + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ +} UART_WakeUpTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +/** + * @} + */ + +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +/** + * @} + */ + +/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode + * @brief UART FIFO mode + * @{ + */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level + * @brief UART TXFIFO threshold level + * @{ + */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level + * @brief UART RXFIFO threshold level + * @{ + */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART5) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == LPUART2) \ + { \ + switch(__HAL_RCC_GET_LPUART2_SOURCE()) \ + { \ + case RCC_LPUART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_LPUART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(STM32G0B0xx) +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART5) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(STM32G081xx) || defined(STM32G071xx) +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(STM32G070xx) +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == USART4) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G051xx) || defined(STM32G061xx) +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(STM32G030xx) || defined(STM32G050xx) +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__ UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param __ADDRESS__ UART wake-up address length. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + +/** + * @brief Ensure that UART TXFIFO threshold level is valid. + * @param __THRESHOLD__ UART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART RXFIFO threshold level is valid. + * @param __THRESHOLD__ UART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_HAL_UART_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_adc.h (revision 3) @@ -0,0 +1,5164 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_adc.h + * @author MCD Application Team + * @brief Header file of ADC LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_LL_ADC_H +#define STM32G0xx_LL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx.h" + +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined (ADC1) + +/** @defgroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Constants ADC Private Constants + * @{ + */ + +/* Internal mask for ADC group regular sequencer: */ +/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ +/* - sequencer rank bits position into the selected register */ + +#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Definition of ADC group regular sequencer bits information to be inserted */ +/* into ADC group regular sequencer ranks literals definition. */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ1" position in register */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ2" position in register */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ3" position in register */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ4" position in register */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ5" position in register */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ6" position in register */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ7" position in register */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ8" position in register */ + + + +/* Internal mask for ADC group regular trigger: */ +/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ +/* - regular trigger source */ +/* - regular trigger edge */ +#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ + +/* Mask containing trigger source masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) ) + +/* Mask containing trigger edge masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) + +/* Definition of ADC group regular trigger bits information. */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */ + + + +/* Internal mask for ADC channel: */ +/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ +/* - channel identifier defined by number */ +/* - channel identifier defined by bitfield */ +/* - channel differentiation between external channels (connected to */ +/* GPIO pins) and internal channels (connected to internal paths) */ +#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH) +#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) +#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */ +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \ + ADC_CHANNEL_ID_INTERNAL_CH_MASK) +/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ + +/* Channel differentiation between external and internal channels */ +#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH) + +/* Definition of channels ID number information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_NUMBER (0x00000000UL) +#define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1) +#define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2) +#define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1) +#define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3) +#define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1) +#define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2) +#define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1) +#define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \ + ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4) +#define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1) + +/* Definition of channels ID bitfield information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0) +#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1) +#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2) +#define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3) +#define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4) +#define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5) +#define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6) +#define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7) +#define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8) +#define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9) +#define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10) +#define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11) +#define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12) +#define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13) +#define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14) +#define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15) +#define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16) +#define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17) +#define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18) + +/* Internal mask for ADC channel sampling time: */ +/* To select into literals LL_ADC_SAMPLINGTIME_x */ +/* the relevant bits for: */ +/* (concatenation of multiple bits used in register SMPR) */ +/* - ADC channels sampling time: setting channel wise, to map each channel */ +/* on one of the common sampling time available. */ +/* - ADC channels common sampling time: set a sampling time into one of the */ +/* common sampling time available. */ +#define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS) +#define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1) +#define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS) + +/* Internal mask for ADC analog watchdog: */ +/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ +/* (concatenation of multiple bits used in different analog watchdogs, */ +/* (feature of several watchdogs not available on all STM32 families)). */ +/* - analog watchdog 1: monitored channel defined by number, */ +/* selection of ADC group (ADC group regular). */ +/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ +/* selection on groups. */ + +/* Internal register offset for ADC analog watchdog channel configuration */ +#define ADC_AWD_CR1_REGOFFSET (0x00000000UL) +#define ADC_AWD_CR2_REGOFFSET (0x00100000UL) +#define ADC_AWD_CR3_REGOFFSET (0x00200000UL) + +/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */ +/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */ +#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0) +#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL) + +#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) +#define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL) + +#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) +#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) +#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) + +#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */ + +/* Internal register offset for ADC analog watchdog threshold configuration */ +#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) +#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) +#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS)) +#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) +#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */ +#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */ +#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */ +#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */ +#define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL) + + + +/* ADC registers bits positions */ +#define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR1_RES" position in register */ +#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */ +#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR1_HT1" position in register */ +#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */ +#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */ +#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */ +#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */ +#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */ +#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */ +#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */ +#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */ +#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */ +#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */ +#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */ +#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */ +#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */ +#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */ +#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */ +#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */ +#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */ +#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */ +#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */ +#define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SMPR_SMP1" position in register */ +#define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_SMPR_SMP2" position in register */ +#define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */ + + +/* ADC registers bits groups */ +#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ + + +/* ADC internal channels related definitions */ +/* Internal voltage reference VrefInt */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) voltage with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ +/* Temperature sensor */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G0, temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Macros ADC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address + */ +#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of ADC common parameters + * and multimode + * (all ADC instances belonging to the same ADC common instance). + * @note The setting of these parameters by function @ref LL_ADC_CommonInit() + * is conditioned to ADC instances state (all ADC instances + * sharing the same ADC common instance): + * All ADC instances sharing the same ADC common instance must be + * disabled. + */ +typedef struct +{ + uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. + This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ + +} LL_ADC_CommonInitTypeDef; + +/** + * @brief Structure definition of some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t Clock; /*!< Set ADC instance clock source and prescaler. + This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE + @note On this STM32 series, this parameter has some clock ratio constraints: + ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle + (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle). + + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock(). + For more details, refer to description of this function. */ + + uint32_t Resolution; /*!< Set ADC resolution. + This parameter can be a value of @ref ADC_LL_EC_RESOLUTION + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ + + uint32_t DataAlignment; /*!< Set ADC conversion data alignment. + This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ + + uint32_t LowPowerMode; /*!< Set ADC low power mode. + This parameter can be a value of @ref ADC_LL_EC_LP_MODE + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */ + +} LL_ADC_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_REG_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE + @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge + (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). + In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. + @note This parameter has an effect only if group regular sequencer is set to mode "fully configurable". Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE + @note This parameter has an effect only if group regular sequencer is enabled + (depending on the sequencer mode: scan length of 2 ranks or more, or several ADC channels enabled in group regular sequencer. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ + + uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). + This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE + Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ + + uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. + This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ + + uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: + data preserved or overwritten. + This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */ + +} LL_ADC_REG_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_LL_EC_FLAG ADC flags + * @brief Flags defines which can be used with LL_ADC_ReadReg function + * @{ + */ +#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ +#define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */ +#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */ +#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */ +#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ +#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ +#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ +#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ +#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ +#define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions + * @{ + */ +#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ +#define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */ +#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */ +#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */ +#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ +#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */ +#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ +#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ +#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ +#define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + * @{ + */ +/* List of ADC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + * @{ + */ +#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */ +#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE ADC common - Clock frequency mode + * @{ + */ +#define LL_ADC_CLOCK_FREQ_MODE_HIGH (0x00000000UL) /*!< ADC clock mode to high frequency. On STM32G0, ADC clock frequency above 3.5MHz. */ +#define LL_ADC_CLOCK_FREQ_MODE_LOW (ADC_CCR_LFMEN) /*!< ADC clock mode to low frequency. On STM32G0, ADC clock frequency below 3.5MHz. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + * @{ + */ +/* Note: Other measurement paths to internal channels may be available */ +/* (connections to other peripherals). */ +/* If they are not listed below, they do not require any specific */ +/* path enable. In this case, Access to measurement path is done */ +/* only by selecting the corresponding ADC internal channel. */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ +#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source + * @{ + */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */ +#define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */ +#define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */ +#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */ +#define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment + * @{ + */ +#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode + * @{ + */ +#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ +#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ +#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */ +#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode + * @{ + */ +#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ +#define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels + * @{ + */ +#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group of channels: sampling time nb 1 */ +#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ +#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */ +#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + * @{ + */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#if defined(TIM2) +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#endif +#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#if defined(TIM4) +#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#endif +#if defined(TIM6) +#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#endif +#if defined(TIM15) +#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ +#endif +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + * @{ + */ +#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ +#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ +#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode + * @{ + */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data + * @{ + */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data + * @{ + */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */ +#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility + * @{ + */ +#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */ +#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */ +#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ +#define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ +#define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ +#define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ +#define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ +#define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ +#define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ +#define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */ +#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ +#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels + * @{ + */ +#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR1_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ +#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + * @{ + */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */ +#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope + * @{ + */ +#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ +#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + * @{ + */ +#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ +#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio + * @{ + */ +#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift + * @{ + */ +#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro + * @{ + */ +#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on calibration parameters. This value is coded on 16 bits (to fit on signed word or double word) and corresponds to an inconsistent temperature value. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ +/* not timeout values. */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Indications for estimation of ADC timeout delays, for this */ +/* STM32 series: */ +/* - ADC calibration time: maximum delay is 82/fADC. */ +/* (refer to device datasheet, parameter "tCAL") */ +/* - ADC enable time: maximum delay is 1 conversion cycle. */ +/* (refer to device datasheet, parameter "tSTAB") */ +/* - ADC disable time: maximum delay should be a few ADC clock cycles */ +/* - ADC stop conversion time: maximum delay should be a few ADC clock */ +/* cycles */ +/* - ADC conversion time: duration depending on ADC clock and ADC */ +/* configuration. */ +/* (refer to device reference manual, section "Timing") */ + +/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ +/* Delay set to maximum value (refer to device datasheet, */ +/* parameter "tADCVREG_STUP"). */ +/* Unit: us */ +#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ + +/* Delay for internal voltage reference stabilization time. */ +/* Delay set to maximum value (refer to device datasheet, */ +/* parameter "tstart_vrefint"). */ +/* Unit: us */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */ + +/* Delay for temperature sensor stabilization time. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time (starting from temperature sensor enable, refer to @ref LL_ADC_SetCommonPathInternalCh()) */ +#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */ + +/* Delay required between ADC end of calibration and ADC enable. */ +/* Note: On this STM32 series, a minimum number of ADC clock cycles */ +/* are required between ADC end of calibration and ADC enable. */ +/* Wait time can be computed in user application by waiting for the */ +/* equivalent number of CPU cycles, by taking into account */ +/* ratio of CPU clock versus ADC clock prescalers. */ +/* Unit: ADC clock cycles. */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration and ADC enable */ + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals LL_ADC_CHANNEL_x. + * @note Example: + * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \ + ( \ + ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ + ) \ + : \ + ((((__CHANNEL__) & ADC_CHANNEL_0_BITFIELD) == ADC_CHANNEL_0_BITFIELD) ? (0UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_1_BITFIELD) == ADC_CHANNEL_1_BITFIELD) ? (1UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_2_BITFIELD) == ADC_CHANNEL_2_BITFIELD) ? (2UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_3_BITFIELD) == ADC_CHANNEL_3_BITFIELD) ? (3UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_4_BITFIELD) == ADC_CHANNEL_4_BITFIELD) ? (4UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_5_BITFIELD) == ADC_CHANNEL_5_BITFIELD) ? (5UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_6_BITFIELD) == ADC_CHANNEL_6_BITFIELD) ? (6UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_7_BITFIELD) == ADC_CHANNEL_7_BITFIELD) ? (7UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_8_BITFIELD) == ADC_CHANNEL_8_BITFIELD) ? (8UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_9_BITFIELD) == ADC_CHANNEL_9_BITFIELD) ? (9UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_10_BITFIELD) == ADC_CHANNEL_10_BITFIELD) ? (10UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_11_BITFIELD) == ADC_CHANNEL_11_BITFIELD) ? (11UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_12_BITFIELD) == ADC_CHANNEL_12_BITFIELD) ? (12UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_13_BITFIELD) == ADC_CHANNEL_13_BITFIELD) ? (13UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_14_BITFIELD) == ADC_CHANNEL_14_BITFIELD) ? (14UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_15_BITFIELD) == ADC_CHANNEL_15_BITFIELD) ? (15UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_16_BITFIELD) == ADC_CHANNEL_16_BITFIELD) ? (16UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_17_BITFIELD) == ADC_CHANNEL_17_BITFIELD) ? (17UL) : \ + ((((__CHANNEL__) & ADC_CHANNEL_18_BITFIELD) == ADC_CHANNEL_18_BITFIELD) ? (18UL) : \ + (0UL))))))))))))))))))))) + +/** + * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "LL_ADC_CHANNEL_4". + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VBAT (2) + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__))) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + */ +#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)) + +/** + * @brief Helper macro to define ADC analog watchdog parameter: + * define a single channel to monitor with analog watchdog + * from sequencer channel and groups definition. + * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). + * Example: + * LL_ADC_SetAnalogWDMonitChannels( + * ADC1, LL_ADC_AWD1, + * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VBAT (2) + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @param __GROUP__ This parameter can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG + * @arg @ref LL_ADC_AWD_CH_VBAT_REG + */ +#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) + +/** + * @brief Helper macro to set the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() + * or @ref LL_ADC_SetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_SetAnalogWDThresholds + * (< ADCx param >, + * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ + ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U ))) + +/** + * @brief Helper macro to get the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to get the value of + * analog watchdog threshold high (on 8 bits): + * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION + * (LL_ADC_RESOLUTION_8B, + * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ + ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U ))) + +/** + * @brief Helper macro to get the ADC analog watchdog threshold high + * or low from raw value containing both thresholds concatenated. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, to get analog watchdog threshold high from the register raw value: + * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, ); + * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ + (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW) + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC1_COMMON) + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + LL_ADC_IsEnabled(ADC1) + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data) + */ +#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ + __ADC_RESOLUTION_CURRENT__,\ + __ADC_RESOLUTION_TARGET__) \ +(((__DATA__) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)) \ +) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ +((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ +) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 series, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ +) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note On this STM32 series, calibration data of temperature sensor + * corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * temperature sensor. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature + * sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value) + */ +#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__)\ +((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \ + (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ + ) \ + : \ + ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \ +) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12 bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * On STM32G0, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32G0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000UL) \ + - \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000UL) \ + ) \ + ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ +) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management + * @{ + */ +/* Note: LL ADC functions to set DMA transfer are located into sections of */ +/* configuration of ADC instance, groups and multimode (if available): */ +/* @ref LL_ADC_REG_SetDMATransfer(), ... */ + +/** + * @brief Function to help to configure DMA transfer from ADC: retrieve the + * ADC register address from ADC instance and a list of ADC registers + * intended to be used (most commonly) with DMA transfer. + * @note These ADC registers are data registers: + * when ADC conversion data is available in ADC data registers, + * ADC generates a DMA transfer request. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), + * (uint32_t)&< array or variable >, + * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + * @note For devices with several ADC: in multimode, some devices + * use a different data register outside of ADC instance scope + * (common data register). This macro manages this register difference, + * only ADC instance has to be set as parameter. + * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr + * @param ADCx ADC instance + * @param Register This parameter can be one of the following values: + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA + * @retval ADC register address + */ +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(Register); + + /* Retrieve address of register DR */ + return (uint32_t) &(ADCx->DR); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances + * @{ + */ + +/** + * @brief Set parameter common to several ADC: Clock source and prescaler. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR PRESC LL_ADC_SetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param CommonClock This parameter can be one of the following values: + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1) + * + * (1) ADC common clock asynchronous prescaler is applied to + * each ADC instance if the corresponding ADC instance clock + * is set to clock source asynchronous. + * (refer to function @ref LL_ADC_SetClock() ). + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock); +} + +/** + * @brief Get parameter common to several ADC: Clock source and prescaler. + * @rmtoll CCR PRESC LL_ADC_GetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1) + * + * (1) ADC common clock asynchronous prescaler is applied to + * each ADC instance if the corresponding ADC instance clock + * is set to clock source asynchronous. + * (refer to function @ref LL_ADC_SetClock() ). + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC)); +} + +/** + * @brief Legacy feature, useless on STM32G0 (ADC common clock low frequency + mode is automatically managed by ADC peripheral on STM32G0). + Function kept for legacy purpose. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CCR LFMEN LL_ADC_SetCommonFrequencyMode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param CommonFrequencyMode This parameter can be one of the following values: + * @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH + * @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonFrequencyMode) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_LFMEN, CommonFrequencyMode); +} + +/** + * @brief Legacy feature, useless on STM32G0 (ADC common clock low frequency + mode is automatically managed by ADC peripheral on STM32G0). + Function kept for legacy purpose. + * @rmtoll CCR LFMEN LL_ADC_GetCommonFrequencyMode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CLOCK_FREQ_MODE_HIGH + * @arg @ref LL_ADC_CLOCK_FREQ_MODE_LOW + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonFrequencyMode(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_LFMEN)); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Configure all paths (overwrite current configuration). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * The values not selected are removed from configuration. + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, + * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n + * CCR TSEN LL_ADC_SetCommonPathInternalCh\n + * CCR VBATEN LL_ADC_SetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Add paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, + * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + SET_BIT(ADCxy_COMMON->CCR, PathInternal); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Remove paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n + * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n + * CCR VBATEN LL_ADC_SetCommonPathInternalChRem + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal); +} + +/** + * @brief Get parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n + * CCR TSEN LL_ADC_GetCommonPathInternalCh\n + * CCR VBATEN LL_ADC_GetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Set ADC instance clock source and prescaler. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 CKMODE LL_ADC_SetClock + * @param ADCx ADC instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2) + * @arg @ref LL_ADC_CLOCK_ASYNC (1) + * + * (1) Asynchronous clock prescaler can be configured using + * function @ref LL_ADC_SetCommonClock().\n + * (2) Caution: This parameter has some clock ratio constraints: + * This configuration must be enabled only if PCLK has a 50% + * duty clock cycle (APB prescaler configured inside the RCC + * must be bypassed and the system clock must by 50% duty + * cycle). + * Refer to reference manual. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); +} + +/** + * @brief Get ADC instance clock source and prescaler. + * @rmtoll CFGR2 CKMODE LL_ADC_GetClock + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2) + * @arg @ref LL_ADC_CLOCK_ASYNC (1) + * + * (1) Asynchronous clock prescaler can be retrieved using + * function @ref LL_ADC_GetCommonClock().\n + * (2) Caution: This parameter has some clock ratio constraints: + * This configuration must be enabled only if PCLK has a 50% + * duty clock cycle (APB prescaler configured inside the RCC + * must be bypassed and the system clock must by 50% duty + * cycle). + * Refer to reference manual. + */ +__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); +} + +/** + * @brief Set ADC calibration factor in the mode single-ended + * or differential (for devices with differential mode available). + * @note This function is intended to set calibration parameters + * without having to perform a new calibration using + * @ref LL_ADC_StartCalibration(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled, without calibration on going, without conversion + * on going on group regular. + * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor + * @param ADCx ADC instance + * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor) +{ + MODIFY_REG(ADCx->CALFACT, + ADC_CALFACT_CALFACT, + CalibrationFactor); +} + +/** + * @brief Get ADC calibration factor in the mode single-ended + * or differential (for devices with differential mode available). + * @note Calibration factors are set by hardware after performing + * a calibration run using function @ref LL_ADC_StartCalibration(). + * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x7F + */ +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT)); +} + +/** + * @brief Set ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 RES LL_ADC_SetResolution + * @param ADCx ADC instance + * @param Resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution); +} + +/** + * @brief Get ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CFGR1 RES LL_ADC_GetResolution + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + */ +__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES)); +} + +/** + * @brief Set ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment); +} + +/** + * @brief Get ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + */ +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN)); +} + +/** + * @brief Set ADC low power mode. + * @note Description of ADC low power modes: + * - ADC low power mode "auto wait": Dynamic low power mode, + * ADC conversions occurrences are limited to the minimum necessary + * in order to reduce power consumption. + * New ADC conversion starts only when the previous + * unitary conversion data (for ADC group regular) + * has been retrieved by user software. + * In the meantime, ADC remains idle: does not performs any + * other conversion. + * This mode allows to automatically adapt the ADC conversions + * triggers to the speed of the software that reads the data. + * Moreover, this avoids risk of overrun for low frequency + * applications. + * How to use this low power mode: + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). + * - Do use with polling: 1. Start conversion, + * 2. Later on, when conversion data is needed: poll for end of + * conversion to ensure that conversion is completed and + * retrieve ADC conversion data. This will trig another + * ADC conversion start. + * - ADC low power mode "auto power-off" (feature available on + * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): + * the ADC automatically powers-off after a conversion and + * automatically wakes up when a new conversion is triggered + * (with startup time between trigger and start of sampling). + * This feature can be combined with low power mode "auto wait". + * @note With ADC low power mode "auto wait", the ADC conversion data read + * is corresponding to previous ADC conversion start, independently + * of delay during which ADC was idle. + * Therefore, the ADC conversion data may be outdated: does not + * correspond to the current voltage level on the selected + * ADC channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n + * CFGR1 AUTOFF LL_ADC_SetLowPowerMode + * @param ADCx ADC instance + * @param LowPowerMode This parameter can be one of the following values: + * @arg @ref LL_ADC_LP_MODE_NONE + * @arg @ref LL_ADC_LP_AUTOWAIT + * @arg @ref LL_ADC_LP_AUTOPOWEROFF + * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) +{ + MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode); +} + +/** + * @brief Get ADC low power mode: + * @note Description of ADC low power modes: + * - ADC low power mode "auto wait": Dynamic low power mode, + * ADC conversions occurrences are limited to the minimum necessary + * in order to reduce power consumption. + * New ADC conversion starts only when the previous + * unitary conversion data (for ADC group regular) + * has been retrieved by user software. + * In the meantime, ADC remains idle: does not performs any + * other conversion. + * This mode allows to automatically adapt the ADC conversions + * triggers to the speed of the software that reads the data. + * Moreover, this avoids risk of overrun for low frequency + * applications. + * How to use this low power mode: + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). + * - Do use with polling: 1. Start conversion, + * 2. Later on, when conversion data is needed: poll for end of + * conversion to ensure that conversion is completed and + * retrieve ADC conversion data. This will trig another + * ADC conversion start. + * - ADC low power mode "auto power-off" (feature available on + * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): + * the ADC automatically powers-off after a conversion and + * automatically wakes up when a new conversion is triggered + * (with startup time between trigger and start of sampling). + * This feature can be combined with low power mode "auto wait". + * @note With ADC low power mode "auto wait", the ADC conversion data read + * is corresponding to previous ADC conversion start, independently + * of delay during which ADC was idle. + * Therefore, the ADC conversion data may be outdated: does not + * correspond to the current voltage level on the selected + * ADC channel. + * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n + * CFGR1 AUTOFF LL_ADC_GetLowPowerMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_LP_MODE_NONE + * @arg @ref LL_ADC_LP_AUTOWAIT + * @arg @ref LL_ADC_LP_AUTOPOWEROFF + * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF + */ +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF))); +} + +/** + * @brief Set ADC trigger frequency mode. + * @note ADC trigger frequency mode must be set to low frequency when + * a duration is exceeded before ADC conversion start trigger event + * (between ADC enable and ADC conversion start trigger event + * or between two ADC conversion start trigger event). + * Duration value: Refer to device datasheet, parameter "tIdle". + * @note When ADC trigger frequency mode is set to low frequency, + * some rearm cycles are inserted before performing ADC conversion + * start, inducing a delay of 2 ADC clock cycles. + * @note Usage of ADC trigger frequency mode with ADC low power mode: + * - Low power mode auto wait: Only the first ADC conversion + * start trigger inserts the rearm delay. + * - Low power mode auto power-off: ADC trigger frequency mode + * is discarded. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode + * @param ADCx ADC instance + * @param TriggerFrequencyMode This parameter can be one of the following values: + * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH + * @arg @ref LL_ADC_TRIGGER_FREQ_LOW + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode); +} + +/** + * @brief Get ADC trigger frequency mode. + * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH + * @arg @ref LL_ADC_TRIGGER_FREQ_LOW + */ +__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); +} + +/** + * @brief Set sampling time common to a group of channels. + * @note Unit: ADC clock cycles. + * @note On this STM32 series, sampling time scope is on ADC instance: + * Sampling time common to all channels. + * (on some other STM32 families, sampling time is channel wise) + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * On this STM32 series, ADC processing time is: + * - 12.5 ADC clock cycles at ADC resolution 12 bits + * - 10.5 ADC clock cycles at ADC resolution 10 bits + * - 8.5 ADC clock cycles at ADC resolution 8 bits + * - 6.5 ADC clock cycles at ADC resolution 6 bits + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n + * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels + * @param ADCx ADC instance + * @param SamplingTimeY This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY, + uint32_t SamplingTime) +{ + MODIFY_REG(ADCx->SMPR, + ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK), + SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); +} + +/** + * @brief Get sampling time common to a group of channels. + * @note Unit: ADC clock cycles. + * @note On this STM32 series, sampling time scope is on ADC instance: + * Sampling time common to all channels. + * (on some other STM32 families, sampling time is channel wise) + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n + * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels + * @param ADCx ADC instance + * @param SamplingTimeY This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 + */ +__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY) +{ + return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) + >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Set ADC group regular conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * external interrupt line). + * @note On this STM32 series, setting trigger source to external trigger + * also set trigger polarity to rising edge + * (default setting for compatibility with some ADC on other + * STM32 families having this setting set by HW default value). + * In case of need to modify trigger edge, use + * function @ref LL_ADC_REG_SetTriggerEdge(). + * @note On this STM32 series, ADC trigger frequency mode must be set + * in function of frequency of ADC group regular conversion trigger. + * Refer to description of function + * @ref LL_ADC_SetTriggerFrequencyMode(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n + * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + * + * (1) On STM32G0, parameter not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource); +} + +/** + * @brief Get ADC group regular conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * external interrupt line). + * @note To determine whether group regular trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") + * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n + * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + * + * (1) On STM32G0, parameter not available on all devices + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +{ + __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ + uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + + /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */ + /* to match with triggers literals definition. */ + return ((TriggerSource + & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN) + ); +} + +/** + * @brief Get ADC group regular conversion trigger source internal (SW start) + * or external. + * @note In case of group regular trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_REG_GetTriggerSource(). + * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL); +} + +/** + * @brief Set ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge + * @param ADCx ADC instance + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge); +} + +/** + * @brief Get ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN)); +} + +/** + * @brief Set ADC group regular sequencer configuration flexibility. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" are + * available: + * - sequencer configured to fully configurable: + * sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerLength(). + * - sequencer configured to not fully configurable: + * sequencer length and each rank affectation to a channel + * are fixed by channel HW number. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerChannels(). + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable + * @param ADCx ADC instance + * @param Configurability This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_FIXED + * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability); +} + +/** + * @brief Get ADC group regular sequencer configuration flexibility. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" are + * available: + * - sequencer configured to fully configurable: + * sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerLength(). + * - sequencer configured to not fully configurable: + * sequencer length and each rank affectation to a channel + * are fixed by channel HW number. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerChannels(). + * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_FIXED + * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD)); +} + +/** + * @brief Set ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * To set scan direction differently, refer to function + * @ref LL_ADC_REG_SetSequencerScanDirection(). + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ8 LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + SET_BIT(ADCx->CHSELR, SequencerNbRanks); +} + +/** + * @brief Get ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * To set scan direction differently, refer to function + * @ref LL_ADC_REG_SetSequencerScanDirection(). + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ8 LL_ADC_REG_GetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +{ + __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); + uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; + uint32_t RankIndex; + + /* Parse register for end of sequence identifier */ + for (RankIndex = 0UL; RankIndex < (32U - 4U); RankIndex += 4U) + { + if ((ChannelsRanks & (ADC_CHSELR_SQ2 << RankIndex)) == (ADC_CHSELR_SQ2 << RankIndex)) + { + SequencerLength = (ADC_CHSELR_SQ2 << RankIndex); + break; + } + } + + return SequencerLength; +} + +/** + * @brief Set ADC group regular sequencer scan direction. + * @note On this STM32 series, parameter relevant only is sequencer is set + * to mode not fully configurable, + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note On some other STM32 series, this setting is not available and + * the default scan direction is forward. + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection + * @param ADCx ADC instance + * @param ScanDirection This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection); +} + +/** + * @brief Get ADC group regular sequencer scan direction. + * @note On this STM32 series, parameter relevant only is sequencer is set + * to mode not fully configurable, + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note On some other STM32 families, this setting is not available and + * the default scan direction is forward. + * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR)); +} + +/** + * @brief Set ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont); +} + +/** + * @brief Get ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN)); +} + +/** + * @brief Set ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note This function performs configuration of: + * - Channels ordering into each rank of scan sequence: + * whatever channel can be placed into whatever rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ2 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ3 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ4 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ5 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ6 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ7 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ8 LL_ADC_REG_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + MODIFY_REG(ADCx->CHSELR, + ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ2 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ3 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ4 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ5 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ6 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ7 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ8 LL_ADC_REG_GetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (2) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2) + * @arg @ref LL_ADC_CHANNEL_VBAT (2) + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n + * (2) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +{ + return (uint32_t)((READ_BIT(ADCx->CHSELR, + ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) + ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ); +} + +/** + * @brief Set ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by overwriting the current sequencer + * configuration. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Add channel to ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by adding them to the current sequencer + * configuration. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by removing them to the current sequencer + * configuration. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note On this STM32 series, after modifying sequencer (functions + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks(), ...) + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, some actions may be ignored. + * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY + * for more details. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels order reading into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be retrieved. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels + * @param ADCx ADC instance + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) +{ + uint32_t ChannelsBitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); + + return ((((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17) +#if defined(ADC_CCR_VBATEN) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18) +#endif + ); +} + +/** + * @brief Set ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode + * @param ADCx ADC instance + * @param Continuous This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous); +} + +/** + * @brief Get ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT)); +} + +/** + * @brief Set ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n + * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer + * @param ADCx ADC instance + * @param DMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer); +} + +/** + * @brief Get ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n + * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG)); +} + +/** + * @brief Set ADC group regular behavior in case of overrun: + * data preserved or overwritten. + * @note Compatibility with devices without feature overrun: + * other devices without this feature have a behavior + * equivalent to data overwritten. + * The default setting of overrun is data preserved. + * Therefore, for compatibility with all devices, parameter + * overrun should be set to data overwritten. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun + * @param ADCx ADC instance + * @param Overrun This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED + * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun); +} + +/** + * @brief Get ADC group regular behavior in case of overrun: + * data preserved or overwritten. + * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED + * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels + * @{ + */ + +/** + * @brief Set sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll SMPR SMPSEL0 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL1 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL2 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL3 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL4 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL5 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL6 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL7 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL8 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL9 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL10 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL11 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL12 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL13 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL14 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL15 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL16 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL17 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @param SamplingTimeY This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + MODIFY_REG(ADCx->SMPR, + (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS), + (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK) + ); +} + +/** + * @brief Get sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @rmtoll SMPR SMPSEL0 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL1 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL2 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL3 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL4 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL5 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL6 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL7 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL8 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL9 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL10 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL11 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL12 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL13 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL14 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL15 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL16 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL17 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 (1) + * @arg @ref LL_ADC_CHANNEL_16 (1) + * @arg @ref LL_ADC_CHANNEL_17 (1) + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VBAT + * + * (1) On STM32G0, parameter can be set in ADC group sequencer + * only if sequencer is set in mode "not fully configurable", + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +{ + __IO uint32_t smpr = READ_REG(ADCx->SMPR); + + /* Retrieve sampling time bit corresponding to the selected channel */ + /* and shift it to position 0. */ + uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK) + >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ADC_SMPR_SMPSEL0_BITOFFSET_POS) & + 0x1FUL)); + + /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */ + return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1) + | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog + * @{ + */ + +/** + * @brief Set ADC analog watchdog monitored channels: + * a single channel, multiple channels or all channels, + * on ADC group regular. + * @note Once monitored channels are selected, analog watchdog + * is enabled. + * @note In case of need to define a single channel to monitor + * with analog watchdog from sequencer channel definition, + * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). + * @note On this STM32 series, there are 2 kinds of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n + * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n + * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n + * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n + * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDChannelGroup This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG + * @arg @ref LL_ADC_AWD_CH_VBAT_REG + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) +{ + /* Set bits with content of parameter "AWDChannelGroup" with bits position */ + /* in register and register position depending on parameter "AWDy". */ + /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ + /* containing other bits reserved for other purpose. */ + __IO uint32_t *preg; + + if (AWDy == LL_ADC_AWD1) + { + preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL); + } + else + { + preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)); + } + + MODIFY_REG(*preg, + (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), + AWDChannelGroup & AWDy); +} + +/** + * @brief Get ADC analog watchdog monitored channel. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Applicable only when the analog watchdog is set to monitor + * one channel. + * @note On this STM32 series, there are 2 kinds of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n + * CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n + * CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels\n + * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n + * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 (1) + * @arg @ref LL_ADC_AWD3 (1) + * + * (1) On this AWD number, monitored channel can be retrieved + * if only 1 channel is programmed (or none or all channels). + * This function cannot retrieve monitored channel if + * multiple channels are programmed simultaneously + * by bitfield. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + + uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); + + /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ + /* (parameter value LL_ADC_AWD_DISABLE). */ + /* Else, the selected AWD is enabled and is monitoring a group of channels */ + /* or a single channel. */ + if (AnalogWDMonitChannels != 0UL) + { + if (AWDy == LL_ADC_AWD1) + { + if ((AnalogWDMonitChannels & ADC_CFGR1_AWD1SGL) == 0UL) + { + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = ((AnalogWDMonitChannels + | (ADC_AWD_CR23_CHANNEL_MASK) + ) + & (~(ADC_CFGR1_AWD1CH)) + ); + } + else + { + /* AWD monitoring a single channel */ + AnalogWDMonitChannels = (AnalogWDMonitChannels + | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR1_AWD1CH_Pos)) + ); + } + } + else + { + if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + { + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK + | (ADC_CFGR1_AWD1EN) + ); + } + else + { + /* AWD monitoring a single channel */ + /* AWD monitoring a group of channels */ + AnalogWDMonitChannels = (AnalogWDMonitChannels + | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) + | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR1_AWD1CH_Pos) + ); + } + } + } + + return AnalogWDMonitChannels; +} + +/** + * @brief Set ADC analog watchdog thresholds value of both thresholds + * high and low. + * @note If value of only one threshold high or low must be set, + * use function @ref LL_ADC_SetAnalogWDThresholds(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note On this STM32 series, there are 2 kinds of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). + * Examples: + * - Oversampling ratio and shift selected to have ADC conversion data + * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): + * ADC analog watchdog thresholds must be divided by 16. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): + * ADC analog watchdog thresholds must be divided by 4. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): + * ADC analog watchdog thresholds match directly to ADC data register. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n + * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n + * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n + * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n + * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n + * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, + uint32_t AWDThresholdLowValue) +{ + /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ + /* position in register and register position depending on parameter */ + /* "AWDy". */ + /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ + /* containing other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + + MODIFY_REG(*preg, + ADC_TR1_HT1 | ADC_TR1_LT1, + (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); +} + +/** + * @brief Set ADC analog watchdog threshold value of threshold + * high or low. + * @note If values of both thresholds high or low must be set, + * use function @ref LL_ADC_ConfigAnalogWDThresholds(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note On this STM32 series, there are 2 kinds of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * - AWD flexible (instances AWD2, AWD3): + * - channels monitored: flexible on channels monitored, selection is + * channel wise, from from 1 to all channels. + * Specificity of this analog watchdog: Multiple channels can + * be selected. For example: + * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) + * - groups monitored: not selection possible (monitoring on both + * groups regular and injected). + * Channels selected are monitored on groups regular and injected: + * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters + * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). + * Examples: + * - Oversampling ratio and shift selected to have ADC conversion data + * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): + * ADC analog watchdog thresholds must be divided by 16. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): + * ADC analog watchdog thresholds must be divided by 4. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): + * ADC analog watchdog thresholds match directly to ADC data register. + * @note On this STM32 series, setting of this feature is not conditioned to + * ADC state: + * ADC can be disabled, enabled with or without conversion on going + * on ADC group regular. + * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n + * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n + * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n + * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n + * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n + * TR3 LT3 LL_ADC_SetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, + uint32_t AWDThresholdValue) +{ + /* Set bits with content of parameter "AWDThresholdValue" with bits */ + /* position in register and register position depending on parameters */ + /* "AWDThresholdsHighLow" and "AWDy". */ + /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ + /* containing other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, + (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + + MODIFY_REG(*preg, + AWDThresholdsHighLow, + AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); +} + +/** + * @brief Get ADC analog watchdog threshold value of threshold high, + * threshold low or raw data with ADC thresholds high and low + * concatenated. + * @note If raw data with ADC thresholds high and low is retrieved, + * the data of each threshold high or low can be isolated + * using helper macro: + * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). + * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n + * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n + * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n + * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n + * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n + * TR3 LT3 LL_ADC_GetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) +{ + /* Set bits with content of parameter "AWDThresholdValue" with bits */ + /* position in register and register position depending on parameters */ + /* "AWDThresholdsHighLow" and "AWDy". */ + /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ + /* containing other bits reserved for other purpose. */ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, + (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + + ((ADC_AWD_CR3_REGOFFSET & AWDy) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + + return (uint32_t)(READ_BIT(*preg, + (AWDThresholdsHighLow | ADC_TR1_LT1)) + >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) + & ~(AWDThresholdsHighLow & ADC_TR1_LT1))); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling + * @{ + */ + +/** + * @brief Set ADC oversampling scope. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope + * @param ADCx ADC instance + * @param OvsScope This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_DISABLE + * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); +} + +/** + * @brief Get ADC oversampling scope. + * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OVS_DISABLE + * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); +} + +/** + * @brief Set ADC oversampling discontinuous mode (triggered mode) + * on the selected ADC group. + * @note Number of oversampled conversions are done either in: + * - continuous mode (all conversions of oversampling ratio + * are done from 1 trigger) + * - discontinuous mode (each conversion of oversampling ratio + * needs a trigger) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont + * @param ADCx ADC instance + * @param OverSamplingDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_REG_CONT + * @arg @ref LL_ADC_OVS_REG_DISCONT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); +} + +/** + * @brief Get ADC oversampling discontinuous mode (triggered mode) + * on the selected ADC group. + * @note Number of oversampled conversions are done either in: + * - continuous mode (all conversions of oversampling ratio + * are done from 1 trigger) + * - discontinuous mode (each conversion of oversampling ratio + * needs a trigger) + * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OVS_REG_CONT + * @arg @ref LL_ADC_OVS_REG_DISCONT + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); +} + +/** + * @brief Set ADC oversampling + * @note This function set the 2 items of oversampling configuration: + * - ratio + * - shift + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n + * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift + * @param ADCx ADC instance + * @param Ratio This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_RATIO_2 + * @arg @ref LL_ADC_OVS_RATIO_4 + * @arg @ref LL_ADC_OVS_RATIO_8 + * @arg @ref LL_ADC_OVS_RATIO_16 + * @arg @ref LL_ADC_OVS_RATIO_32 + * @arg @ref LL_ADC_OVS_RATIO_64 + * @arg @ref LL_ADC_OVS_RATIO_128 + * @arg @ref LL_ADC_OVS_RATIO_256 + * @param Shift This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_SHIFT_NONE + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 + * @retval None + */ +__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) +{ + MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); +} + +/** + * @brief Get ADC oversampling ratio + * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio + * @param ADCx ADC instance + * @retval Ratio This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_RATIO_2 + * @arg @ref LL_ADC_OVS_RATIO_4 + * @arg @ref LL_ADC_OVS_RATIO_8 + * @arg @ref LL_ADC_OVS_RATIO_16 + * @arg @ref LL_ADC_OVS_RATIO_32 + * @arg @ref LL_ADC_OVS_RATIO_64 + * @arg @ref LL_ADC_OVS_RATIO_128 + * @arg @ref LL_ADC_OVS_RATIO_256 + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); +} + +/** + * @brief Get ADC oversampling shift + * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift + * @param ADCx ADC instance + * @retval Shift This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_SHIFT_NONE + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Enable ADC instance internal voltage regulator. + * @note On this STM32 series, there are three possibilities to enable + * the voltage regulator: + * - by enabling it manually + * using function @ref LL_ADC_EnableInternalRegulator(). + * - by launching a calibration + * using function @ref LL_ADC_StartCalibration(). + * - by enabling the ADC + * using function @ref LL_ADC_Enable(). + * @note On this STM32 series, after ADC internal voltage regulator enable, + * a delay for ADC internal voltage regulator stabilization + * is required before performing a ADC calibration or ADC enable. + * Refer to device datasheet, parameter "tADCVREG_STUP". + * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADVREGEN); +} + +/** + * @brief Disable ADC internal voltage regulator. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS)); +} + +/** + * @brief Get the selected ADC instance internal voltage regulator state. + * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled + * @param ADCx ADC instance + * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the selected ADC instance. + * @note On this STM32 series, after ADC enable, a delay for + * ADC internal analog stabilization is required before performing a + * ADC conversion start. + * Refer to device datasheet, parameter tSTAB. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled and ADC internal voltage regulator enabled. + * @rmtoll CR ADEN LL_ADC_Enable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADEN); +} + +/** + * @brief Disable the selected ADC instance. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be not disabled. Must be enabled without conversion on going + * on group regular. + * @rmtoll CR ADDIS LL_ADC_Disable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADDIS); +} + +/** + * @brief Get the selected ADC instance enable state. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll CR ADEN LL_ADC_IsEnabled + * @param ADCx ADC instance + * @retval 0: ADC is disabled, 1: ADC is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the selected ADC instance disable state. + * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing + * @param ADCx ADC instance + * @retval 0: no ADC disable command on going. + */ +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); +} + +/** + * @brief Start ADC calibration in the mode single-ended + * or differential (for devices with differential mode available). + * @note On this STM32 series, a minimum number of ADC clock cycles + * are required between ADC end of calibration and ADC enable. + * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. + * @note In case of usage of ADC with DMA transfer: + * On this STM32 series, ADC DMA transfer request should be disabled + * during calibration: + * Calibration factor is available in data register + * and also transferred by DMA. + * To not insert ADC calibration factor among ADC conversion data + * in array variable, DMA transfer must be disabled during + * calibration. + * (DMA transfer setting backup and disable before calibration, + * DMA transfer setting restore after calibration. + * Refer to functions @ref LL_ADC_REG_GetDMATransfer(), + * @ref LL_ADC_REG_SetDMATransfer() ). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADCAL LL_ADC_StartCalibration + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADCAL); +} + +/** + * @brief Get ADC calibration state. + * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing + * @param ADCx ADC instance + * @retval 0: calibration complete, 1: calibration in progress. + */ +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Start ADC group regular conversion. + * @note On this STM32 series, this function is relevant for both + * internal trigger (SW start) and external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * will start at next trigger event (on the selected trigger edge) + * following the ADC start conversion command. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion on going on group regular, + * without conversion stop command on going on group regular, + * without ADC disable command on going. + * @rmtoll CR ADSTART LL_ADC_REG_StartConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADSTART); +} + +/** + * @brief Stop ADC group regular conversion. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled with conversion on going on group regular, + * without ADC disable command on going. + * @rmtoll CR ADSTP LL_ADC_REG_StopConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADSTP); +} + +/** + * @brief Get ADC group regular conversion state. + * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing + * @param ADCx ADC instance + * @retval 0: no conversion is on going on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group regular command of conversion stop state + * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing + * @param ADCx ADC instance + * @retval 0: no command of conversion stop is on going on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 10 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 8 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +{ + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 6 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) +{ + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management + * @{ + */ + +/** + * @brief Get flag ADC ready. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC channel configuration ready. + * @note On this STM32 series, after modifying sequencer + * it is mandatory to wait for the assertion of CCRDY flag + * using @ref LL_ADC_IsActiveFlag_CCRDY(). + * Otherwise, performing some actions (configuration update, + * ADC conversion start, ... ) will be ignored. + * Functions requiring wait for CCRDY flag are: + * @ref LL_ADC_REG_SetSequencerLength() + * @ref LL_ADC_REG_SetSequencerRanks() + * @ref LL_ADC_REG_SetSequencerChannels() + * @ref LL_ADC_REG_SetSequencerChAdd() + * @ref LL_ADC_REG_SetSequencerChRem() + * @ref LL_ADC_REG_SetSequencerScanDirection() + * @ref LL_ADC_REG_SetSequencerConfigurable() + * @note Duration of ADC channel configuration ready: CCRDY handshake + * requires 1APB + 2 ADC + 3 APB cycles after the channel configuration + * has been changed. + * @rmtoll ISR CCRDY LL_ADC_IsActiveFlag_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of unitary conversion. + * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of sequence conversions. + * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular overrun. + * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of sampling phase. + * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 1 flag + * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 2. + * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 3. + * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC end of calibration. + * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL); +} + +/** + * @brief Clear flag ADC ready. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY); +} + +/** + * @brief Clear flag ADC channel configuration ready. + * @rmtoll ISR CCRDY LL_ADC_ClearFlag_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY); +} + +/** + * @brief Clear flag ADC group regular end of unitary conversion. + * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); +} + +/** + * @brief Clear flag ADC group regular end of sequence conversions. + * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); +} + +/** + * @brief Clear flag ADC group regular overrun. + * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); +} + +/** + * @brief Clear flag ADC group regular end of sampling phase. + * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); +} + +/** + * @brief Clear flag ADC analog watchdog 1. + * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1); +} + +/** + * @brief Clear flag ADC analog watchdog 2. + * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2); +} + +/** + * @brief Clear flag ADC analog watchdog 3. + * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); +} + +/** + * @brief Clear flag ADC end of calibration. + * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_IT_Management ADC IT management + * @{ + */ + +/** + * @brief Enable ADC ready. + * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY); +} + +/** + * @brief Enable interruption ADC channel configuration ready. + * @rmtoll IER ADRDYIE LL_ADC_EnableIT_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY); +} + +/** + * @brief Enable interruption ADC group regular end of unitary conversion. + * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOC); +} + +/** + * @brief Enable interruption ADC group regular end of sequence conversions. + * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOS); +} + +/** + * @brief Enable ADC group regular interruption overrun. + * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_OVR); +} + +/** + * @brief Enable interruption ADC group regular end of sampling. + * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); +} + +/** + * @brief Enable interruption ADC analog watchdog 1. + * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD1); +} + +/** + * @brief Enable interruption ADC analog watchdog 2. + * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD2); +} + +/** + * @brief Enable interruption ADC analog watchdog 3. + * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD3); +} + +/** + * @brief Enable interruption ADC end of calibration. + * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL); +} + +/** + * @brief Disable interruption ADC ready. + * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY); +} + +/** + * @brief Disable interruption ADC channel configuration ready. + * @rmtoll IER ADRDYIE LL_ADC_DisableIT_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY); +} + +/** + * @brief Disable interruption ADC group regular end of unitary conversion. + * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC); +} + +/** + * @brief Disable interruption ADC group regular end of sequence conversions. + * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS); +} + +/** + * @brief Disable interruption ADC group regular overrun. + * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR); +} + +/** + * @brief Disable interruption ADC group regular end of sampling. + * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); +} + +/** + * @brief Disable interruption ADC analog watchdog 1. + * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1); +} + +/** + * @brief Disable interruption ADC analog watchdog 2. + * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2); +} + +/** + * @brief Disable interruption ADC analog watchdog 3. + * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3); +} + +/** + * @brief Disable interruption ADC end of calibration. + * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL); +} + +/** + * @brief Get state of interruption ADC ready + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC channel configuration ready. + * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_CCRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of unitary conversion + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular overrun + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of sampling + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC analog watchdog 1 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption Get ADC analog watchdog 2 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption Get ADC analog watchdog 3 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC end of calibration + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/* Initialization of some features of ADC common parameters and multimode */ +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); + +/* De-initialization of ADC instance */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); + +/* Initialization of some features of ADC instance */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); + +/* Initialization of some features of ADC instance and ADC group regular */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_LL_ADC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dma.h (revision 3) @@ -0,0 +1,2272 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_LL_DMA_H +#define STM32G0xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx.h" +#include "stm32g0xx_ll_dmamux.h" + +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), +#if defined(DMA1_Channel6_BASE) + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), +#endif +#if defined(DMA1_Channel7_BASE) + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE), +#endif +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @param __DMA_INSTANCE__ DMAx + * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0). + */ +#define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ +(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7) +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#if defined(DMA1_Channel6) +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +#endif +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#if defined(DMA1_Channel6) +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +#endif +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */ +#if defined(DMA1_Channel6) +#define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */ +#endif +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#if defined(DMA2) +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) +#else /* DMA1 */ +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) +#endif + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#if defined(DMA2) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + LL_DMA_CHANNEL_5) +#endif +#endif /* DMA2 */ + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#if defined(DMA2) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + DMA1_Channel5) +#endif +#endif /* DMA2 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); +} + +/** + * @brief Set DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_COM + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_USART4_RX + * @arg @ref LL_DMAMUX_REQ_USART4_TX + * @arg @ref LL_DMAMUX_REQ_UCPD1_RX + * @arg @ref LL_DMAMUX_REQ_UCPD1_TX + * @arg @ref LL_DMAMUX_REQ_UCPD2_RX + * @arg @ref LL_DMAMUX_REQ_UCPD2_TX + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); + MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMA request for DMA Channels on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_COM + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_USART4_RX + * @arg @ref LL_DMAMUX_REQ_USART4_TX + * @arg @ref LL_DMAMUX_REQ_UCPD1_RX + * @arg @ref LL_DMAMUX_REQ_UCPD1_TX + * @arg @ref LL_DMAMUX_REQ_UCPD2_RX + * @arg @ref LL_DMAMUX_REQ_UCPD2_TX + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); + return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); +} + +#endif +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); +} + +#endif +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); +} + +#endif +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); +} + +#endif +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); +} + +#endif +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); +} + +#endif +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); +} + +#endif +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); +} + +#endif +/** + * @brief Clear Channel 1 global interrupt flag. + * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, + LL_DMA_ClearFlag_TE1. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @note Do not Clear Channel 2 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, + LL_DMA_ClearFlag_TE2. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @note Do not Clear Channel 3 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, + LL_DMA_ClearFlag_TE3. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @note Do not Clear Channel 4 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, + LL_DMA_ClearFlag_TE4. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @note Do not Clear Channel 5 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, + LL_DMA_ClearFlag_TE5. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 global interrupt flag. + * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, + LL_DMA_ClearFlag_TE6. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} + +#endif +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 global interrupt flag. + * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, + LL_DMA_ClearFlag_TE7. bug id 2.4.1 in Product Errata Sheet. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} + +#endif +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} + +#endif +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} + +#endif +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} + +#endif +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} + +#endif +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} + +#endif +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} + +#endif +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_LL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_dmamux.h (revision 3) @@ -0,0 +1,1828 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_dmamux.h + * @author MCD Application Team + * @brief Header file of DMAMUX LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_LL_DMAMUX_H +#define STM32G0xx_LL_DMAMUX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx.h" + +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined (DMAMUX1) + +/** @defgroup DMAMUX_LL DMAMUX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants + * @{ + */ +/* Define used to get DMAMUX CCR register size */ +#define DMAMUX_CCR_SIZE 0x00000004UL + +/* Define used to get DMAMUX RGCR register size */ +#define DMAMUX_RGCR_SIZE 0x00000004UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants + * @{ + */ +/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function + * @{ + */ +#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#if defined(DMAMUX1_Channel5) +#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#endif +#if defined(DMAMUX1_Channel6) +#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#endif +#if defined(DMA2) +#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#endif /* DMA2 */ +#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function + * @{ + */ +#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */ +#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */ +#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */ +#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */ +#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */ +#if defined(DMAMUX1_Channel5) +#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */ +#endif +#if defined(DMAMUX1_Channel6) +#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */ +#endif +#if defined(DMA2) +#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */ +#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */ +#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */ +#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */ +#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */ +#endif /* DMA2 */ +#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */ +#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions + * @{ + */ +#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */ +#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request + * @{ + */ +#define LL_DMAMUX_REQ_MEM2MEM 0x00000000U /*!< memory to memory transfer */ +#define LL_DMAMUX_REQ_GENERATOR0 0x00000001U /*!< DMAMUX request generator 0 */ +#define LL_DMAMUX_REQ_GENERATOR1 0x00000002U /*!< DMAMUX request generator 1 */ +#define LL_DMAMUX_REQ_GENERATOR2 0x00000003U /*!< DMAMUX request generator 2 */ +#define LL_DMAMUX_REQ_GENERATOR3 0x00000004U /*!< DMAMUX request generator 3 */ +#define LL_DMAMUX_REQ_ADC1 0x00000005U /*!< DMAMUX ADC1 request */ +#if defined(AES) +#define LL_DMAMUX_REQ_AES_IN 0x00000006U /*!< DMAMUX AES_IN request */ +#define LL_DMAMUX_REQ_AES_OUT 0x00000007U /*!< DMAMUX AES_OUT request */ +#endif +#if defined(DAC1) +#define LL_DMAMUX_REQ_DAC1_CH1 0x00000008U /*!< DMAMUX DAC_CH1 request */ +#define LL_DMAMUX_REQ_DAC1_CH2 0x00000009U /*!< DMAMUX DAC_CH2 request */ +#endif +#define LL_DMAMUX_REQ_I2C1_RX 0x0000000AU /*!< DMAMUX I2C1 RX request */ +#define LL_DMAMUX_REQ_I2C1_TX 0x0000000BU /*!< DMAMUX I2C1 TX request */ +#define LL_DMAMUX_REQ_I2C2_RX 0x0000000CU /*!< DMAMUX I2C2 RX request */ +#define LL_DMAMUX_REQ_I2C2_TX 0x0000000DU /*!< DMAMUX I2C2 TX request */ +#if defined(LPUART1) +#define LL_DMAMUX_REQ_LPUART1_RX 0x0000000EU /*!< DMAMUX LPUART1 RX request */ +#define LL_DMAMUX_REQ_LPUART1_TX 0x0000000FU /*!< DMAMUX LPUART1 TX request */ +#endif +#define LL_DMAMUX_REQ_SPI1_RX 0x00000010U /*!< DMAMUX SPI1 RX request */ +#define LL_DMAMUX_REQ_SPI1_TX 0x00000011U /*!< DMAMUX SPI1 TX request */ +#define LL_DMAMUX_REQ_SPI2_RX 0x00000012U /*!< DMAMUX SPI2 RX request */ +#define LL_DMAMUX_REQ_SPI2_TX 0x00000013U /*!< DMAMUX SPI2 TX request */ +#define LL_DMAMUX_REQ_TIM1_CH1 0x00000014U /*!< DMAMUX TIM1 CH1 request */ +#define LL_DMAMUX_REQ_TIM1_CH2 0x00000015U /*!< DMAMUX TIM1 CH2 request */ +#define LL_DMAMUX_REQ_TIM1_CH3 0x00000016U /*!< DMAMUX TIM1 CH3 request */ +#define LL_DMAMUX_REQ_TIM1_CH4 0x00000017U /*!< DMAMUX TIM1 CH4 request */ +#define LL_DMAMUX_REQ_TIM1_TRIG_COM 0x00000018U /*!< DMAMUX TIM1 TRIG COM request */ +#define LL_DMAMUX_REQ_TIM1_UP 0x00000019U /*!< DMAMUX TIM1 UP request */ +#if defined(TIM2) +#define LL_DMAMUX_REQ_TIM2_CH1 0x0000001AU /*!< DMAMUX TIM2 CH1 request */ +#define LL_DMAMUX_REQ_TIM2_CH2 0x0000001BU /*!< DMAMUX TIM2 CH2 request */ +#define LL_DMAMUX_REQ_TIM2_CH3 0x0000001CU /*!< DMAMUX TIM2 CH3 request */ +#define LL_DMAMUX_REQ_TIM2_CH4 0x0000001DU /*!< DMAMUX TIM2 CH4 request */ +#define LL_DMAMUX_REQ_TIM2_TRIG 0x0000001EU /*!< DMAMUX TIM2 TRIG request */ +#define LL_DMAMUX_REQ_TIM2_UP 0x0000001FU /*!< DMAMUX TIM2 UP request */ +#endif +#define LL_DMAMUX_REQ_TIM3_CH1 0x00000020U /*!< DMAMUX TIM3 CH1 request */ +#define LL_DMAMUX_REQ_TIM3_CH2 0x00000021U /*!< DMAMUX TIM3 CH2 request */ +#define LL_DMAMUX_REQ_TIM3_CH3 0x00000022U /*!< DMAMUX TIM3 CH3 request */ +#define LL_DMAMUX_REQ_TIM3_CH4 0x00000023U /*!< DMAMUX TIM3 CH4 request */ +#define LL_DMAMUX_REQ_TIM3_TRIG 0x00000024U /*!< DMAMUX TIM3 TRIG request */ +#define LL_DMAMUX_REQ_TIM3_UP 0x00000025U /*!< DMAMUX TIM3 UP request */ +#if defined(TIM6) +#define LL_DMAMUX_REQ_TIM6_UP 0x00000026U /*!< DMAMUX TIM6 UP request */ +#endif +#if defined(TIM7) +#define LL_DMAMUX_REQ_TIM7_UP 0x00000027U /*!< DMAMUX TIM7 UP request */ +#endif +#if defined(TIM15) +#define LL_DMAMUX_REQ_TIM15_CH1 0x00000028U /*!< DMAMUX TIM15 CH1 request */ +#define LL_DMAMUX_REQ_TIM15_CH2 0x00000029U /*!< DMAMUX TIM15 CH2 request */ +#define LL_DMAMUX_REQ_TIM15_TRIG_COM 0x0000002AU /*!< DMAMUX TIM15 TRIG COM request */ +#define LL_DMAMUX_REQ_TIM15_UP 0x0000002BU /*!< DMAMUX TIM15 UP request */ +#endif +#define LL_DMAMUX_REQ_TIM16_CH1 0x0000002CU /*!< DMAMUX TIM16 CH1 request */ +#define LL_DMAMUX_REQ_TIM16_COM 0x0000002DU /*!< DMAMUX TIM16 COM request */ +#define LL_DMAMUX_REQ_TIM16_UP 0x0000002EU /*!< DMAMUX TIM16 UP request */ +#define LL_DMAMUX_REQ_TIM17_CH1 0x0000002FU /*!< DMAMUX TIM17 CH1 request */ +#define LL_DMAMUX_REQ_TIM17_COM 0x00000030U /*!< DMAMUX TIM17 COM request */ +#define LL_DMAMUX_REQ_TIM17_UP 0x00000031U /*!< DMAMUX TIM17 UP request */ +#define LL_DMAMUX_REQ_USART1_RX 0x00000032U /*!< DMAMUX USART1 RX request */ +#define LL_DMAMUX_REQ_USART1_TX 0x00000033U /*!< DMAMUX USART1 TX request */ +#define LL_DMAMUX_REQ_USART2_RX 0x00000034U /*!< DMAMUX USART2 RX request */ +#define LL_DMAMUX_REQ_USART2_TX 0x00000035U /*!< DMAMUX USART2 TX request */ +#if defined(USART3) +#define LL_DMAMUX_REQ_USART3_RX 0x00000036U /*!< DMAMUX USART3 RX request */ +#define LL_DMAMUX_REQ_USART3_TX 0x00000037U /*!< DMAMUX USART3 TX request */ +#endif +#if defined(USART4) +#define LL_DMAMUX_REQ_USART4_RX 0x00000038U /*!< DMAMUX USART4 RX request */ +#define LL_DMAMUX_REQ_USART4_TX 0x00000039U /*!< DMAMUX USART4 TX request */ +#endif +#if defined(UCPD1) +#define LL_DMAMUX_REQ_UCPD1_RX 0x0000003AU /*!< DMAMUX UCPD1 RX request */ +#define LL_DMAMUX_REQ_UCPD1_TX 0x0000003BU /*!< DMAMUX UCPD1 TX request */ +#endif +#if defined(UCPD2) +#define LL_DMAMUX_REQ_UCPD2_RX 0x0000003CU /*!< DMAMUX UCPD2 RX request */ +#define LL_DMAMUX_REQ_UCPD2_TX 0x0000003DU /*!< DMAMUX UCPD2 TX request */ +#endif + +#if defined(I2C3) +#define LL_DMAMUX_REQ_I2C3_RX 0x0000003EU /*!< DMAMUX I2C3 RX request */ +#define LL_DMAMUX_REQ_I2C3_TX 0x0000003FU /*!< DMAMUX I2C3 TX request */ +#endif + +#if defined(LPUART2) +#define LL_DMAMUX_REQ_LPUART2_RX 0x00000040U /*!< DMAMUX LPUART2 RX request */ +#define LL_DMAMUX_REQ_LPUART2_TX 0x00000041U /*!< DMAMUX LPUART2 TX request */ +#endif + +#if defined(SPI3) +#define LL_DMAMUX_REQ_SPI3_RX 0x00000042U /*!< DMAMUX SPI3 RX request */ +#define LL_DMAMUX_REQ_SPI3_TX 0x00000043U /*!< DMAMUX SPI3 TX request */ +#endif + +#if defined(TIM4) +#define LL_DMAMUX_REQ_TIM4_CH1 0x00000044U /*!< DMAMUX TIM4 CH1 request */ +#define LL_DMAMUX_REQ_TIM4_CH2 0x00000045U /*!< DMAMUX TIM4 CH2 request */ +#define LL_DMAMUX_REQ_TIM4_CH3 0x00000046U /*!< DMAMUX TIM4 CH3 request */ +#define LL_DMAMUX_REQ_TIM4_CH4 0x00000047U /*!< DMAMUX TIM4 CH4 request */ +#define LL_DMAMUX_REQ_TIM4_TRIG 0x00000048U /*!< DMAMUX TIM4 TRIG request */ +#define LL_DMAMUX_REQ_TIM4_UP 0x00000049U /*!< DMAMUX TIM4 UP request */ +#endif + +#if defined(USART5) +#define LL_DMAMUX_REQ_USART5_RX 0x0000004AU /*!< DMAMUX USART5 RX request */ +#define LL_DMAMUX_REQ_USART5_TX 0x0000004BU /*!< DMAMUX USART5 TX request */ +#endif + +#if defined(USART6) +#define LL_DMAMUX_REQ_USART6_RX 0x0000004CU /*!< DMAMUX USART6 RX request */ +#define LL_DMAMUX_REQ_USART6_TX 0x0000004DU /*!< DMAMUX USART6 TX request */ +#endif + +#if defined(STM32G0C1xx)||defined(STM32G0B1xx) +#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART6_TX +#elif defined(STM32G0B0xx) +#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART4_TX +#elif defined(STM32G081xx)||defined(STM32G071xx) +#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_UCPD2_TX +#elif defined(STM32G070xx) +#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART4_TX +#else +#define LL_DMAMUX_MAX_REQ LL_DMAMUX_REQ_USART2_TX +#endif +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel + * @{ + */ +#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */ +#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */ +#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */ +#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */ +#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */ +#if defined(DMAMUX1_Channel5) +#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */ +#endif +#if defined(DMAMUX1_Channel6) +#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */ +#endif +#if defined(DMA2) +#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA2 Channel 1 */ +#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 2 */ +#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 3 */ +#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 4 */ +#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 5 */ +#endif +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity + * @{ + */ +#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */ +#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */ +#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */ +#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event + * @{ + */ +#define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U /*!< Synchronization signal from EXTI Line0 */ +#define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */ +#define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */ +#define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */ +#define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */ +#define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */ +#define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */ +#define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */ +#define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */ +#define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */ +#define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */ +#define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */ +#define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */ +#define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 3 */ +#define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line1 4 */ +#define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line1 5 */ +#define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */ +#define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */ +#if defined(LPTIM1) +#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */ +#endif +#if defined(LPTIM2) +#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Output */ +#endif +#define LL_DMAMUX_SYNC_TIM14_OC (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from TIM14 OC */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel + * @{ + */ +#define LL_DMAMUX_REQ_GEN_0 0x00000000U +#define LL_DMAMUX_REQ_GEN_1 0x00000001U +#define LL_DMAMUX_REQ_GEN_2 0x00000002U +#define LL_DMAMUX_REQ_GEN_3 0x00000003U +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity + * @{ + */ +#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */ +#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */ +#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */ +#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */ +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation + * @{ + */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U /*!< Request signal generation from EXTI Line0 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */ +#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */ +#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */ +#if defined(LPTIM1) +#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */ +#endif +#if defined(LPTIM2) +#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Output */ +#endif +#define LL_DMAMUX_REQ_GEN_TIM14_OC (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from TIM14 OC */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros + * @{ + */ + +/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMAMUX register + * @param __INSTANCE__ DMAMUX Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions + * @{ + */ + +/** @defgroup DMAMUX_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Set DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_COM + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_USART4_RX + * @arg @ref LL_DMAMUX_REQ_USART4_TX + * @arg @ref LL_DMAMUX_REQ_UCPD1_RX + * @arg @ref LL_DMAMUX_REQ_UCPD1_TX + * @arg @ref LL_DMAMUX_REQ_UCPD2_RX + * @arg @ref LL_DMAMUX_REQ_UCPD2_TX + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); +} + +/** + * @brief Get DMAMUX request ID for DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_MEM2MEM + * @arg @ref LL_DMAMUX_REQ_GENERATOR0 + * @arg @ref LL_DMAMUX_REQ_GENERATOR1 + * @arg @ref LL_DMAMUX_REQ_GENERATOR2 + * @arg @ref LL_DMAMUX_REQ_GENERATOR3 + * @arg @ref LL_DMAMUX_REQ_ADC1 + * @arg @ref LL_DMAMUX_REQ_AES_IN + * @arg @ref LL_DMAMUX_REQ_AES_OUT + * @arg @ref LL_DMAMUX_REQ_DAC1_CH1 + * @arg @ref LL_DMAMUX_REQ_DAC1_CH2 + * @arg @ref LL_DMAMUX_REQ_I2C1_RX + * @arg @ref LL_DMAMUX_REQ_I2C1_TX + * @arg @ref LL_DMAMUX_REQ_I2C2_RX + * @arg @ref LL_DMAMUX_REQ_I2C2_TX + * @arg @ref LL_DMAMUX_REQ_LPUART1_RX + * @arg @ref LL_DMAMUX_REQ_LPUART1_TX + * @arg @ref LL_DMAMUX_REQ_SPI1_RX + * @arg @ref LL_DMAMUX_REQ_SPI1_TX + * @arg @ref LL_DMAMUX_REQ_SPI2_RX + * @arg @ref LL_DMAMUX_REQ_SPI2_TX + * @arg @ref LL_DMAMUX_REQ_TIM1_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM1_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM1_UP + * @arg @ref LL_DMAMUX_REQ_TIM2_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM2_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM2_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM2_UP + * @arg @ref LL_DMAMUX_REQ_TIM3_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH3 + * @arg @ref LL_DMAMUX_REQ_TIM3_CH4 + * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG + * @arg @ref LL_DMAMUX_REQ_TIM3_UP + * @arg @ref LL_DMAMUX_REQ_TIM6_UP + * @arg @ref LL_DMAMUX_REQ_TIM7_UP + * @arg @ref LL_DMAMUX_REQ_TIM15_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM15_CH2 + * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG_COM + * @arg @ref LL_DMAMUX_REQ_TIM15_UP + * @arg @ref LL_DMAMUX_REQ_TIM16_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM16_COM + * @arg @ref LL_DMAMUX_REQ_TIM16_UP + * @arg @ref LL_DMAMUX_REQ_TIM17_CH1 + * @arg @ref LL_DMAMUX_REQ_TIM17_COM + * @arg @ref LL_DMAMUX_REQ_TIM17_UP + * @arg @ref LL_DMAMUX_REQ_USART1_RX + * @arg @ref LL_DMAMUX_REQ_USART1_TX + * @arg @ref LL_DMAMUX_REQ_USART2_RX + * @arg @ref LL_DMAMUX_REQ_USART2_TX + * @arg @ref LL_DMAMUX_REQ_USART3_RX + * @arg @ref LL_DMAMUX_REQ_USART3_TX + * @arg @ref LL_DMAMUX_REQ_USART4_RX + * @arg @ref LL_DMAMUX_REQ_USART4_TX + * @arg @ref LL_DMAMUX_REQ_UCPD1_RX + * @arg @ref LL_DMAMUX_REQ_UCPD1_TX + * @arg @ref LL_DMAMUX_REQ_UCPD2_RX + * @arg @ref LL_DMAMUX_REQ_UCPD2_TX + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); +} + +/** + * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is synchronized. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is synchronized. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_NO_EVENT + * @arg @ref LL_DMAMUX_SYNC_POL_RISING + * @arg @ref LL_DMAMUX_SYNC_POL_FALLING + * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); +} + +/** + * @brief Enable the Event Generation on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Disable the Event Generation on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); +} + +/** + * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the synchronization mode. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SE LL_DMAMUX_EnableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Disable the synchronization mode. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SE LL_DMAMUX_DisableSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); +} + +/** + * @brief Check if the synchronization mode is enabled or disabled. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); +} + +/** + * @brief Set DMAMUX synchronization ID on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @param SyncID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX_SYNC_TIM14_OC + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +{ + (void)(DMAMUXx); + MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); +} + +/** + * @brief Get DMAMUX synchronization ID on DMAMUX Channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14 + * @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT + * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT + * @arg @ref LL_DMAMUX_SYNC_TIM14_OC + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID)); +} + +/** + * @brief Enable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Disable the Request Generator. + * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); +} + +/** + * @brief Check if the Request Generator is enabled or disabled. + * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); +} + +/** + * @brief Set the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); +} + +/** + * @brief Get the polarity of the signal on which the DMA request is generated. + * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING + * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); +} + +/** + * @brief Set the number of DMA request that will be autorized after a generation event. + * @note This field can only be written when Generator is disabled. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); +} + +/** + * @brief Get the number of DMA request that will be autorized after a generation event. + * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Between Min_Data = 1 and Max_Data = 32 + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); +} + +/** + * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @param RequestSignalID This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +{ + (void)(DMAMUXx); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); +} + +/** + * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x. + * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14 + * @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2 + * @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3 + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT + * @arg @ref LL_DMAMUX_REQ_GEN_TIM14_OC + */ +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Synchronization Event Overrun Flag Channel 0. + * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 1. + * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 2. + * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 3. + * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Synchronization Event Overrun Flag Channel 4. + * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); +} + +#if defined(DMAMUX1_Channel5) +/** + * @brief Get Synchronization Event Overrun Flag Channel 5. + * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); +} + +#endif +#if defined(DMAMUX1_Channel6) +/** + * @brief Get Synchronization Event Overrun Flag Channel 6. + * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); +} + +#endif +#if defined(DMAMUX1_Channel7) +/** + * @brief Get Synchronization Event Overrun Flag Channel 7. + * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); +} + +#endif +#if defined(DMAMUX1_Channel8) +/** + * @brief Get Synchronization Event Overrun Flag Channel 8. + * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); +} + +#endif +#if defined(DMAMUX1_Channel9) +/** + * @brief Get Synchronization Event Overrun Flag Channel 9. + * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); +} + +#endif +#if defined(DMAMUX1_Channel10) +/** + * @brief Get Synchronization Event Overrun Flag Channel 10. + * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); +} + +#endif +#if defined(DMAMUX1_Channel11) +/** + * @brief Get Synchronization Event Overrun Flag Channel 11. + * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); +} + +#endif +/** + * @brief Get Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 0. + * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 1. + * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 2. + * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 3. + * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); +} + +/** + * @brief Clear Synchronization Event Overrun Flag Channel 4. + * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); +} + +#if defined(DMAMUX1_Channel5) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 5. + * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); +} + +#endif +#if defined(DMAMUX1_Channel6) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 6. + * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); +} + +#endif +#if defined(DMAMUX1_Channel7) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 7. + * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); +} + +#endif +#if defined(DMAMUX1_Channel8) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 8. + * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); +} + +#endif +#if defined(DMAMUX1_Channel9) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 9. + * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); +} + +#endif +#if defined(DMAMUX1_Channel10) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 10. + * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); +} + +#endif +#if defined(DMAMUX1_Channel11) +/** + * @brief Clear Synchronization Event Overrun Flag Channel 11. + * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); +} + +#endif +/** + * @brief Clear Request Generator 0 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0); +} + +/** + * @brief Clear Request Generator 1 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1); +} + +/** + * @brief Clear Request Generator 2 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2); +} + +/** + * @brief Clear Request Generator 3 Trigger Event Overrun Flag. + * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3 + * @param DMAMUXx DMAMUXx DMAMUXx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +{ + (void)(DMAMUXx); + SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3); +} + +/** + * @} + */ + +/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); +} + +/** + * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. + * DMAMUX channel 7 to 11 are mapped to DMA2 channel 1 to 5 (**** only available on chip which support DMA2 ****). + * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO + * @param DMAMUXx DMAMUXx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_CHANNEL_0 + * @arg @ref LL_DMAMUX_CHANNEL_1 + * @arg @ref LL_DMAMUX_CHANNEL_2 + * @arg @ref LL_DMAMUX_CHANNEL_3 + * @arg @ref LL_DMAMUX_CHANNEL_4 + * @arg @ref LL_DMAMUX_CHANNEL_5 (**** only available on some devices ****) + * @arg @ref LL_DMAMUX_CHANNEL_6 (**** only available on some devices ****) + * + * @arg All the next values are only available on chip which support DMA2: + * @arg @ref LL_DMAMUX_CHANNEL_7 + * @arg @ref LL_DMAMUX_CHANNEL_8 + * @arg @ref LL_DMAMUX_CHANNEL_9 + * @arg @ref LL_DMAMUX_CHANNEL_10 + * @arg @ref LL_DMAMUX_CHANNEL_11 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +{ + (void)(DMAMUXx); + return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x. + * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval None + */ +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); +} + +/** + * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled. + * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO + * @param DMAMUXx DMAMUXx Instance + * @param RequestGenChannel This parameter can be one of the following values: + * @arg @ref LL_DMAMUX_REQ_GEN_0 + * @arg @ref LL_DMAMUX_REQ_GEN_1 + * @arg @ref LL_DMAMUX_REQ_GEN_2 + * @arg @ref LL_DMAMUX_REQ_GEN_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +{ + (void)(DMAMUXx); + return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMAMUX1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_LL_DMAMUX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_exti.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_exti.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_exti.h (revision 3) @@ -0,0 +1,1559 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_LL_EXTI_H +#define STM32G0xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx.h" + +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +#define LL_EXTI_REGISTER_PINPOS_SHFT 16u /*!< Define used to shift pin position in EXTICR register */ + +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ +#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) + uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ +#endif + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR1_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ +#endif +#if defined(EXTI_IMR1_IM17) +#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#endif +#if defined(EXTI_IMR1_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#endif +#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR1_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR1_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR1_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ +#endif +#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ +#if defined(EXTI_IMR1_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR1_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR1_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR1_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR1_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR1_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR1_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR1_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved*/ + +#if defined(EXTI_IMR2_IM32) +#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */ +#endif +#if defined(EXTI_IMR2_IM33) +#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */ +#endif +#if defined(EXTI_IMR2_IM34) +#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */ +#endif +#if defined(EXTI_IMR2_IM35) +#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */ +#endif +#if defined(EXTI_IMR2_IM36) +#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */ +#endif +#if defined(EXTI_IMR2_IM32) || defined(EXTI_IMR2_IM33) || defined(EXTI_IMR2_IM34) || defined(EXTI_IMR2_IM35) || defined(EXTI_IMR2_IM36) +#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/ +#endif + +#define LL_EXTI_LINE_ALL 0xFFFFFFFFU /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup EXTI_LL_EC_CONFIG_PORT EXTI CONFIG PORT + * @{ + */ +#define LL_EXTI_CONFIG_PORTA 0U /*!< EXTI PORT A */ +#define LL_EXTI_CONFIG_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */ +#define LL_EXTI_CONFIG_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */ +#if defined(GPIOD_BASE) +#define LL_EXTI_CONFIG_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */ +#endif /*GPIOD_BASE*/ +#if defined(GPIOE_BASE) +#define LL_EXTI_CONFIG_PORTE EXTI_EXTICR1_EXTI0_2 /*!< EXTI PORT E */ +#endif /*GPIOE_BASE*/ +#define LL_EXTI_CONFIG_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_CONFIG_LINE EXTI CONFIG LINE + * @{ + */ +#define LL_EXTI_CONFIG_LINE0 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE1 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE2 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_16 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE3 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_24 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE4 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE5 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE6 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_16 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE7 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_24 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE8 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_EXTI_CONFIG_LINE9 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_EXTI_CONFIG_LINE10 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_16 | EXTICR[2] */ +#define LL_EXTI_CONFIG_LINE11 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_24 | EXTICR[2] */ +#define LL_EXTI_CONFIG_LINE12 ((0uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_EXTI_CONFIG_LINE13 ((8uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_EXTI_CONFIG_LINE14 ((16uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_16 | EXTICR[3] */ +#define LL_EXTI_CONFIG_LINE15 ((24uL << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_24 | EXTICR[3] */ +/** + * @} + */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR1, ExtiLine); +} + +#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 + * @note The reset value for the direct lines (lines 32 & 33) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR2, ExtiLine); +} +#endif + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR1, ExtiLine); +} + +#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 + * @note The reset value for the direct lines (lines 32 & 33) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR2, ExtiLine); +} +#endif + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 + * @note The reset value for the direct lines (lines 32 & 33) + * is set to 1 in order to enable the interrupt by default. + * @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR1, ExtiLine); + +} + +#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Enable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR2, ExtiLine); +} +#endif +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR1, ExtiLine); +} + +#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Disable ExtiLine Event request for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR2, ExtiLine); +} +#endif +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 + * @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_32 + * @arg @ref LL_EXTI_LINE_33 + * @arg @ref LL_EXTI_LINE_34 + * @arg @ref LL_EXTI_LINE_35 + * @arg @ref LL_EXTI_LINE_36 + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR1, ExtiLine); + +} +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR2, ExtiLine); + +} +#endif + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR1, ExtiLine); + +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR2, ExtiLine); + +} +#endif + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Check if rising edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR1, ExtiLine); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR2, ExtiLine); +} +#endif + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR1, ExtiLine); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR2, ExtiLine); +} +#endif + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Check if falling edge trigger is enabled for Lines in range 32 to 63 + * @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER1, ExtiLine); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Generate a software Interrupt Event for Lines in range 32 to 63 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER2, ExtiLine); +} +#endif + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_IsActiveFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Check if the ExtLine Falling Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR2 FPIFx LL_EXTI_IsActiveFallingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif + +/** + * @brief Read ExtLine Combination Falling Flag for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_ReadFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FPR1, ExtiLine)); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Read ExtLine Combination Falling Flag for Lines in range 32 to 63 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR2 FPIFx LL_EXTI_ReadFallingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_32_63(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FPR2, ExtiLine)); +} +#endif + +/** + * @brief Clear ExtLine Falling Flags for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_ClearFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->FPR1, ExtiLine); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Clear ExtLine Falling Flags for Lines in range 32 to 63 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR2 FPIFx LL_EXTI_ClearFallingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->FPR2, ExtiLine); +} +#endif + +/** + * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_IsActiveRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 32 to 63 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR2 RPIFx LL_EXTI_IsActiveRisingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_32_63(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RPR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif + +/** + * @brief Read ExtLine Combination Rising Flag for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_ReadRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RPR1, ExtiLine)); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Read ExtLine Combination Rising Flag for Lines in range 32 to 63 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR2 RPIFx LL_EXTI_ReadRisingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_32_63(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RPR2, ExtiLine)); +} +#endif + +/** + * @brief Clear ExtLine Rising Flags for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_ClearRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_20 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->RPR1, ExtiLine); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) +/** + * @brief Clear ExtLine Rising Flags for Lines in range 32 to 63 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR2 RPIFx LL_EXTI_ClearRisingFlag_32_63 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_34 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_32_63(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->RPR2, ExtiLine); +} +#endif + +/** + * @} + */ +/** @defgroup EXTI_LL_EF_Config EF configuration functions + * @{ + */ + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref EXTI_LL_EC_CONFIG_PORT + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_CONFIG_LINE0 + * @arg @ref LL_EXTI_CONFIG_LINE1 + * @arg @ref LL_EXTI_CONFIG_LINE2 + * @arg @ref LL_EXTI_CONFIG_LINE3 + * @arg @ref LL_EXTI_CONFIG_LINE4 + * @arg @ref LL_EXTI_CONFIG_LINE5 + * @arg @ref LL_EXTI_CONFIG_LINE6 + * @arg @ref LL_EXTI_CONFIG_LINE7 + * @arg @ref LL_EXTI_CONFIG_LINE8 + * @arg @ref LL_EXTI_CONFIG_LINE9 + * @arg @ref LL_EXTI_CONFIG_LINE10 + * @arg @ref LL_EXTI_CONFIG_LINE11 + * @arg @ref LL_EXTI_CONFIG_LINE12 + * @arg @ref LL_EXTI_CONFIG_LINE13 + * @arg @ref LL_EXTI_CONFIG_LINE14 + * @arg @ref LL_EXTI_CONFIG_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(EXTI->EXTICR[Line & 0x03u], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_CONFIG_LINE0 + * @arg @ref LL_EXTI_CONFIG_LINE1 + * @arg @ref LL_EXTI_CONFIG_LINE2 + * @arg @ref LL_EXTI_CONFIG_LINE3 + * @arg @ref LL_EXTI_CONFIG_LINE4 + * @arg @ref LL_EXTI_CONFIG_LINE5 + * @arg @ref LL_EXTI_CONFIG_LINE6 + * @arg @ref LL_EXTI_CONFIG_LINE7 + * @arg @ref LL_EXTI_CONFIG_LINE8 + * @arg @ref LL_EXTI_CONFIG_LINE9 + * @arg @ref LL_EXTI_CONFIG_LINE10 + * @arg @ref LL_EXTI_CONFIG_LINE11 + * @arg @ref LL_EXTI_CONFIG_LINE12 + * @arg @ref LL_EXTI_CONFIG_LINE13 + * @arg @ref LL_EXTI_CONFIG_LINE14 + * @arg @ref LL_EXTI_CONFIG_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref EXTI_LL_EC_CONFIG_PORT + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) +{ + return (READ_BIT(EXTI->EXTICR[Line & 0x03u], (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_LL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_rcc.h (revision 3) @@ -0,0 +1,3886 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G0xx_LL_RCC_H +#define STM32G0xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx.h" + +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ + + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 48000000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +#if defined(RCC_HSI48_SUPPORT) +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ +#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection + * @{ + */ +#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ +#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_1 /*!< PLL selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_1 /*!< PLL used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSI_DIV HSI division factor + * @{ + */ +#define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI not divided */ +#define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI divided by 2 */ +#define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI divided by 4 */ +#define LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0) /*!< HSI divided by 8 */ +#define LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2 /*!< HSI divided by 16 */ +#define LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0) /*!< HSI divided by 32 */ +#define LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1) /*!< HSI divided by 64 */ +#define LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV /*!< HSI divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_1 /*!< HSI48 selection as MCO1 source */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ +#if defined(RCC_CFGR_MCOSEL_3) +#define LL_RCC_MCO1SOURCE_PLLPCLK RCC_CFGR_MCOSEL_3 /*!< PLLPCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_0) /*!< PLLQCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_RTCCLK (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1) /*!< RTCCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_RTC_WKUP (RCC_CFGR_MCOSEL_3|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_0) /*!< RTC_Wakeup selection as MCO1 source */ +#endif /* RCC_CFGR_MCOSEL_3 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO1 not divided */ +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO1 divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO1 divided by 4 */ +#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO1 divided by 16 */ +#define LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 32 */ +#define LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO1 divided by 64 */ +#define LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 128 */ +#if defined(RCC_CFGR_MCOPRE_3) +#define LL_RCC_MCO1_DIV_256 RCC_CFGR_MCOPRE_3 /*!< MCO divided by 256 */ +#define LL_RCC_MCO1_DIV_512 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 512 */ +#define LL_RCC_MCO1_DIV_1024 (RCC_CFGR_MCOPRE_3 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 1024 */ +#endif /* RCC_CFGR_MCOPRE_3 */ +/** + * @} + */ + +#if defined(RCC_MCO2_SUPPORT) +/** @defgroup RCC_LL_EC_MCO2SOURCE MCO2 SOURCE selection + * @{ + */ +#define LL_RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_MCO2SOURCE_HSI48 RCC_CFGR_MCO2SEL_1 /*!< HSI48 selection as MCO2 source */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< HSI16 selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLCLK (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_0) /*!< Main PLL "R" clock selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1) /*!< LSI selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_2 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< LSE selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLPCLK RCC_CFGR_MCO2SEL_3 /*!< PLL "P" clock selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLQCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_0) /*!< PLL "Q" clock selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_RTCCLK (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1) /*!< RTC Clock selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_RTC_WKUP (RCC_CFGR_MCO2SEL_3 | RCC_CFGR_MCO2SEL_1 | RCC_CFGR_MCO2SEL_0) /*!< RTC Wakeup timer selection as MCO2 source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO2_DIV MCO2 prescaler + * @{ + */ +#define LL_RCC_MCO2_DIV_1 0x00000000U /*!< MCO2 not divided */ +#define LL_RCC_MCO2_DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO2 divided by 2 */ +#define LL_RCC_MCO2_DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO2 divided by 4 */ +#define LL_RCC_MCO2_DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 8 */ +#define LL_RCC_MCO2_DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO2 divided by 16 */ +#define LL_RCC_MCO2_DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 32 */ +#define LL_RCC_MCO2_DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 64 */ +#define LL_RCC_MCO2_DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 128 */ +#define LL_RCC_MCO2_DIV_256 RCC_CFGR_MCO2PRE_3 /*!< MCO2 divided by 256 */ +#define LL_RCC_MCO2_DIV_512 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_0) /*!< MCO2 divided by 512 */ +#define LL_RCC_MCO2_DIV_1024 (RCC_CFGR_MCO2PRE_3 | RCC_CFGR_MCO2PRE_1) /*!< MCO2 divided by 1024 */ +/** + * @} + */ +#endif /* RCC_MCO2_SUPPORT */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */ +#define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */ +#if defined(RCC_CCIPR_USART3SEL) +#define LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_CCIPR_USART3SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */ +#endif /* RCC_CCIPR_USART3SEL */ +/** + * @} + */ + +#if defined(LPUART1) || defined(LPUART2) +/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection + * @{ + */ +#if defined(LPUART2) +#define LL_RCC_LPUART2_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as LPUART2 clock source */ +#define LL_RCC_LPUART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_0) /*!< SYSCLK clock used as LPUART2 clock source */ +#define LL_RCC_LPUART2_CLKSOURCE_HSI ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL_1) /*!< HSI clock used as LPUART2 clock source */ +#define LL_RCC_LPUART2_CLKSOURCE_LSE ((RCC_CCIPR_LPUART2SEL << 16U) | RCC_CCIPR_LPUART2SEL) /*!< LSE clock used as LPUART2 clock source */ +#endif /* LPUART2 */ +#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 ((RCC_CCIPR_LPUART1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_0) /*!< SYSCLK clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_HSI ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL_1) /*!< HSI clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_LSE ((RCC_CCIPR_LPUART1SEL << 16U) | RCC_CCIPR_LPUART1SEL) /*!< LSE clock used as LPUART1 clock source */ +/** + * @} + */ +#endif /* LPUART1 || LPUART2 */ + +/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C1SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_0) /*!< SYSCLK clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_CCIPR_I2C1SEL << 16U) | RCC_CCIPR_I2C1SEL_1) /*!< HSI clock used as I2C1 clock source */ +#if defined(RCC_CCIPR_I2C2SEL) +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_CCIPR_I2C2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_0) /*!< SYSCLK clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_CCIPR_I2C2SEL << 16U) | RCC_CCIPR_I2C2SEL_1) /*!< HSI clock used as I2C2 clock source */ +#endif /* RCC_CCIPR_I2C2SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Sx_CLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define LL_RCC_I2S1_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S1SEL << 16U) | 0x00000000U) /*!< SYSCLK clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PLL ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_0) /*!< PLL clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_HSI ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL_1) /*!< HSI clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PIN ((RCC_CCIPR2_I2S1SEL << 16U) | RCC_CCIPR2_I2S1SEL) /*!< External clock used as I2S1 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_SYSCLK ((RCC_CCIPR2_I2S2SEL << 16U) | 0x00000000U) /*!< SYSCLK clock used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_PLL ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_0) /*!< PLL clock used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_HSI ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL_1) /*!< HSI clock used as I2S2 clock source */ +#define LL_RCC_I2S2_CLKSOURCE_PIN ((RCC_CCIPR2_I2S2SEL << 16U) | RCC_CCIPR2_I2S2SEL) /*!< External clock used as I2S2 clock source */ +#else +#define LL_RCC_I2S1_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PLL RCC_CCIPR_I2S1SEL_0 /*!< PLL clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_HSI RCC_CCIPR_I2S1SEL_1 /*!< HSI clock used as I2S1 clock source */ +#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CCIPR_I2S1SEL /*!< External clock used as I2S1 clock source */ +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +/** + * @} + */ + +#if defined(RCC_CCIPR_TIM1SEL) +/** @defgroup RCC_LL_EC_TIMx_CLKSOURCE Peripheral TIM clock source selection + * @{ + */ +#define LL_RCC_TIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM1SEL | (0x00000000U >> 16U)) /*!< PCLK1 clock used as TIM1 clock source */ +#define LL_RCC_TIM1_CLKSOURCE_PLL (RCC_CCIPR_TIM1SEL | (RCC_CCIPR_TIM1SEL >> 16U)) /*!< PLL used as TIM1 clock source */ +/** + * @} + */ +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) +/** @addtogroup RCC_LL_EC_TIMx_CLKSOURCE + * @{ + */ +#define LL_RCC_TIM15_CLKSOURCE_PCLK1 (RCC_CCIPR_TIM15SEL | (0x00000000U >> 16U)) /*!< PCLK1 clock used as TIM15 clock source */ +#define LL_RCC_TIM15_CLKSOURCE_PLL (RCC_CCIPR_TIM15SEL | (RCC_CCIPR_TIM15SEL >> 16U)) /*!< PLL used as TIM15 clock source */ +/** + * @} + */ +#endif /* RCC_CCIPR_TIM15SEL */ + +#if defined(LPTIM1) && defined(LPTIM2) +/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16U)) /*!< PCLK1 selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /*!< LSI selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /*!< HSI selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16U)) /*!< LSE selected as LPTIM1 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16U)) /*!< PCLK1 selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /*!< LSI selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /*!< HSI selected as LPTIM2 clock */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16U)) /*!< LSE selected as LPTIM2 clock */ +/** + * @} + */ +#endif /* LPTIM1 && LPTIM2*/ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE_HSI Peripheral CEC clock source selection + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */ +#define LL_RCC_CEC_CLKSOURCE_LSE RCC_CCIPR_CECSEL /*!< LSE oscillator clock used as CEC clock */ + +/** + * @} +*/ +#endif /* CEC */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE_HSI Peripheral FDCAN clock source selection + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 oscillator clock used as FDCAN clock */ +#define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR2_FDCANSEL_0 /*!< PLL "Q" oscillator clock used as FDCAN clock */ +#define LL_RCC_FDCAN_CLKSOURCE_HSE RCC_CCIPR2_FDCANSEL_1 /*!< HSE oscillator clock used as FDCAN clock */ + +/** + * @} +*/ +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(RNG) +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RNG clock */ +#define LL_RCC_RNG_CLKSOURCE_HSI_DIV8 RCC_CCIPR_RNGSEL_0 /*!< HSI oscillator clock divided by 8 used as RNG clock, available on cut2.0 */ +#define LL_RCC_RNG_CLKSOURCE_SYSCLK RCC_CCIPR_RNGSEL_1 /*!< SYSCLK divided by 1 used as RNG clock */ +#define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_RNGSEL /*!< PLL used as RNG clock */ +/** + * @} + */ +#endif /* RNG */ + +#if defined(RNG) +/** @defgroup RCC_LL_EC_RNG_CLK_DIV Peripheral RNG clock division factor + * @{ + */ +#define LL_RCC_RNG_CLK_DIV1 0x00000000U /*!< RNG clock not divided */ +#define LL_RCC_RNG_CLK_DIV2 RCC_CCIPR_RNGDIV_0 /*!< RNG clock divided by 2 */ +#define LL_RCC_RNG_CLK_DIV4 RCC_CCIPR_RNGDIV_1 /*!< RNG clock divided by 4 */ +#define LL_RCC_RNG_CLK_DIV8 RCC_CCIPR_RNGDIV /*!< RNG clock divided by 8 */ +/** + * @} + */ +#endif /* RNG */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_USB_CLKSOURCE_HSE RCC_CCIPR2_USBSEL_0 /*!< PLL clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR2_USBSEL_1 /*!< PLL clock used as USB clock source */ +/** + * @} + */ +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as ADC clock */ +#define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_0 /*!< PLL used as ADC clock */ +#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_1 /*!< HSI used as ADC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USARTx Peripheral USARTx get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */ +#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */ +#if defined(RCC_CCIPR_USART3SEL) +#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */ +#endif /* RCC_CCIPR_USART3SEL */ +/** + * @} + */ + +#if defined(LPUART1) +/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */ +#if defined(LPUART2) +#define LL_RCC_LPUART2_CLKSOURCE RCC_CCIPR_LPUART2SEL /*!< LPUART2 Clock source selection */ +#endif /* LPUART2 */ +/** + * @} + */ +#endif /* LPUART1 */ + +/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 Clock source selection */ +#if defined(RCC_CCIPR_I2C2SEL) +#define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL /*!< I2C2 Clock source selection */ +#endif /* RCC_CCIPR_I2C2SEL */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source + * @{ + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR2_I2S1SEL /*!< I2S1 Clock source selection */ +#define LL_RCC_I2S2_CLKSOURCE RCC_CCIPR2_I2S2SEL /*!< I2S2 Clock source selection */ +#else +#define LL_RCC_I2S1_CLKSOURCE RCC_CCIPR_I2S1SEL /*!< I2S1 Clock source selection */ +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +/** + * @} + */ + +#if defined(RCC_CCIPR_TIM1SEL) +/** @defgroup RCC_LL_EC_TIMx Peripheral TIMx get clock source + * @{ + */ +#define LL_RCC_TIM1_CLKSOURCE RCC_CCIPR_TIM1SEL /*!< TIM1 Clock source selection */ +#if defined(RCC_CCIPR_TIM15SEL) +#define LL_RCC_TIM15_CLKSOURCE RCC_CCIPR_TIM15SEL /*!< TIM15 Clock source selection */ +#endif /* RCC_CCIPR_TIM15SEL */ +/** + * @} + */ +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(LPTIM1) && defined(LPTIM2) +/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM2 Clock source selection */ +#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 Clock source selection */ +/** + * @} + */ +#endif /* LPTIM1 && LPTIM2 */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE RCC_CCIPR_CECSEL /*!< CEC Clock source selection */ +/** + * @} + */ +#endif /* CEC */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source + * @{ + */ +#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR2_FDCANSEL /*!< FDCAN Clock source selection */ +/** + * @} + */ +#endif /* FDCAN1 */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_CCIPR2_USBSEL /*!< USB Clock source selection */ +/** + * @} + */ +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(RNG) +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL /*!< RNG Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG_DIV Peripheral RNG get clock division factor + * @{ + */ +#define LL_RCC_RNG_CLKDIV RCC_CCIPR_RNGDIV /*!< RNG Clock division factor */ +/** + * @} + */ +#endif /* RNG */ + +/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor (PLLM) + * @{ + */ +#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL division factor by 1 */ +#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 2 */ +#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 3 */ +#define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 4 */ +#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL division factor by 5 */ +#define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 6 */ +#define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL division factor by 7 */ +#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL division factor by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) + * @{ + */ +#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ +#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */ +#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ +#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */ +#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ +#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */ +#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) + * @{ + */ +#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */ +#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */ +#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */ +#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */ +#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */ +#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */ +#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */ +#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */ +#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */ +#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */ +#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */ +#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */ +#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */ +#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */ +#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */ +#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */ +#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */ +#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */ +#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */ +#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */ +#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */ +#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */ +#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */ +#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */ +#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */ +#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/ +#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */ +#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */ +#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */ +#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */ +#define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */ +/** + * @} + */ + +#if defined(RCC_PLLQ_SUPPORT) +/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) + * @{ + */ +#define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 2 */ +#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 3 */ +#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */ +#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 5 */ +#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */ +#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */ +#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */ +/** + * @} + */ +#endif /* RCC_PLLQ_SUPPORT */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLLCLK frequency on system domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U)) + +/** + * @brief Helper macro to calculate the PLLPCLK frequency used on I2S domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_I2S1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) + +#if defined(RCC_CCIPR2_I2S2SEL) +/** + * @brief Helper macro to calculate the PLLPCLK frequency used on I2S2 domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S2_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_I2S2_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) +#endif /* RCC_CCIPR2_I2S2SEL */ + +/** + * @brief Helper macro to calculate the PLLPCLK frequency used on ADC domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U)) + +#if defined(RNG) +/** + * @brief Helper macro to calculate the PLLQCLK frequency used on RNG domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_RNG_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_RNG_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +#endif /* RNG */ + +#if defined(RCC_PLLQ_SUPPORT) +/** + * @brief Helper macro to calculate the PLLQCLK frequency used on TIM1 domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM1_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_TIM1_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +#if defined(TIM15) +/** + * @brief Helper macro to calculate the PLLQCLK frequency used on TIM15 domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_TIM15_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_TIM15_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +#endif /* TIM15 */ +#endif /* RCC_PLLQ_SUPPORT */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** + * @brief Helper macro to calculate the PLLQCLK frequency used on FDCAN domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FDCAN_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Helper macro to calculate the PLLQCLK frequency used on USB domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_USB_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param __PLLN__ Between Min_Data = 8 and Max_Data = 86 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_USB_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ + ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \ + (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U)) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) \ + ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU)) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \ + ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos] & 0x1FU)) + +/** + * @brief Helper macro to calculate the HSISYS frequency + * @param __HSIDIV__ This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + * @retval HSISYS clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) (HSI_VALUE / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos))) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI even in stop mode + * @note HSI oscillator is forced ON even in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Check if HSI in stop mode is enabled + * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL); +} + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 64, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 127 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0 and Max_Data = 127 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 + * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Disable HSI48 + * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); +} + +/** + * @brief Check if HSI48 oscillator Ready + * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL); +} + +/** + * @brief Get HSI48 Calibration value + * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); +} + +/** + * @} + */ +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Enable Clock security system on LSE. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Disable Clock security system on LSE. + * @note Clock security system can be disabled only after a LSE + * failure detection. In that case it MUST be disabled by software. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); +} + +/** + * @brief Check if CSS on LSE failure Detection + * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSCO LSCO + * @{ + */ + +/** + * @brief Enable Low speed clock + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Disable Low speed clock + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Configure Low speed clock selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); +} + +/** + * @brief Get Low speed clock selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_LSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); +} + +/** + * @brief Set HSI16 division factor + * @rmtoll CR HSIDIV LL_RCC_SetHSIDiv + * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as + * system clock source. + * @param HSIDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetHSIDiv(uint32_t HSIDiv) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, HSIDiv); +} +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); +} + +/** + * @brief Get HSI16 Division factor + * @rmtoll CR HSIDIV LL_RCC_GetHSIDiv + * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as + * system clock source. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetHSIDiv(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)); +} +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO1 MCO1 + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n + * CFGR MCOPRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLPCLK (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLQCLK (*) + * @arg @ref LL_RCC_MCO1SOURCE_RTCCLK (*) + * @arg @ref LL_RCC_MCO1SOURCE_RTC_WKUP (*) + * + * (*) value not defined in all devices. + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_32 + * @arg @ref LL_RCC_MCO1_DIV_64 + * @arg @ref LL_RCC_MCO1_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +} + +/** + * @} + */ + +#if defined(RCC_MCO2_SUPPORT) +/** @defgroup RCC_LL_EF_MCO2 MCO2 + * @{ + */ + +/** + * @brief Configure MCO2 + * @rmtoll CFGR MCO2SEL LL_RCC_ConfigMCO2\n + * CFGR MCO2PRE LL_RCC_ConfigMCO2 + * @note feature not available in all devices. + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO2SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_HSI + * @arg @ref LL_RCC_MCO2SOURCE_HSI48 + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO2SOURCE_LSI + * @arg @ref LL_RCC_MCO2SOURCE_LSE + * @arg @ref LL_RCC_MCO2SOURCE_PLLPCLK + * @arg @ref LL_RCC_MCO2SOURCE_PLLQCLK + * @arg @ref LL_RCC_MCO2SOURCE_RTCCLK + * @arg @ref LL_RCC_MCO2SOURCE_RTC_WKUP + * + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_8 + * @arg @ref LL_RCC_MCO2_DIV_16 + * @arg @ref LL_RCC_MCO2_DIV_32 + * @arg @ref LL_RCC_MCO2_DIV_64 + * @arg @ref LL_RCC_MCO2_DIV_128 + * @arg @ref LL_RCC_MCO2_DIV_256 + * @arg @ref LL_RCC_MCO2_DIV_512 + * @arg @ref LL_RCC_MCO2_DIV_1024 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO2(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE, MCOxSource | MCOxPrescaler); +} + +/** + * @} + */ +#endif /* RCC_MCO2_SUPPORT */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); +} + +#if defined(LPUART1) +/** + * @brief Configure LPUARTx clock source + * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource + * @rmtoll CCIPR LPUART2SEL LL_RCC_SetLPUARTClockSource + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE (*) + * (*) feature not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) +{ + MODIFY_REG(RCC->CCIPR, (LPUARTxSource >> 16U), (LPUARTxSource & 0x0000FFFFU)); +} +#endif /* LPUART1 */ + +/** + * @brief Configure I2Cx clock source + * @rmtoll CCIPR I2C1SEL LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*) + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + MODIFY_REG(RCC->CCIPR, (I2CxSource >> 16U), (I2CxSource & 0x0000FFFFU)); +} + +#if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL) +/** + * @brief Configure TIMx clock source + * @rmtoll CCIPR TIMxSEL LL_RCC_SetTIMClockSource + * @param TIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL + * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1 + * @if defined(STM32G081xx) + * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL + * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1 + * @endif + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource) +{ + MODIFY_REG(RCC->CCIPR, (TIMxSource & 0xFFFF0000U), (TIMxSource << 16)); +} +#endif /* RCC_CCIPR_TIM1SEL && RCC_CCIPR_TIM15SEL */ + +#if defined(LPTIM1) && defined(LPTIM2) +/** + * @brief Configure LPTIMx clock source + * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U)); +} +#endif /* LPTIM1 && LPTIM2 */ + +#if defined(CEC) +/** + * @brief Configure CEC clock source + * @rmtoll CCIPR CECSEL LL_RCC_SetCECClockSource + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CECSEL, CECxSource); +} +#endif /* CEC */ + +#if defined(RCC_CCIPR_RNGDIV) +/** + * @brief Configure RNG division factor + * @rmtoll CCIPR RNGDIV LL_RCC_SetRNGClockDiv + * @param RNGxDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLK_DIV1 + * @arg @ref LL_RCC_RNG_CLK_DIV2 + * @arg @ref LL_RCC_RNG_CLK_DIV4 + * @arg @ref LL_RCC_RNG_CLK_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockDiv(uint32_t RNGxDiv) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGDIV, RNGxDiv); +} +#endif /* RNG */ + +#if defined (RCC_CCIPR_RNGSEL) +/** + * @brief Configure RNG clock source + * @rmtoll CCIPR RNGSEL LL_RCC_SetRNGClockSource + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI_DIV8 + * @arg @ref LL_RCC_RNG_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource); +} +#endif /* RNG */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Configure USB clock source + * @rmtoll CCIPR2 CK48MSEL LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_USB_CLKSOURCE_HSE + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBSEL, USBxSource); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined (FDCAN1) || defined (FDCAN2) +/** + * @brief Configure FDCAN clock source + * @rmtoll CCIPR2 FDCANSEL LL_RCC_SetFDCANClockSource + * @param FDCANxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL, FDCANxSource); +} +#endif /* FDCAN1 || FDCAN2 */ + +/** + * @brief Configure ADC clock source + * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL + * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Configure I2Sx clock source + * @rmtoll CCIPR2 I2SxSEL LL_RCC_SetI2SClockSource + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) +{ + MODIFY_REG(RCC->CCIPR2, (I2SxSource >> 16U), (I2SxSource & 0x0000FFFFU)); +} + +#else +/** + * @brief Configure I2Sx clock source + * @rmtoll CCIPR I2S1SEL LL_RCC_SetI2SClockSource + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S1SEL, I2SxSource); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +/** + * @brief Get USARTx clock source + * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART3_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*) + * (*) feature not available on all devices + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U)); +} + +#if defined (LPUART2) || defined (LPUART1) +/** + * @brief Get LPUARTx clock source + * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource\n + * CCIPR LPUART2SEL LL_RCC_GetLPUARTClockSource + * @param LPUARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @arg @ref LL_RCC_LPUART2_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_LPUART2_CLKSOURCE_LSE (*) + * (*) feature not available on all devices + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx) | (LPUARTx << 16U)); +} +#endif /* LPUART2 || LPUART1 */ + +/** + * @brief Get I2Cx clock source + * @rmtoll CCIPR I2C1SEL LL_RCC_GetI2CClockSource\n + * CCIPR I2C2SEL LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, I2Cx) | (I2Cx << 16U)); +} + +#if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL) +/** + * @brief Get TIMx clock source + * @rmtoll CCIPR TIMxSEL LL_RCC_GetTIMClockSource + * @param TIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM1_CLKSOURCE + * @arg @ref LL_RCC_TIM15_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL + * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK1 + * @if defined(STM32G081xx) + * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL + * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK1 + * @endif + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx) +{ + return (uint32_t)((READ_BIT(RCC->CCIPR, TIMx) >> 16U) | TIMx); +} +#endif /* RCC_CCIPR_TIM1SEL || RCC_CCIPR_TIM15SEL */ + +#if defined(LPTIM1) && defined(LPTIM2) +/** + * @brief Get LPTIMx clock source + * @rmtoll CCIPR LPTIM1SEL LL_RCC_GetLPTIMClockSource\n + CCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx); +} +#endif /* LPTIM1 && LPTIM2 */ + +#if defined (RCC_CCIPR_CECSEL) +/** + * @brief Get CEC clock source + * @rmtoll CCIPR CECSEL LL_RCC_GetCECClockSource + * @param CECx This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, CECx)); +} +#endif /* CEC */ + +#if defined(RCC_CCIPR2_FDCANSEL) +/** + * @brief Get FDCAN clock source + * @rmtoll CCIPR2 FDCANSEL LL_RCC_GetFDCANClockSource + * @param FDCANx This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, FDCANx)); +} +#endif /* RCC_CCIPR2_FDCANSEL */ + +#if defined(RNG) +/** + * @brief Get RNGx clock source + * @rmtoll CCIPR RNGSEL LL_RCC_GetRNGClockSource + * @param RNGx This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_NONE + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI_DIV8 + * @arg @ref LL_RCC_RNG_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx)); +} +#endif /* RNG */ + +#if defined(RNG) +/** + * @brief Get RNGx clock division factor + * @rmtoll CCIPR RNGDIV LL_RCC_GetRNGClockDiv + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLK_DIV1 + * @arg @ref LL_RCC_RNG_CLK_DIV2 + * @arg @ref LL_RCC_RNG_CLK_DIV4 + * @arg @ref LL_RCC_RNG_CLK_DIV8 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockDiv(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)); +} +#endif /* RNG */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Get USBx clock source + * @rmtoll CCIPR2 CK48MSEL LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, USBx)); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +/** + * @brief Get ADCx clock source + * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource + * @param ADCx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL + * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx)); +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Get I2Sx clock source + * @rmtoll CCIPR2 I2S1SEL LL_RCC_GetI2SClockSource\n + * CCIPR2 I2S2SEL LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE + * @arg @ref LL_RCC_I2S2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, I2Sx) | (I2Sx << 16U)); +} +#else +/** + * @brief Get I2Sx clock source + * @rmtoll CCIPR I2S1SEL LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @arg @ref LL_RCC_I2S1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx)); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @} + */ + + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL used for SYSCLK Domain + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR); +} + +/** + * @brief Configure PLL used for ADC domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLP can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: I2S1) + * @note This can be selected for ADC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n + * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_ADC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); +} + +/** + * @brief Configure PLL used for I2S1 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLP can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: ADC) + * @note This can be selected for I2S1 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S1\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S1\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S1\n + * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_I2S1 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S1(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); +} + +#if defined(RCC_CCIPR2_I2S2SEL) +/** + * @brief Configure PLL used for I2S2 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLP can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: ADC) + * @note This can be selected for I2S2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S2\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S2\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S2\n + * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_I2S2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S2(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP); +} +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(RNG) +/** + * @brief Configure PLL used for RNG domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: TIM1, TIM15) + * @note This can be selected for RNG + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_RNG\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_RNG\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_RNG\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_RNG + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_RNG(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} +#endif /* RNG */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** + * @brief Configure PLL used for FDCAN domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: TIM1, TIM15) + * @note This can be selected for FDCAN + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_FDCAN\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_FDCAN\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_FDCAN\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_FDCAN + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_FDCAN(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Configure PLL used for USB domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: TIM1, TIM15) + * @note This can be selected for USB + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_USB\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_USB\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_USB\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_USB + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_USB(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(RCC_PLLQ_SUPPORT) +/** + * @brief Configure PLL used for TIM1 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: RNG, TIM15) + * @note This can be selected for TIM1 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_TIM1\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_TIM1\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_TIM1\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_TIM1 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM1(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} +#endif /* RCC_PLLQ_SUPPORT */ + +#if defined(RCC_PLLQ_SUPPORT) && defined(TIM15) +/** + * @brief Configure PLL used for TIM15 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL is disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note User shall verify whether the PLL configuration is not done through + * other functions (ex: RNG, TIM1) + * @note This can be selected for TIM15 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_TIM15\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_TIM15\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_TIM15\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_TIM15 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @param PLLN Between 8 and 86 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_TIM15(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ); +} +#endif /* RCC_PLLQ_SUPPORT && TIM15 */ + +/** + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 8 and 86 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); +} + +/** + * @brief Get Main PLL division factor for PLLP + * @note used for PLLPCLK (ADC & I2S clock) + * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_3 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_5 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_7 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @arg @ref LL_RCC_PLLP_DIV_9 + * @arg @ref LL_RCC_PLLP_DIV_10 + * @arg @ref LL_RCC_PLLP_DIV_11 + * @arg @ref LL_RCC_PLLP_DIV_12 + * @arg @ref LL_RCC_PLLP_DIV_13 + * @arg @ref LL_RCC_PLLP_DIV_14 + * @arg @ref LL_RCC_PLLP_DIV_15 + * @arg @ref LL_RCC_PLLP_DIV_16 + * @arg @ref LL_RCC_PLLP_DIV_17 + * @arg @ref LL_RCC_PLLP_DIV_18 + * @arg @ref LL_RCC_PLLP_DIV_19 + * @arg @ref LL_RCC_PLLP_DIV_20 + * @arg @ref LL_RCC_PLLP_DIV_21 + * @arg @ref LL_RCC_PLLP_DIV_22 + * @arg @ref LL_RCC_PLLP_DIV_23 + * @arg @ref LL_RCC_PLLP_DIV_24 + * @arg @ref LL_RCC_PLLP_DIV_25 + * @arg @ref LL_RCC_PLLP_DIV_26 + * @arg @ref LL_RCC_PLLP_DIV_27 + * @arg @ref LL_RCC_PLLP_DIV_28 + * @arg @ref LL_RCC_PLLP_DIV_29 + * @arg @ref LL_RCC_PLLP_DIV_30 + * @arg @ref LL_RCC_PLLP_DIV_31 + * @arg @ref LL_RCC_PLLP_DIV_32 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); +} + +#if defined(RCC_PLLQ_SUPPORT) +/** + * @brief Get Main PLL division factor for PLLQ + * @note used for PLLQCLK selected for RNG, TIM1, TIM15 clock + * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); +} +#endif /* RCC_PLLQ_SUPPORT */ + +/** + * @brief Get Main PLL division factor for PLLR + * @note used for PLLCLK (system clock) + * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); +} + +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_1 + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +} + +/** + * @brief Enable PLL output mapped on ADC domain clock + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC + * @note User shall check that PLL enable is not done through + * other functions (ex: I2S1) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} + +/** + * @brief Disable PLL output mapped on ADC domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: I2S1) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} + +/** + * @brief Enable PLL output mapped on I2S domain clock + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_I2S1 + * @note User shall check that PLL enable is not done through + * other functions (ex: ADC) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S1(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} + +#if defined(RCC_CCIPR2_I2S2SEL) +/** + * @brief Enable PLL output mapped on I2S2 domain clock + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_I2S2 + * @note User shall check that PLL enable is not done through + * other functions (ex: ADC) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S2(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} +#endif /* RCC_CCIPR2_I2S2SEL */ + +/** + * @brief Disable PLL output mapped on I2S1 domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: RNG) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_I2S1 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S1(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} + +#if defined(RCC_CCIPR2_I2S2SEL) +/** + * @brief Disable PLL output mapped on I2S2 domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: RNG) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_I2S2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S2(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN); +} +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(RNG) +/** + * @brief Enable PLL output mapped on RNG domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_RNG + * @note User shall check that PLL enable is not done through + * other functions (ex: TIM1, TIM15) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_RNG(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on RNG domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: TIM, TIM15) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_RNG + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_RNG(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} +#endif /* RNG */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** + * @brief Enable PLL output mapped on FDCAN domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_FDCAN + * @note User shall check that PLL enable is not done through + * other functions (ex: TIM1, TIM15) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_FDCAN(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on FDCAN domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: TIM, TIM15) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_FDCAN + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_FDCAN(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Enable PLL output mapped on USB domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_USB + * @note User shall check that PLL enable is not done through + * other functions (ex: TIM1, TIM15) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_USB(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on USB domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: TIM, TIM15) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_USB + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_USB(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(RCC_PLLQ_SUPPORT) +/** + * @brief Enable PLL output mapped on TIM1 domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_TIM1 + * @note User shall check that PLL enable is not done through + * other functions (ex: RNG, TIM15) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM1(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on TIM1 domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: RNG, TIM15) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_TIM1 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM1(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} +#endif /* RCC_PLLQ_SUPPORT */ + +#if defined(RCC_PLLQ_SUPPORT) && defined(TIM15) +/** + * @brief Enable PLL output mapped on TIM15 domain clock + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_TIM15 + * @note User shall check that PLL enable is not done through + * other functions (ex: RNG, TIM1) + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_TIM15(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} + +/** + * @brief Disable PLL output mapped on TIM15 domain clock + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note User shall check that PLL is not used by any other peripheral + * (ex: RNG, TIM1) + * @note In order to save power, when the PLLCLK of the PLL is + * not used, should be 0 + * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_TIM15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_TIM15(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN); +} +#endif /* RCC_PLLQ_SUPPORT && TIM15 */ + +/** + * @brief Enable PLL output mapped on SYSCLK domain + * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void) +{ + SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); +} + +/** + * @brief Disable PLL output mapped on SYSCLK domain + * @note Cannot be disabled if the PLL clock is used as the system clock + * @note In order to save power, when the PLLCLK of the PLL is + * not used, Main PLL should be 0 + * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void) +{ + CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN); +} + +/** + * @} + */ + + + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); +} +#endif /* RCC_HSI48_SUPPORT */ +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSSC); +} + +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Option byte reset is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR or POR/PDR reset is set or not. + * @rmtoll CSR PWRRSTF LL_RCC_IsActiveFlag_PWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PWRRSTF) == (RCC_CSR_PWRRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +#if defined(LPUART1) || defined(LPUART2) +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +#endif /* LPUART1 */ +#if defined(LPTIM1) && defined(LPTIM2) +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +#endif /* LPTIM1 && LPTIM2 */ +#if defined(RNG) +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +#endif /* RNG */ +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +#if defined(CEC) +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +#endif /* CEC */ +#if defined(FDCAN1) || defined(FDCAN2) +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); +#endif /* FDCAN1 */ +uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource); +uint32_t LL_RCC_GetRTCClockFreq(void); +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G0xx_LL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal.c (revision 3) @@ -0,0 +1,759 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @brief HAL module driver + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @brief STM32G0xx HAL Driver version number + */ +#define __STM32G0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32G0xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32G0xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ +#define __STM32G0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32G0xx_HAL_VERSION ((__STM32G0xx_HAL_VERSION_MAIN << 24U)\ + |(__STM32G0xx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32G0xx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32G0xx_HAL_VERSION_RC)) + +#if defined(VREFBUF) +#define VREFBUF_TIMEOUT_VALUE 10U /*!< 10 ms */ +#endif /* VREFBUF */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Exported variables ---------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @brief HAL Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### HAL Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the Flash interface the NVIC allocation and initial time base + clock configuration. + (+) De-initialize common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief Configure the Flash prefetch and the Instruction cache, + * the time base source, NVIC and any required global low level hardware + * by calling the HAL_MspInit() callback function to be optionally defined in user file + * stm32g0xx_hal_msp.c. + * + * @note HAL_Init() function is called at the beginning of program after reset and before + * the clock configuration. + * + * @note In the default implementation the System Timer (Systick) is used as source of time base. + * The Systick configuration is based on HSI clock, as HSI is the clock + * used after a system Reset. + * Once done, time base tick starts incrementing: the tick variable counter is incremented + * each 1ms in the SysTick_Handler() interrupt handler. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Configure Flash prefetch, Instruction cache */ + /* Default configuration at reset is: */ + /* - Prefetch disabled */ + /* - Instruction cache enabled */ + +#if (INSTRUCTION_CACHE_ENABLE == 0U) + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + } + + /* Return function status */ + return status; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the source of time base. + * @note This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); + + __HAL_RCC_IOP_FORCE_RESET(); + __HAL_RCC_IOP_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base: + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/ + if ((uint32_t)uwTickFreq != 0U) + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U /(uint32_t)uwTickFreq)) == 0U) + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief return tick frequency. + * @retval tick period in Hz + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32G0xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return ((DBG->IDCODE & DBG_IDCODE_REV_ID) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return ((DBG->IDCODE) & DBG_IDCODE_DEV_ID); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group3 + * @brief HAL Debug functions + * +@verbatim + =============================================================================== + ##### HAL Debug functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBG->CR, DBG_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY); +} + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group4 + * @brief SYSCFG configuration functions + * +@verbatim + =============================================================================== + ##### HAL SYSCFG configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Pin remap + (+) Configure the Voltage reference buffer + (+) Enable/Disable the Voltage reference buffer + (+) Enable/Disable the I/O analog switch voltage booster + (+) Enable/Disable dead battery behavior(*) + (+) Configure Clamping Diode on specific pins(*) + (*) Feature not available on all devices + +@endverbatim + * @{ + */ +#if defined(VREFBUF) +/** + * @brief Configure the internal voltage reference buffer voltage scale. + * @param VoltageScaling specifies the output voltage to achieve + * This parameter can be one of the following values: + * @arg @ref SYSCFG_VREFBUF_VoltageScale + * @retval None + */ +void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); +} + +/** + * @brief Configure the internal voltage reference buffer high impedance mode. + * @param Mode specifies the high impedance mode + * This parameter can be one of the following values: + * @arg @ref SYSCFG_VREFBUF_HighImpedance + * @retval None + */ +void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); + + MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); +} + +/** + * @brief Tune the Internal Voltage Reference buffer (VREFBUF). + * @note VrefBuf voltage scale is calibrated in production for each device, + * using voltage scale 1. This calibration value is loaded + * as default trimming value at device power up. + * This trimming value can be fine tuned for voltage scales 0 and 1 + * using this function. + * @retval None + */ +void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); + + MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); +} + +/** + * @brief Enable the Internal Voltage Reference buffer (VREFBUF). + * @retval HAL_OK/HAL_TIMEOUT + */ +HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) +{ + uint32_t tickstart; + + SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for VRR bit */ + while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U) + { + if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable the Internal Voltage Reference buffer (VREFBUF). + * + * @retval None + */ +void HAL_SYSCFG_DisableVREFBUF(void) +{ + CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); +} +#endif /* VREFBUF */ + +/** + * @brief Enable the I/O analog switch voltage booster + * @retval None + */ +void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Disable the I/O analog switch voltage booster + * @retval None + */ +void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Enable the remap on PA11_PA12 + * @param PinRemap specifies which pins have to be remapped + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_REMAP_PA11 + * @arg @ref SYSCFG_REMAP_PA12 + * @retval None + */ +void HAL_SYSCFG_EnableRemap(uint32_t PinRemap) +{ + /* Check the parameter */ + assert_param(IS_HAL_REMAP_PIN(PinRemap)); + SET_BIT(SYSCFG->CFGR1, PinRemap); +} + +/** + * @brief Disable the remap on PA11_PA12 + * @param PinRemap specifies which pins will behave normally + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_REMAP_PA11 + * @arg @ref SYSCFG_REMAP_PA12 + * @retval None + */ +void HAL_SYSCFG_DisableRemap(uint32_t PinRemap) +{ + /* Check the parameter */ + assert_param(IS_HAL_REMAP_PIN(PinRemap)); + CLEAR_BIT(SYSCFG->CFGR1, PinRemap); +} + +#if defined(SYSCFG_CDEN_SUPPORT) +/** + * @brief Enable Clamping Diode on specified IO + * @param PinConfig specifies on which pins clamping Diode has to be enabled + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_ClampingDiode + * @retval None + */ +void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig)); + SET_BIT(SYSCFG->CFGR2, PinConfig); +} + +/** + * @brief Disable Clamping Diode on specified IO + * @param PinConfig specifies on which pins clamping Diode has to be disabled + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_ClampingDiode + * @retval None + */ +void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_CLAMPINGDIODE(PinConfig)); + CLEAR_BIT(SYSCFG->CFGR2, PinConfig); +} +#endif /* SYSCFG_CDEN_SUPPORT */ + +#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE) +/** + * @brief Strobe configuration of GPIO depending on UCPDx dead battery settings + * @param ConfigDeadBattery specifies on which pins to make effective or not Dead Battery sw configuration + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_UCPD1_STROBE + * @arg @ref SYSCFG_UCPD2_STROBE + * @retval None + */ +void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery) +{ + assert_param(IS_SYSCFG_DBATT_CONFIG(ConfigDeadBattery)); + + /* Change strobe configuration of GPIO depending on UCPDx dead battery settings */ + MODIFY_REG(SYSCFG->CFGR1, (SYSCFG_CFGR1_UCPD1_STROBE | SYSCFG_CFGR1_UCPD2_STROBE), ConfigDeadBattery); +} +#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc.c (revision 3) @@ -0,0 +1,3006 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_adc.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Converter (ADC) + * peripheral: + * + Initialization and de-initialization functions + * ++ Initialization and Configuration of ADC + * + Operation functions + * ++ Start, stop, get result of conversions of regular + * group, using 3 possible modes: polling, interruption or DMA. + * + Control functions + * ++ Channels configuration on regular group + * ++ Analog Watchdog configuration + * + State functions + * ++ ADC state machine management + * ++ Interrupts and flags management + * Other functions (extended functions) are available in file + * "stm32g0xx_hal_adc_ex.c". + * + @verbatim + ============================================================================== + ##### ADC peripheral features ##### + ============================================================================== + [..] + (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. + + (+) Interrupt generation at the end of regular conversion and in case of + analog watchdog or overrun events. + + (+) Single and continuous conversion modes. + + (+) Scan mode for conversion of several channels sequentially. + + (+) Data alignment with in-built data coherency. + + (+) Programmable sampling time (common to group of channels) + + (+) External trigger (timer or EXTI) with configurable polarity + + (+) DMA request generation for transfer of conversions data of regular group. + + (+) ADC calibration + + (+) ADC conversion of regular group. + + (+) ADC supply requirements: 1.62 V to 3.6 V. + + (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to + Vdda or to an external voltage reference). + + + ##### How to use this driver ##### + ============================================================================== + [..] + + *** Configuration of top level parameters related to ADC *** + ============================================================ + [..] + + (#) Enable the ADC interface + (++) As prerequisite, ADC clock must be configured at RCC top level. + Caution: On STM32G0, ADC clock frequency max is 35MHz (refer + to device datasheet). + Therefore, ADC clock source from RCC and ADC clock + prescaler must be configured to remain below + this maximum frequency. + + (++) Two clock settings are mandatory: + (+++) ADC clock (core clock, also possibly conversion clock). + + (+++) ADC clock (conversions clock). + Four possible clock sources: synchronous clock from APB clock (same as ADC core clock) + or asynchronous clock from RCC level: SYSCLK, HSI16, PLLPCLK. + + (+++) Example: + Into HAL_ADC_MspInit() (recommended code location) or with + other device clock parameters configuration: + (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory: core clock) + + (++) ADC clock source and clock prescaler are configured at ADC level with + parameter "ClockPrescaler" using function HAL_ADC_Init(). + + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_ENABLE() + (++) Configure these ADC pins in analog mode + using function HAL_GPIO_Init() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Configure the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding ADC interruption vector + ADCx_IRQHandler(). + + (#) Optionally, in case of usage of DMA: + (++) Configure the DMA (DMA channel, mode normal or circular, ...) + using function HAL_DMA_Init(). + (++) Configure the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding DMA interruption vector + DMAx_Channelx_IRQHandler(). + + *** Configuration of ADC, group regular, channels parameters *** + ================================================================ + [..] + + (#) Configure the ADC parameters (resolution, data alignment, ...) + and regular group parameters (conversion trigger, sequencer, ...) + using function HAL_ADC_Init(). + + (#) Configure the channels for regular group parameters (channel number, + channel rank into sequencer, ..., into regular group) + using function HAL_ADC_ConfigChannel(). + + (#) Optionally, configure the analog watchdog parameters (channels + monitored, thresholds, ...) + using function HAL_ADC_AnalogWDGConfig(). + + *** Execution of ADC conversions *** + ==================================== + [..] + + (#) Optionally, perform an automatic ADC calibration to improve the + conversion accuracy + using function HAL_ADCEx_Calibration_Start(). + + (#) ADC driver can be used among three modes: polling, interruption, + transfer by DMA. + + (++) ADC conversion by polling: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start() + (+++) Wait for ADC conversion completion + using function HAL_ADC_PollForConversion() + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop() + + (++) ADC conversion by interruption: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_IT() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() + (this function must be implemented in user program) + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_IT() + + (++) ADC conversion with transfer by DMA: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_DMA() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() + (these functions must be implemented in user program) + (+++) Conversion results are automatically transferred by DMA into + destination variable address. + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_DMA() + + [..] + + (@) Callback functions must be implemented in user program: + (+@) HAL_ADC_ErrorCallback() + (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) + (+@) HAL_ADC_ConvCpltCallback() + (+@) HAL_ADC_ConvHalfCpltCallback + + *** Deinitialization of ADC *** + ============================================================ + [..] + + (#) Disable the ADC interface + (++) ADC clock can be hard reset and disabled at RCC top level. + (++) Hard reset of ADC peripherals + using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). + (++) ADC clock disable + using the equivalent macro/functions as configuration step. + (+++) Example: + Into HAL_ADC_MspDeInit() (recommended code location) or with + other device clock parameters configuration: + (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; + (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (#) ADC pins configuration + (++) Disable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_DISABLE() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Disable the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + + (#) Optionally, in case of usage of DMA: + (++) Deinitialize the DMA + using function HAL_DMA_Init(). + (++) Disable the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + + [..] + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_ADC_RegisterCallback() + to register an interrupt callback. + [..] + + Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + [..] + + By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() + or @ref HAL_ADC_Init() function. + [..] + + When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + +/* Fixed timeout values for ADC calibration, enable settling time, disable */ +/* settling time. */ +/* Values defined to be higher than worst cases: low clock frequency, */ +/* maximum prescaler. */ +/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ +/* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ +/* Unit: ms */ +#define ADC_ENABLE_TIMEOUT (2UL) +#define ADC_DISABLE_TIMEOUT (2UL) +#define ADC_STOP_CONVERSION_TIMEOUT (2UL) +#define ADC_CHANNEL_CONF_RDY_TIMEOUT (1UL) + +/* Register CHSELR bits corresponding to ranks 2 to 8 . */ +#define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | \ + ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief ADC Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC. + (+) De-initialize the ADC. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the ADC peripheral and regular group according to + * parameters specified in structure "ADC_InitTypeDef". + * @note As prerequisite, ADC clock must be configured at RCC top level + * (refer to description of RCC configuration for ADC + * in header of this file). + * @note Possibility to update parameters on the fly: + * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when + * coming from ADC state reset. Following calls to this function can + * be used to reconfigure some parameters of ADC_InitTypeDef + * structure on the fly, without modifying MSP configuration. If ADC + * MSP has to be modified again, HAL_ADC_DeInit() must be called + * before HAL_ADC_Init(). + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_InitTypeDef". + * @note This function configures the ADC within 2 scopes: scope of entire + * ADC and scope of regular group. For parameters details, see comments + * of structure "ADC_InitTypeDef". + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmpCFGR1 = 0UL; + uint32_t tmpCFGR2 = 0UL; + uint32_t tmp_adc_reg_is_conversion_on_going; + __IO uint32_t wait_loop_index = 0UL; + + /* Check ADC handle */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); + assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1)); + assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); + + assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode)); + + if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + { + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + + if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) + { + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + } + } + + /* ADC group regular discontinuous mode can be enabled only if */ + /* continuous mode is disabled. */ + assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); + + /* Actions performed only if ADC is coming from state reset: */ + /* - Initialization of ADC MSP */ + if (hadc->State == HAL_ADC_STATE_RESET) + { +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + /* Init the ADC Callback settings */ + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ + hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ + hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ + hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ + + if (hadc->MspInitCallback == NULL) + { + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Initialize Lock */ + hadc->Lock = HAL_UNLOCKED; + } + + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + { + /* Enable ADC internal voltage regulator */ + LL_ADC_EnableInternalRegulator(hadc->Instance); + + /* Delay for ADC stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + + /* Verification that ADC voltage regulator is correctly enabled, whether */ + /* or not ADC is coming from state reset (if any potential problem of */ + /* clocking, voltage regulator would not be enabled). */ + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed and if there is no conversion on going on regular */ + /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ + /* called to update a parameter on the fly). */ + tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + + if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + && (tmp_adc_reg_is_conversion_on_going == 0UL) + ) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Configuration of common ADC parameters */ + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - Internal voltage regulator (no parameter in HAL ADC init structure) */ + /* - Clock configuration */ + /* - ADC resolution */ + /* - Oversampling */ + /* - Trigger frequency mode */ + /* Note: If low power mode AutoPowerOff is enabled, ADC enable */ + /* and disable phases are performed automatically by hardware */ + /* (in this case, flag ADC_FLAG_RDY is not set). */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Some parameters of this register are not reset, since they are set */ + /* by other functions and must be kept in case of usage of this */ + /* function on the fly (update of a parameter of ADC_InitTypeDef */ + /* without needing to reconfigure all other ADC groups/channels */ + /* parameters): */ + /* - internal measurement paths: Vbat, temperature sensor, Vref */ + /* (set into HAL_ADC_ConfigChannel() ) */ + + /* Configuration of ADC resolution */ + MODIFY_REG(hadc->Instance->CFGR1, + ADC_CFGR1_RES, + hadc->Init.Resolution); + + tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | + hadc->Init.Oversampling.Ratio | + hadc->Init.Oversampling.RightBitShift | + hadc->Init.Oversampling.TriggeredMode | + hadc->Init.TriggerFrequencyMode + ); + + if (hadc->Init.OversamplingMode == ENABLE) + { + SET_BIT(tmpCFGR2, ADC_CFGR2_OVSE); + } + + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_CKMODE | + ADC_CFGR2_LFTRIG | + ADC_CFGR2_OVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS | + ADC_CFGR2_TOVS, + tmpCFGR2); + + /* Configuration of ADC clock mode: asynchronous clock source */ + /* with selectable prescaler. */ + if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) && + ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) && + ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4)) + { + MODIFY_REG(ADC1_COMMON->CCR, + ADC_CCR_PRESC, + hadc->Init.ClockPrescaler & ADC_CCR_PRESC); + } + } + + /* Configuration of ADC: */ + /* - discontinuous mode */ + /* - LowPowerAutoWait mode */ + /* - LowPowerAutoPowerOff mode */ + /* - continuous conversion mode */ + /* - overrun */ + /* - external trigger to start conversion */ + /* - external trigger polarity */ + /* - data alignment */ + /* - resolution */ + /* - scan direction */ + /* - DMA continuous request */ + tmpCFGR1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | + ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | + hadc->Init.DataAlign | + ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | + ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); + + /* Update setting of discontinuous mode only if continuous mode is disabled */ + if (hadc->Init.DiscontinuousConvMode == ENABLE) + { + if (hadc->Init.ContinuousConvMode == DISABLE) + { + /* Enable the selected ADC group regular discontinuous mode */ + tmpCFGR1 |= ADC_CFGR1_DISCEN; + } + else + { + /* ADC regular group discontinuous was intended to be enabled, */ + /* but ADC regular group modes continuous and sequencer discontinuous */ + /* cannot be enabled simultaneously. */ + + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | + hadc->Init.ExternalTrigConvEdge); + } + + /* Update ADC configuration register with previous settings */ + MODIFY_REG(hadc->Instance->CFGR1, + ADC_CFGR1_DISCEN | + ADC_CFGR1_AUTOFF | + ADC_CFGR1_WAIT | + ADC_CFGR1_CONT | + ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTSEL | + ADC_CFGR1_EXTEN | + ADC_CFGR1_ALIGN | + ADC_CFGR1_SCANDIR | + ADC_CFGR1_DMACFG, + tmpCFGR1); + + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_LFTRIG | + ADC_CFGR2_OVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS | + ADC_CFGR2_TOVS, + tmpCFGR2); + + /* Channel sampling time configuration */ + LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1); + LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2); + + /* Configuration of regular group sequencer: */ + /* - if scan mode is disabled, regular channels sequence length is set to */ + /* 0x00: 1 channel converted (channel on regular rank 1) */ + /* Parameter "NbrOfConversion" is discarded. */ + /* Note: Scan mode is not present by hardware on this device, but */ + /* emulated by software for alignment over all STM32 devices. */ + /* - if scan mode is enabled, regular channels sequence length is set to */ + /* parameter "NbrOfConversion". */ + /* Channels must be configured into each rank using function */ + /* "HAL_ADC_ConfigChannel()". */ + if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) + { + /* Set sequencer scan length by clearing ranks above rank 1 */ + /* and do not modify rank 1 value. */ + SET_BIT(hadc->Instance->CHSELR, + ADC_CHSELR_SQ2_TO_SQ8); + } + else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) + { + /* Count number of ranks available in HAL ADC handle variable */ + uint32_t ADCGroupRegularSequencerRanksCount; + + /* Parse all ranks from 1 to 8 */ + for (ADCGroupRegularSequencerRanksCount = 0UL; ADCGroupRegularSequencerRanksCount < (8UL); ADCGroupRegularSequencerRanksCount++) + { + /* Check each sequencer rank until value of end of sequence */ + if (((hadc->ADCGroupRegularSequencerRanks >> (ADCGroupRegularSequencerRanksCount * 4UL)) & ADC_CHSELR_SQ1) == + ADC_CHSELR_SQ1) + { + break; + } + } + + if (ADCGroupRegularSequencerRanksCount == 1UL) + { + /* Set ADC group regular sequencer: */ + /* Set sequencer scan length by clearing ranks above rank 1 */ + /* and do not modify rank 1 value. */ + SET_BIT(hadc->Instance->CHSELR, + ADC_CHSELR_SQ2_TO_SQ8); + } + else + { + /* Set ADC group regular sequencer: */ + /* - Set ADC group regular sequencer to value memorized */ + /* in HAL ADC handle */ + /* Note: This value maybe be initialized at a unknown value, */ + /* therefore after the first call of "HAL_ADC_Init()", */ + /* each rank corresponding to parameter "NbrOfConversion" */ + /* must be set using "HAL_ADC_ConfigChannel()". */ + /* - Set sequencer scan length by clearing ranks above maximum rank */ + /* and do not modify other ranks value. */ + MODIFY_REG(hadc->Instance->CHSELR, + ADC_CHSELR_SQ_ALL, + (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) | (hadc->ADCGroupRegularSequencerRanks) + ); + } + } + + /* Check back that ADC registers have effectively been configured to */ + /* ensure of no potential problem of ADC core peripheral clocking. */ + /* Check through register CFGR1 (excluding analog watchdog configuration: */ + /* set into separate dedicated function, and bits of ADC resolution set */ + /* out of temporary variable 'tmpCFGR1'). */ + if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_RES)) + == tmpCFGR1) + { + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Deinitialize the ADC peripheral registers to their default reset + * values, with deinitialization of the ADC MSP. + * @note For devices with several ADCs: reset of ADC common registers is done + * only if all ADCs sharing the same common group are disabled. + * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: + * all ADC instances use the same core clock at RCC level, disabling + * the core clock reset all ADC instances). + * If this is not the case, reset of these common parameters reset is + * bypassed without error reporting: it can be the intended behavior in + * case of reset of a single ADC while the other ADCs sharing the same + * common group is still running. + * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: + * this saves more power by reducing leakage currents + * and is particularly interesting before entering MCU low-power modes. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check ADC handle */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + + /* Stop potential conversion on going, on regular group */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + + /* Disable ADC internal voltage regulator */ + LL_ADC_DisableInternalRegulator(hadc->Instance); + } + + /* Note: HAL ADC deInit is done independently of ADC conversion stop */ + /* and disable return status. In case of status fail, attempt to */ + /* perform deinitialization anyway and it is up user code in */ + /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */ + /* system RCC hard reset. */ + + /* ========== Reset ADC registers ========== */ + /* Reset register IER */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | + ADC_IT_AWD1 | ADC_IT_OVR | + ADC_IT_EOS | ADC_IT_EOC | + ADC_IT_EOSMP | ADC_IT_RDY)); + + /* Reset register ISR */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | + ADC_FLAG_AWD1 | ADC_FLAG_OVR | + ADC_FLAG_EOS | ADC_FLAG_EOC | + ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + + /* Reset register CR */ + /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ + /* "read-set": no direct reset applicable. */ + + /* Reset register CFGR1 */ + hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN | + ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | + ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN); + + /* Reset register CFGR2 */ + /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ + /* already done above. */ + hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; + + /* Reset register SMPR */ + hadc->Instance->SMPR &= ~ADC_SMPR_SMP1; + + /* Reset register TR1 */ + hadc->Instance->TR1 &= ~(ADC_TR1_HT1 | ADC_TR1_LT1); + + /* Reset register CHSELR */ + hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable */ + + /* Reset register CCR */ + ADC1_COMMON->CCR &= ~(ADC_CCR_VBATEN | ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_PRESC); + + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripheral: ADC state is */ + /* forced to a similar state after device power-on. */ + /* If needed, copy-paste and uncomment the following reset code into */ + /* function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ + /* */ + /* __HAL_RCC_ADC1_FORCE_RESET() */ + /* __HAL_RCC_ADC1_RELEASE_RESET() */ + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hadc->MspDeInitCallback(hadc); +#else + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Reset HAL ADC handle variable */ + hadc->ADCGroupRegularSequencerRanks = 0x00000000UL; + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set ADC state */ + hadc->State = HAL_ADC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Initialize the ADC MSP. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspInit must be implemented in the user file. + */ +} + +/** + * @brief DeInitialize the ADC MSP. + * @param hadc ADC handle + * @note All ADC instances use the same core clock at RCC level, disabling + * the core clock reset all ADC instances). + * @retval None + */ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspDeInit must be implemented in the user file. + */ +} + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ADC Callback + * To be used instead of the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID + * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = pCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = pCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : + hadc->LevelOutOfWindow2Callback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : + hadc->LevelOutOfWindow3Callback = pCallback; + break; + + case HAL_ADC_END_OF_SAMPLING_CB_ID : + hadc->EndOfSamplingCallback = pCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a ADC Callback + * ADC callback is redirected to the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID + * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hadc->State & HAL_ADC_STATE_READY) != 0) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = HAL_ADC_ErrorCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : + hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : + hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; + break; + + case HAL_ADC_END_OF_SAMPLING_CB_ID : + hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions + * @brief ADC IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of regular group. + (+) Stop conversion of regular group. + (+) Poll for conversion complete on regular group. + (+) Poll for conversion event. + (+) Get result of regular channel conversion. + (+) Start conversion of regular group and enable interruptions. + (+) Stop conversion of regular group and disable interruptions. + (+) Handle ADC interrupt request + (+) Start conversion of regular group and enable DMA transfer. + (+) Stop conversion of regular group and disable ADC DMA transfer. +@endverbatim + * @{ + */ + +/** + * @brief Enable ADC, start conversion of regular group. + * @note Interruptions enabled in this function: None. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Set ADC error code */ + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Clear ADC group regular conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + } + else + { + tmp_hal_status = HAL_BUSY; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC peripheral. + * @note: ADC peripheral disable is forcing stop of potential + * conversion on injected group. If injected group is under use, it + * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on ADC group regular */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Wait for regular group conversion to be completed. + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function, with an exception: + * if low power feature "LowPowerAutoWait" is enabled, flags are + * not cleared to not interfere with this feature until data register + * is read using function HAL_ADC_GetValue(). + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence (ADC init + * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t tmp_Flag_End; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* If end of conversion selected to end of sequence conversions */ + if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) + { + tmp_Flag_End = ADC_FLAG_EOS; + } + /* If end of conversion selected to end of unitary conversion */ + else /* ADC_EOC_SINGLE_CONV */ + { + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and and polling for end of each conversion. */ + if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + return HAL_ERROR; + } + else + { + tmp_Flag_End = (ADC_FLAG_EOC); + } + } + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Wait until End of unitary conversion or sequence conversions flag is raised */ + while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) + { + /* Check whether end of sequence is reached */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Clear end of conversion flag of regular group if low power feature */ + /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ + /* until data register is read using function HAL_ADC_GetValue(). */ + if (hadc->Init.LowPowerAutoWait == DISABLE) + { + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Poll for ADC event. + * @param hadc ADC handle + * @param EventType the ADC event type. + * This parameter can be one of the following values: + * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event + * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) + * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) + * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) + * @arg @ref ADC_OVR_EVENT ADC Overrun event + * @param Timeout Timeout value in millisecond. + * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. + * Indeed, the latter is reset only if hadc->Init.Overrun field is set + * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten + * by a new converted data as soon as OVR is cleared. + * To reset OVR flag once the preserved data is retrieved, the user can resort + * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EVENT_TYPE(EventType)); + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Check selected event flag */ + while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + + switch (EventType) + { + /* End Of Sampling event */ + case ADC_EOSMP_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); + + /* Clear the End Of Sampling flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); + + break; + + /* Analog watchdog (level out of window) event */ + /* Note: In case of several analog watchdog enabled, if needed to know */ + /* which one triggered and on which ADCx, test ADC state of analog watchdog */ + /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ + /* For example: */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ + + /* Check analog watchdog 1 flag */ + case ADC_AWD_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); + + break; + + /* Check analog watchdog 2 flag */ + case ADC_AWD2_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); + + break; + + /* Check analog watchdog 3 flag */ + case ADC_AWD3_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); + + break; + + /* Overrun event */ + default: /* Case ADC_OVR_EVENT */ + /* If overrun is set to overwrite previous data, overrun event is not */ + /* considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + } + else + { + /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN + otherwise, data register is potentially overwritten by new converted data as soon + as OVR is cleared. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + break; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enable ADC, start conversion of regular group with interruption. + * @note Interruptions enabled in this function according to initialization + * setting : EOC (end of conversion), EOS (end of sequence), + * OVR overrun. + * Each of these interruptions has its dedicated callback function. + * @note To guarantee a proper reset of all interruptions once all the needed + * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure + * a correct stop of the IT-based conversions. + * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling + * interruption. If required (e.g. in case of oversampling with trigger + * mode), the user must: + * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) + * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) + * before calling HAL_ADC_Start_IT(). + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + + /* Set ADC error code */ + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Clear ADC group regular conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Disable all interruptions before enabling the desired ones */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + + /* Enable ADC end of conversion interrupt */ + switch (hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); + break; + } + + /* Enable ADC overrun interrupt */ + /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is + ADC_IT_OVR enabled; otherwise data overwrite is considered as normal + behavior and no CPU time is lost for a non-processed interruption */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + } + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + + } + else + { + tmp_hal_status = HAL_BUSY; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on ADC group regular */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable ADC end of conversion interrupt for regular group */ + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Enable ADC, start conversion of regular group and transfer result through DMA. + * @note Interruptions enabled in this function: + * overrun (if applicable), DMA half transfer, DMA transfer complete. + * Each of these interruptions has its dedicated callback function. + * @param hadc ADC handle + * @param pData Destination Buffer address. + * @param Length Number of data to be transferred from ADC peripheral to memory + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Specific case for first call occurrence of this function (DMA transfer */ + /* not activated and ADC disabled), DMA transfer must be activated */ + /* with ADC disabled. */ + if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) == 0UL) + { + if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + { + /* Disable ADC */ + LL_ADC_Disable(hadc->Instance); + } + + /* Enable ADC DMA mode */ + hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; + } + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Set ADC error code */ + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC */ + /* operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Start the DMA channel */ + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + } + else + { + tmp_hal_status = HAL_BUSY; + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable + * ADC peripheral. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* 1. Stop potential ADC group regular conversion on going */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable the DMA channel (in case of DMA in circular mode or stop */ + /* while DMA transfer is on going) */ + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) + { + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } + } + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* 2. Disable the ADC peripheral */ + /* Update "tmp_hal_status" only if DMA channel disabling passed, */ + /* to keep in memory a potential failing status. */ + if (tmp_hal_status == HAL_OK) + { + tmp_hal_status = ADC_Disable(hadc); + } + else + { + (void)ADC_Disable(hadc); + } + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + + /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ + CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Get ADC regular group conversion result. + * @note Reading register DR automatically clears ADC flag EOC + * (ADC group regular end of unitary conversion). + * @note This function does not clear ADC flag EOS + * (ADC group regular end of sequence conversion). + * Occurrence of flag EOS rising: + * - If sequencer is composed of 1 rank, flag EOS is equivalent + * to flag EOC. + * - If sequencer is composed of several ranks, during the scan + * sequence flag EOC only is raised, at the end of the scan sequence + * both flags EOC and EOS are raised. + * To clear this flag, either use function: + * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming + * model polling: @ref HAL_ADC_PollForConversion() + * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). + * @param hadc ADC handle + * @retval ADC group regular conversion data + */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Note: EOC flag is not cleared here by software because automatically */ + /* cleared by hardware when reading register DR. */ + + /* Return ADC converted value */ + return hadc->Instance->DR; +} + +/** + * @brief Handle ADC interrupt request. + * @param hadc ADC handle + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) +{ + uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ + uint32_t tmp_isr = hadc->Instance->ISR; + uint32_t tmp_ier = hadc->Instance->IER; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + + /* ========== Check End of Sampling flag for ADC group regular ========== */ + if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) + { + /* Update state machine on end of sampling status if not in error state */ + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); + } + + /* End Of Sampling callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->EndOfSamplingCallback(hadc); +#else + HAL_ADCEx_EndOfSamplingCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); + } + + /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ + if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || + (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) + { + /* Update state machine on conversion status if not in error state */ + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + } + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going */ + /* to disable interruption. */ + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) + { + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Conversion complete callback */ + /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ + /* to determine if conversion has been triggered from EOC or EOS, */ + /* possibility to use: */ + /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ + /* conversion flags clear induces the release of the preserved data.*/ + /* Therefore, if the preserved data value is needed, it must be */ + /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); + } + + /* ========== Check Analog watchdog 1 flag ========== */ + if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Level out of window 1 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else + HAL_ADC_LevelOutOfWindowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); + } + + /* ========== Check analog watchdog 2 flag ========== */ + if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Level out of window 2 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindow2Callback(hadc); +#else + HAL_ADCEx_LevelOutOfWindow2Callback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); + } + + /* ========== Check analog watchdog 3 flag ========== */ + if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Level out of window 3 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindow3Callback(hadc); +#else + HAL_ADCEx_LevelOutOfWindow3Callback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); + } + + /* ========== Check Overrun flag ========== */ + if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) + { + /* If overrun is set to overwrite previous data (default setting), */ + /* overrun event is not considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + /* Exception for usage with DMA overrun event always considered as an */ + /* error. */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + overrun_error = 1UL; + } + else + { + /* Check DMA configuration */ + if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE) + { + overrun_error = 1UL; + } + } + + if (overrun_error == 1UL) + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Error callback */ + /* Note: In case of overrun, ADC conversion data is preserved until */ + /* flag OVR is reset. */ + /* Therefore, old ADC conversion data can be retrieved in */ + /* function "HAL_ADC_ErrorCallback()". */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + + /* ========== Check channel configuration ready flag ========== */ + if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY)) + { + /* Level out of window 1 callback */ + HAL_ADCEx_ChannelConfigReadyCallback(hadc); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_CCRDY); + } +} + +/** + * @brief Conversion complete callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Conversion DMA half-transfer callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog 1 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC error callback in non-blocking mode + * (ADC conversion with interruption or transfer by DMA). + * @note In case of error due to overrun when using ADC with DMA transfer + * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". + * - If needed, restart a new ADC conversion using function + * "HAL_ADC_Start_DMA()" + * (this function is also clearing overrun flag) + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ErrorCallback must be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels on regular group + (+) Configure the analog watchdog + +@endverbatim + * @{ + */ + +/** + * @brief Configure a channel to be assigned to ADC group regular. + * @note In case of usage of internal measurement channels: + * Vbat/VrefInt/TempSensor. + * These internal paths can be disabled using function + * HAL_ADC_DeInit(). + * @note Possibility to update parameters on the fly: + * This function initializes channel into ADC group regular, + * following calls to this function can be used to reconfigure + * some parameters of structure "ADC_ChannelConfTypeDef" on the fly, + * without resetting the ADC. + * The setting of these parameters is conditioned to ADC state: + * Refer to comments of structure "ADC_ChannelConfTypeDef". + * @param hadc ADC handle + * @param sConfig Structure of ADC channel assigned to ADC group regular. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_config_internal_channel; + __IO uint32_t wait_loop_index = 0UL; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_SAMPLING_TIME_COMMON(sConfig->SamplingTime)); + + if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || + (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) + { + assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(sConfig->Rank)); + } + else + { + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + + assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Channel number */ + /* - Channel sampling time */ + /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Configure channel: depending on rank setting, add it or remove it from */ + /* ADC sequencer. */ + /* If sequencer set to not fully configurable with channel rank set to */ + /* none, remove the channel from the sequencer. */ + /* Otherwise (sequencer set to fully configurable or to to not fully */ + /* configurable with channel rank to be set), configure the selected */ + /* channel. */ + if (sConfig->Rank != ADC_RANK_NONE) + { + /* Regular sequence configuration */ + /* Note: ADC channel configuration requires few ADC clock cycles */ + /* to be ready. Processing of ADC settings in this function */ + /* induce that a specific wait time is not necessary. */ + /* For more details on ADC channel configuration ready, */ + /* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */ + if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || + (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) + { + /* Sequencer set to not fully configurable: */ + /* Set the channel by enabling the corresponding bitfield. */ + LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel); + } + else + { + /* Sequencer set to fully configurable: */ + /* Set the channel by entering it into the selected rank. */ + + /* Memorize the channel set into variable in HAL ADC handle */ + MODIFY_REG(hadc->ADCGroupRegularSequencerRanks, + ADC_CHSELR_SQ1 << (sConfig->Rank & 0x1FUL), + __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) << (sConfig->Rank & 0x1FUL)); + + /* If the selected rank is below ADC group regular sequencer length, */ + /* apply the configuration in ADC register. */ + /* Note: Otherwise, configuration is not applied. */ + /* To apply it, parameter'NbrOfConversion' must be increased. */ + if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion) + { + LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); + } + } + + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); + + /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + /* internal measurement paths enable: If internal channel selected, */ + /* enable dedicated internal buffers and path. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit() or removing the channel from sequencer with */ + /* channel configuration parameter "Rank". */ + if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + { + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + /* If the requested internal measurement path has already been enabled, */ + /* bypass the configuration processing. */ + if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && + ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); + + /* Delay for temperature sensor stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); + } + else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && + ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); + } + else + { + /* nothing to do */ + } + } + } + else + { + /* Regular sequencer configuration */ + /* Note: Case of sequencer set to fully configurable: */ + /* Sequencer rank cannot be disabled, only affected to */ + /* another channel. */ + /* To remove a rank, use parameter 'NbrOfConversion". */ + if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || + (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) + { + /* Sequencer set to not fully configurable: */ + /* Reset the channel by disabling the corresponding bitfield. */ + LL_ADC_REG_SetSequencerChRem(hadc->Instance, sConfig->Channel); + } + + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ + /* If internal channel selected, enable dedicated internal buffers and */ + /* paths. */ + if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) + { + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel); + } + else if (sConfig->Channel == ADC_CHANNEL_VBAT) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + ~LL_ADC_PATH_INTERNAL_VBAT & tmp_config_internal_channel); + } + else if (sConfig->Channel == ADC_CHANNEL_VREFINT) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel); + } + else + { + /* nothing to do */ + } + } + } + } + + /* If a conversion is on going on regular group, no update on regular */ + /* channel could be done on neither of the channel configuration structure */ + /* parameters. */ + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Configure the analog watchdog. + * @note Possibility to update parameters on the fly: + * This function initializes the selected analog watchdog, successive + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting + * the ADC. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_AnalogWDGConfTypeDef". + * @note On this STM32 series, analog watchdog thresholds can be modified + * while ADC conversion is on going. + * In this case, some constraints must be taken into account: + * the programmed threshold values are effective from the next + * ADC EOC (end of unitary conversion). + * Considering that registers write delay may happen due to + * bus activity, this might cause an uncertainty on the + * effective timing of the new programmed threshold values. + * @param hadc ADC handle + * @param AnalogWDGConfig Structure of ADC analog watchdog configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmpAWDHighThresholdShifted; + uint32_t tmpAWDLowThresholdShifted; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); + assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); + assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + + if (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) + { + assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + } + + /* Verify thresholds range */ + if (hadc->Init.OversamplingMode == ENABLE) + { + /* Case of oversampling enabled: depending on ratio and shift configuration, + analog watchdog thresholds can be higher than ADC resolution. + Verify if thresholds are within maximum thresholds range. */ + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); + } + else + { + /* Verify if thresholds are within the selected ADC resolution */ + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on ADC group regular: */ + /* - Analog watchdog channels */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Analog watchdog configuration */ + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + { + /* Configuration of analog watchdog: */ + /* - Set the analog watchdog enable mode: one or overall group of */ + /* channels. */ + switch (AnalogWDGConfig->WatchdogMode) + { + case ADC_ANALOGWATCHDOG_SINGLE_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, + __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); + break; + + case ADC_ANALOGWATCHDOG_ALL_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); + break; + + default: /* ADC_ANALOGWATCHDOG_NONE */ + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); + break; + } + + /* Update state, clear previous result related to AWD1 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD1(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if (AnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD1(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD1(hadc->Instance); + } + } + /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ + else + { + switch (AnalogWDGConfig->WatchdogMode) + { + case ADC_ANALOGWATCHDOG_SINGLE_REG: + /* Update AWD by bitfield to keep the possibility to monitor */ + /* several channels by successive calls of this function. */ + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + { + SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + } + else + { + SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); + } + break; + + case ADC_ANALOGWATCHDOG_ALL_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG); + break; + + default: /* ADC_ANALOGWATCHDOG_NONE */ + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); + break; + } + + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + { + /* Update state, clear previous result related to AWD2 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD2(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if (AnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD2(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD2(hadc->Instance); + } + } + /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ + else + { + /* Update state, clear previous result related to AWD3 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD3(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if (AnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD3(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD3(hadc->Instance); + } + } + } + + } + + /* Analog watchdog thresholds configuration */ + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + { + /* Shift the offset with respect to the selected ADC resolution: */ + /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ + /* are set to 0. */ + tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); + tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); + } + /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ + else + { + /* No need to shift the offset with respect to the selected ADC resolution: */ + /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ + /* are set to 0. */ + tmpAWDHighThresholdShifted = AnalogWDGConfig->HighThreshold; + tmpAWDLowThresholdShifted = AnalogWDGConfig->LowThreshold; + } + + /* Set ADC analog watchdog thresholds value of both thresholds high and low */ + LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, + tmpAWDLowThresholdShifted); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions + * @brief ADC Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral state and errors functions ##### + =============================================================================== + [..] + This subsection provides functions to get in run-time the status of the + peripheral. + (+) Check the ADC state + (+) Check the ADC error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the ADC handle state. + * @note ADC state machine is managed by bitfields, ADC status must be + * compared with states bits. + * For example: + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " + * @param hadc ADC handle + * @retval ADC handle state (bitfield on 32 bits) + */ +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Return ADC handle state */ + return hadc->State; +} + +/** + * @brief Return the ADC error code. + * @param hadc ADC handle + * @retval ADC error code (bitfield on 32 bits) + */ +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + return hadc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @brief Stop ADC conversion. + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped to disable the ADC. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Verification if ADC is not already stopped on regular group to bypass */ + /* this function if not needed. */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) + { + /* Stop potential conversion on going on regular group */ + /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ + if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) + { + /* Stop ADC group regular conversion */ + LL_ADC_REG_StopConversion(hadc->Instance); + } + + /* Wait for conversion effectively stopped */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Enable the selected ADC. + * @note Prerequisite condition to use this function: ADC must be disabled + * and voltage regulator must be enabled (done into HAL_ADC_Init()). + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) +{ + uint32_t tickstart; + __IO uint32_t wait_loop_index = 0UL; + + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ + /* enabling phase not yet completed: flag ADC ready not yet set). */ + /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ + /* causes: ADC clock not running, ...). */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Check if conditions to enable the ADC are fulfilled */ + if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + + /* Enable the ADC peripheral */ + LL_ADC_Enable(hadc->Instance); + + if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL) + { + /* Delay for temperature sensor buffer stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware and flag ADC ready is not set. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + { + /* Wait for ADC effectively enabled */ + tickstart = HAL_GetTick(); + + while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit + has been cleared (after a calibration), ADEN bit is reset by the + calibration logic. + The workaround is to continue setting ADEN until ADRDY is becomes 1. + Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this + 4 ADC clock cycle duration */ + /* Note: Test of ADC enabled required due to hardware constraint to */ + /* not enable ADC if already enabled. */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + LL_ADC_Enable(hadc->Instance); + } + + if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Disable the selected ADC. + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) +{ + uint32_t tickstart; + const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); + + /* Verification if ADC is not already disabled: */ + /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ + /* disabled. */ + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) + && (tmp_adc_is_disable_on_going == 0UL) + ) + { + /* Check if conditions to disable the ADC are fulfilled */ + if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) + { + /* Disable the ADC peripheral */ + LL_ADC_Disable(hadc->Instance); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + + /* Wait for ADC effectively disabled */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going */ + /* to disable interruption. */ + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) + { + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else /* DMA and-or internal error occurred */ + { + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) + { + /* Call HAL ADC Error Callback function */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else + { + /* Call ADC DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } + } +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Half conversion callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvHalfCpltCallback(hadc); +#else + HAL_ADC_ConvHalfCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + + /* Set ADC error code to DMA error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); + + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c (revision 3) @@ -0,0 +1,356 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_adc_ex.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Converter (ADC) + * peripheral: + * + Operation functions + * ++ Calibration + * +++ ADC automatic self-calibration + * +++ Calibration factors get or set + * Other functions (generic functions) are available in file + * "stm32g0xx_hal_adc.c". + * + @verbatim + [..] + (@) Sections "ADC peripheral features" and "How to use this driver" are + available in file of generic functions "stm32g0xx_hal_adc.c". + [..] + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup ADCEx ADCEx + * @brief ADC Extended HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants + * @{ + */ + +/* Fixed timeout value for ADC calibration. */ +/* Values defined to be higher than worst cases: maximum ratio between ADC */ +/* and CPU clock frequencies. */ +/* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock */ +/* source PLL 8MHz, ADC clock prescaler 256), CPU frequency 52MHz. */ +/* Calibration time max = 116 / fADC (refer to datasheet) */ +/* = 193 024 CPU cycles */ +#define ADC_CALIBRATION_TIMEOUT (193024UL) /*!< ADC calibration time-out value (unit: CPU cycles) */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions + * @{ + */ + +/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Perform the ADC self-calibration. + (+) Get calibration factors. + (+) Set calibration factors. + +@endverbatim + * @{ + */ + +/** + * @brief Perform an ADC automatic self-calibration + * Calibration prerequisite: ADC must be disabled (execute this + * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). + * @note Calibration factor can be read after calibration, using function + * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + __IO uint32_t wait_loop_index = 0UL; + uint32_t backup_setting_adc_dma_transfer; /* Note: Variable not declared as volatile because register read is already declared as volatile */ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Calibration prerequisite: ADC must be disabled. */ + + /* Disable the ADC (if not already disabled) */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Disable ADC DMA transfer request during calibration */ + /* Note: Specificity of this STM32 series: Calibration factor is */ + /* available in data register and also transferred by DMA. */ + /* To not insert ADC calibration factor among ADC conversion data */ + /* in array variable, DMA transfer must be disabled during */ + /* calibration. */ + backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + + /* Start ADC calibration */ + SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL); + + /* Wait for calibration completion */ + while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) + { + wait_loop_index++; + if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + + /* Restore ADC DMA transfer request after calibration */ + SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Note: No need to update variable "tmp_hal_status" here: already set */ + /* to state "HAL_ERROR" by function disabling the ADC. */ + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Get the calibration factor. + * @param hadc ADC handle. + * @retval Calibration value. + */ +uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Return the selected ADC calibration value */ + return ((hadc->Instance->CALFACT) & 0x0000007FU); +} + +/** + * @brief Set the calibration factor to overwrite automatic conversion result. + * ADC must be enabled and no conversion is ongoing. + * @param hadc ADC handle + * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) + * @retval HAL state + */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_adc_is_conversion_on_going_regular; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CALFACT(CalibrationFactor)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Verification of hardware constraints before modifying the calibration */ + /* factors register: ADC must be enabled, no conversion on going. */ + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) + && (tmp_adc_is_conversion_on_going_regular == 0UL) + ) + { + hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT; + hadc->Instance->CALFACT |= CalibrationFactor; + } + else + { + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + /* Update ADC error code */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + /* Update ADC state machine to error */ + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Analog watchdog 2 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog 3 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. + */ +} + + +/** + * @brief End Of Sampling callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC channel configuration ready callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_ChannelConfigReadyCallback must be implemented in the user file. + */ +} + +/** + * @} + */ + +/** + * @brief Disable ADC voltage regulator. + * @note Disabling voltage regulator allows to save power. This operation can + * be carried out only when ADC is disabled. + * @note To enable again the voltage regulator, the user is expected to + * resort to HAL_ADC_Init() API. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + LL_ADC_DisableInternalRegulator(hadc->Instance); + tmp_hal_status = HAL_OK; + } + else + { + tmp_hal_status = HAL_ERROR; + } + + return tmp_hal_status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_comp.c (revision 3) @@ -0,0 +1,1156 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_comp.c + * @author MCD Application Team + * @brief COMP HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the COMP peripheral: + * + Initialization and de-initialization functions + * + Start/Stop operation functions in polling mode + * + Start/Stop operation functions in interrupt mode (through EXTI interrupt) + * + Peripheral control functions + * + Peripheral state functions + * + @verbatim +================================================================================ + ##### COMP Peripheral features ##### +================================================================================ + + [..] + The STM32G0xx device family integrates two analog comparators instances: + COMP1, COMP2. + (#) Comparators input minus (inverting input) and input plus (non inverting input) + can be set to internal references or to GPIO pins + (refer to GPIO list in reference manual). + + (#) Comparators output level is available using HAL_COMP_GetOutputLevel() + and can be redirected to other peripherals: GPIO pins (in mode + alternate functions for comparator), timers. + (refer to GPIO list in reference manual). + + (#) The comparators have interrupt capability through the EXTI controller + with wake-up from sleep and stop modes. + + (#) Pairs of comparators instances can be combined in window mode + (2 consecutive instances odd and even COMP and COMP). + + From the corresponding IRQ handler, the right interrupt source can be retrieved + using macro __HAL_COMP_COMPx_EXTI_GET_FLAG(). + + ##### How to use this driver ##### +================================================================================ + [..] + This driver provides functions to configure and program the comparator instances + of STM32G0xx devices. + + To use the comparator, perform the following steps: + + (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit(): + (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode + using HAL_GPIO_Init(). + (++) If needed, configure the GPIO connected to comparator output in alternate function mode + using HAL_GPIO_Init(). + (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and + selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator + interrupt vector using HAL_NVIC_EnableIRQ() function. + + (#) Configure the comparator using HAL_COMP_Init() function: + (++) Select the input minus (inverting input) + (++) Select the input plus (non-inverting input) + (++) Select the hysteresis + (++) Select the blanking source + (++) Select the output polarity + (++) Select the power mode + (++) Select the window mode + + -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() + to enable internal control clock of the comparators. + However, this is a legacy strategy. In future STM32 families, + COMP clock enable must be implemented by user in "HAL_COMP_MspInit()". + Therefore, for compatibility anticipation, it is recommended to + implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()". + + (#) Reconfiguration on-the-fly of comparator can be done by calling again + function HAL_COMP_Init() with new input structure parameters values. + + (#) Enable the comparator using HAL_COMP_Start() function. + + (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions + to manage comparator outputs (events and output level). + + (#) Disable the comparator using HAL_COMP_Stop() function. + + (#) De-initialize the comparator using HAL_COMP_DeInit() function. + + (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function. + The only way to unlock the comparator is a device hardware reset. + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_COMP_RegisterCallback() + to register an interrupt callback. + [..] + + Function HAL_COMP_RegisterCallback() allows to register following callbacks: + (+) TriggerCallback : callback for COMP trigger. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function HAL_COMP_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TriggerCallback : callback for COMP trigger. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + + By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET + all callbacks are set to the corresponding weak functions: + example HAL_COMP_TriggerCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit() + or HAL_COMP_Init() function. + [..] + + When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +#ifdef HAL_COMP_MODULE_ENABLED + +#if defined (COMP1) || defined (COMP2) + +/** @defgroup COMP COMP + * @brief COMP HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup COMP_Private_Constants + * @{ + */ + +/* Delay for COMP startup time. */ +/* Note: Delay required to reach propagation delay specification. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */ + +/* Delay for COMP voltage scaler stabilization time. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART_SCALER"). */ +/* Unit: us */ +#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL) /*!< Delay for COMP voltage scaler stabilization time */ + +#define COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup COMP_Exported_Functions COMP Exported Functions + * @{ + */ + +/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and de-initialization functions. + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions to initialize and de-initialize comparators + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the COMP according to the specified + * parameters in the COMP_InitTypeDef and initialize the associated handle. + * @note If the selected comparator is locked, initialization can't be performed. + * To unlock the configuration, perform a system reset. + * @param hcomp COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) +{ + uint32_t tmp_csr; + uint32_t exti_line; + uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */ + __IO uint32_t wait_loop_index = 0UL; + HAL_StatusTypeDef status = HAL_OK; +#if defined(COMP3) + __IO uint32_t * comp_common_odd; + __IO uint32_t * comp_common_even; +#endif + + /* Check the COMP handle allocation and lock status */ + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameters */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.InputPlus)); + assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InputMinus)); + assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol)); + assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode)); + assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); + assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); + assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); + assert_param(IS_COMP_WINDOWMODE(hcomp->Instance, hcomp->Init.WindowMode)); + if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE) + { + assert_param(IS_COMP_WINDOWOUTPUT(hcomp->Init.WindowOutput)); + } + + if(hcomp->State == HAL_COMP_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcomp->Lock = HAL_UNLOCKED; + + /* Set COMP error code to none */ + COMP_CLEAR_ERRORCODE(hcomp); + + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + /* Init the COMP Callback settings */ + hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ + + if (hcomp->MspInitCallback == NULL) + { + hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + /* Note: Internal control clock of the comparators must */ + /* be enabled in "HAL_COMP_MspInit()" */ + /* using "__HAL_RCC_SYSCFG_CLK_ENABLE()". */ + hcomp->MspInitCallback(hcomp); +#else + /* Init the low level hardware */ + /* Note: Internal control clock of the comparators must */ + /* be enabled in "HAL_COMP_MspInit()" */ + /* using "__HAL_RCC_SYSCFG_CLK_ENABLE()". */ + HAL_COMP_MspInit(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + } + + /* Memorize voltage scaler state before initialization */ + comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)); + + /* Set COMP parameters */ + tmp_csr = ( hcomp->Init.InputMinus + | hcomp->Init.InputPlus + | hcomp->Init.BlankingSrce + | hcomp->Init.Hysteresis + | hcomp->Init.OutputPol + | hcomp->Init.Mode + ); + + /* Set parameters in COMP register */ + /* Note: Update all bits except read-only, lock and enable bits */ + MODIFY_REG(hcomp->Instance->CSR, + COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | + COMP_CSR_WINMODE | COMP_CSR_POLARITY | COMP_CSR_HYST | + COMP_CSR_BLANKING , + tmp_csr + ); + + /* Set window mode */ + /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ + /* instances. Therefore, this function can update another COMP */ + /* instance that the one currently selected. */ +#if defined(COMP3) + if(hcomp->Instance == COMP3) + { + /* Note: Exception for STM32G0 devices featuring ADC3 instance: in common */ + /* group of COMP2 and COMP3, instances odd and even are inverted. */ + /* Perform switch of parameter selected. */ + comp_common_odd = &(COMP23_COMMON->CSR_EVEN); + comp_common_even = &(COMP23_COMMON->CSR_ODD); + } + else + { + comp_common_odd = &(COMP12_COMMON->CSR_ODD); + comp_common_even = &(COMP12_COMMON->CSR_EVEN); + } + + if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) + { + CLEAR_BIT(*comp_common_odd, COMP_CSR_WINMODE); + SET_BIT(*comp_common_even, COMP_CSR_WINMODE); + } + else if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) + { + SET_BIT(*comp_common_odd, COMP_CSR_WINMODE); + CLEAR_BIT(*comp_common_even, COMP_CSR_WINMODE); + } + else + { + CLEAR_BIT(*comp_common_odd, COMP_CSR_WINMODE); + CLEAR_BIT(*comp_common_even, COMP_CSR_WINMODE); + } + + /* Set window mode output */ + /* Note: Window mode mode output can also be used when window mode */ + /* is disabled, to use comparators in independent mode with their */ + /* output connected through exclusive-or circuitry. */ + switch (hcomp->Init.WindowOutput) + { + case COMP_WINDOWOUTPUT_COMP1: /* idem COMP_WINDOWOUTPUT_COMP3 (same literal value) */ + SET_BIT(*comp_common_odd, COMP_CSR_WINOUT); + CLEAR_BIT(*comp_common_even, COMP_CSR_WINOUT); + break; + + case COMP_WINDOWOUTPUT_COMP2: + CLEAR_BIT(*comp_common_odd, COMP_CSR_WINOUT); + SET_BIT(*comp_common_even, COMP_CSR_WINOUT); + break; + + case COMP_WINDOWOUTPUT_BOTH: + SET_BIT(*comp_common_odd, COMP_CSR_WINOUT); + SET_BIT(*comp_common_even, COMP_CSR_WINOUT); + break; + + default: /* COMP_WINDOWOUTPUT_EACH_COMP */ + CLEAR_BIT(*comp_common_odd, COMP_CSR_WINOUT); + CLEAR_BIT(*comp_common_even, COMP_CSR_WINOUT); + break; + } +#else + if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) + { + CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); + SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + } + else if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) + { + SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); + CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + } + else + { + CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); + CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + } + + /* Set window mode output */ + /* Note: Window mode mode output can also be used when window mode */ + /* is disabled, to use comparators in independent mode with their */ + /* output connected through exclusive-or circuitry. */ + switch (hcomp->Init.WindowOutput) + { + case COMP_WINDOWOUTPUT_COMP1: + SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT); + CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); + break; + + case COMP_WINDOWOUTPUT_COMP2: + CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT); + SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); + break; + + case COMP_WINDOWOUTPUT_BOTH: + SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT); + SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); + break; + + default: /* COMP_WINDOWOUTPUT_EACH_COMP */ + CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT); + CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); + break; + } +#endif + + /* Delay for COMP scaler bridge voltage stabilization */ + /* Apply the delay if voltage scaler bridge is required and not already enabled */ + if ((READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)) != 0UL) && + (comp_voltage_scaler_initialized == 0UL) ) + { + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while(wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + + /* Get the EXTI line corresponding to the selected COMP instance */ + exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); + + /* Manage EXTI settings */ + if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) + { + /* Configure EXTI rising edge */ + if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) + { + LL_EXTI_EnableRisingTrig_0_31(exti_line); + } + else + { + LL_EXTI_DisableRisingTrig_0_31(exti_line); + } + + /* Configure EXTI falling edge */ + if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) + { + LL_EXTI_EnableFallingTrig_0_31(exti_line); + } + else + { + LL_EXTI_DisableFallingTrig_0_31(exti_line); + } + + /* Clear COMP EXTI pending bit (if any) */ + LL_EXTI_ClearRisingFlag_0_31(exti_line); + LL_EXTI_ClearFallingFlag_0_31(exti_line); + + /* Configure EXTI event mode */ + if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) + { + LL_EXTI_EnableEvent_0_31(exti_line); + } + else + { + LL_EXTI_DisableEvent_0_31(exti_line); + } + + /* Configure EXTI interrupt mode */ + if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) + { + LL_EXTI_EnableIT_0_31(exti_line); + } + else + { + LL_EXTI_DisableIT_0_31(exti_line); + } + } + else + { + /* Disable EXTI event mode */ + LL_EXTI_DisableEvent_0_31(exti_line); + + /* Disable EXTI interrupt mode */ + LL_EXTI_DisableIT_0_31(exti_line); + } + + /* Set HAL COMP handle state */ + /* Note: Transition from state reset to state ready, */ + /* otherwise (coming from state ready or busy) no state update. */ + if (hcomp->State == HAL_COMP_STATE_RESET) + { + hcomp->State = HAL_COMP_STATE_READY; + } + } + + return status; +} + +/** + * @brief DeInitialize the COMP peripheral. + * @note Deinitialization cannot be performed if the COMP configuration is locked. + * To unlock the configuration, perform a system reset. + * @param hcomp COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Set COMP_CSR register to reset value */ + WRITE_REG(hcomp->Instance->CSR, 0x00000000UL); + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + if (hcomp->MspDeInitCallback == NULL) + { + hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, RCC clock, NVIC */ + hcomp->MspDeInitCallback(hcomp); +#else + /* DeInit the low level hardware: GPIO, RCC clock, NVIC */ + HAL_COMP_MspDeInit(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + + /* Set HAL COMP handle state */ + hcomp->State = HAL_COMP_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcomp); + } + + return status; +} + +/** + * @brief Initialize the COMP MSP. + * @param hcomp COMP handle + * @retval None + */ +__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcomp); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_COMP_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the COMP MSP. + * @param hcomp COMP handle + * @retval None + */ +__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcomp); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_COMP_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User COMP Callback + * To be used instead of the weak predefined callback + * @param hcomp Pointer to a COMP_HandleTypeDef structure that contains + * the configuration information for the specified COMP. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID + * @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_COMP_STATE_READY == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_TRIGGER_CB_ID : + hcomp->TriggerCallback = pCallback; + break; + + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = pCallback; + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_COMP_STATE_RESET == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = pCallback; + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a COMP Callback + * COMP callback is redirected to the weak predefined callback + * @param hcomp Pointer to a COMP_HandleTypeDef structure that contains + * the configuration information for the specified COMP. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID + * @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_COMP_STATE_READY == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_TRIGGER_CB_ID : + hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ + break; + + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_COMP_STATE_RESET == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions + * @brief Start-Stop operation functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start a comparator instance. + (+) Stop a comparator instance. + +@endverbatim + * @{ + */ + +/** + * @brief Start the comparator. + * @param hcomp COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) +{ + __IO uint32_t wait_loop_index = 0UL; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + if(hcomp->State == HAL_COMP_STATE_READY) + { + /* Enable the selected comparator */ + SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN); + + /* Set HAL COMP handle state */ + hcomp->State = HAL_COMP_STATE_BUSY; + + /* Delay for COMP startup time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + while(wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Stop the comparator. + * @param hcomp COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */ + /* (all states except HAL_COMP_STATE_RESET and except locked status. */ + if(hcomp->State != HAL_COMP_STATE_RESET) + { + /* Disable the selected comparator */ + CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN); + + /* Set HAL COMP handle state */ + hcomp->State = HAL_COMP_STATE_READY; + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Comparator IRQ handler. + * @param hcomp COMP handle + * @retval None + */ +void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) +{ + /* Get the EXTI line corresponding to the selected COMP instance */ + uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); + uint32_t comparator_window_mode; + uint32_t comparator_window_exti_lines; + +#if defined(COMP3) + if(hcomp->Instance == COMP3) + { + /* Case of window mode with COMP2 and COMP3 */ + comparator_window_mode = READ_BIT(COMP23_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + comparator_window_exti_lines = (COMP_EXTI_LINE_COMP2 | COMP_EXTI_LINE_COMP3); + } + else + { + comparator_window_mode = READ_BIT(COMP23_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + if( (hcomp->Instance == COMP2) && (comparator_window_mode != 0UL)) + { + /* Case of window mode with COMP2 and COMP3 */ + comparator_window_exti_lines = (COMP_EXTI_LINE_COMP2 | COMP_EXTI_LINE_COMP3); + } + else + { + /* Case of window mode with COMP1 and COMP2 */ + comparator_window_mode = READ_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); + comparator_window_mode |= READ_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + comparator_window_exti_lines = (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2); + } + } +#else + comparator_window_mode = READ_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); + comparator_window_mode |= READ_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + comparator_window_exti_lines = (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2); +#endif + + /* Check COMP EXTI flag */ + if(LL_EXTI_IsActiveRisingFlag_0_31(exti_line) != 0UL) + { + /* Check whether comparator is in independent or window mode */ + if(comparator_window_mode != 0UL) + { + /* Clear COMP EXTI line pending bit of the pair of comparators */ + /* in window mode. */ + /* Note: Pair of comparators in window mode can both trig IRQ when */ + /* input voltage is changing from "out of window" area */ + /* (low or high ) to the other "out of window" area (high or low).*/ + /* Both flags must be cleared to call comparator trigger */ + /* callback is called once. */ + LL_EXTI_ClearRisingFlag_0_31(comparator_window_exti_lines); + } + else + { + /* Clear COMP EXTI line pending bit */ + LL_EXTI_ClearRisingFlag_0_31(exti_line); + } + + /* COMP trigger user callback */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + hcomp->TriggerCallback(hcomp); +#else + HAL_COMP_TriggerCallback(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + } + else if(LL_EXTI_IsActiveFallingFlag_0_31(exti_line) != 0UL) + { + /* Check whether comparator is in independent or window mode */ + if(comparator_window_mode != 0UL) + { + /* Clear COMP EXTI line pending bit of the pair of comparators */ + /* in window mode. */ + /* Note: Pair of comparators in window mode can both trig IRQ when */ + /* input voltage is changing from "out of window" area */ + /* (low or high ) to the other "out of window" area (high or low).*/ + /* Both flags must be cleared to call comparator trigger */ + /* callback is called once. */ + LL_EXTI_ClearFallingFlag_0_31(comparator_window_exti_lines); + } + else + { + /* Clear COMP EXTI line pending bit */ + LL_EXTI_ClearFallingFlag_0_31(exti_line); + } + + /* COMP trigger callback */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + hcomp->TriggerCallback(hcomp); +#else + HAL_COMP_TriggerCallback(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + } + else + { + /* nothing to do */ + } +} + +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions. + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the comparators. + +@endverbatim + * @{ + */ + +/** + * @brief Lock the selected comparator configuration. + * @note A system reset is required to unlock the comparator configuration. + * @note Locking the comparator from reset state is possible + * if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before. + * @param hcomp COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if(hcomp == NULL) + { + status = HAL_ERROR; + } + else if(__HAL_COMP_IS_LOCKED(hcomp)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Set HAL COMP handle state */ + switch(hcomp->State) + { + case HAL_COMP_STATE_RESET: + hcomp->State = HAL_COMP_STATE_RESET_LOCKED; + break; + case HAL_COMP_STATE_READY: + hcomp->State = HAL_COMP_STATE_READY_LOCKED; + break; + default: /* HAL_COMP_STATE_BUSY */ + hcomp->State = HAL_COMP_STATE_BUSY_LOCKED; + break; + } + } + + if(status == HAL_OK) + { + /* Set the lock bit corresponding to selected comparator */ + __HAL_COMP_LOCK(hcomp); + } + + return status; +} + +/** + * @brief Return the output level (high or low) of the selected comparator. + * The output level depends on the selected polarity. + * If the polarity is not inverted: + * - Comparator output is low when the input plus is at a lower + * voltage than the input minus + * - Comparator output is high when the input plus is at a higher + * voltage than the input minus + * If the polarity is inverted: + * - Comparator output is high when the input plus is at a lower + * voltage than the input minus + * - Comparator output is low when the input plus is at a higher + * voltage than the input minus + * @param hcomp COMP handle + * @retval Returns the selected comparator output level: + * @arg COMP_OUTPUT_LEVEL_LOW + * @arg COMP_OUTPUT_LEVEL_HIGH + * + */ +uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) +{ + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE) + >> COMP_OUTPUT_LEVEL_BITOFFSET_POS); +} + +/** + * @brief Comparator trigger callback. + * @param hcomp COMP handle + * @retval None + */ +__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcomp); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_COMP_TriggerCallback should be implemented in the user file + */ +} + + +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the COMP handle state. + * @param hcomp COMP handle + * @retval HAL state + */ +HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) +{ + /* Check the COMP handle allocation */ + if(hcomp == NULL) + { + return HAL_COMP_STATE_RESET; + } + + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Return HAL COMP handle state */ + return hcomp->State; +} + +/** + * @brief Return the COMP error code. + * @param hcomp COMP handle + * @retval COMP error code + */ +uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp) +{ + /* Check the parameters */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + return hcomp->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* COMP1 || COMP2 */ + +#endif /* HAL_COMP_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_cortex.c (revision 3) @@ -0,0 +1,417 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and Configuration functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex M0+ exceptions are managed by CMSIS functions. + (#) Enable and Configure the priority of the selected IRQ Channels. + The priority can be 0..3. + + -@- Lower priority values gives higher priority. + -@- Priority Order: + (#@) Lowest priority. + (#@) Lowest hardware priority (IRQn position). + + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + + -@- Negative value of IRQn_Type are not allowed. + + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x03). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32g0xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number . + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to stm32g0xx.h file) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 3. + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * with stm32g0xx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0+ based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn,PreemptPriority); +} + +/** + * @brief Enable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiate a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +/** + * @brief Get the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) + * @retval None + */ +uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) +{ + /* Get priority for Cortex-M system or device specific interrupts */ + return NVIC_GetPriority(IRQn); +} + +/** + * @brief Set Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Get Pending Interrupt (read the pending register in the NVIC + * and return the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clear the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g0xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Configure the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief Handle SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +#if (__MPU_PRESENT == 1U) +/** + * @brief Enable the MPU. + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + + +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + + +/** + * @brief Initialize and configure the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + if ((MPU_Init->Enable) != 0U) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + } + else + { + MPU->RBAR = 0x00U; + MPU->RASR = 0x00U; + } +} +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac.c (revision 3) @@ -0,0 +1,1509 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_dac.c + * @author MCD Application Team + * @brief DAC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Digital to Analog Converter (DAC) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + * + @verbatim + ============================================================================== + ##### DAC Peripheral features ##### + ============================================================================== + [..] + *** DAC Channels *** + ==================== + [..] + STM32G0 devices integrate two 12-bit Digital Analog Converters + + The 2 converters (i.e. channel1 & channel2) + can be used independently or simultaneously (dual mode): + (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip + peripherals (ex. timers). + (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip + peripherals (ex. timers). + + *** DAC Triggers *** + ==================== + [..] + Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE + and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. + [..] + Digital to Analog conversion can be triggered by: + (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9. + The used pin (GPIOx_PIN_9) must be configured in input mode. + + (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 + (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...) + + (#) Software using DAC_TRIGGER_SOFTWARE + + *** DAC Buffer mode feature *** + =============================== + [..] + Each DAC channel integrates an output buffer that can be used to + reduce the output impedance, and to drive external loads directly + without having to add an external operational amplifier. + To enable, the output buffer use + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; + [..] + (@) Refer to the device datasheet for more details about output + impedance value with and without output buffer. + + *** DAC connect feature *** + =============================== + [..] + Each DAC channel can be connected internally. + To connect, use + sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE; + + *** GPIO configurations guidelines *** + ===================== + [..] + When a DAC channel is used (ex channel1 on PA4) and the other is not + (ex channel2 on PA5 is configured in Analog and disabled). + Channel1 may disturb channel2 as coupling effect. + Note that there is no coupling on channel2 as soon as channel2 is turned on. + Coupling on adjacent channel could be avoided as follows: + when unused PA5 is configured as INPUT PULL-UP or DOWN. + PA5 is configured in ANALOG just before it is turned on. + + *** DAC Sample and Hold feature *** + ======================== + [..] + For each converter, 2 modes are supported: normal mode and + "sample and hold" mode (i.e. low power mode). + In the sample and hold mode, the DAC core converts data, then holds the + converted voltage on a capacitor. When not converting, the DAC cores and + buffer are completely turned off between samples and the DAC output is + tri-stated, therefore reducing the overall power consumption. A new + stabilization period is needed before each new conversion. + + The sample and hold allow setting internal or external voltage @ + low power consumption cost (output value can be at any given rate either + by CPU or DMA). + + The Sample and hold block and registers uses either LSI & run in + several power modes: run mode, sleep mode, low power run, low power sleep + mode & stop1 mode. + + Low power stop1 mode allows only static conversion. + + To enable Sample and Hold mode + Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI & + RCC_LSI_ON parameters. + + Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE; + & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime, + DAC_HoldTime & DAC_RefreshTime; + + *** DAC calibration feature *** + =================================== + [..] + (#) The 2 converters (channel1 & channel2) provide calibration capabilities. + (++) Calibration aims at correcting some offset of output buffer. + (++) The DAC uses either factory calibration settings OR user defined + calibration (trimming) settings (i.e. trimming mode). + (++) The user defined settings can be figured out using self calibration + handled by HAL_DACEx_SelfCalibrate. + (++) HAL_DACEx_SelfCalibrate: + (+++) Runs automatically the calibration. + (+++) Enables the user trimming mode + (+++) Updates a structure with trimming values with fresh calibration + results. + The user may store the calibration results for larger + (ex monitoring the trimming as a function of temperature + for instance) + + *** DAC wave generation feature *** + =================================== + [..] + Both DAC channels can be used to generate + (#) Noise wave + (#) Triangle wave + + *** DAC data format *** + ======================= + [..] + The DAC data format can be: + (#) 8-bit right alignment using DAC_ALIGN_8B_R + (#) 12-bit left alignment using DAC_ALIGN_12B_L + (#) 12-bit right alignment using DAC_ALIGN_12B_R + + *** DAC data value to voltage correspondence *** + ================================================ + [..] + The analog output voltage on each DAC channel pin is determined + by the following equation: + [..] + DAC_OUTx = VREF+ * DOR / 4095 + (+) with DOR is the Data Output Register + [..] + VEF+ is the input voltage reference (refer to the device datasheet) + [..] + e.g. To set DAC_OUT1 to 0.7V, use + (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + + *** DMA requests *** + ===================== + [..] + A DMA1 request can be generated when an external trigger (but not a software trigger) + occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA(). + DMA requests are mapped as following: + (#) DAC channel1: mapped on DMA channel1 request 8 + (#) DAC channel2: mapped on DMA channel2 request 9 + + [..] + (@) For Dual mode and specific signal (Triangle and noise) generation please + refer to Extended Features Driver description + + ##### How to use this driver ##### + ============================================================================== + [..] + (+) DAC APB clock must be enabled to get write access to DAC + registers using HAL_DAC_Init() + (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. + (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. + (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions. + + *** Calibration mode IO operation *** + ====================================== + [..] + (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset() + (+) Run the calibration using HAL_DACEx_SelfCalibrate() + (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming() + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the DAC peripheral using HAL_DAC_Start() + (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. + (+) Stop the DAC peripheral using HAL_DAC_Stop() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue(). + (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 + (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. + HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1() + (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. + (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. + (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. + (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. + (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. + (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. + (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. + (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. + (+) MspInitCallback : DAC MspInit. + (+) MspDeInitCallback : DAC MspdeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. + (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. + (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. + (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. + (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. + (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. + (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. + (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. + (+) MspInitCallback : DAC MspInit. + (+) MspDeInitCallback : DAC MspdeInit. + (+) All Callbacks + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init + and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit + or @ref HAL_DAC_Init function. + + When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + *** DAC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DAC HAL driver. + + (+) __HAL_DAC_ENABLE : Enable the DAC peripheral + (+) __HAL_DAC_DISABLE : Disable the DAC peripheral + (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags + (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status + + [..] + (@) You can refer to the DAC HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +#ifdef HAL_DAC_MODULE_ENABLED +#if defined(DAC1) + +/** @defgroup DAC DAC + * @brief DAC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DAC_Private_Constants DAC Private Constants + * @{ + */ +#define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions -------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Functions DAC Exported Functions + * @{ + */ + +/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DAC. + (+) De-initialize the DAC. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DAC peripheral according to the specified parameters + * in the DAC_InitStruct and initialize the associated handle. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) +{ + /* Check DAC handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); + + if (hdac->State == HAL_DAC_STATE_RESET) + { +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + /* Init the DAC Callback settings */ + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + + if (hdac->MspInitCallback == NULL) + { + hdac->MspInitCallback = HAL_DAC_MspInit; + } +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + /* Allocate lock resource and initialize it */ + hdac->Lock = HAL_UNLOCKED; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + /* Init the low level hardware */ + hdac->MspInitCallback(hdac); +#else + /* Init the low level hardware */ + HAL_DAC_MspInit(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } + + /* Initialize the DAC state*/ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Set DAC error code to none */ + hdac->ErrorCode = HAL_DAC_ERROR_NONE; + + /* Initialize the DAC state*/ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitialize the DAC peripheral registers to their default reset values. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac) +{ + /* Check DAC handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + if (hdac->MspDeInitCallback == NULL) + { + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + } + /* DeInit the low level hardware */ + hdac->MspDeInitCallback(hdac); +#else + /* DeInit the low level hardware */ + HAL_DAC_MspDeInit(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + /* Set DAC error code to none */ + hdac->ErrorCode = HAL_DAC_ERROR_NONE; + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the DAC MSP. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the DAC MSP. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion. + (+) Stop conversion. + (+) Start conversion and enable DMA transfer. + (+) Stop conversion and disable DMA transfer. + (+) Get result of conversion. + +@endverbatim + * @{ + */ + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, Channel); + + if (Channel == DAC_CHANNEL_1) + { + /* Check if software trigger enabled */ + if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) + { + /* Enable the selected DAC software conversion */ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); + } + } + else + { + /* Check if software trigger enabled */ + if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << Channel)) + { + /* Enable the selected DAC software conversion*/ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); + } + } + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables DAC and stop conversion of channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the Peripheral */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, + uint32_t Alignment) +{ + HAL_StatusTypeDef status; + uint32_t tmpreg = 0U; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + if (Channel == DAC_CHANNEL_1) + { + /* Set the DMA transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; + + /* Set the DMA half transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; + + /* Set the DMA error callback for channel1 */ + hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; + + /* Enable the selected DAC channel1 DMA request */ + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + + /* Case of use of channel 1 */ + switch (Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R1; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L1; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R1; + break; + default: + break; + } + } + else + { + /* Set the DMA transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; + + /* Set the DMA half transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; + + /* Set the DMA error callback for channel2 */ + hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; + + /* Enable the selected DAC channel2 DMA request */ + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + + /* Case of use of channel 2 */ + switch (Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R2; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L2; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R2; + break; + default: + break; + } + } + + /* Enable the DMA channel */ + if (Channel == DAC_CHANNEL_1) + { + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); + + /* Enable the DMA channel */ + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + } + else + { + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); + + /* Enable the DMA channel */ + status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdac); + + if (status == HAL_OK) + { + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, Channel); + } + else + { + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + } + + /* Return function status */ + return status; +} + +/** + * @brief Disables DAC and stop conversion of channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the selected DAC channel DMA request */ + hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL)); + + /* Disable the Peripheral */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Disable the DMA channel */ + + /* Channel1 is used */ + if (Channel == DAC_CHANNEL_1) + { + /* Disable the DMA channel */ + status = HAL_DMA_Abort(hdac->DMA_Handle1); + + /* Disable the DAC DMA underrun interrupt */ + __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); + } + else /* Channel2 is used for */ + { + /* Disable the DMA channel */ + status = HAL_DMA_Abort(hdac->DMA_Handle2); + + /* Disable the DAC DMA underrun interrupt */ + __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); + } + + /* Check if DMA Channel effectively disabled */ + if (status != HAL_OK) + { + /* Update DAC state machine to error */ + hdac->State = HAL_DAC_STATE_ERROR; + } + else + { + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Handles DAC interrupt request + * This function uses the interruption of DMA + * underrun. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) +{ + if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) + { + /* Check underrun flag of DAC channel 1 */ + if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to chanel1 DMA underrun error */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); + + /* Disable the selected DAC channel1 DMA request */ + CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + + /* Error callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->DMAUnderrunCallbackCh1(hdac); +#else + HAL_DAC_DMAUnderrunCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } + } + + if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) + { + /* Check underrun flag of DAC channel 2 */ + if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to channel2 DMA underrun error */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); + + /* Disable the selected DAC channel2 DMA request */ + CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + + /* Error callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->DMAUnderrunCallbackCh2(hdac); +#else + HAL_DACEx_DMAUnderrunCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Set the specified data holding register value for DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Alignment Specifies the data alignment. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data Data to be loaded in the selected data holding register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)hdac->Instance; + if (Channel == DAC_CHANNEL_1) + { + tmp += DAC_DHR12R1_ALIGNMENT(Alignment); + } + else + { + tmp += DAC_DHR12R2_ALIGNMENT(Alignment); + } + + /* Set the DAC channel selected data holding register */ + *(__IO uint32_t *) tmp = Data; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Conversion complete callback in non-blocking mode for Channel1 + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel1. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for channel1. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels. + (+) Set the specified data holding register value for DAC channel. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Returns the DAC channel data output register value */ + if (Channel == DAC_CHANNEL_1) + { + return hdac->Instance->DOR1; + } + else + { + return hdac->Instance->DOR2; + } +} + +/** + * @brief Configures the selected DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) +{ + uint32_t tmpreg1; + uint32_t tmpreg2; + uint32_t tickstart = 0U; + + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); + assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral)); + assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming)); + if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER) + { + assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)); + } + assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold)); + if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) + { + assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime)); + assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); + assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); + } + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) + /* Sample on old configuration */ + { + /* SampleTime */ + if (Channel == DAC_CHANNEL_1) + { + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* SHSR1 can be written when BWST1 is cleared */ + while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) + { + /* Update error code */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); + + /* Change the DMA state */ + hdac->State = HAL_DAC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + HAL_Delay(1); + hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; + } + else /* Channel 2 */ + { + /* SHSR2 can be written when BWST2 is cleared */ + + while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) + { + /* Update error code */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); + + /* Change the DMA state */ + hdac->State = HAL_DAC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + HAL_Delay(1U); + hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; + } + + /* HoldTime */ + MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); + /* RefreshTime */ + MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); + } + + if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) + /* USER TRIMMING */ + { + /* Get the DAC CCR value */ + tmpreg1 = hdac->Instance->CCR; + /* Clear trimming value */ + tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL)); + /* Configure for the selected trimming offset */ + tmpreg2 = sConfig->DAC_TrimmingValue; + /* Calculate CCR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); + /* Write to DAC CCR */ + hdac->Instance->CCR = tmpreg1; + } + /* else factory trimming is used (factory setting are available at reset)*/ + /* SW Nothing has nothing to do */ + + /* Get the DAC MCR value */ + tmpreg1 = hdac->Instance->MCR; + /* Clear DAC_MCR_MODEx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); + /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ + tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral); + /* Calculate MCR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); + /* Write to DAC MCR */ + hdac->Instance->MCR = tmpreg1; + + /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ + CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL)); + + /* Get the DAC CR value */ + tmpreg1 = hdac->Instance->CR; + /* Clear TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL)); + /* Configure for the selected DAC channel: trigger */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + tmpreg2 = sConfig->DAC_Trigger; + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); + /* Write to DAC CR */ + hdac->Instance->CR = tmpreg1; + /* Disable wave generation */ + hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL)); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DAC state. + (+) Check the DAC Errors. + +@endverbatim + * @{ + */ + +/** + * @brief return the DAC handle state + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL state + */ +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) +{ + /* Return DAC handle state */ + return hdac->State; +} + + +/** + * @brief Return the DAC error code + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval DAC Error Code + */ +uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) +{ + return hdac->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group1 + * @{ + */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DAC Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hdac DAC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID + * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID + * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID + * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID + * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID + * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID + * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID + * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID + * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID + * + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, + pDAC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdac); + + if (hdac->State == HAL_DAC_STATE_READY) + { + switch (CallbackID) + { + case HAL_DAC_CH1_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_ERROR_ID : + hdac->ErrorCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh1 = pCallback; + break; + case HAL_DAC_CH2_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_ERROR_ID : + hdac->ErrorCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh2 = pCallback; + break; + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = pCallback; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hdac->State == HAL_DAC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = pCallback; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdac); + return status; +} + +/** + * @brief Unregister a User DAC Callback + * DAC Callback is redirected to the weak (surcharged) predefined callback + * @param hdac DAC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Transfer Complete Callback ID + * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID + * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID + * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID + * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID + * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID + * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID + * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID + * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID + * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks + * @retval status + */ +HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdac); + + if (hdac->State == HAL_DAC_STATE_READY) + { + switch (CallbackID) + { + case HAL_DAC_CH1_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + break; + case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + break; + case HAL_DAC_CH1_ERROR_ID : + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + break; + case HAL_DAC_CH1_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + break; + case HAL_DAC_CH2_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + break; + case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + break; + case HAL_DAC_CH2_ERROR_ID : + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + break; + case HAL_DAC_CH2_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + break; + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = HAL_DAC_MspInit; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + case HAL_DAC_ALL_CB_ID : + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + hdac->MspInitCallback = HAL_DAC_MspInit; + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hdac->State == HAL_DAC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = HAL_DAC_MspInit; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdac); + return status; +} +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Functions + * @{ + */ + +/** + * @brief DMA conversion complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvCpltCallbackCh1(hdac); +#else + HAL_DAC_ConvCpltCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Conversion complete callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvHalfCpltCallbackCh1(hdac); +#else + HAL_DAC_ConvHalfCpltCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ErrorCallbackCh1(hdac); +#else + HAL_DAC_ErrorCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC1 */ + +#endif /* HAL_DAC_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dac_ex.c (revision 3) @@ -0,0 +1,621 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_dac_ex.c + * @author MCD Application Team + * @brief DAC HAL module driver. + * This file provides firmware functions to manage the extended + * functionalities of the DAC peripheral. + * + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + *** Dual mode IO operation *** + ============================== + (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : + Use HAL_DACEx_DualGetValue() to get digital data to be converted and use + HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in + Channel 1 and Channel 2. + + *** Signal generation operation *** + =================================== + (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. + (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. + + (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel. + (+) HAL_DACEx_SetUserTrimming to set user trimming value. + (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting + after reset, user setting if HAL_DACEx_SetUserTrimming have been used + at least one time after reset). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +#ifdef HAL_DAC_MODULE_ENABLED + +#if defined(DAC1) + +/** @defgroup DACEx DACEx + * @brief DAC Extended HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DACEx_Exported_Functions DACEx Exported Functions + * @{ + */ + +/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions + * @brief Extended IO operation functions + * +@verbatim + ============================================================================== + ##### Extended features functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion. + (+) Stop conversion. + (+) Start conversion and enable DMA transfer. + (+) Stop conversion and disable DMA transfer. + (+) Get result of conversion. + (+) Get result of dual mode conversion. + +@endverbatim + * @{ + */ + +/** + * @brief Enable or disable the selected DAC channel wave generation. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Amplitude Select max triangle amplitude. + * This parameter can be one of the following values: + * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 + * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 + * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 + * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 + * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 + * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 + * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 + * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 + * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 + * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 + * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 + * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the triangle wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enable or disable the selected DAC channel wave generation. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Amplitude Unmask DAC channel LFSR for noise wave generation. + * This parameter can be one of the following values: + * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation + * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the noise wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the specified data holding register value for dual DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Alignment Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * DAC_ALIGN_8B_R: 8bit right data alignment selected + * DAC_ALIGN_12B_L: 12bit left data alignment selected + * DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register. + * @note In dual mode, a unique register access is required to write in both + * DAC channels at the same time. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) +{ + uint32_t data; + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (Alignment == DAC_ALIGN_8B_R) + { + data = ((uint32_t)Data2 << 8U) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16U) | Data1; + } + + tmp = (uint32_t)hdac->Instance; + tmp += DAC_DHR12RD_ALIGNMENT(Alignment); + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Conversion complete callback in non-blocking mode for Channel2. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel2. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for Channel2. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Run the self calibration of one DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param sConfig DAC channel configuration structure. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming + * @retval HAL status + * @note Calibration runs about 7 ms. + */ + +HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + __IO uint32_t tmp; + uint32_t trimmingvalue; + uint32_t delta; + + /* store/restore channel configuration structure purpose */ + uint32_t oldmodeconfiguration; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Check the DAC handle allocation */ + /* Check if DAC running */ + if (hdac == NULL) + { + status = HAL_ERROR; + } + else if (hdac->State == HAL_DAC_STATE_BUSY) + { + status = HAL_ERROR; + } + else + { + /* Process locked */ + __HAL_LOCK(hdac); + + /* Store configuration */ + oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL))); + + /* Disable the selected DAC channel */ + CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL))); + + /* Set mode in MCR for calibration */ + MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U); + + /* Set DAC Channel1 DHR register to the middle value */ + tmp = (uint32_t)hdac->Instance; + + if (Channel == DAC_CHANNEL_1) + { + tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R); + } + else + { + tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R); + } + + *(__IO uint32_t *) tmp = 0x0800U; + + /* Enable the selected DAC channel calibration */ + /* i.e. set DAC_CR_CENx bit */ + SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); + + /* Init trimming counter */ + /* Medium value */ + trimmingvalue = 16U; + delta = 8U; + while (delta != 0U) + { + /* Set candidate trimming */ + MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); + + /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ + /* i.e. minimum time needed between two calibration steps */ + HAL_Delay(1); + + if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) + { + /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */ + trimmingvalue -= delta; + } + else + { + /* DAC_SR_CAL_FLAGx is LOW try lower trimming */ + trimmingvalue += delta; + } + delta >>= 1U; + } + + /* Still need to check if right calibration is current value or one step below */ + /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */ + /* Set candidate trimming */ + MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); + + /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ + /* i.e. minimum time needed between two calibration steps */ + HAL_Delay(1U); + + if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) + { + /* OPAMP_CSR_OUTCAL is actually one value more */ + trimmingvalue++; + /* Set right trimming */ + MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); + } + + /* Disable the selected DAC channel calibration */ + /* i.e. clear DAC_CR_CENx bit */ + CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL))); + + sConfig->DAC_TrimmingValue = trimmingvalue; + sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; + + /* Restore configuration */ + MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration); + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + } + + return status; +} + +/** + * @brief Set the trimming mode and trimming value (user trimming mode applied). + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param sConfig DAC configuration structure updated with new DAC trimming value. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param NewTrimmingValue DAC new trimming value + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, + uint32_t NewTrimmingValue) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue)); + + /* Check the DAC handle allocation */ + if (hdac == NULL) + { + status = HAL_ERROR; + } + else + { + /* Process locked */ + __HAL_LOCK(hdac); + + /* Set new trimming */ + MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL))); + + /* Update trimming mode */ + sConfig->DAC_UserTrimming = DAC_TRIMMING_USER; + sConfig->DAC_TrimmingValue = NewTrimmingValue; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + } + return status; +} + +/** + * @brief Return the DAC trimming value. + * @param hdac DAC handle + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval Trimming value : range: 0->31 + * + */ + +uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + /* Check the parameter */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Retrieve trimming */ + return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL)); +} + +/** + * @} + */ + +/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Set the specified data holding register value for DAC channel. + +@endverbatim + * @{ + */ + +/** + * @brief Return the last data output value of the selected DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) +{ + uint32_t tmp = 0U; + + tmp |= hdac->Instance->DOR1; + + tmp |= hdac->Instance->DOR2 << 16U; + + /* Returns the DAC channel data output register value */ + return tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DACEx_Private_Functions DACEx private functions + * @brief Extended private functions + * @{ + */ + +/** + * @brief DMA conversion complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvCpltCallbackCh2(hdac); +#else + HAL_DACEx_ConvCpltCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Conversion complete callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvHalfCpltCallbackCh2(hdac); +#else + HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ErrorCallbackCh2(hdac); +#else + HAL_DACEx_ErrorCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC1 */ + +#endif /* HAL_DAC_MODULE_ENABLED */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma.c (revision 3) @@ -0,0 +1,1192 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Channel + (except for internal SRAM / FLASH memories: no initialization is + necessary). Please refer to the Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Channel, program the required configuration through the following parameters: + Channel request, Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode + using HAL_DMA_Init() function. + + Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX + thanks to: + (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(); + (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); + + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function to register callbacks with HAL_DMA_RegisterCallback(). + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup DMA_Private_Functions DMA Private Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Channel source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); + + /* Compute the channel index */ +#if defined(DMA2) + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } +#else + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; +#endif + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ + CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); + + /* Set the DMA Channel configuration */ + SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ + hdma->Init.PeriphInc | hdma->Init.MemInc | \ + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | \ + hdma->Init.Mode | hdma->Init.Priority)); + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + else + { + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA peripheral. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA handle allocation */ + if (NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + + /* Compute the channel index */ +#if defined(DMA2) + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + hdma->DmaBaseAddress = DMA2; + } +#else + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; +#endif + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + + /* Clear all flags */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); +#endif + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + /* Reset the DMAMUX channel that corresponds to the DMA channel */ + hdma->DMAmuxChannel->CCR = 0U; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Reset Request generator parameters if any */ + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief Input and Output operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + (+) Register and Unregister DMA callbacks + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA Transfer. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if (NULL != hdma->XferHalfCpltCallback) + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + } + + /* Check if DMAMUX Synchronization is enabled*/ + if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if (hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Abort the DMA Transfer. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* Check the DMA peripheral handle */ + if (NULL == hdma) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); +#endif + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear all flags */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); +#endif + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if (hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + +/** + * @brief Polling for transfer complete. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CompleteLevel Specifies the DMA level complete. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + uint32_t temp; + uint32_t tickstart; + + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if (HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Transfer Complete flag */ + temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU); + } + else + { + /* Half Transfer Complete flag */ + temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + +#if defined(DMA2) + while ((hdma->DmaBaseAddress->ISR & temp) == 0U) + { + if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } +#else + while (0U == __HAL_DMA_GET_FLAG(hdma, temp)) + { + if (0U != __HAL_DMA_GET_FLAG(hdma, (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU)))) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } +#endif + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + } + + /*Check for DMAMUX Request generator (if used) overrun status */ + if (hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ + if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + } + } + + /* Check for DMAMUX Synchronization overrun */ + if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + } + + if (HAL_DMA_FULL_TRANSFER == CompleteLevel) + { + /* Clear the transfer complete flag */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); +#endif + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* The selected Channelx EN bit is cleared (DMA is disabled and + all transfers are complete) */ + hdma->State = HAL_DMA_STATE_READY; + } + else + { + /* Clear the half transfer complete flag */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))); +#endif + } + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ +#if defined(DMA2) + uint32_t flag_it = hdma->DmaBaseAddress->ISR; +#else + uint32_t flag_it = DMA1->ISR; +#endif + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))); +#endif + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if (hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC))) + { + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + + /* Transfer Error Interrupt management **************************************/ + else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Clear all flags */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); +#endif + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + else + { + /* Nothing To Do */ + } + return; +} + +/** + * @brief Register callbacks + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback Pointer to private callbacsk function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if (hdma->State == HAL_DMA_STATE_READY) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if (hdma->State == HAL_DMA_STATE_READY) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + + + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the DMA handle state. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + /* Return DMA handle state */ + return hdma->State; +} + +/** + * @brief Return the DMA error code. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + /* Return the DMA error code */ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if (hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + /* Clear all flags */ +#if defined(DMA2) + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); +#else + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); +#endif + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + + /* Memory to Peripheral */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Channel source address */ + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + +/** + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on channel number + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t channel_number; + +#if defined(DMA2) + /* check if instance is not outside the DMA channel range */ + if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) + { + /* DMA1 */ + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; + } + else + { + /* DMA2 */ + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U); + } +#else + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; +#endif + + /* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */ + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + + /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */ + hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); +} + +/** + * @brief Updates the DMA handle with the DMAMUX request generator params + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ + +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + + /* DMA Channels are connected to DMAMUX1 request generator blocks*/ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + + /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ + hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_dma_ex.c (revision 3) @@ -0,0 +1,320 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + + (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from + the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. + As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be + called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project + (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + + +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. + (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. + Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used + to respectively enable/disable the request generator. + (+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from + the DMAMUX IRQ handler + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @param pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef contains the DMAMUX synchronization parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); + + assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); + assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); + assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); + assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); + + /*Check if the DMA state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ + MODIFY_REG(hdma->DMAmuxChannel->CCR, \ + (~DMAMUX_CxCR_DMAREQ_ID), \ + (pSyncConfig->SyncSignalID | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ + pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ + ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos))); + + /* Process UnLocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Return error status */ + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef + * contains the request generator parameters. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) +{ + HAL_StatusTypeDef status; + HAL_DMA_StateTypeDef temp_state = hdma->State; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); + + assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); + assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if (hdma->DMAmuxRequestGen == 0U) + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* error status */ + status = HAL_ERROR; + } + else if (((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY)) + { + /* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */ + + /* Process Locked */ + __HAL_LOCK(hdma); + + /* Set the request generator new parameters*/ + hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ + ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos) | \ + pRequestGeneratorConfig->Polarity; + /* Process UnLocked */ + __HAL_UNLOCK(hdma); + + return HAL_OK; + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + { + + /* Enable the request generator*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* check if the DMA state is ready + and DMA is using a DMAMUX request generator block + */ + if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) + { + + /* Disable the request generator*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handles DMAMUX interrupt request. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA channel. + * @retval None + */ +void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) +{ + /* Check for DMAMUX Synchronization overrun */ + if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Disable the synchro overrun interrupt */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + + if (hdma->DMAmuxRequestGen != 0) + { + /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ + if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Disable the request gen overrun interrupt */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_exti.c (revision 3) @@ -0,0 +1,681 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two diffenrents + interrupt pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[linepos >> 2u]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + EXTI->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* Configure event mode : read current mode */ + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configiguration structure */ + pExtiConfig->Line = hexti->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + } + + /* Get falling configuration */ + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + } + else + { + pExtiConfig->GPIOSel = 0x00u; + } + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[linepos >> 2u]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + EXTI->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicaated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->RisingCallback = pPendingCbfn; + hexti->FallingCallback = pPendingCbfn; + break; + + case HAL_EXTI_RISING_CB_ID: + hexti->RisingCallback = pPendingCbfn; + break; + + case HAL_EXTI_FALLING_CB_ID: + hexti->FallingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get rising edge pending bit */ + regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0x00u) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->RisingCallback != NULL) + { + hexti->RisingCallback(); + } + } + + /* Get falling edge pending bit */ + regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0x00u) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->FallingCallback != NULL) + { + hexti->FallingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending bit */ + regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get rising edge pending bit */ + regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending register address */ + regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get falling edge pending register address */ + regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* Clear Pending bit */ + *regaddr = maskline; +} + + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check parameterd */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash.c (revision 3) @@ -0,0 +1,719 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch and cache lines. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Option bytes programming + (+) Prefetch on I-Code + (+) 32 cache lines of 4*64 bits on I-Code + (+) Error code correction (ECC) : Data in flash are 72-bits word + (8 bits added per double word) + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32G0xx devices. + + (#) Flash Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: double word and fast program (full row programming) + (++) There are two modes of programming: + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions: + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Callback functions are called when the flash operations are finished : + HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise + HAL_FLASH_OperationErrorCallback() + (++) Get error flag status by calling HAL_GetError() + + (#) Option bytes management functions : + (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and + HAL_FLASH_OB_Lock() functions + (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function. + In this case, a reset is generated + + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the Instruction cache + (+) Reset the Instruction cache + (+) Enable/Disable the Flash power-down during low-power run and sleep modes + (+) Enable/Disable the Flash interrupts + (+) Monitor the Flash flags status + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/** + * @brief Variable used for Program/Erase sectors under interruption + */ +FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ + .ErrorCode = HAL_FLASH_ERROR_NONE, \ + .ProcedureOnGoing = FLASH_TYPENONE, \ + .Address = 0U, \ + .Banks = 0U, \ + .Page = 0U, \ + .NbPagesToErase = 0U + }; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); +static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program double word or fast program of a row at a specified address. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed + * This parameter is the data for the double word program and the address where + * are stored the data for the row fast program. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Program double-word (64-bit) at a specified address */ + FLASH_Program_DoubleWord(Address, Data); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address)); + + /* Fast program a 32 row double-word (64-bit) at a specified address */ + FLASH_Program_Fast(Address, (uint32_t)Data); + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG or FSTPG Bit */ + CLEAR_BIT(FLASH->CR, TypeProgram); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + +/** + * @brief Program double word or fast program of a row at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed + * This parameter is the data for the double word program and the address where + * are stored the data for the row fast program. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = TypeProgram; + pFlash.Address = Address; + + /* Enable End of Operation and Error interrupts */ + FLASH->CR |= FLASH_CR_EOPIE | FLASH_CR_ERRIE; + + if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) + { + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Program double-word (64-bit) at a specified address */ + FLASH_Program_DoubleWord(Address, Data); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address)); + + /* Fast program a 32 row double-word (64-bit) at a specified address */ + FLASH_Program_Fast(Address, (uint32_t)Data); + } + } + + /* return status */ + return status; +} + +/** + * @brief Handle FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t param; + uint32_t error; + + /* Save flash errors. */ + error = (FLASH->SR & FLASH_SR_ERRORS); + + /* A] Set parameter for user or error callbacks */ + /* check operation was a program or erase */ + if ((pFlash.ProcedureOnGoing & FLASH_TYPEERASE_MASS) != 0x00U) + { + /* return bank number */ + param = pFlash.Banks; + } + else + { + /* Clear operation only for page erase or program */ + CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing); + + if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0x00U) + { + /* return address being programmed */ + param = pFlash.Address; + } + else + { + /* return page number being erased */ + param = pFlash.Page; + } + } + + /* B] Check errors */ + if (error != 0x00U) + { + /*Save the error code*/ + pFlash.ErrorCode |= error; + + /* clear error flags */ + FLASH->SR = FLASH_SR_ERRORS; + + /*Stop the procedure ongoing*/ + pFlash.ProcedureOnGoing = FLASH_TYPENONE; + + /* Error callback */ + HAL_FLASH_OperationErrorCallback(param); + } + + /* C] Check FLASH End of Operation flag */ + if ((FLASH->SR & FLASH_SR_EOP) != 0x00U) + { + /* Clear FLASH End of Operation pending bit */ + FLASH->SR = FLASH_SR_EOP; + + if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_PAGES) + { + /* Nb of pages to erased can be decreased */ + pFlash.NbPagesToErase--; + + /* Check if there are still pages to erase*/ + if (pFlash.NbPagesToErase != 0x00U) + { + /* Increment page number */ + pFlash.Page++; + FLASH_PageErase(pFlash.Banks, pFlash.Page); + } + else + { + /* No more pages to erase: stop erase pages procedure */ + pFlash.ProcedureOnGoing = FLASH_TYPENONE; + } + } + else + { + /*Stop the ongoing procedure */ + pFlash.ProcedureOnGoing = FLASH_TYPENONE; + } + + /* User callback */ + HAL_FLASH_EndOfOperationCallback(param); + } + + if (pFlash.ProcedureOnGoing == FLASH_TYPENONE) + { + /* Disable End of Operation and Error interrupts */ + FLASH->CR &= ~(FLASH_CR_EOPIE | FLASH_CR_ERRIE); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } +} + +/** + * @brief FLASH end of operation interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: 0 + * Page Erase: Page which has been erased + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * Mass Erase: 0 + * Page Erase: Page number which returned an error + * Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* verify Flash is unlock */ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00U) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Lock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0x00u) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Unlock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00U) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + + /* verify option bytes are unlocked */ + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0x00U) + { + status = HAL_OK; + } + } + + return status; +} + +/** + * @brief Lock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK); + + /* verify option bytes are locked */ + if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0x00u) + { + status = HAL_OK; + } + + return status; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the bit to force the option byte reloading */ + SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + + /* We should not reach here : Option byte launch generates Option byte reset + so return error */ + return HAL_ERROR; +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be + * @arg @ref HAL_FLASH_ERROR_NONE No error set + * @arg @ref HAL_FLASH_ERROR_OP Operation error + * @arg @ref HAL_FLASH_ERROR_PROG Programming error + * @arg @ref HAL_FLASH_ERROR_WRP Write protection error + * @arg @ref HAL_FLASH_ERROR_PGA Programming alignment error + * @arg @ref HAL_FLASH_ERROR_SIZ Size error + * @arg @ref HAL_FLASH_ERROR_PGS Programming sequence error + * @arg @ref HAL_FLASH_ERROR_MIS Fast programming data miss error + * @arg @ref HAL_FLASH_ERROR_FAST Fast programming error + * @arg @ref HAL_FLASH_ERROR_RD Read Protection error (PCROP)(*) + * @arg @ref HAL_FLASH_ERROR_OPTV Option validity error + * @arg @ref HAL_FLASH_ERROR_ECCD two ECC errors have been detected + * @note (*) availability depends on devices + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + uint32_t error; + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + uint32_t timeout = HAL_GetTick() + Timeout; + + /* Wait if any operation is ongoing */ +#if defined(FLASH_DBANK_SUPPORT) + error = (FLASH_SR_BSY1 | FLASH_SR_BSY2); +#else + error = FLASH_SR_BSY1; +#endif + + while ((FLASH->SR & error) != 0x00U) + { + if (HAL_GetTick() >= timeout) + { + return HAL_TIMEOUT; + } + } + + /* check flash errors */ + error = (FLASH->SR & FLASH_SR_ERRORS); + + /* Clear SR register */ + FLASH->SR = FLASH_SR_CLEAR; + + if (error != 0x00U) + { + /*Save the error code*/ + pFlash.ErrorCode = error; + return HAL_ERROR; + } + + /* Wait for control register to be written */ + timeout = HAL_GetTick() + Timeout; + + while ((FLASH->SR & FLASH_SR_CFGBSY) != 0x00U) + { + if (HAL_GetTick() >= timeout) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Program double-word (64-bit) at a specified address. + * @param Address Specifies the address to be programmed. + * @param Data Specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) +{ + /* Set PG bit */ + SET_BIT(FLASH->CR, FLASH_CR_PG); + + /* Program first word */ + *(uint32_t *)Address = (uint32_t)Data; + + /* Barrier to ensure programming is performed in 2 steps, in right order + (independently of compiler optimization behavior) */ + __ISB(); + + /* Program second word */ + *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U); +} + +/** + * @brief Fast program a 32 row double-word (64-bit) at a specified address. + * @param Address Specifies the address to be programmed. + * @param DataAddress Specifies the address where the data are stored. + * @retval None + */ +static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress) +{ + uint8_t index = 0; + uint32_t dest = Address; + uint32_t src = DataAddress; + uint32_t primask_bit; + + /* Set FSTPG bit */ + SET_BIT(FLASH->CR, FLASH_CR_FSTPG); + + /* Enter critical section: row programming should not be longer than 7 ms */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Fast Program : 64 words */ + while (index < 64U) + { + *(uint32_t *)dest = *(uint32_t *)src; + src += 4U; + dest += 4U; + index++; + } + + /* wait for BSY1 in order to be sure that flash operation is ended befoire + allowing prefetch in flash. Timeout does not return status, as it will + be anyway done later */ + +#if defined(FLASH_DBANK_SUPPORT) + while ((FLASH->SR & (FLASH_SR_BSY1 | FLASH_SR_BSY2)) != 0x00U) +#else + while ((FLASH->SR & FLASH_SR_BSY1) != 0x00U) +#endif + { + } + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_flash_ex.c (revision 3) @@ -0,0 +1,1308 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extended peripheral: + * + Extended programming operations functions + * + @verbatim + ============================================================================== + ##### Flash Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32G0xx + devices contains the following additional features + + (+) Capacity up to 128 Kbytes with single bank architecture supporting read-while-write + capability (RWW) + (+) Single bank memory organization + (+) PCROP protection + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32G0xx devices. It includes + (#) Flash Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Erase page, erase all sectors + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to : + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Configure the PCROP protection + (++) Set Securable memory area and boot entry point + + (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to : + (++) Get the value of a write protection area + (++) Know if the read protection is activated + (++) Get the value of the user Option Bytes + (++) Get Securable memory area and boot entry point information + + (#) Enable or disable debugger usage using HAL_FLASHEx_EnableDebugger and + HAL_FLASHEx_DisableDebugger. + + (#) Check is flash content is empty or not using HAL_FLASHEx_FlashEmptyCheck. + and modify this setting (for flash loader purpose e.g.) using + HAL_FLASHEx_ForceFlashEmpty. + + (#) Enable securable memory area protectionusing HAL_FLASHEx_EnableSecMemProtection + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH Extended HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +static void FLASH_MassErase(uint32_t Banks); +void FLASH_FlushCaches(void); +static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); +static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset); +static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel); +static uint32_t FLASH_OB_GetRDP(void); +static uint32_t FLASH_OB_GetUser(void); +#if defined(FLASH_PCROP_SUPPORT) +static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr); +static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr); +static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr); +static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr); +#if defined(FLASH_DBANK_SUPPORT) +static void FLASH_OB_PCROP2AConfig(uint32_t PCROP2AStartAddr, uint32_t PCROP2AEndAddr); +static void FLASH_OB_PCROP2BConfig(uint32_t PCROP2BStartAddr, uint32_t PCROP2BEndAddr); +static void FLASH_OB_GetPCROP2A(uint32_t *PCROP2AStartAddr, uint32_t *PCROP2AEndAddr); +static void FLASH_OB_GetPCROP2B(uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEndAddr); +#endif +#endif +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +#if defined(FLASH_DBANK_SUPPORT) +static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize, uint32_t SecSize2); +static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize, uint32_t *SecSize2); +#else +static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize); +static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize); +#endif +#endif +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages. + * @param[in] pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * @param[out] PageError Pointer to variable that contains the configuration + * information on faulty page in case of error (0xFFFFFFFF means that all + * the pages have been correctly erased) + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status; + uint32_t index; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { +#if !defined(FLASH_DBANK_SUPPORT) + /* For single bank product force Banks to Bank 1 */ + pEraseInit->Banks = FLASH_BANK_1; +#endif + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS) + { + /* Proceed to Mass Erase */ + FLASH_MassErase(pEraseInit->Banks); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + else + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + for (index = pEraseInit->Page; index < (pEraseInit->Page + pEraseInit->NbPages); index++) + { + /* Start erase page */ + FLASH_PageErase(pEraseInit->Banks, index); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty address */ + *PageError = index; + break; + } + } + + /* If operation is completed or interrupted, disable the Page Erase Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. + * @param pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* save procedure for interrupt treatment */ + pFlash.ProcedureOnGoing = pEraseInit->TypeErase; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { +#if !defined(FLASH_DBANK_SUPPORT) + /* For single bank product force Banks to Bank 1 */ + pEraseInit->Banks = FLASH_BANK_1; +#endif + /* Store Bank number */ + pFlash.Banks = pEraseInit->Banks; + + /* Enable End of Operation and Error interrupts */ + FLASH->CR |= FLASH_CR_EOPIE | FLASH_CR_ERRIE; + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASS) + { + /* Set Page to 0 for Interrupt callback management */ + pFlash.Page = 0; + + /* Proceed to Mass Erase */ + FLASH_MassErase(pEraseInit->Banks); + } + else + { + /* Erase by page to be done */ + pFlash.NbPagesToErase = pEraseInit->NbPages; + pFlash.Page = pEraseInit->Page; + + /*Erase 1st page and wait for IT */ + FLASH_PageErase(pEraseInit->Banks, pEraseInit->Page); + } + } + + /* return status */ + return status; +} + +/** + * @brief Program Option bytes. + * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * @note To configure any option bytes, the option lock bit OPTLOCK must be + * cleared with the call of @ref HAL_FLASH_OB_Unlock() function. + * @note New option bytes configuration will be taken into account only + * - after an option bytes launch through the call of @ref HAL_FLASH_OB_Launch() + * - a Power On Reset + * - an exit from Standby or Shutdown mode. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + uint32_t optr; + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Write protection configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0x00U) + { + /* Configure of Write protection on the selected area */ + FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset); + } + + /* Option register */ + if ((pOBInit->OptionType & (OPTIONBYTE_RDP | OPTIONBYTE_USER)) == (OPTIONBYTE_RDP | OPTIONBYTE_USER)) + { + /* Fully modify OPTR register with RDP & user data */ + FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, pOBInit->RDPLevel); + } + else if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0x00U) + { + /* Only modify RDP so get current user data */ + optr = FLASH_OB_GetUser(); + FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel); + } + else if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0x00U) + { + /* Only modify user so get current RDP level */ + optr = FLASH_OB_GetRDP(); + FLASH_OB_OptrConfig(pOBInit->USERType, pOBInit->USERConfig, optr); + } + else + { + /* nothing to do */ + } + +#if defined(FLASH_PCROP_SUPPORT) + /* PCROP Configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0x00U) + { + /* Check the parameters */ + assert_param(IS_OB_PCROP_CONFIG(pOBInit->PCROPConfig)); + + if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0x00U) + { + /* Configure the 1A Proprietary code readout protection */ + FLASH_OB_PCROP1AConfig(pOBInit->PCROPConfig, pOBInit->PCROP1AStartAddr, pOBInit->PCROP1AEndAddr); + } + + if ((pOBInit->PCROPConfig & OB_PCROP_ZONE_B) != 0x00U) + { + /* Configure the 1B Proprietary code readout protection */ + FLASH_OB_PCROP1BConfig(pOBInit->PCROP1BStartAddr, pOBInit->PCROP1BEndAddr); + } + +#if defined(FLASH_DBANK_SUPPORT) + if ((pOBInit->PCROPConfig & OB_PCROP_ZONE2_A) != 0x00U) + { + /* Configure the 2A Proprietary code readout protection */ + FLASH_OB_PCROP2AConfig(pOBInit->PCROP2AStartAddr, pOBInit->PCROP2AEndAddr); + } + + if ((pOBInit->PCROPConfig & OB_PCROP_ZONE2_B) != 0x00U) + { + /* Configure the 2B Proprietary code readout protection */ + FLASH_OB_PCROP2BConfig(pOBInit->PCROP2BStartAddr, pOBInit->PCROP2BEndAddr); + } +#endif + } +#endif + +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) + /* Securable Memory Area Configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_SEC) != 0x00U) + { +#if defined(FLASH_DBANK_SUPPORT) + /* Configure the securable memory area protection */ + FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize, pOBInit->SecSize2); +#else + /* Configure the securable memory area protection */ + FLASH_OB_SecMemConfig(pOBInit->BootEntryPoint, pOBInit->SecSize); +#endif + } +#endif + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set OPTSTRT Bit */ + SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the option byte program operation is completed, disable the OPTSTRT Bit */ + CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + +/** + * @brief Get the Option bytes configuration. + * @note warning: this API only read flash register, it does not reflect any + * change that would have been programmed between previous Option byte + * loading and current call. + * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that contains the + * configuration information. The fields pOBInit->WRPArea should + * indicate which area is requested for the WRP. + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_ALL; + + /* Get write protection on the selected area */ + FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); + + /* Get Read protection level */ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /* Get the user option bytes */ + pOBInit->USERConfig = FLASH_OB_GetUser(); + pOBInit->USERType = OB_USER_ALL; + +#if defined(FLASH_PCROP_SUPPORT) + /* Get the Proprietary code readout protection */ + FLASH_OB_GetPCROP1A(&(pOBInit->PCROPConfig), &(pOBInit->PCROP1AStartAddr), &(pOBInit->PCROP1AEndAddr)); + FLASH_OB_GetPCROP1B(&(pOBInit->PCROP1BStartAddr), &(pOBInit->PCROP1BEndAddr)); + pOBInit->PCROPConfig |= (OB_PCROP_ZONE_A | OB_PCROP_ZONE_B); +#if defined(FLASH_DBANK_SUPPORT) + FLASH_OB_GetPCROP2A(&(pOBInit->PCROP2AStartAddr), &(pOBInit->PCROP2AEndAddr)); + FLASH_OB_GetPCROP2B(&(pOBInit->PCROP2BStartAddr), &(pOBInit->PCROP2BEndAddr)); + pOBInit->PCROPConfig |= (OB_PCROP_ZONE2_A | OB_PCROP_ZONE2_B); +#endif +#endif + +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +#if defined(FLASH_DBANK_SUPPORT) + /* Get the Securable Memory Area protection */ + FLASH_OB_GetSecMem(&(pOBInit->BootEntryPoint), &(pOBInit->SecSize), &(pOBInit->SecSize2)); +#else + /* Get the Securable Memory Area protection */ + FLASH_OB_GetSecMem(&(pOBInit->BootEntryPoint), &(pOBInit->SecSize)); +#endif +#endif +} + +#if defined(FLASH_ACR_DBG_SWEN) +/** + * @brief Enable Debugger. + * @note After calling this API, flash interface allow debugger intrusion. + * @retval None + */ +void HAL_FLASHEx_EnableDebugger(void) +{ + FLASH->ACR |= FLASH_ACR_DBG_SWEN; +} + + +/** + * @brief Disable Debugger. + * @note After calling this API, Debugger is disabled: it is no more possible to + * break, see CPU register, etc... + * @retval None + */ +void HAL_FLASHEx_DisableDebugger(void) +{ + FLASH->ACR &= ~FLASH_ACR_DBG_SWEN; +} +#endif /* FLASH_ACR_DBG_SWEN */ + +/** + * @brief Flash Empty check + * @note This API checks if first location in Flash is programmed or not. + * This check is done once by Option Byte Loader. + * @retval 0 if 1st location is not programmed else + */ +uint32_t HAL_FLASHEx_FlashEmptyCheck(void) +{ + return ((FLASH->ACR & FLASH_ACR_PROGEMPTY)); +} + + +/** + * @brief Force Empty check value. + * @note Allows to modify program empty check value in order to force this + * infrmation in Flash Interface, for all next reset that do not launch + * Option Byte Loader. + * @param FlashEmpty this parameter can be a value of @ref FLASHEx_Empty_Check + * @retval None + */ +void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty) +{ + uint32_t acr; + assert_param(IS_FLASH_EMPTY_CHECK(FlashEmpty)); + + acr = (FLASH->ACR & ~FLASH_ACR_PROGEMPTY); + FLASH->ACR = (acr | FlashEmpty); +} + + +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +/** + * @brief Securable memory area protection enable + * @param Banks Select Bank to be secured. + * This parameter can be a value of @ref FLASH_Banks + * @note On some devices, there is only 1 bank so parameter has to be set FLASH_BANK_1. + * @note This API locks Securable memory area which is defined in SEC_SIZE option byte + * (that can be retrieved calling HAL_FLASHEx_OBGetConfig API and checking + * Secsize). + * @note SEC_PROT bit can only be set, it will be reset by system reset. + * @retval None + */ +void HAL_FLASHEx_EnableSecMemProtection(uint32_t Banks) +{ +#if defined(FLASH_DBANK_SUPPORT) + assert_param(IS_FLASH_BANK(Banks)); + + if (Banks == (FLASH_BANK_2 | FLASH_BANK_1)) + { + FLASH->CR |= (FLASH_CR_SEC_PROT2 | FLASH_CR_SEC_PROT); + } + else if (Banks == FLASH_BANK_2) + { + FLASH->CR |= FLASH_CR_SEC_PROT2; + } + else +#else + UNUSED(Banks); +#endif + { + FLASH->CR |= FLASH_CR_SEC_PROT; + } +} +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ + +/** + * @brief Mass erase of FLASH memory. + * @param Banks: Banks to be erased + * This parameter can be a combination of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased* + * @note (*) availability depends on devices + * @retval None + */ +static void FLASH_MassErase(uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + /* Set the Mass Erase Bit and start bit */ + FLASH->CR |= (FLASH_CR_STRT | Banks); +} + +/** + * @brief Erase the specified FLASH memory page. + * @param Banks: Banks to be erased + * This parameter can one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased* + * @param Page FLASH page to erase + * This parameter must be a value between 0 and (max number of pages in Flash - 1) + * @note (*) availability depends on devices + * @retval None + */ +void FLASH_PageErase(uint32_t Banks, uint32_t Page) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + assert_param(IS_FLASH_PAGE(Page)); + + /* Get configuration register, then clear page number */ + tmp = (FLASH->CR & ~FLASH_CR_PNB); + +#if defined(FLASH_DBANK_SUPPORT) + /* Check if page has to be erased in bank 1 or 2 */ + if(Banks != FLASH_BANK_1) + { + tmp |= FLASH_CR_BKER; + } + else + { + tmp &= ~FLASH_CR_BKER; + } +#endif + + /* Set page number, Page Erase bit & Start bit */ + FLASH->CR = (tmp | (FLASH_CR_STRT | (Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER)); +} + +/** + * @brief Flush the instruction cache. + * @retval None + */ +void FLASH_FlushCaches(void) +{ + /* Flush instruction cache */ + if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) + { + /* Disable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + /* Reset instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + /* Enable instruction cache */ + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + } +} + + +/** + * @brief Configure the write protection of the desired pages. + * @note When WRP is active in a zone, it cannot be erased or programmed. + * Consequently, a software mass erase cannot be performed if one zone + * is write-protected. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase Flash memory if the CPU debug + * features are connected (JTAG or single wire) or boot code is being + * executed from RAM or System flash, even if WRP is not activated. + * @param WRPArea Specifies the area to be configured. + * This parameter can be one of the following values: + * @arg @ref OB_WRPAREA_ZONE_A Flash Zone A + * @arg @ref OB_WRPAREA_ZONE_B Flash Zone B + * @arg @ref OB_WRPAREA_ZONE2_A Flash Bank 2 Zone A (*) + * @arg @ref OB_WRPAREA_ZONE2_B Flash Bank 2 Zone B (*) + * @note (*) availability depends on devices + * @param WRPStartOffset Specifies the start page of the write protected area + * This parameter can be page number between 0 and (max number of pages in the Flash Bank - 1) + * @param WRDPEndOffset Specifies the end page of the write protected area + * This parameter can be page number between WRPStartOffset and (max number of pages in the Flash Bank - 1) + * @retval None + */ +static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) +{ + /* Check the parameters */ + assert_param(IS_OB_WRPAREA(WRPArea)); + assert_param(IS_FLASH_PAGE(WRPStartOffset)); + assert_param(IS_FLASH_PAGE(WRDPEndOffset)); + + /* Configure the write protected area */ + if (WRPArea == OB_WRPAREA_ZONE_A) + { + FLASH->WRP1AR = ((WRDPEndOffset << FLASH_WRP1AR_WRP1A_END_Pos) | WRPStartOffset); + } +#if defined(FLASH_DBANK_SUPPORT) + else if (WRPArea == OB_WRPAREA_ZONE2_A) + { + FLASH->WRP2AR = ((WRDPEndOffset << FLASH_WRP2AR_WRP2A_END_Pos) | WRPStartOffset); + } + else if (WRPArea == OB_WRPAREA_ZONE2_B) + { + FLASH->WRP2BR = ((WRDPEndOffset << FLASH_WRP2BR_WRP2B_END_Pos) | WRPStartOffset); + } +#endif + else + { + FLASH->WRP1BR = ((WRDPEndOffset << FLASH_WRP1BR_WRP1B_END_Pos) | WRPStartOffset); + } +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @param[in] WRPArea Specifies the area to be returned. + * This parameter can be one of the following values: + * @arg @ref OB_WRPAREA_ZONE_A Flash Zone A + * @arg @ref OB_WRPAREA_ZONE_B Flash Zone B + * @arg @ref OB_WRPAREA_ZONE2_A Flash Bank 2 Zone A (*) + * @arg @ref OB_WRPAREA_ZONE2_B Flash Bank 2 Zone B (*) + * @note (*) availability depends on devices + * @param[out] WRPStartOffset Specifies the address where to copied the start page + * of the write protected area + * @param[out] WRDPEndOffset Dpecifies the address where to copied the end page of + * the write protected area + * @retval None + */ +static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset) +{ + /* Check the parameters */ + assert_param(IS_OB_WRPAREA(WRPArea)); + + /* Get the configuration of the write protected area */ + if (WRPArea == OB_WRPAREA_ZONE_A) + { + *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT); + *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos); + } +#if defined(FLASH_DBANK_SUPPORT) + else if (WRPArea == OB_WRPAREA_ZONE2_A) + { + *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT); + *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos); + } + else if (WRPArea == OB_WRPAREA_ZONE2_B) + { + *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT); + *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos); + } +#endif +else + { + *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT); + *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos); + } +} + +/** + * @brief Set user & RDP configuration + * @note !!! Warning : When enabling OB_RDP level 2 it is no more possible + * to go back to level 1 or 0 !!! + * @param UserType The FLASH User Option Bytes to be modified. + * This parameter can be a combination of @ref FLASH_OB_USER_Type + * @param UserConfig The FLASH User Option Bytes values. + * This parameter can be a combination of: + * @arg @ref FLASH_OB_USER_BOR_ENABLE(*) + * @arg @ref FLASH_OB_USER_BOR_LEVEL(*) + * @arg @ref FLASH_OB_USER_RESET_CONFIG(*) + * @arg @ref FLASH_OB_USER_nRST_STOP + * @arg @ref FLASH_OB_USER_nRST_STANDBY + * @arg @ref FLASH_OB_USER_nRST_SHUTDOWN(*) + * @arg @ref FLASH_OB_USER_IWDG_SW + * @arg @ref FLASH_OB_USER_IWDG_STOP + * @arg @ref FLASH_OB_USER_IWDG_STANDBY + * @arg @ref FLASH_OB_USER_WWDG_SW + * @arg @ref FLASH_OB_USER_SRAM_PARITY + * @arg @ref FLASH_OB_USER_BANK_SWAP(*) + * @arg @ref FLASH_OB_USER_DUAL_BANK(*) + * @arg @ref FLASH_OB_USER_nBOOT_SEL + * @arg @ref FLASH_OB_USER_nBOOT1 + * @arg @ref FLASH_OB_USER_nBOOT0 + * @arg @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*) + * @param RDPLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Memory Read protection + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + * @note (*) availability depends on devices + * @retval None + */ +static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel) +{ + uint32_t optr; + + /* Check the parameters */ + assert_param(IS_OB_USER_TYPE(UserType)); + assert_param(IS_OB_USER_CONFIG(UserType, UserConfig)); + assert_param(IS_OB_RDP_LEVEL(RDPLevel)); + + /* Configure the RDP level in the option bytes register */ + optr = FLASH->OPTR; + optr &= ~(UserType | FLASH_OPTR_RDP); + FLASH->OPTR = (optr | UserConfig | RDPLevel); +} + +/** + * @brief Return the FLASH Read Protection level. + * @retval FLASH ReadOut Protection Status: + * This return value can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t rdplvl = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); + + if ((rdplvl != OB_RDP_LEVEL_0) && (rdplvl != OB_RDP_LEVEL_2)) + { + return (OB_RDP_LEVEL_1); + } + else + { + return rdplvl; + } +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values. It will be a combination of all the following values: + * @arg @ref FLASH_OB_USER_BOR_ENABLE(*) + * @arg @ref FLASH_OB_USER_BOR_LEVEL(*) + * @arg @ref FLASH_OB_USER_RESET_CONFIG(*) + * @arg @ref FLASH_OB_USER_nRST_STOP + * @arg @ref FLASH_OB_USER_nRST_STANDBY + * @arg @ref FLASH_OB_USER_nRST_SHUTDOWN(*) + * @arg @ref FLASH_OB_USER_IWDG_SW + * @arg @ref FLASH_OB_USER_IWDG_STOP + * @arg @ref FLASH_OB_USER_IWDG_STANDBY + * @arg @ref FLASH_OB_USER_WWDG_SW + * @arg @ref FLASH_OB_USER_SRAM_PARITY + * @arg @ref FLASH_OB_USER_BANK_SWAP(*) + * @arg @ref FLASH_OB_USER_DUAL_BANK(*) + * @arg @ref FLASH_OB_USER_nBOOT_SEL + * @arg @ref FLASH_OB_USER_nBOOT1 + * @arg @ref FLASH_OB_USER_nBOOT0 + * @arg @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*) + * @note (*) availability depends on devices + */ +static uint32_t FLASH_OB_GetUser(void) +{ + uint32_t user = ((FLASH->OPTR & ~FLASH_OPTR_RDP) & OB_USER_ALL); + return user; +} + +#if defined(FLASH_PCROP_SUPPORT) +/** + * @brief Configure the 1A Proprietary code readout protection & erase configuration on RDP regression. + * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid + * having some executable code in a page where PCROP zone starts or ends. + * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END. + * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity + * has to be set to 512 Bytes + * @param PCROPConfig specifies the erase configuration (OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE) + * on RDP level 1 regression. + * @param PCROP1AStartAddr Specifies the Zone 1A Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP1AEndAddr Specifies the Zone 1A end address of the Proprietary code readout protection + * This parameter can be an address between PCROP1AStartAddr and end of the flash + * @retval None + */ +static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr) +{ + uint32_t startoffset; + uint32_t endoffset; + uint32_t pcrop1aend; + uint32_t ropbase; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_CONFIG(PCROPConfig)); + +#if defined(FLASH_DBANK_SUPPORT) + /* Check if banks are swapped (valid if only one bank) */ + if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U)) + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1AStartAddr)); + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1AEndAddr)); + + /* Bank swap, bank 1 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else +#endif + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1AStartAddr)); + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1AEndAddr)); + + /* No Bank swap, bank 1 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + /* get pcrop 1A end register */ + pcrop1aend = FLASH->PCROP1AER; + + /* Configure the Proprietary code readout protection offset */ + if ((PCROPConfig & OB_PCROP_ZONE_A) != 0x00U) + { + /* Compute offset depending on pcrop granularity */ + startoffset = ((PCROP1AStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + endoffset = ((PCROP1AEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + + /* Set Zone A start offset */ + FLASH->PCROP1ASR = startoffset; + + /* Set Zone A end offset */ + pcrop1aend &= ~FLASH_PCROP1AER_PCROP1A_END; + pcrop1aend |= endoffset; + } + + /* Set RDP erase protection if needed. This bit is only set & will be reset by mass erase */ + if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0x00U) + { + pcrop1aend |= FLASH_PCROP1AER_PCROP_RDP; + } + + /* set 1A End register */ + FLASH->PCROP1AER = pcrop1aend; +} + +/** + * @brief Configure the 1B Proprietary code readout protection. + * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid + * having some executable code in a page where PCROP zone starts or ends. + * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPB_STRT and PCROPB_END. + * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity + * has to be set to 512 Bytes + * @param PCROP1BStartAddr Specifies the Zone 1B Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP1BEndAddr Specifies the Zone 1B end address of the Proprietary code readout protection + * This parameter can be an address between PCROP1BStartAddr and end of the flash + * @retval None + */ +static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr) +{ + uint32_t startoffset; + uint32_t endoffset; + uint32_t ropbase; + +#if defined(FLASH_DBANK_SUPPORT) + /* Check if banks are swapped (valid if only one bank) */ + if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U)) + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1BStartAddr)); + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP1BEndAddr)); + + /* Bank swap, bank 1 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else +#endif + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1BStartAddr)); + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP1BEndAddr)); + + /* No Bank swap, bank 1 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + /* Configure the Proprietary code readout protection offset */ + startoffset = ((PCROP1BStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + endoffset = ((PCROP1BEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + + /* Set Zone B start offset */ + FLASH->PCROP1BSR = startoffset; + /* Set Zone B end offset */ + FLASH->PCROP1BER = endoffset; +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @param PCROPConfig [out] specifies the configuration of PCROP_RDP option. + * @param PCROP1AStartAddr [out] Specifies the address where to copied the start address + * of the 1A Proprietary code readout protection + * @param PCROP1AEndAddr [out] Specifies the address where to copied the end address of + * the 1A Proprietary code readout protection + * @retval None + */ +static void FLASH_OB_GetPCROP1A(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr, uint32_t *PCROP1AEndAddr) +{ + uint32_t pcrop; + uint32_t ropbase; + +#if defined(FLASH_DBANK_SUPPORT) + /* Check if banks are swapped (valid if only one bank) */ + if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U)) + { + /* Bank swap, bank 1 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else +#endif + { + /* No Bank swap, bank 1 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + pcrop = (FLASH->PCROP1ASR & FLASH_PCROP1ASR_PCROP1A_STRT); + *PCROP1AStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP1AStartAddr += ropbase; + + pcrop = FLASH->PCROP1AER; + *PCROP1AEndAddr = ((pcrop & FLASH_PCROP1AER_PCROP1A_END) << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP1AEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); + + *PCROPConfig &= ~OB_PCROP_RDP_ERASE; + *PCROPConfig |= (pcrop & FLASH_PCROP1AER_PCROP_RDP); +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @param PCROP1BStartAddr [out] Specifies the address where to copied the start address + * of the 1B Proprietary code readout protection + * @param PCROP1BEndAddr [out] Specifies the address where to copied the end address of + * the 1B Proprietary code readout protection + * @retval None + */ +static void FLASH_OB_GetPCROP1B(uint32_t *PCROP1BStartAddr, uint32_t *PCROP1BEndAddr) +{ + uint32_t pcrop; + uint32_t ropbase; + +#if defined(FLASH_DBANK_SUPPORT) + /* Check if banks are swapped (valid if only one bank) */ + if (((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != FLASH_OPTR_nSWAP_BANK) && (FLASH_BANK_NB == 2U)) + { + /* Bank swap, bank 1 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else +#endif + { + /* No Bank swap, bank 1 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + pcrop = (FLASH->PCROP1BSR & FLASH_PCROP1BSR_PCROP1B_STRT); + *PCROP1BStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP1BStartAddr += ropbase; + + pcrop = (FLASH->PCROP1BER & FLASH_PCROP1BER_PCROP1B_END); + *PCROP1BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP1BEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); +} + +#if defined(FLASH_DBANK_SUPPORT) +/** + * @brief Configure the 2A Proprietary code readout protection. + * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid + * having some executable code in a page where PCROP zone starts or ends. + * @note Minimum PCROP area size is 2 times the chosen granularity: PCROPA_STRT and PCROPA_END. + * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity + * has to be set to 512 Bytes + * @param PCROP2AStartAddr Specifies the Zone 2A Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP2AEndAddr Specifies the Zone 2A end address of the Proprietary code readout protection + * This parameter can be an address between PCROP2AStartAddr and end of the flash + * @retval None + */ +static void FLASH_OB_PCROP2AConfig(uint32_t PCROP2AStartAddr, uint32_t PCROP2AEndAddr) +{ + uint32_t startoffset; + uint32_t endoffset; + uint32_t ropbase; + + /* Check if banks are swapped */ + if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u) + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2AStartAddr)); + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2AEndAddr)); + + /* No Bank swap, bank 2 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2AStartAddr)); + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2AEndAddr)); + + /* Bank swap, bank 2 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + /* Configure the Proprietary code readout protection offset */ + startoffset = ((PCROP2AStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + endoffset = ((PCROP2AEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + + /* Set Zone A start offset */ + FLASH->PCROP2ASR = startoffset; + /* Set Zone A end offset */ + FLASH->PCROP2AER = endoffset; +} + +/** + * @brief Configure the 2B Proprietary code readout protection. + * @note It is recommended to align PCROP zone with page granularity when using PCROP_RDP or avoid + * having some executable code in a page where PCROP zone starts or ends. + * @note Minimum PCROP area size is 2 times the chosen granularity: PCROP_STRT and PCROP_END. + * So if the requirement is to be able to read-protect 1KB areas, the ROP granularity + * has to be set to 512 Bytes + * @param PCROP2BStartAddr Specifies the Zone 2B Start address of the Proprietary code readout protection + * This parameter can be an address between begin and end of the flash + * @param PCROP2BEndAddr Specifies the Zone 2B end address of the Proprietary code readout protection + * This parameter can be an address between PCROP2BStartAddr and end of the flash + * @retval None + */ +static void FLASH_OB_PCROP2BConfig(uint32_t PCROP2BStartAddr, uint32_t PCROP2BEndAddr) +{ + uint32_t startoffset; + uint32_t endoffset; + uint32_t ropbase; + + /* Check if banks are swapped */ + if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u) + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2BStartAddr)); + assert_param(IS_FLASH_MAIN_SECONDHALF_MEM_ADDRESS(PCROP2BEndAddr)); + + /* No Bank swap, bank 2 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2BStartAddr)); + assert_param(IS_FLASH_MAIN_FIRSTHALF_MEM_ADDRESS(PCROP2BEndAddr)); + + /* Bank swap, bank 2 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + /* Configure the Proprietary code readout protection offset */ + startoffset = ((PCROP2BStartAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + endoffset = ((PCROP2BEndAddr - ropbase) >> FLASH_PCROP_GRANULARITY_OFFSET); + + /* Set Zone B start offset */ + FLASH->PCROP2BSR = startoffset; + /* Set Zone B end offset */ + FLASH->PCROP2BER = endoffset; +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @param PCROP2AStartAddr [out] Specifies the address where to copied the start address + * of the 2A Proprietary code readout protection + * @param PCROP2AEndAddr [out] Specifies the address where to copied the end address of + * the 2A Proprietary code readout protection + * @retval None + */ +static void FLASH_OB_GetPCROP2A(uint32_t *PCROP2AStartAddr, uint32_t *PCROP2AEndAddr) +{ + uint32_t pcrop; + uint32_t ropbase; + + /* Check if banks are swapped */ + if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u) + { + /* No Bank swap, bank 2 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else + { + /* Bank swap, bank 2 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + pcrop = (FLASH->PCROP2ASR & FLASH_PCROP2ASR_PCROP2A_STRT); + *PCROP2AStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP2AStartAddr += ropbase; + + pcrop = (FLASH->PCROP2AER & FLASH_PCROP2AER_PCROP2A_END); + *PCROP2AEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP2AEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @param PCROP2BStartAddr [out] Specifies the address where to copied the start address + * of the 2B Proprietary code readout protection + * @param PCROP2BEndAddr [out] Specifies the address where to copied the end address of + * the 2B Proprietary code readout protection + * @retval None + */ +static void FLASH_OB_GetPCROP2B(uint32_t *PCROP2BStartAddr, uint32_t *PCROP2BEndAddr) +{ + uint32_t pcrop; + uint32_t ropbase; + + /* Check if banks are swapped */ + if ((FLASH->OPTR & FLASH_OPTR_nSWAP_BANK) != 0x00u) + { + /* No Bank swap, bank 2 read only protection is on second half of Flash */ + ropbase = (FLASH_BASE + FLASH_BANK_SIZE); + } + else + { + /* Bank swap, bank 2 read only protection is on first half of Flash */ + ropbase = FLASH_BASE; + } + + pcrop = (FLASH->PCROP2BSR & FLASH_PCROP2BSR_PCROP2B_STRT); + *PCROP2BStartAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP2BStartAddr += ropbase; + + pcrop = (FLASH->PCROP2BER & FLASH_PCROP2BER_PCROP2B_END); + *PCROP2BEndAddr = (pcrop << FLASH_PCROP_GRANULARITY_OFFSET); + *PCROP2BEndAddr += (ropbase + FLASH_PCROP_GRANULARITY - 1U); +} +#endif +#endif + +#if defined(FLASH_SECURABLE_MEMORY_SUPPORT) +#if defined(FLASH_DBANK_SUPPORT) +/** + * @brief Configure Securable Memory area feature. + * @param BootEntry specifies if boot scheme is forced to Flash (System or user) or not + * This parameter can be one of the following values: + * @arg @ref OB_BOOT_ENTRY_FORCED_NONE No boot entry forced + * @arg @ref OB_BOOT_ENTRY_FORCED_FLASH Flash selected as unique entry boot + * @param SecSize specifies number of pages to protect as securable memory area, starting from + * beginning of Bank1 (page 0). + * @param SecSize2 specifies number of pages to protect as securable memory area, starting from + * beginning of Bank2 (page 0). + * @retval None + */ +static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize, uint32_t SecSize2) +{ + uint32_t secmem; + + /* Check the parameters */ + assert_param(IS_OB_SEC_BOOT_LOCK(BootEntry)); + assert_param(IS_OB_SEC_SIZE(SecSize)); + + if ((FLASH_BANK_NB == 2U)) + { + assert_param(IS_OB_SEC_SIZE(SecSize2)); + } + + /* Set securable memory area configuration */ + secmem = (FLASH->SECR & ~(FLASH_SECR_BOOT_LOCK | FLASH_SECR_SEC_SIZE | FLASH_SECR_SEC_SIZE2)); + FLASH->SECR = (secmem | BootEntry | SecSize | (SecSize2 << FLASH_SECR_SEC_SIZE2_Pos)); +} + +/** + * @brief Return the FLASH Securable memory area protection Option Bytes value. + * @param BootEntry specifies boot scheme configuration + * @param SecSize specifies number of pages to protect as secure memory area, starting from + * beginning of Bank1 (page 0). + * @param SecSize2 specifies number of pages to protect as secure memory area, starting from + * beginning of Bank2 (page 0). + * @retval None + */ +static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize, uint32_t *SecSize2) +{ + uint32_t secmem = FLASH->SECR; + + *BootEntry = (secmem & FLASH_SECR_BOOT_LOCK); + *SecSize = (secmem & FLASH_SECR_SEC_SIZE); + *SecSize2 = (secmem & FLASH_SECR_SEC_SIZE2) >> FLASH_SECR_SEC_SIZE2_Pos; +} + +#else +/** + * @brief Configure Securable Memory area feature. + * @param BootEntry specifies if boot scheme is forced to Flash (System or user) or not + * This parameter can be one of the following values: + * @arg @ref OB_BOOT_ENTRY_FORCED_NONE No boot entry forced + * @arg @ref OB_BOOT_ENTRY_FORCED_FLASH FLash selected as unique entry boot + * @param SecSize specifies number of pages to protect as securable memory area, starting from + * beginning of the Flash (page 0). + * @retval None + */ +static void FLASH_OB_SecMemConfig(uint32_t BootEntry, uint32_t SecSize) +{ + uint32_t secmem; + + /* Check the parameters */ + assert_param(IS_OB_SEC_BOOT_LOCK(BootEntry)); + assert_param(IS_OB_SEC_SIZE(SecSize)); + + /* Set securable memory area configuration */ + secmem = (FLASH->SECR & ~(FLASH_SECR_BOOT_LOCK | FLASH_SECR_SEC_SIZE)); + FLASH->SECR = (secmem | BootEntry | SecSize); +} + +/** + * @brief Return the FLASH Securable memory area protection Option Bytes value. + * @param BootEntry specifies boot scheme configuration + * @param SecSize specifies number of pages to protect as secure memory area, starting from + * beginning of the Flash (page 0). + * @retval None + */ +static void FLASH_OB_GetSecMem(uint32_t *BootEntry, uint32_t *SecSize) +{ + uint32_t secmem = FLASH->SECR; + + *BootEntry = (secmem & FLASH_SECR_BOOT_LOCK); + *SecSize = (secmem & FLASH_SECR_SEC_SIZE); +} +#endif +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_gpio.c (revision 3) @@ -0,0 +1,554 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 28 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PF0 and PF1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * HAL_GPIO_Init + * HAL_GPIO_DeInit + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE (0x00000003u) +#define EXTI_MODE (0x10000000u) +#define GPIO_MODE_IT (0x00010000u) +#define GPIO_MODE_EVT (0x00020000u) +#define RISING_EDGE (0x00100000u) +#define FALLING_EDGE (0x00200000u) +#define GPIO_OUTPUT_TYPE (0x00000010u) + +#define GPIO_NUMBER (16u) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t temp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + temp |= (GPIO_Init->Speed << (position * 2u)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT0 << position) ; + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position); + GPIOx->OTYPER = temp; + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + temp |= ((GPIO_Init->Pull) << (position * 2u)); + GPIOx->PUPDR = temp; + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3u]; + temp &= ~(0xFu << ((position & 0x07u) * 4u)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + GPIOx->AFR[position >> 3u] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2u)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + { + temp = EXTI->EXTICR[position >> 2u]; + temp &= ~(0x0FuL << (8u * (position & 0x03u))); + temp |= (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u))); + EXTI->EXTICR[position >> 2u] = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + { + temp |= iocurrent; + } + EXTI->IMR1 = temp; + + temp = EXTI->EMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + { + temp |= iocurrent; + } + EXTI->EMR1 = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + { + temp |= iocurrent; + } + EXTI->RTSR1 = temp; + + temp = EXTI->FTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + { + temp |= iocurrent; + } + EXTI->FTSR1 = temp; + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00u; + uint32_t iocurrent; + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + + if (iocurrent != 0x00u) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = EXTI->EXTICR[position >> 2u]; + tmp &= (0x0FuL << (8u * (position & 0x03u))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (8u * (position & 0x03u)))) + { + /* Clear EXTI line configuration */ + EXTI->IMR1 &= ~(iocurrent); + EXTI->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR1 &= ~(iocurrent); + EXTI->FTSR1 &= ~(iocurrent); + + tmp = 0x0FuL << (8u * (position & 0x03u)); + EXTI->EXTICR[position >> 2u] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u)); + } + + position++; + } +} + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0x00u) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Set or clear the selected data port bit. + * + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + * @param GPIO_Pin specifies the pin to be toggled. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** +* @brief Lock GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32G0xx family + * @param GPIO_Pin specifies the port bits to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00u) + { + __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); + } + + if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00u) + { + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file + */ +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr.c (revision 3) @@ -0,0 +1,545 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Defines PWR Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the HAL PWR peripheral registers to their default reset + values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + [..] + *** WakeUp pin configuration *** + ================================ + [..] + (+) WakeUp pins are used to wakeup the system from Standby mode or + Shutdown mode. WakeUp pins polarity can be set to configure event + detection on high level (rising edge) or low level (falling edge). + + *** Low Power mode configuration *** + ===================================== + [..] + The devices feature 7 low-power modes: + (+) Low-power run mode: core and peripherals are running at low frequency. + Regulator is in low power mode. + (+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running, + regulator is main mode. + (+) Low-power Sleep mode: Cortex-M0+ core stopped, peripherals kept running + and regulator in low power mode. + (+) Stop 0 mode: all clocks are stopped except LSI and LSE, regulator is + main mode. + (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator + off, low power regulator on. + (+) Standby mode: all clocks are stopped except LSI and LSE, regulator is + disable. + (+) Shutdown mode: all clocks are stopped except LSE, regulator is + disable. + + *** Low-power run mode *** + ========================== + [..] + (+) Entry: (from main run mode) + (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after + having decreased the system clock below 2 MHz. + (+) Exit: + (++) clear LPR bit then wait for REGLPF bit to be reset with + HAL_PWREx_DisableLowPowerRunMode() API. Only then can the + system clock frequency be increased above 2 MHz. + + *** Sleep mode / Low-power sleep mode *** + ========================================= + [..] + (+) Entry: + The Sleep & Low-power Sleep modes are entered through + HAL_PWR_EnterSLEEPMode() API specifying whether or not the regulator + is forced to low-power mode and if exit is interrupt or event + triggered. + (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode). + (++) PWR_LOWPOWERREGULATOR_ON: Low-power Sleep mode (regulator in low + power mode). In this case, the system clock frequency must have + been decreased below 2 MHz beforehand. + (++) PWR_SLEEPENTRY_WFI: Core enters sleep mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: Core enters sleep mode with WFE instruction + (+) WFI Exit: + (++) Any interrupt enabled in nested vectored interrupt controller (NVIC) + (+) WFE Exit: + (++) Any wakeup event if cortex is configured with SEVONPEND = 0 + (++) Interrupt even when disabled in NVIC if cortex is configured with + SEVONPEND = 1 + [..] When exiting the Low-power Sleep mode by issuing an interrupt or a wakeup event, + the MCU is in Low-power Run mode. + + *** Stop 0 & Stop 1 modes *** + ============================= + [..] + (+) Entry: + The Stop modes are entered through the following APIs: + (++) HAL_PWR_EnterSTOPMode() with following settings: + (+++) PWR_MAINREGULATOR_ON to enter STOP0 mode. + (+++) PWR_LOWPOWERREGULATOR_ON to enter STOP1 mode. + (+) Exit (interrupt or event-triggered, specified when entering STOP mode): + (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction + (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction + (+) WFI Exit: + (++) Any EXTI line (internal or external) configured in interrupt mode + with corresponding interrupt enable in NVIC + (+) WFE Exit: + (++) Any EXTI line (internal or external) configured in event mode if + cortex is configured with SEVONPEND = 0 + (++) Any EXTI line configured in interrupt mode (even if the + corresponding EXTI Interrupt vector is disabled in the NVIC) if + cortex is configured with SEVONPEND = 0. The interrupt source can + be external interrupts or peripherals with wakeup capability. + [..] When exiting Stop, the MCU is either in Run mode or in Low-power Run mode + depending on the LPR bit setting. + + *** Standby mode *** + ==================== + [..] In Standby mode, it is possible to keep backup SRAM content (defined as + full SRAM) keeping low power regulator on. This is achievable by setting + Ram retention bit calling HAL_PWREx_EnableSRAMRetention API. This increases + power consumption. + Its also possible to define I/O states using APIs: + HAL_PWREx_EnableGPIOPullUp, HAL_PWREx_EnableGPIOPullDown & + HAL_PWREx_EnablePullUpPullDownConfig + (+) Entry: + (++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API, by + setting SLEEPDEEP in Cortex control register. + (+) Exit: + (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp), + tamper event (internal & external), LSE CSS detection, reset on + NRST pin, IWDG reset & BOR reset. + [..] Exiting Standby generates a power reset: Cortex is reset and execute + Reset handler vector, all registers in the Vcore domain are set to + their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG, + and Standby/Shutdown modes control) are not impacted. + + *** Shutdown mode *** + ====================== + [..] + In Shutdown mode, + voltage regulator is disabled, all clocks are off except LSE, RRS bit is + cleared. SRAM and registers contents are lost except for backup domain + registers. + (+) Entry: + (++) The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API, + by setting SLEEPDEEP in Cortex control register. + (+) Exit: + (++) WKUP pin edge detection, RTC event (wakeup, alarm, timestamp), + tamper event (internal & external), LSE CSS detection, reset on + NRST pin. + [..] Exiting Shutdown generates a brown out reset: Cortex is reset and execute + Reset handler vector, all registers are set to their reset value but ones + in backup domain. + +@endverbatim + * @{ + */ + +/** + * @brief Enable access to the backup domain + * (RTC & TAMP registers, backup registers, RCC BDCR register). + * @note After reset, the backup domain is protected against + * possible unwanted write accesses. All RTC & TAMP registers (backup + * registers included) and RCC BDCR register are concerned. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + + +/** + * @brief Disable access to the backup domain + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values which set + * the default polarity i.e. detection on high level (rising edge): + * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3(*), + * PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6 + * or one of the following value where the user can explicitly specify + * the enabled pin and the chosen polarity: + * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW + * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW + * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW (*) + * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW + * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW (*) + * @arg @ref PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @note (*) availability depends on devices + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* Specifies the Wake-Up pin polarity for the event detection + (rising or falling edge) */ + MODIFY_REG(PWR->CR4, (PWR_CR4_WP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); + + /* Enable wake-up pin */ + SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); +} + + +/** + * @brief Disable the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2,PWR_WAKEUP_PIN3(*), + * PWR_WAKEUP_PIN4,PWR_WAKEUP_PIN5(*),PWR_WAKEUP_PIN6 + * @note (*) availability depends on devices + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); +} + + +/** + * @brief Enter Sleep or Low-power Sleep mode. + * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as + * in Run mode. + * @param Regulator Specifies the regulator state in Sleep/Low-power Sleep + * mode. This parameter can be one of the following values: + * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode) + * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator + * in low-power mode) + * @note Low-power Sleep mode is entered from Low-power Run mode only. In + * case Regulator parameter is set to Low Power but MCU is in Run mode, + * we will first enter in Low-power Run mode. Therefore, user should + * take care that HCLK frequency is less than 2 MHz. + * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. + * To switch back to Run mode, user must call + * HAL_PWREx_DisableLowPowerRunMode() API. + * @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE + * instruction. This parameter can be one of the following values: + * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep + * mode with WFI instruction + * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep + * mode with WFE instruction + * @note When WFI entry is used, tick interrupt have to be disabled if not + * desired as the interrupt wake up source. + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Set Regulator parameter */ + if(Regulator != PWR_MAINREGULATOR_ON) + { + /* If in run mode, first move to low-power run mode. + The system clock frequency must be below 2 MHz at this point. */ + if((PWR->SR2 & PWR_SR2_REGLPF) == 0x00u) + { + HAL_PWREx_EnableLowPowerRunMode(); + } + } + else + { + /* If in low-power run mode at this point, exit it */ + if((PWR->SR2 & PWR_SR2_REGLPF) != 0x00u) + { + if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK) + { + return ; + } + } + } + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + + +/** + * @brief Enter Stop mode + * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with + * legacy code running on devices where only "Stop mode" is mentioned + * with main or low power regulator ON. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note All clocks in the VCORE domain are stopped; the PLL, the HSI and the + * HSE oscillators are disabled. Some peripherals with the wakeup + * capability can switch on the HSI to receive a frame, and switch off + * the HSI after receiving the frame if it is not a wakeup frame. + * SRAM and register contents are preserved. + * The BOR is available. + * The voltage regulator can be configured either in normal (Stop 0) or + * low-power mode (Stop 1). + * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a + * wakeup event, the HSI RC oscillator is selected as system clock + * @note When the voltage regulator operates in low power mode (Stop 1), + * an additional startup delay is incurred when waking up. By keeping + * the internal regulator ON during Stop mode (Stop 0), the consumption + * is higher although the startup time is reduced. + * @param Regulator Specifies the regulator state in Stop mode + * This parameter can be one of the following values: + * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON) + * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power + * regulator ON) + * @param STOPEntry Specifies Stop 0 or Stop 1 mode is entered with WFI or + * WFE instruction. This parameter can be one of the following values: + * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI + * instruction. + * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE + * instruction. + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + if (Regulator != PWR_MAINREGULATOR_ON) + { + /* Stop mode with Low-Power Regulator */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP1); + } + else + { + /* Stop mode with Main Regulator */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0); + } + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + + +/** + * @brief Enter Standby mode. + * @note In Standby mode, the PLL, the HSI and the HSE oscillators are + * switched off. The voltage regulator is disabled. SRAM and register + * contents are lost except for registers in the Backup domain and + * Standby circuitry. BOR is available. + * @note The I/Os can be configured either with a pull-up or pull-down or can + * be kept in analog state. + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() + * respectively enable Pull Up and PullDown state. + * HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown() + * disable the same. These states are effective in Standby mode only if + * APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note Sram content can be kept setting RRS through HAL_PWREx_EnableSRAMRetention() + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Set Stand-by mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + + /* Request Wait For Interrupt */ + __WFI(); +} + + +/** + * @brief Enable Sleep-On-Exit Cortex feature + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor enters SLEEP or DEEPSLEEP mode when an interruption + * handling is over returning to thread mode. Setting this bit is + * useful when the processor is expected to run only on interruptions + * handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Disable Sleep-On-Exit Cortex feature + * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor enters SLEEP or DEEPSLEEP mode when an interruption + * handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Enable Cortex Sev On Pending feature. + * @note Set SEVONPEND bit of SCR register. When this bit is set, enabled + * events and all interrupts, including disabled ones can wakeup + * processor from WFE. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + +/** + * @brief Disable Cortex Sev On Pending feature. + * @note Clear SEVONPEND bit of SCR register. When this bit is clear, only + * enable interrupts or events can wakeup processor from WFE + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_pwr_ex.c (revision 3) @@ -0,0 +1,1019 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Extended Initialization and de-initialization functions + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines + * @{ + */ + +#if defined(PWR_PVD_SUPPORT) +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT 0x00010000U /*!< Mask for interruption yielded + by PVD threshold crossing */ +#define PVD_MODE_EVT 0x00020000U /*!< Mask for event yielded + by PVD threshold crossing */ +#define PVD_RISING_EDGE 0x00000001U /*!< Mask for rising edge set as + PVD trigger */ +#define PVD_FALLING_EDGE 0x00000002U /*!< Mask for falling edge set as + PVD trigger */ +/** + * @} + */ +#endif + +/** @defgroup PWREx_TimeOut_Value PWREx Flag Setting Time Out Value + * @{ + */ +#define PWR_REGLPF_SETTING_DELAY_6_US 6u /*!< REGLPF should rise in about 5 us plus + 2 APB clock. Taking in account max Sysclk at + 2 MHz, and rounded to upper value */ + +#define PWR_VOSF_SETTING_DELAY_6_US 6u /*!< VOSF should rise in about 5 us plus + 2 APB clock. Taking in account max Sysclk at + 16 MHz, and rounded to upper value */ +/** + * @} + */ + +/** @defgroup PWREx_Gpio_Pin_Number PWREx Gpio Pin Number + * @{ + */ +#define PWR_GPIO_PIN_NB 16u /*!< Number of gpio pin in bank */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Initialization and de-initialization functions ##### + =============================================================================== + [..] + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PVDRT[2:0] & PVDFT[2:0] bits in + PWR CR2 register). + (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line 16 and can generate an interrupt if enabled. + (+) The PVD is stopped in Standby & Shutdown mode. + + *** PVM configuration *** + ========================= + [..] + +@endverbatim + * @{ + */ + +/** + * @brief Enable battery charging. + * @note When VDD is present, charge the external battery on VBAT through an + * internal resistor. + * @param ResistorSelection specifies the resistor impedance. + * This parameter can be one of the following values: + * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor + * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor + * @retval None + */ +void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) +{ + uint32_t tmpreg; + assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); + + /* Specify resistor selection and enable battery charging */ + tmpreg = (PWR->CR4 & ~PWR_CR4_VBRS); + PWR->CR4 = (tmpreg | ResistorSelection | PWR_CR4_VBE); +} + + +/** + * @brief Disable battery charging. + * @retval None + */ +void HAL_PWREx_DisableBatteryCharging(void) +{ + CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); +} + +#if defined(PWR_CR3_ENB_ULP) +/** + * @brief Enable POR Monitor sampling mode. + * @note When entering ultra low power modes (standby, shutdown) this feature + * can be enabled to reduce further consumption: Power On Reset monitor + * is then set in sampling mode, and no more in always on mode. + * @retval None + */ +void HAL_PWREx_EnablePORMonitorSampling(void) +{ + PWR->CR3 |= PWR_CR3_ENB_ULP; +} + + +/** + * @brief Disable POR Monitor sampling mode. + * @retval None + */ +void HAL_PWREx_DisablePORMonitorSampling(void) +{ + PWR->CR3 &= ~PWR_CR3_ENB_ULP; +} +#endif + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Configure the Power Voltage Detector (PVD). + * @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the + PVD configuration information: threshold levels, operating mode. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage thresholds corresponding to each + * detection level. + * @note User should take care that rising threshold is higher than falling + * one in order to avoid having always PVDO output set. + * @retval HAL_OK + */ +HAL_StatusTypeDef HAL_PWREx_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PVD level bits only according to PVDLevel value */ + MODIFY_REG(PWR->CR2, (PWR_CR2_PVDFT | PWR_CR2_PVDRT), sConfigPVD->PVDLevel); + + /* Clear any previous config, in case no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } + + return HAL_OK; +} + + +/** + * @brief Enable the Power Voltage Detector (PVD). + * @retval None + */ +void HAL_PWREx_EnablePVD(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_PVDE); +} + + +/** + * @brief Disable the Power Voltage Detector (PVD). + * @retval None + */ +void HAL_PWREx_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); +} +#endif + +#if defined(PWR_PVM_SUPPORT) +/** + * @brief Enable VDDUSB supply. + * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. + * @retval None + */ +void HAL_PWREx_EnableVddUSB(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_USV); +} + +/** + * @brief Disable VDDUSB supply. + * @retval None + */ +void HAL_PWREx_DisableVddUSB(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_USV); +} +#endif + +#if defined(PWR_CR2_IOSV) +/** + * @brief Enable VDDIO2 supply. + * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. + * @retval None + */ +void HAL_PWREx_EnableVddIO2(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_IOSV); +} + + +/** + * @brief Disable VDDIO2 supply. + * @retval None + */ +void HAL_PWREx_DisableVddIO2(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); +} +#endif /* PWR_CR2_IOSV */ + +#if defined (PWR_PVM_SUPPORT) +/** + * @brief Enable the Power Voltage Monitoring for USB peripheral (power domain Vddio2) + * @retval None + */ +void HAL_PWREx_EnablePVMUSB(void) +{ + SET_BIT(PWR->CR2, PWR_PVM_USB); +} + +/** + * @brief Disable the Power Voltage Monitoring for USB peripheral (power domain Vddio2) + * @retval None + */ +void HAL_PWREx_DisablePVMUSB(void) +{ + CLEAR_BIT(PWR->CR2, PWR_PVM_USB); +} +#endif + +#if defined(PWR_PVM_SUPPORT) +/** + * @brief Configure the Peripheral Voltage Monitoring (PVM). + * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the + * PVM configuration information. + * @note The API configures a single PVM according to the information contained + * in the input structure. To configure several PVMs, the API must be singly + * called for each PVM used. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage thresholds corresponding to each + * detection level and to each monitored supply. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); + assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); + + /* Configure EXTI 34 interrupts if so required: + scan through PVMType to detect which PVMx is set and + configure the corresponding EXTI line accordingly. */ + switch (sConfigPVM->PVMType) + { + case PWR_PVM_USB: + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVM_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVM_EXTI_DISABLE_IT(); + __HAL_PWR_PVM_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVM_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) + { + __HAL_PWR_PVM_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) + { + __HAL_PWR_PVM_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) + { + __HAL_PWR_PVM_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) + { + __HAL_PWR_PVM_EXTI_ENABLE_FALLING_EDGE(); + } + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif +/** + * @brief Enable Internal Wake-up Line. + * @retval None + */ +void HAL_PWREx_EnableInternalWakeUpLine(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_EIWUL); +} + +/** + * @brief Disable Internal Wake-up Line. + * @retval None + */ +void HAL_PWREx_DisableInternalWakeUpLine(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); +} + +/** + * @brief Enable GPIO pull-up state in Standby and Shutdown modes. + * @note Set the relevant PUy bit of PWR_PUCRx register to configure the I/O in + * pull-up state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. + * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding + * PDy bit of PWR_PDCRx register is cleared unless it is reserved. + * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + SET_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); + CLEAR_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); + break; + + case PWR_GPIO_B: + SET_BIT(PWR->PUCRB, GPIONumber); + CLEAR_BIT(PWR->PDCRB, GPIONumber); + break; + + case PWR_GPIO_C: + SET_BIT(PWR->PUCRC, GPIONumber); + CLEAR_BIT(PWR->PDCRC, GPIONumber); + break; + + case PWR_GPIO_D: + SET_BIT(PWR->PUCRD, GPIONumber); + CLEAR_BIT(PWR->PDCRD, GPIONumber); + break; + +#if defined(GPI0E) + case PWR_GPIO_E: + SET_BIT(PWR->PUCRE, GPIONumber); + CLEAR_BIT(PWR->PDCRE, GPIONumber); + break; +#endif + case PWR_GPIO_F: + SET_BIT(PWR->PUCRF, GPIONumber); + CLEAR_BIT(PWR->PDCRF, GPIONumber); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. + * @note Reset the relevant PUy bit of PWR_PUCRx register used to configure the I/O + * in pull-up state in Standby and Shutdown modes. + * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_F + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + CLEAR_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); + break; + + case PWR_GPIO_B: + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; + + case PWR_GPIO_C: + CLEAR_BIT(PWR->PUCRC, GPIONumber); + break; + + case PWR_GPIO_D: + CLEAR_BIT(PWR->PUCRD, GPIONumber); + break; + +#if defined(GPI0E) + case PWR_GPIO_E: + CLEAR_BIT(PWR->PUCRE, GPIONumber); + break; +#endif + case PWR_GPIO_F: + CLEAR_BIT(PWR->PUCRF, GPIONumber); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Enable GPIO pull-down state in Standby and Shutdown modes. + * @note Set the relevant PDy bit of PWR_PDCRx register to configure the I/O in + * pull-down state in Standby and Shutdown modes. + * @note This state is effective in Standby and Shutdown modes only if APC bit + * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @note The configuration is lost when exiting the Shutdown mode due to the + * power-on reset, maintained when exiting the Standby mode. + * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding + * PUy bit of PWR_PUCRx register is cleared unless it is reserved. + * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + * I/O pins are available) or the logical OR of several of them to set + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + SET_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); + CLEAR_BIT(PWR->PUCRA, (GPIONumber & ~PWR_GPIO_BIT_14)); + break; + + case PWR_GPIO_B: + SET_BIT(PWR->PDCRB, GPIONumber); + CLEAR_BIT(PWR->PUCRB, GPIONumber); + break; + + case PWR_GPIO_C: + SET_BIT(PWR->PDCRC, GPIONumber); + CLEAR_BIT(PWR->PUCRC, GPIONumber); + break; + + case PWR_GPIO_D: + SET_BIT(PWR->PDCRD, GPIONumber); + CLEAR_BIT(PWR->PUCRD, GPIONumber); + break; + +#if defined(GPIOE) + case PWR_GPIO_E: + SET_BIT(PWR->PDCRE, GPIONumber); + CLEAR_BIT(PWR->PUCRE, GPIONumber); + break; +#endif + case PWR_GPIO_F: + SET_BIT(PWR->PDCRF, GPIONumber); + CLEAR_BIT(PWR->PUCRF, GPIONumber); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Disable GPIO pull-down state in Standby and Shutdown modes. + * @note Reset the relevant PDy bit of PWR_PDCRx register used to configure the I/O + * in pull-down state in Standby and Shutdown modes. + * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_F + * to select the GPIO peripheral. + * @param GPIONumber Specify the I/O pins numbers. + * This parameter can be one of the following values: + * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for ports where less + * I/O pins are available) or the logical OR of several of them to reset + * several bits for a given port in a single API call. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) +{ + HAL_StatusTypeDef status = HAL_OK; + + assert_param(IS_PWR_GPIO(GPIO)); + assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); + + switch (GPIO) + { + case PWR_GPIO_A: + CLEAR_BIT(PWR->PDCRA, (GPIONumber & ~PWR_GPIO_BIT_13)); + break; + + case PWR_GPIO_B: + CLEAR_BIT(PWR->PDCRB, GPIONumber); + break; + + case PWR_GPIO_C: + CLEAR_BIT(PWR->PDCRC, GPIONumber); + break; + + case PWR_GPIO_D: + CLEAR_BIT(PWR->PDCRD, GPIONumber); + break; + +#if defined(GPIOE) + case PWR_GPIO_E: + CLEAR_BIT(PWR->PDCRE, GPIONumber); + break; +#endif + case PWR_GPIO_F: + CLEAR_BIT(PWR->PDCRF, GPIONumber); + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Enable pull-up and pull-down configuration. + * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. + * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding + * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() APIs ensure there + * is no conflict when setting PUy or PDy bit. + * @retval None + */ +void HAL_PWREx_EnablePullUpPullDownConfig(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_APC); +} + +/** + * @brief Disable pull-up and pull-down configuration. + * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in + * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. + * @retval None + */ +void HAL_PWREx_DisablePullUpPullDownConfig(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_APC); +} + +#if defined(PWR_CR3_RRS) +/** + * @brief Enable SRAM content retention in Standby mode. + * @note When RRS bit is set, SRAM is powered by the low-power regulator in + * Standby mode and its content is kept. + * @retval None + */ +void HAL_PWREx_EnableSRAMRetention(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_RRS); +} + + +/** + * @brief Disable SRAM content retention in Standby mode. + * @note When RRS bit is reset, SRAM is powered off in Standby mode + * and its content is lost. + * @retval None + */ +void HAL_PWREx_DisableSRAMRetention(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); +} +#endif + +/** + * @brief Enable Flash Power Down. + * @note This API allows to enable flash power down capabilities in low power + * run, low power sleep and stop modes. + * @param PowerMode this can be a combination of following values: + * @arg @ref PWR_FLASHPD_LPRUN + * @arg @ref PWR_FLASHPD_LPSLEEP + * @arg @ref PWR_FLASHPD_STOP + * @retval None + */ +void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode) +{ + assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode)); + + PWR->CR1 |= PowerMode; +} + + +/** + * @brief Disable Flash Power Down. + * @note This API allows to disable flash power down capabilities in low power + * run, low power sleep and stop modes. + * @param PowerMode this can be a combination of following values: + * @arg @ref PWR_FLASHPD_LPRUN + * @arg @ref PWR_FLASHPD_LPSLEEP + * @arg @ref PWR_FLASHPD_STOP + * @retval None + */ +void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode) +{ + assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode)); + + PWR->CR1 &= ~PowerMode; +} + + +/** + * @brief Return Voltage Scaling Range. + * @retval VOS bit field: + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->CR1 & PWR_CR1_VOS); +} + + +/** + * @brief Configure the main regulator output voltage. + * @param VoltageScaling specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, + * typical output voltage at 1.2 V, + * system frequency up to 64 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, + * typical output voltage at 1.0 V, + * system frequency up to 16 MHz. + * @note When moving from Range 1 to Range 2, the system frequency must be decreased to + * a value below 16 MHz before calling HAL_PWREx_ControlVoltageScaling() API. + * When moving from Range 2 to Range 1, the system frequency can be increased to + * a value up to 64 MHz after calling HAL_PWREx_ControlVoltageScaling() API. + * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be + * cleared before returning the status. If the flag is not cleared within + * 6 microseconds, HAL_TIMEOUT status is reported. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t wait_loop_index; + + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* Modify voltage scaling range */ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); + + /* In case of Range 1 selected, we need to ensure that main regulator reaches new value */ + if(VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) + { + /* Set timeout value */ + wait_loop_index = ((PWR_VOSF_SETTING_DELAY_6_US * SystemCoreClock ) / 1000000U) + 1U; + + /* Wait until VOSF is reset */ + while(HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) + { + if(wait_loop_index != 0U) + { + wait_loop_index--; + } + else + { + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + + + +/** + * @brief Enter Low-power Run mode + * @note System clock frequency has to be decreased below 2 MHz before entering + * low power run mode + * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. + * @retval None + */ +void HAL_PWREx_EnableLowPowerRunMode(void) +{ + /* Set Regulator parameter */ + SET_BIT(PWR->CR1, PWR_CR1_LPR); +} + + +/** + * @brief Exit Low-power Run mode. + * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that + * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode + * returns HAL_TIMEOUT status). The system clock frequency can then be + * increased above 2 MHz. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) +{ + uint32_t wait_loop_index = ((PWR_REGLPF_SETTING_DELAY_6_US * SystemCoreClock ) / 1000000U) + 1U; + + /* Clear LPR bit */ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); + + /* Wait until REGLPF is reset */ + while(HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) + { + if(wait_loop_index != 0U) + { + wait_loop_index--; + } + else + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + + +#if defined(PWR_SHDW_SUPPORT) +/** + * @brief Enter Shutdown mode. + * @note In Shutdown mode, the PLL, the HSI, the LSI and the HSE oscillators are switched + * off. The voltage regulator is disabled and Vcore domain is powered off. + * SRAM and registers contents are lost except for registers in the Backup domain. + * The BOR is not available. + * @note The I/Os can be configured either with a pull-up or pull-down or can + * be kept in analog state. + * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() + * respectively enable Pull Up and PullDown state. + * HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown() + * disable the same. These states are effective in Standby mode only if + * APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API. + * @retval None + + * @retval None + */ +void HAL_PWREx_EnterSHUTDOWNMode(void) +{ + /* Set Shutdown mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_SHUTDOWN); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + + /* Request Wait For Interrupt */ + __WFI(); +} +#endif + +#if defined(PWR_PVD_SUPPORT) && defined(PWR_PVM_SUPPORT) +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWREx_PVD_PVM_IRQHandler(void) +{ + /* Check PWR PVD exti Rising flag */ + if(__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVD interrupt rising user callback */ + HAL_PWREx_PVD_PVM_Rising_Callback(); + } + + /* Check PWR exti fallling flag */ + if(__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVD interrupt falling user callback */ + HAL_PWREx_PVD_PVM_Falling_Callback(); + } + + /* Check PWR PVM exti Rising flag */ + if(__HAL_PWR_PVM_EXTI_GET_RISING_FLAG() != 0x0U) + { + /* Clear PVM exti pending bit */ + __HAL_PWR_PVM_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVD PVM interrupt rising user callback */ + HAL_PWREx_PVD_PVM_Rising_Callback(); + } + + /* Check PWR PVM exti fallling flag */ + if(__HAL_PWR_PVM_EXTI_GET_FALLING_FLAG() != 0x0U) + { + /* Clear PVM exti pending bit */ + __HAL_PWR_PVM_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVM interrupt falling user callback */ + HAL_PWREx_PVD_PVM_Falling_Callback(); + } +} + +/** + * @brief PWR PVD interrupt rising callback + * @retval None + */ +__weak void HAL_PWREx_PVD_PVM_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVD_Rising_Callback can be implemented in the user file + */ +} + +/** + * @brief PWR PVD interrupt Falling callback + * @retval None + */ +__weak void HAL_PWREx_PVD_PVM_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVD_Falling_Callback can be implemented in the user file + */ +} +#elif defined(PWR_PVD_SUPPORT) +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWREx_PVD_IRQHandler(void) +{ + /* Check PWR exti Rising flag */ + if(__HAL_PWR_PVD_EXTI_GET_RISING_FLAG() != 0x0U) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVD interrupt rising user callback */ + HAL_PWREx_PVD_Rising_Callback(); + } + + /* Check PWR exti fallling flag */ + if(__HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() != 0x0U) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVD interrupt falling user callback */ + HAL_PWREx_PVD_Falling_Callback(); + } +} + +/** + * @brief PWR PVD interrupt rising callback + * @retval None + */ +__weak void HAL_PWREx_PVD_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVD_Rising_Callback can be implemented in the user file + */ +} + +/** + * @brief PWR PVD interrupt Falling callback + * @retval None + */ +__weak void HAL_PWREx_PVD_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVD_Falling_Callback can be implemented in the user file + */ +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc.c (revision 3) @@ -0,0 +1,1437 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from High Speed Internal oscillator + (from 8 MHz to reach 16MHz) with Flash 0 wait state. Flash prefetch buffer, + D-Cache and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses: + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in analog mode, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (RTC, ADC, RNG, HSTIM) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ + +#if defined(RCC_HSI48_SUPPORT) +#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#endif /* RCC_HSI48_SUPPORT */ +#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ + +#define PLLSOURCE_NONE (0U) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +#if defined(RCC_MCO2_SUPPORT) +#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO2_GPIO_PORT GPIOA +#define MCO2_PIN GPIO_PIN_10 +#endif /* RCC_MCO2_SUPPORT */ + +#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ + (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__))) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal and external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB) + + [..] Internal/external clock and PLL configuration + (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also optionally as RTC clock source. + + (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source. + + (+) PLL (clocked by HSI, HSE) providing up to three independent output clocks: + (++) The first output (R) is used to generate the high speed system clock (up to 64MHz). + (++) The second output(Q) is used to generate the clock for the random analog generator and HStim. + (++) The Third output (P) is used to generate the clock for the Analog to Digital Converter and I2S. + + (+) CSS (Clock security system): once enabled, if a HSE or LSE clock failure occurs + (HSE used directly or through PLL as System clock source), the System clock + is automatically switched respectively to HSI or LSI and an interrupt is generated + if enabled. The interrupt is linked to the Cortex-M0+ NMI (Non-Maskable Interrupt) + exception vector. + + (+) MCOx (microcontroller clock output): + (++) MCO1 used to output LSI, HSI48(*), HSI, LSE, HSE or main PLL clock (through a configurable prescaler) on PA8 pin. + (++) MCO2(*) used to output LSI, HSI48(*), HSI, LSE, HSE, main PLLR clock, PLLQ clock, PLLP clock, RTC clock or RTC_Wakeup (through a configurable prescaler) on PA10 pin. + (*) available on certain devices only + + [..] System, AHB and APB buses clocks configuration + (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE, LSI, LSE and main PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...).and APB (PCLK1) clock is derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. + You have to use @ref __HAL_RCC_RTC_ENABLE() and @ref HAL_RCCEx_PeriphCLKConfig() function + to configure this clock. + + (+@) RNG(*) requires a frequency equal or lower than 48 MHz. + This clock is derived from the main PLL or HSI or System clock. + (*) available on certain devices only + + (+@) IWDG clock which is always the LSI clock. + + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK is 64 MHz. + Depending on the device voltage range, the maximum frequency should be + adapted accordingly. + + @endverbatim + + (++) Table 1. HCLK clock frequency. + (++) +-------------------------------------------------------+ + (++) | Latency | HCLK clock frequency (MHz) | + (++) | |-------------------------------------| + (++) | | voltage range 1 | voltage range 2 | + (++) | | 1.2 V | 1.0 V | + (++) |-----------------|------------------|------------------| + (++) |0WS(1 CPU cycles)| HCLK <= 24 | HCLK <= 8 | + (++) |-----------------|------------------|------------------| + (++) |1WS(2 CPU cycles)| HCLK <= 48 | HCLK <= 16 | + (++) |-----------------|------------------|------------------| + (++) |2WS(3 CPU cycles)| HCLK <= 64 | - | + (++) |-----------------|------------------|------------------| + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL OFF + * - AHB and APB prescaler set to 1. + * - CSS, MCO1 OFF + * - All interrupts disabled + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[6:0] bits to the reset value */ + RCC->ICSCR = RCC_ICSCR_HSITRIM_6; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Reset CFGR register (HSI is selected as system clock source) */ + RCC->CFGR = 0x00000000u; + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */ + RCC->CR = RCC_CR_HSION; + + /* Then again to HSEBYP in case bypass was enabled */ + RCC->CR = RCC_CR_HSION; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* once PLL is OFF, reset PLLCFGR register to default value */ + RCC->PLLCFGR = RCC_PLLCFGR_PLLN_4; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000u; + + /* Clear all flags */ + RCC->CICR = 0xFFFFFFFFu; + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Initialize the RCC Oscillators according to the specified parameters in the + * @ref RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to a @ref RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then to HSE On or HSE Bypass. + * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then to LSE On or LSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t temp_sysclksrc; + uint32_t temp_pllckcfg; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE)) + { + if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); + + /* Check if HSI16 is used as system clock or as PLL source when PLL is selected as system clock */ + temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE(); + if (((temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI)) + { + /* When HSI is used as system clock or as PLL input clock it can not be disabled */ + if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + + if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) + { + /* Adjust the HSI16 division factor */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); + + /* Update the SystemCoreClock global variable with HSISYS value */ + SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); + } + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Configure the HSI16 division factor */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); + + /* Enable the Internal High Speed oscillator (HSI16). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI16). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check if LSI is used as system clock */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) + { + /* When LSI is used as system clock it will not be disabled */ + if ((((RCC->CSR) & RCC_CSR_LSIRDY) != 0U) && (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled */ + while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* When the LSE is used as system clock, it is not allowed disable it */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) + { + if ((((RCC->BDCR) & RCC_BDCR_LSERDY) != 0U) && (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + } +#if defined(RCC_HSI48_SUPPORT) + /*------------------------------ HSI48 Configuration -----------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) + { + /* Enable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (HSI48). */ + __HAL_RCC_HSI48_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI48 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } +#endif /* RCC_HSI48_SUPPORT */ + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + + if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); +#if defined(RCC_PLLQ_SUPPORT) + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); +#endif /* RCC_PLLQ_SUPPORT */ + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, +#if defined(RCC_PLLQ_SUPPORT) + RCC_OscInitStruct->PLL.PLLQ, +#endif /* RCC_PLLQ_SUPPORT */ + RCC_OscInitStruct->PLL.PLLR); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Enable PLLR Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLRCLK); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Disable all PLL outputs to save power */ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE); + +#if defined(RCC_PLLQ_SUPPORT) + __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN); +#else + __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLREN); +#endif /* RCC_PLLQ_SUPPORT */ + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + temp_pllckcfg = RCC->PLLCFGR; + if ((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || +#if defined (RCC_PLLQ_SUPPORT) + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) || +#endif /* RCC_PLLQ_SUPPORT */ + (READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + { + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Initialize the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to a @ref RCC_ClkInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle + * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used by default as system clock source after + * startup from Reset, wake-up from STANDBY mode. After restart from Reset, + * the HSI frequency is set to 8 Mhz, then it reaches its default value 16 MHz. + * + * @note The HSI can be selected as system clock source after + * from STOP modes or in case of failure of the HSE used directly or indirectly + * as system clock (if the Clock Security System CSS is enabled). + * + * @note The LSI can be selected as system clock source after + * in case of failure of the LSE used directly or indirectly + * as system clock (if the Clock Security System LSECSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source is ready. + * + * @note You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the FLASH clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by polling the FLASH_ACR register */ + tickstart = HAL_GetTick(); + + while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APB divider in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + { + /* Check the HSI ready flag */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + return HAL_ERROR; + } + } + /* LSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) + { + /* Check the LSI ready flag */ + if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + { + return HAL_ERROR; + } + } + /* LSE is selected as System Clock Source */ + else + { + /* Check the LSE ready flag */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + return HAL_ERROR; + } + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by polling the FLASH_ACR register */ + tickstart = HAL_GetTick(); + + while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); + + /* Configure the source of time base considering new system clocks settings*/ + return HAL_InitTick(uwTickPrio); +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to: + + (+) Output clock to MCO pin. + (+) Retrieve current clock frequencies. + (+) Enable the Clock Security System. + +@endverbatim + * @{ + */ + +/** + * @brief Select the clock source to output on MCO1 pin(PA8) or MC02 pin (PA10)(*). + * @note PA8, PA10(*) should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * For STM32G0xx family this parameter can have only one value: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @arg @ref RCC_MCO2 Clock source to output on MCO2 pin(PA10)(*). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO + * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48(*) + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLLR clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLLPCLK PLLP clock selected as MCO1 source(*) + * @arg @ref RCC_MCO1SOURCE_PLLQCLK PLLQ clock selected as MCO1 source(*) + * @arg @ref RCC_MCO1SOURCE_RTCCLK RTC clock selected as MCO1 source(*) + * @arg @ref RCC_MCO1SOURCE_RTC_WKUP RTC_Wakeup selected as MCO1 source(*) + * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO2 output disabled, no clock on MCO2(*) + * @arg @ref RCC_MCO2SOURCE_SYSCLK system clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_HSI48 HSI48 clock selected as MCO2 source for devices with HSI48(*) + * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_PLLCLK main PLLR clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_PLLPCLK PLLP clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_PLLQCLK PLLQ clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_RTCCLK RTC clock selected as MCO2 source(*) + * @arg @ref RCC_MCO2SOURCE_RTC_WKUP RTC_Wakeup selected as MCO2 source(*) + * @param RCC_MCODiv specifies the MCO prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock + * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock + * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock + * @arg @ref RCC_MCO2DIV_1 no division applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_2 division by 2 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_4 division by 4 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_8 division by 8 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_16 division by 16 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_32 division by 32 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_64 division by 64 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_128 division by 128 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_256 division by 256 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_512 division by 512 applied to MCO2 clock(*) + * @arg @ref RCC_MCO2DIV_1024 division by 1024 applied to MCO2 clock(*) + * + * (*) Feature not available on all devices of the family + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + + /* Common GPIO init parameters */ + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + + if (RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); + } +#if defined(RCC_MCO2_SUPPORT) + else if (RCC_MCOx == RCC_MCO2) + { + assert_param(IS_RCC_MCO2DIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + /* MCO2 Clock Enable */ + MCO2_CLK_ENABLE(); + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO2_PIN; + GPIO_InitStruct.Alternate = GPIO_AF3_MCO2; + HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2SEL | RCC_CFGR_MCO2PRE), (RCC_MCOSource | RCC_MCODiv)); + } +#endif /* RCC_MCO2_SUPPORT */ +} + +/** + * @brief Return the SYSCLK frequency. + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE/HSIDIV(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note If SYSCLK source is LSI, function returns values based on LSI_VALUE(***) + * @note If SYSCLK source is LSE, function returns values based on LSE_VALUE(****) + * @note (*) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * @note (***) LSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 32768 Hz). + * @note (****) LSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 32000 Hz). + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllvco, pllsource, pllr, pllm, hsidiv; + uint32_t sysclockfreq; + + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + { + /* HSISYS can be derived for HSI16 */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); + + /* HSI used as system clock source */ + sysclockfreq = (HSI_VALUE / hsidiv); + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + { + /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + /* PLL used as system clock source */ + + /* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ; + + switch (pllsource) + { + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + break; + + case RCC_PLLSOURCE_HSI: /* HSI16 used as PLL clock source */ + default: /* HSI16 used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) ; + break; + } + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U); + sysclockfreq = pllvco / pllr; + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSE) + { + /* LSE used as system clock source */ + sysclockfreq = LSE_VALUE; + } + else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_LSI) + { + /* LSI used as system clock source */ + sysclockfreq = LSI_VALUE; + } + else + { + sysclockfreq = 0U; + } + + return sysclockfreq; +} + +/** + * @brief Return the HCLK frequency. + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Return the PCLK1 frequency. + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); +} + +/** + * @brief Configure the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Check the parameters */ + assert_param(RCC_OscInitStruct != (void *)NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ +#if defined(RCC_HSI48_SUPPORT) + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; +#else + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; +#endif /* RCC_HSI48_SUPPORT */ + + /* Get the HSE configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = ((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); + RCC_OscInitStruct->HSIDiv = ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + +#if defined(RCC_HSI48_SUPPORT) + /* Get the HSI48 configuration ---------------------------------------------*/ + if (READ_BIT(RCC->CR, RCC_CR_HSI48ON) == RCC_CR_HSI48ON) + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; + } + else + { + RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; + } +#endif /* RCC_HSI48_SUPPORT */ + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (RCC->PLLCFGR & RCC_PLLCFGR_PLLP); +#if defined(RCC_PLLQ_SUPPORT) + RCC_OscInitStruct->PLL.PLLQ = (RCC->PLLCFGR & RCC_PLLCFGR_PLLQ); +#endif /* RCC_PLLQ_SUPPORT */ + RCC_OscInitStruct->PLL.PLLR = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR); +} + +/** + * @brief Configure the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct Pointer to a @ref RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != (void *)NULL); + assert_param(pFLatency != (void *)NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE); + + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief Enable the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector. + * @note The Clock Security System can only be cleared by reset. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON) ; +} + +/** + * @brief Enable the LSE Clock Security System. + * @note If a failure is detected on the LSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0+ NMI (Non-Maskable Interrupt) exception vector. + * @note The LSE Clock Security System Detection bit (LSECSSD in BDCR) can only be + * cleared by a backup domain reset. + * @retval None + */ +void HAL_RCC_EnableLSECSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +} + +/** + * @brief Disable the LSE Clock Security System. + * @note After LSE failure detection, the software must disable LSECSSON + * @note The Clock Security System can only be cleared by reset otherwise. + * @retval None + */ +void HAL_RCC_DisableLSECSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +} + +/** + * @brief Handle the RCC Clock Security System interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + uint32_t itflag = RCC->CIFR; + + /* Clear interrupt flags related to CSS */ + RCC->CICR = (itflag & (RCC_CIFR_CSSF | RCC_CIFR_LSECSSF)); + + /* Check RCC CSSF interrupt flag */ + if ((itflag & RCC_CIFR_CSSF) != 0x00u) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + } + + /* Check RCC LSECSSF interrupt flag */ + if ((itflag & RCC_CIFR_LSECSSF) != 0x00u) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_LSECSSCallback(); + } +} + +/** + * @brief Handle the RCC HSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCC_CSSCallback should be implemented in the user file + */ +} + +/** + * @brief RCC LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCC_LSECSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RCC_LSECSSCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_rcc_ex.c (revision 3) @@ -0,0 +1,1682 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extended peripheral: + * + Extended Peripheral Control functions + * + Extended Clock management functions + * + Extended Clock Recovery System Control functions + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC Extended HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants RCCEx Private Constants + * @{ + */ +#define PLL_TIMEOUT_VALUE 100U /* 100 ms (minimum Tick + 1) */ + +#define LSCO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define LSCO_GPIO_PORT GPIOA +#define LSCO_PIN GPIO_PIN_2 +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ +/** + * @brief Initialize the RCC extended peripherals clocks according to the specified + * parameters in the @ref RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to a @ref RCC_PeriphCLKInitTypeDef structure that + * contains a field PeriphClockSelection which can be a combination of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock (2) + * @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_LPUART2 LPUART2 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock (1)(2) + * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock (1)(2) + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (2) + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock (2) + * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (1) + * + * @note (1) Peripherals are not available on all devices + * @note (2) Peripherals clock selection is not available on all devices + * @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source: in this case the access to Backup domain is enabled. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tmpregister; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*-------------------------- RTC clock source configuration ----------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + FlagStatus pwrclkchanged = RESET; + + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + + if (ret == HAL_OK) + { + /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ + tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpregister; + } + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + } + + if (ret == HAL_OK) + { + /* Apply new RTC clock source selection */ + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + else + { + /* set overall return value */ + status = ret; + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*-------------------------- USART1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + +#if defined(RCC_CCIPR_USART2SEL) + /*-------------------------- USART2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } +#endif /* RCC_CCIPR_USART2SEL */ + +#if defined(RCC_CCIPR_USART3SEL) + /*-------------------------- USART3 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(LPUART1) + /*-------------------------- LPUART1 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUART1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + } +#endif /* LPUART1 */ + +#if defined(LPUART2) + /*-------------------------- LPUART2 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART2) == RCC_PERIPHCLK_LPUART2) + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART2CLKSOURCE(PeriphClkInit->Lpuart2ClockSelection)); + + /* Configure the LPUART clock source */ + __HAL_RCC_LPUART2_CONFIG(PeriphClkInit->Lpuart2ClockSelection); + } +#endif /* LPUART2 */ + +#if defined(RCC_CCIPR_LPTIM1SEL) + /*-------------------------- LPTIM1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + { + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } +#endif /* RCC_CCIPR_LPTIM1SEL */ + +#if defined(RCC_CCIPR_LPTIM2SEL) + /*-------------------------- LPTIM2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + { + assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + } +#endif /* RCC_CCIPR_LPTIM2SEL */ + + /*-------------------------- I2C1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + +#if defined(RCC_CCIPR_I2C2SEL) + /*-------------------------- I2C2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + } +#endif /* (RCC_CCIPR_I2C2SEL */ + +#if defined(RNG) + /*-------------------------- RNG clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) + { + assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + + if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + } + } +#endif /* RNG */ + /*-------------------------- ADC clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC interface clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLADC) + { + /* Enable PLLPCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); + } + } + +#if defined(CEC) + /*-------------------------- CEC clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } +#endif /* CEC */ + +#if defined(RCC_CCIPR_TIM1SEL) + /*-------------------------- TIM1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); + + /* Configure the TIM1 clock source */ + __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); + + if (PeriphClkInit->Tim1ClockSelection == RCC_TIM1CLKSOURCE_PLL) + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + } + } +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) + /*-------------------------- TIM15 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15) + { + /* Check the parameters */ + assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection)); + + /* Configure the TIM15 clock source */ + __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection); + + if (PeriphClkInit->Tim15ClockSelection == RCC_TIM15CLKSOURCE_PLL) + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + } + } +#endif /* RCC_CCIPR_TIM15SEL */ + + /*-------------------------- I2S1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection)); + + /* Configure the I2S1 clock source */ + __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection); + + if (PeriphClkInit->I2s1ClockSelection == RCC_I2S1CLKSOURCE_PLL) + { + /* Enable PLLPCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); + } + } + +#if defined(RCC_CCIPR2_I2S2SEL) + /*-------------------------- I2S2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); + + /* Configure the I2S2 clock source */ + __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); + + if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL) + { + /* Enable PLLPCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLPCLK); + } + } +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) + /*-------------------------- USB clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + /* Check the parameters */ + assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); + + /* Configure the USB clock source */ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + + if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + } + } +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(FDCAN1) || defined(FDCAN2) + /*-------------------------- FDCAN clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + { + /* Check the parameters */ + assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection)); + + /* Configure the FDCAN clock source */ + __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); + + if (PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL) + { + /* Enable PLLQCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLLQCLK); + } + } +#endif /* FDCAN1 || FDCAN2 */ + + return status; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals + * clocks: I2C1, I2S1, USART1, RTC, ADC, + * LPTIM1 (1), LPTIM2 (1), TIM1 (2), TIM15 (1)(2), USART2 (2), LPUART1 (1), CEC (1) and RNG (1) + * @note (1) Peripheral is not available on all devices + * @note (2) Peripheral clock selection is not available on all devices + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2S1 | \ + RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC ; + +#if defined(RCC_CCIPR_LPTIM1SEL) && defined(RCC_CCIPR_LPTIM2SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM1; +#endif /* RCC_CCIPR_LPTIM1SEL && RCC_CCIPR_LPTIM2SEL */ +#if defined(RCC_CCIPR_RNGSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_RNG; +#endif /* RCC_CCIPR_RNGSEL */ +#if defined(RCC_CCIPR_LPUART1SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPUART1; +#endif /* RCC_CCIPR_LPUART1SEL */ +#if defined(RCC_CCIPR_LPUART2SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPUART2; +#endif /* RCC_CCIPR_LPUART2SEL */ +#if defined(RCC_CCIPR_CECSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; +#endif /* RCC_CCIPR_CECSEL */ +#if defined(RCC_CCIPR_TIM1SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1; +#endif /* RCC_CCIPR_TIM1SEL */ +#if defined(RCC_CCIPR_TIM15SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15; +#endif /* RCC_CCIPR_TIM15SEL */ +#if defined(RCC_CCIPR_USART2SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2; +#endif /* RCC_CCIPR_USART2SEL */ +#if defined(RCC_CCIPR_USART3SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3; +#endif /* RCC_CCIPR_USART3SEL */ +#if defined(RCC_CCIPR_I2C2SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2; +#endif /* RCC_CCIPR_I2C2SEL */ +#if defined(RCC_CCIPR2_I2S2SEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2; +#endif /* RCC_CCIPR2_I2S2SEL */ +#if defined(RCC_CCIPR2_USBSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; +#endif /* RCC_CCIPR2_USBSEL */ +#if defined(RCC_CCIPR2_FDCANSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_FDCAN; +#endif /* RCC_CCIPR_FDCANSEL */ + /* Get the USART1 clock source ---------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); +#if defined(RCC_CCIPR_USART2SEL) + /* Get the USART2 clock source ---------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); +#endif /* RCC_CCIPR_USART2SEL */ +#if defined(RCC_CCIPR_USART3SEL) + /* Get the USART3 clock source ---------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); +#endif /* RCC_CCIPR_USART3SEL */ +#if defined(RCC_CCIPR_LPUART1SEL) + /* Get the LPUART1 clock source --------------------------------------------*/ + PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); +#endif /* RCC_CCIPR_LPUART1SEL */ +#if defined(RCC_CCIPR_LPUART2SEL) + /* Get the LPUART2 clock source --------------------------------------------*/ + PeriphClkInit->Lpuart2ClockSelection = __HAL_RCC_GET_LPUART2_SOURCE(); +#endif /* RCC_CCIPR_LPUART2SEL */ + /* Get the I2C1 clock source -----------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#if defined(RCC_CCIPR_I2C2SEL) + /* Get the I2C2 clock source -----------------------------------------------*/ + PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); +#endif /* RCC_CCIPR_I2C2SEL */ +#if defined(RCC_CCIPR_LPTIM1SEL) + /* Get the LPTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); +#endif /* RCC_CCIPR_LPTIM1SEL */ +#if defined(RCC_CCIPR_LPTIM2SEL) + /* Get the LPTIM2 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); +#endif /* RCC_CCIPR_LPTIM2SEL */ +#if defined(RCC_CCIPR_TIM1SEL) + /* Get the TIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE(); +#endif /* RCC_CCIPR_TIM1SEL */ +#if defined(RCC_CCIPR_TIM15SEL) + /* Get the TIM15 clock source ---------------------------------------------*/ + PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE(); +#endif /* RCC_CCIPR_TIM15SEL */ + /* Get the RTC clock source ------------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); +#if defined(RCC_CCIPR_RNGSEL) + /* Get the RNG clock source ------------------------------------------------*/ + PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); +#endif /* RCC_CCIPR_RNGSEL */ + /* Get the ADC clock source -----------------------------------------------*/ + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); +#if defined(RCC_CCIPR_CECSEL) + /* Get the CEC clock source -----------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); +#endif /* RCC_CCIPR_CECSEL */ +#if defined(RCC_CCIPR2_USBSEL) + /* Get the USB clock source -----------------------------------------------*/ + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); +#endif /* RCC_CCIPR2_USBSEL */ +#if defined(RCC_CCIPR2_FDCANSEL) + /* Get the FDCAN clock source -----------------------------------------------*/ + PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); +#endif /* RCC_CCIPR2_FDCANSEL */ + /* Get the I2S1 clock source -----------------------------------------------*/ + PeriphClkInit->I2s1ClockSelection = __HAL_RCC_GET_I2S1_SOURCE(); +#if defined(RCC_CCIPR2_I2S2SEL) + /* Get the I2S2 clock source -----------------------------------------------*/ + PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE(); +#endif /* RCC_CCIPR2_I2S2SEL */ +} + +/** + * @brief Return the peripheral clock frequency for peripherals with clock source from PLL + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_I2S1 I2S1 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (1)(2) + * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock (1)(2) + * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock (1)(2) + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock(1) + * @arg @ref RCC_PERIPHCLK_LPUART2 LPUART2 peripheral clock(1) + * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock (1) + * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock (1) + * @note (1) Peripheral not available on all devices + * @note (2) Peripheral Clock configuration not available on all devices + * @retval Frequency in Hz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t frequency = 0U; + uint32_t srcclk; + uint32_t pllvco; + uint32_t plln; +#if defined(RCC_CCIPR_RNGSEL) + uint32_t rngclk; + uint32_t rngdiv; +#endif /* RCC_CCIPR_RNGSEL */ + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + if (PeriphClk == RCC_PERIPHCLK_RTC) + { + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready and if RTC clock selection is LSE */ + if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Check if LSI is ready and if RTC clock selection is LSI */ + else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI)) + { + frequency = LSI_VALUE; + } + /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32)) + { + frequency = HSE_VALUE / 32U; + } + /* Clock not enabled for RTC*/ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + } + else + { + /* Other external peripheral clock source than RTC */ + + /* Compute PLL clock input */ + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) /* HSI ? */ + { + pllvco = HSI_VALUE; + } + else if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) /* HSE ? */ + { + pllvco = HSE_VALUE; + } + else /* No source */ + { + pllvco = 0U; + } + + /* f(PLL Source) / PLLM */ + pllvco = (pllvco / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U)); + + switch (PeriphClk) + { +#if defined(RCC_CCIPR_RNGSEL) + case RCC_PERIPHCLK_RNG: + + srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGSEL); + if (srcclk == RCC_RNGCLKSOURCE_HSI_DIV8) /* HSI_DIV8 ? */ + { + rngclk = HSI_VALUE / 8U; + } + else if (srcclk == RCC_RNGCLKSOURCE_PLL) /* PLL ? */ + { + /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + rngclk = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U); + } + else if (srcclk == RCC_RNGCLKSOURCE_SYSCLK) /* SYSCLK ? */ + { + rngclk = HAL_RCC_GetSysClockFreq(); + } + else /* No clock source */ + { + rngclk = 0U; + } + + rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos)); + frequency = (rngclk / rngdiv); + + break; +#endif /* RCC_CCIPR_RNGSEL */ + case RCC_PERIPHCLK_USART1: + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + if (srcclk == RCC_USART1CLKSOURCE_PCLK1) /* PCLK1 ? */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) /* SYSCLK ? */ + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#if defined(RCC_CCIPR_USART2SEL) + case RCC_PERIPHCLK_USART2: + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); + + if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART2 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_USART2SEL */ + +#if defined(RCC_CCIPR_USART3SEL) + case RCC_PERIPHCLK_USART3: + /* Get the current USART3 source */ + srcclk = __HAL_RCC_GET_USART3_SOURCE(); + + if (srcclk == RCC_USART3CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for USART3 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_USART3SEL */ + +#if defined(RCC_CCIPR_CECSEL) + case RCC_PERIPHCLK_CEC: + /* Get the current CEC source */ + srcclk = __HAL_RCC_GET_CEC_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_CECCLKSOURCE_HSI_DIV488)) + { + frequency = (HSI_VALUE / 488U); + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_CECCLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for CEC */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_CECSEL */ + +#if defined(RCC_CCIPR_LPUART1SEL) + case RCC_PERIPHCLK_LPUART1: + /* Get the current LPUART1 source */ + srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); + + if (srcclk == RCC_LPUART1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPUART1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_LPUART1SEL */ + +#if defined(RCC_CCIPR_LPUART2SEL) + case RCC_PERIPHCLK_LPUART2: + /* Get the current LPUART2 source */ + srcclk = __HAL_RCC_GET_LPUART2_SOURCE(); + + if (srcclk == RCC_LPUART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_LPUART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPUART2 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_LPUART2SEL */ + + case RCC_PERIPHCLK_ADC: + + srcclk = __HAL_RCC_GET_ADC_SOURCE(); + + if (srcclk == RCC_ADCCLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_ADCCLKSOURCE_HSI) + { + frequency = HSI_VALUE; + } + else if (srcclk == RCC_ADCCLKSOURCE_PLLADC) + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U) + { + /* f(PLLP) = f(VCO input) * PLLN / PLLP */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U); + } + } + /* Clock not enabled for ADC */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + + case RCC_PERIPHCLK_I2C1: + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + /* Clock not enabled for I2C1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + +#if defined(RCC_CCIPR_I2C2SEL) + case RCC_PERIPHCLK_I2C2: + /* Get the current I2C2 source */ + srcclk = __HAL_RCC_GET_I2C2_SOURCE(); + + if (srcclk == RCC_I2C2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + /* Clock not enabled for I2C2 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_I2C2SEL */ + + case RCC_PERIPHCLK_I2S1: + /* Get the current I2S1 source */ + srcclk = __HAL_RCC_GET_I2S1_SOURCE(); + + if (srcclk == RCC_I2S1CLKSOURCE_PLL) + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U) + { + /* f(PLLP) = f(VCO input) * PLLN / PLLP */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U); + } + } + else if (srcclk == RCC_I2S1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2S1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if (srcclk == RCC_I2S1CLKSOURCE_EXT) + { + /* External clock used.*/ + frequency = EXTERNAL_I2S1_CLOCK_VALUE; + } + /* Clock not enabled for I2S1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; + +#if defined(RCC_CCIPR2_I2S2SEL) + case RCC_PERIPHCLK_I2S2: + /* Get the current I2S2 source */ + srcclk = __HAL_RCC_GET_I2S2_SOURCE(); + + if (srcclk == RCC_I2S2CLKSOURCE_PLL) + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLPCLK) != 0U) + { + /* f(PLLP) = f(VCO input) * PLLN / PLLP */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U); + } + } + else if (srcclk == RCC_I2S2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2S2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if (srcclk == RCC_I2S2CLKSOURCE_EXT) + { + /* External clock used.*/ + frequency = EXTERNAL_I2S2_CLOCK_VALUE; + } + /* Clock not enabled for I2S2 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(RCC_CCIPR_LPTIM1SEL) + case RCC_PERIPHCLK_LPTIM1: + /* Get the current LPTIM1 source */ + srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); + + if (srcclk == RCC_LPTIM1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) + { + frequency = LSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM1 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_LPTIM1SEL */ + +#if defined(RCC_CCIPR_LPTIM2SEL) + case RCC_PERIPHCLK_LPTIM2: + /* Get the current LPTIM2 source */ + srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); + + if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI)) + { + frequency = LSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI)) + { + frequency = HSI_VALUE; + } + else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE)) + { + frequency = LSE_VALUE; + } + /* Clock not enabled for LPTIM2 */ + else + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_LPTIM2SEL */ + +#if defined(RCC_CCIPR_TIM1SEL) + case RCC_PERIPHCLK_TIM1: + + srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL); + + if (srcclk == RCC_TIM1CLKSOURCE_PLL) /* PLL ? */ + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U) + { + /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U); + } + } + else if (srcclk == RCC_TIM1CLKSOURCE_PCLK1) /* PCLK1 ? */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else /* No clock source */ + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_TIM1SEL */ + +#if defined(RCC_CCIPR_TIM15SEL) + case RCC_PERIPHCLK_TIM15: + + srcclk = READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL); + + if (srcclk == RCC_TIM15CLKSOURCE_PLL) /* PLL ? */ + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U) + { + /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U); + } + } + else if (srcclk == RCC_TIM15CLKSOURCE_PCLK1) /* PCLK1 ? */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else /* No clock source */ + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR_TIM15SEL */ + +#if defined(RCC_CCIPR2_USBSEL) + case RCC_PERIPHCLK_USB: + + srcclk = READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBSEL); + + if (srcclk == RCC_USBCLKSOURCE_PLL) /* PLL ? */ + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U) + { + /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U); + } + } +#if defined(RCC_HSI48_SUPPORT) + else if (srcclk == RCC_USBCLKSOURCE_HSI48) /* HSI48 ? */ + { + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_USBCLKSOURCE_HSI48)) + { + frequency = HSI48_VALUE; + } + } +#endif /* RCC_HSI48_SUPPORT */ + else if (srcclk == RCC_USBCLKSOURCE_HSE) + { + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + } + else /* No clock source */ + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR2_USBSEL */ + +#if defined(RCC_CCIPR2_FDCANSEL) + case RCC_PERIPHCLK_FDCAN: + + srcclk = READ_BIT(RCC->CCIPR2, RCC_CCIPR2_FDCANSEL); + + if (srcclk == RCC_FDCANCLKSOURCE_PLL) /* PLL ? */ + { + if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLLQCLK) != 0U) + { + /* f(PLLQ) = f(VCO input) * PLLN / PLLQ */ + plln = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos; + frequency = (pllvco * plln) / ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos) + 1U); + } + } + else if (srcclk == RCC_FDCANCLKSOURCE_PCLK1) /* PCLK1 ? */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCANCLKSOURCE_HSE)) + { + frequency = HSE_VALUE; + } + else /* No clock source */ + { + /* Nothing to do as frequency already initialized to 0U */ + } + break; +#endif /* RCC_CCIPR2_FDCANSEL */ + + default: + break; + } + } + + return (frequency); +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of LSE CSS, Low speed clock output and + clock after wake-up from STOP mode. +@endverbatim + * @{ + */ + +/** + * @brief Select the Low Speed clock source to output on LSCO pin (PA2). + * @param LSCOSource specifies the Low Speed clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source + * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source + * @retval None + */ +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) +{ + GPIO_InitTypeDef GPIO_InitStruct; + FlagStatus pwrclkchanged = RESET; + FlagStatus backupchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); + + /* LSCO Pin Clock Enable */ + LSCO_CLK_ENABLE(); + + /* Configure the LSCO pin in analog mode */ + GPIO_InitStruct.Pin = LSCO_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(LSCO_GPIO_PORT, &GPIO_InitStruct); + + /* Update LSCOSEL clock source in Backup Domain control register */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + HAL_PWR_EnableBkUpAccess(); + backupchanged = SET; + } + + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); + + if (backupchanged == SET) + { + HAL_PWR_DisableBkUpAccess(); + } + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } +} + +/** + * @brief Disable the Low Speed clock output. + * @retval None + */ +void HAL_RCCEx_DisableLSCO(void) +{ + FlagStatus pwrclkchanged = RESET; + FlagStatus backupchanged = RESET; + + /* Update LSCOEN bit in Backup Domain control register */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + /* Enable access to the backup domain */ + HAL_PWR_EnableBkUpAccess(); + backupchanged = SET; + } + + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); + + /* Restore previous configuration */ + if (backupchanged == SET) + { + /* Disable access to the backup domain */ + HAL_PWR_DisableBkUpAccess(); + } + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } +} + +/** + * @} + */ + +#if defined(CRS) + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and sychronization frequencies values + (##) Call function HAL_RCCEx_CRSConfig which + (+++) Resets CRS registers to their default values. + (+++) Configures CRS registers with synchronization configuration + (+++) Enables automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the upcounting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (CRS_IRQn/CRS_IRQHandler) + (++) Call function HAL_RCCEx_CRSConfig() + (++) Enable CRS_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) HAL_RCCEx_CRS_SyncOkCallback() + (+++) HAL_RCCEx_CRS_SyncWarnCallback() + (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +{ + uint32_t value; /* no init needed */ + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Prescaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[6:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != (void *)NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Wait for CRS Synchronization status. + * @param Timeout Duration of the timeout + * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization + * frequency. + * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. + * @retval Combination of Synchronization status + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_TIMEOUT + * @arg @ref RCC_CRS_SYNCOK + * @arg @ref RCC_CRS_SYNCWARN + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + */ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or timeout detection */ + do + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } + while (RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) + { + if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) + { + crserror |= RCC_CRS_SYNCERR; + } + if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) + { + crserror |= RCC_CRS_SYNCMISS; + } + if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + +/** + * @} + */ + +#endif /* CRS */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim.c (revision 3) @@ -0,0 +1,7719 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_TIM_RegisterCallback() to register a callback. + @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup TIM_Private_Constants + * @{ + */ +#define TIMx_OR1_OCREF_CLR 0x00000001U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + break; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + break; + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_ALL: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + default: + break; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + { + if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; + } + + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; + } + + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + default: + break; + } + + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR1 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR1 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + break; + } + + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR1 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR1 + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_TISEL + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + break; + } + + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + break; + } + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + + /* Clear TIMx_OR1_OCREF_CLR (reset value) */ + CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR); + break; + } +#if defined(COMP1) || defined(COMP2) || defined(COMP3) +#if defined(COMP1) && defined(COMP2) + case TIM_CLEARINPUTSOURCE_COMP1: + case TIM_CLEARINPUTSOURCE_COMP2: +#endif /* COMP1 && COMP2 */ +#if defined(COMP3) + case TIM_CLEARINPUTSOURCE_COMP3: +#endif /* COMP3 */ + { + /* Clear the OCREF clear selection bit */ + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + + /* OCREF_CLR_INT is connected to COMPx output */ + MODIFY_REG(htim->Instance->OR1, TIMx_OR1_OCREF_CLR, sClearInputConfig->ClearInputSource); + break; + } +#endif /* COMP1 || COMP2 || COMP3 */ + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + + /* Clear TIMx_OR1_OCREF_CLR (reset value) */ + CLEAR_BIT(htim->Instance->OR1, TIMx_OR1_OCREF_CLR); + break; + } + + default: + break; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } + default: + break; + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htim); + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 5 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 6 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + break; + } + return HAL_OK; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */ +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_tim_ex.c (revision 3) @@ -0,0 +1,2800 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + * + Time OCRef clear configuration + * + Timer remapping capabilities configuration + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants + * @{ + */ +/* Timeout for break input rearm */ +#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. + (+) Start the Complementary Input Capture measurement. + (+) Stop the Complementary Input Capture. + (+) Start the Complementary Input Capture and enable interrupts. + (+) Stop the Complementary Input Capture and disable interrupts. + (+) Start the Complementary Input Capture and enable DMA transfers. + (+) Stop the Complementary Input Capture and disable DMA transfers. + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + break; + } + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + break; + } + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); + HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @param htim TIM One Pulse handle + * @param OutputChannel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + (+) Select timer input source. + (+) Enable or disable channel grouping. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); + + /* Set BREAK AF mode */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); + } + + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + + if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); + + /* Set BREAK2 AF mode */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); + } + } + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the break input source. + * @param htim TIM handle. + * @param BreakInput Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) + +{ + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); + + /* Check input state */ + __HAL_LOCK(htim); + + switch (sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; + bkin_polarity_mask = TIM1_AF1_BKINP; + bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; + break; + } +#if defined(COMP1) && defined(COMP2) + case TIM_BREAKINPUTSOURCE_COMP1: + { + bkin_enable_mask = TIM1_AF1_BKCMP1E; + bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP1P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP2: + { + bkin_enable_mask = TIM1_AF1_BKCMP2E; + bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP2P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; + break; + } +#endif /* COMP1 && COMP2 */ +#if defined(COMP3) + case TIM_BREAKINPUTSOURCE_COMP3: + { + bkin_enable_mask = TIM1_AF1_BKCMP3E; + bkin_enable_bitpos = TIM1_AF1_BKCMP3E_Pos; + bkin_polarity_mask = TIM1_AF1_BKCMP3P; + bkin_polarity_bitpos = TIM1_AF1_BKCMP3P_Pos; + break; + } +#endif /* COMP3 */ + + default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; + break; + } + } + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + break; + } + default: + break; + } + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * For TIM1, the parameter can take one of the following values: + * @arg TIM_TIM1_ETR_GPIO: TIM1 ETR is is connected to GPIO + * @arg TIM_TIM1_ETR_COMP1: TIM1 ETR is connected to COMP1 output + * @arg TIM_TIM1_ETR_COMP2: TIM1 ETR is connected to COMP2 output + * @arg TIM_TIM1_ETR_COMP3: TIM1 ETR is connected to COMP3 output (**) + * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1 ETR is connected to ADC1 AWD1 + * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1 ETR is connected to ADC1 AWD2 + * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1 ETR is connected to ADC1 AWD3 + * + * For TIM2, the parameter can take one of the following values: (*) + * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to GPIO + * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output + * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output + * @arg TIM_TIM2_ETR_COMP3: TIM2_ETR is connected to COMP3 output (**) + * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE + * @arg TIM_TIM2_ETR_MCO: TIM2_ETR is connected to MCO (**) + * @arg TIM_TIM2_ETR_MCO2: TIM2_ETR is connected to MCO2 (**) + * + * For TIM3, the parameter can take one of the following values: + * @arg TIM_TIM3_ETR_GPIO TIM3_ETR is connected to GPIO + * @arg TIM_TIM3_ETR_COMP1 TIM3_ETR is connected to COMP1 output + * @arg TIM_TIM3_ETR_COMP2 TIM3_ETR is connected to COMP2 output + * @arg TIM_TIM3_ETR_COMP3 TIM3_ETR is connected to COMP3 output (**) + * + * For TIM4, the parameter can take one of the following values:(*) + * @arg TIM_TIM4_ETR_GPIO TIM4_ETR is connected to GPIO + * @arg TIM_TIM4_ETR_COMP1 TIM4_ETR is connected to COMP1 output + * @arg TIM_TIM4_ETR_COMP2 TIM4_ETR is connected to COMP2 output + * @arg TIM_TIM4_ETR_COMP3 TIM4_ETR is connected to COMP3 output (**) + * + * (*) Timer instance not available on all devices \n + * (**) Value not defined in all devices. \n + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + __HAL_LOCK(htim); + + MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Select the timer input source + * @param htim TIM handle. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TI1 input channel + * @arg TIM_CHANNEL_2: TI2 input channel + * @arg TIM_CHANNEL_3: TI3 input channel + * @param TISelection specifies the timer input source + * + * For TIM1 this parameter can be one of the following values: + * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO + * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output + * @arg TIM_TIM1_TI2_GPIO: TIM1 TI2 is connected to GPIO + * @arg TIM_TIM1_TI2_COMP2: TIM1 TI2 is connected to COMP2 output + * @arg TIM_TIM1_TI3_GPIO: TIM1 TI3 is connected to GPIO + * @arg TIM_TIM1_TI3_COMP3: TIM1 TI3 is connected to COMP3 output (**) + * + * For TIM2, the parameter is one of the following values: (*) + * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO + * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output + * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO + * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output + * @arg TIM_TIM2_TI3_GPIO: TIM2 TI3 is connected to GPIO + * @arg TIM_TIM2_TI3_COMP3: TIM2 TI3 is connected to COMP3 output (**) + * + * For TIM3, the parameter is one of the following values: + * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO + * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output + * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO + * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output + * @arg TIM_TIM3_TI3_GPIO: TIM3 TI3 is connected to GPIO + * @arg TIM_TIM3_TI3_COMP3: TIM3 TI3 is connected to COMP3 output (**) + * + * For TIM4, the parameter is one of the following values: (*) + * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO + * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output + * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO + * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output + * @arg TIM_TIM4_TI3_GPIO: TIM4 TI3 is connected to GPIO + * @arg TIM_TIM4_TI3_COMP3: TIM4 TI3 is connected to COMP3 output + * + * For TIM14, the parameter is one of the following values: + * @arg TIM_TIM14_TI1_GPIO: TIM14 TI1 is connected to GPIO + * @arg TIM_TIM14_TI1_RTC: TIM14 TI1 is connected to RTC clock + * @arg TIM_TIM14_TI1_HSE_32: TIM14 TI1 is connected to HSE div 32 + * @arg TIM_TIM14_TI1_MCO: TIM14 TI1 is connected to MCO + * @arg TIM_TIM14_TI1_MCO2: TIM14 TI1 is connected to MCO2 (**) + * + * For TIM15, the parameter is one of the following values: + * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO + * @arg TIM_TIM15_TI1_TIM2_CH1: TIM15 TI1 is connected to TIM2 CH1 + * @arg TIM_TIM15_TI1_TIM3_CH1: TIM15 TI1 is connected to TIM3 CH1 + * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO + * @arg TIM_TIM15_TI2_TIM2_CH2: TIM15 TI2 is connected to TIM2 CH2 + * @arg TIM_TIM15_TI2_TIM3_CH2: TIM15 TI2 is connected to TIM3 CH2 + * + * For TIM16, the parameter can have the following values: + * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO + * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI + * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE + * @arg TIM_TIM16_TI1_RTC_WAKEUP: TIM16 TI1 is connected to TRC wakeup interrupt + * @arg TIM_TIM16_TI1_MCO2: TIM16 TI1 is connected to MCO2 (**) + * + * For TIM17, the parameter can have the following values: + * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO + * @arg TIM_TIM14_TI1_HSI: TIM17 TI1 is connected to HSI (**) + * @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32 + * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO + * @arg TIM_TIM17_TI1_MCO2: TIM17 TI1 is connected to MCO2 (**) + * + * (*) Timer instance not available on all devices \n + * (**) Value not defined in all devices. \n + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TISEL(TISelection)); + + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); + break; + case TIM_CHANNEL_2: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); + break; + case TIM_CHANNEL_3: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI3SEL, TISelection); + break; + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(Channels)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= Channels; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Disarm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to disarm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + uint32_t tmpbdtr; + + /* Check the parameters */ + assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); + } + break; + } + default: + break; + } + + return HAL_OK; +} + +/** + * @brief Arm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to arm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note Arming is possible at anytime, even if fault is present. + * @note Break input is automatically armed as soon as MOE bit is set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) + { + /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + do + { + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != TIM_BDTR_BKDSRM) + { + return HAL_OK; + } + } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); + + return HAL_TIMEOUT; + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) + { + /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + do + { + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != TIM_BDTR_BK2DSRM) + { + return HAL_OK; + } + } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); + + return HAL_TIMEOUT; + } + break; + } + default: + break; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Hall commutation changed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Hall commutation changed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart.c (revision 3) @@ -0,0 +1,4624 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart handle AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + by calling the HAL_LIN_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function @ref HAL_UART_RegisterCallback() to register a user callback. + Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. + @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak (surcharged) functions: + examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() + and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() + or @ref HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (surcharged) callbacks are used. + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ + USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ + USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ + +#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ +#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + and UART multiprocessor mode configuration procedures (details for the procedures + are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + /* LIN mode limited to 8-bit data length */ + if (huart->Init.WordLength != UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief DeInitialize the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Initialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used instead of the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = pCallback; + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = pCallback; + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + __HAL_LOCK(huart); + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + return status; +} + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two mode of transfer: + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (+) HAL_UART_Transmit() + (+) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (+) HAL_UART_Transmit_IT() + (+) HAL_UART_Receive_IT() + (+) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (+) HAL_UART_Transmit_DMA() + (+) HAL_UART_Receive_DMA() + (+) HAL_UART_DMAPause() + (+) HAL_UART_DMAResume() + (+) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (+) HAL_UART_TxHalfCpltCallback() + (+) HAL_UART_TxCpltCallback() + (+) HAL_UART_RxHalfCpltCallback() + (+) HAL_UART_RxCpltCallback() + (+) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (+) HAL_UART_Abort() + (+) HAL_UART_AbortTransmit() + (+) HAL_UART_AbortReceive() + (+) HAL_UART_Abort_IT() + (+) HAL_UART_AbortTransmit_IT() + (+) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (+) HAL_UART_AbortCpltCallback() + (+) HAL_UART_AbortTransmitCpltCallback() + (+) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: + (+) HAL_UARTEx_RxEventCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be filled into TDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + huart->TxISR = NULL; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Configure Tx interrupt processing */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT_FIFOEN; + } + else + { + huart->TxISR = UART_TxISR_8BIT_FIFOEN; + } + + __HAL_UNLOCK(huart); + + /* Enable the TX FIFO threshold interrupt */ + SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + } + else + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + __HAL_UNLOCK(huart); + + /* Enable the Transmit Data Register Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using u16 pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data to be received from RDR will be + handled through a u16 cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return(UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) + * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data copy into TDR will be + handled by DMA from a u16 frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + + __HAL_UNLOCK(huart); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier + * (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required + * to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, as data copy from RDR will be + handled by DMA from a u16 frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return(UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + __HAL_LOCK(huart); + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + /* Disable the UART DMA Tx request */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; + + /* Disable interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + &&((isrflags & USART_ISR_IDLE) != 0U) + &&((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ( (nb_remaining_rx_data > 0U) + &&(nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif + } + return; + } + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ( (huart->RxXferCount > 0U) + &&(nb_rx_data > 0U) ) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif + } + return; + } + } + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_UARTEx_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_UARTEx_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters +@endverbatim + * @{ + */ + +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + } +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart UART handle. + * @retval None + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart UART handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + + +/** + * @brief Transmit break characters. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +{ + uint32_t temp1; + uint32_t temp2; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t lpuart_ker_ck_pres; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + if (UART_INSTANCE_LOWPOWER(huart)) + { + assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); + } + else + { + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + } + + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + tmpreg |= (uint32_t)huart->FifoMode; + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + + if (!(UART_INSTANCE_LOWPOWER(huart))) + { + tmpreg |= huart->Init.OneBitSampling; + } + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + + /* Check LPUART instance */ + if (UART_INSTANCE_LOWPOWER(huart)) + { + /* Retrieve frequency clock */ + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + /* If proper clock source reported */ + if (pclk != 0U) + { + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + { + ret = HAL_ERROR; + } + else + { + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ + } + /* Check UART Over Sampling to set Baud Rate Register */ + else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + { + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + } + } + else + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + if (pclk != 0U) + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } + } + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + huart->NbRxDataToProcess = 1; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + return ret; +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Handle UART Communication Timeout. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, TXFT interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; +} + + +/** + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + { + huart->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + { + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize/2U); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + huart->TxXferCount = 0U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + huart->RxXferCount = 0U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->TxXferCount = 0U; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + tmp = (uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_uart_ex.c (revision 3) @@ -0,0 +1,1059 @@ +/** + ****************************************************************************** + * @file stm32g0xx_hal_uart_ex.c + * @author MCD Application Team + * @brief Extended UART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + @verbatim + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When UART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_hal.h" + +/** @addtogroup STM32G0xx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UARTEX_Private_Constants UARTEx Private Constants + * @{ + */ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + procedures (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of Wakeup and FIFO mode related callback functions. + + (#) Wakeup from Stop mode Callback: + (+) HAL_UARTEx_WakeupCallback() + + (#) TX/RX Fifos Callbacks: + (+) HAL_UARTEx_RxFifoFullCallback() + (+) HAL_UARTEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +/** + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + +/** + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. + (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + trigger: address match, Start Bit detection or RXNE bit status. + (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UARTEx_DisableStopMode() API disables the above functionality + (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (+) Detection of inactivity period (RX line has not been active for a given period). + (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (+) Detection that a specific character has been received. + + (#) There are two mode of transfer: + (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (+) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (+) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (+) HAL_UARTEx_ReceiveToIdle_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UESM bit */ + SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UESM bit */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_ENABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_DISABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param huart UART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_TXFIFO_THRESHOLD_1_8 + * @arg @ref UART_TXFIFO_THRESHOLD_1_4 + * @arg @ref UART_TXFIFO_THRESHOLD_1_2 + * @arg @ref UART_TXFIFO_THRESHOLD_3_4 + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param huart UART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_RXFIFO_THRESHOLD_1_8 + * @arg @ref UART_RXFIFO_THRESHOLD_1_4 + * @arg @ref UART_RXFIFO_THRESHOLD_1_2 + * @arg @ref UART_RXFIFO_THRESHOLD_3_4 + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data to be received from RDR will be + handled through a uint16_t cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data to be received from RDR will be + handled through a uint16_t cast. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + status = UART_Start_Receive_IT(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) + * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, + * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a uint16_t frontier, as data copy from RDR will be + handled by DMA from a uint16_t frontier. */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + if ((((uint32_t)pData) & 1U) != 0U) + { + return HAL_ERROR; + } + } + + __HAL_LOCK(huart); + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ + +/** + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + { + huart->NbTxDataToProcess = 1U; + huart->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_adc.c (revision 3) @@ -0,0 +1,787 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_adc.c + * @author MCD Application Team + * @brief ADC LL module driver + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_ll_adc.h" +#include "stm32g0xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined (ADC1) + +/** @addtogroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup ADC_LL_Private_Constants + * @{ + */ + +/* Definitions of ADC hardware constraints delays */ +/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ +/* not timeout values: */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ +/* values definition. */ +/* Note: ADC timeout values are defined here in CPU cycles to be independent */ +/* of device clock setting. */ +/* In user application, ADC timeout values should be defined with */ +/* temporal values, in function of device clock settings. */ +/* Highest ratio CPU clock frequency vs ADC clock frequency: */ +/* - ADC clock from synchronous clock with AHB prescaler 512, */ +/* APB prescaler 16, ADC prescaler 4. */ +/* - ADC clock from asynchronous clock (HSI) with prescaler 1, */ +/* with highest ratio CPU clock frequency vs HSI clock frequency: */ +/* CPU clock frequency max 56MHz, HSI frequency 16MHz: ratio 4. */ +/* Unit: CPU cycles. */ +#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL) +#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) +#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) +/* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */ +/* after the channel configuration has been changed. */ +/* Driver timeout is approximated to 6 CPU cycles. */ +#define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup ADC_LL_Private_Macros + * @{ + */ + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* common to several ADC instances. */ +#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ + (((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ + ) + +#define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__) \ + (((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH) \ + || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC instance. */ +#define IS_LL_ADC_CLOCK(__CLOCK__) \ + (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \ + ) + +#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ + (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ + ) + +#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ + (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ + || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ + ) + +#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ + (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ + || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ + || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \ + || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC group regular */ +#if defined(TIM15) && defined(TIM6) && defined(TIM2) +#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + ) +#elif defined(TIM15) && defined(TIM6) +#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + ) +#elif defined(TIM2) +#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + ) +#else +#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + ) +#endif + +#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ + (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ + || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ + ) + +#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ + (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ + ) + +#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ + (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ + || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ + ) + +#define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \ + (((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \ + || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ + (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ + (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ + ) + +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize registers of all ADC instances belonging to + * the same ADC common instance to their default reset values. + * @note This function is performing a hard reset, using high level + * clock source RCC ADC reset. + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + + /* Force reset of ADC clock (core clock) */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC); + + /* Release reset of ADC clock (core clock) */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC); + + return SUCCESS; +} + +/** + * @brief Initialize some features of ADC common parameters + * (all ADC instances belonging to the same ADC common instance) + * and multimode (for devices with several ADC instances available). + * @note The setting of ADC common parameters is conditioned to + * ADC instances state: + * All ADC instances belonging to the same ADC common instance + * must be disabled. + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are initialized + * - ERROR: ADC common registers are not initialized + */ +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); + + /* Note: Hardware constraint (refer to description of functions */ + /* "LL_ADC_SetCommonXXX()": */ + /* On this STM32 series, setting of these features is conditioned to */ + /* ADC state: */ + /* All ADC instances of the ADC common group must be disabled. */ + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - common to several ADC */ + /* (all ADC instances belonging to the same ADC common instance) */ + /* - Set ADC clock (conversion clock) */ + LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); + } + else + { + /* Initialization error: One or several ADC instances belonging to */ + /* the same ADC common instance are not disabled. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. + * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +{ + /* Set ADC_CommonInitStruct fields to default values */ + /* Set fields of ADC common */ + /* (all ADC instances belonging to the same ADC common instance) */ + ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; + +} + +/** + * @brief De-initialize registers of the selected ADC instance + * to their default reset values. + * @note To reset all ADC instances quickly (perform a hard reset), + * use function @ref LL_ADC_CommonDeInit(). + * @note If this functions returns error status, it means that ADC instance + * is in an unknown state. + * In this case, perform a hard reset using high level + * clock source RCC ADC reset. + * Refer to function @ref LL_ADC_CommonDeInit(). + * @param ADCx ADC instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are de-initialized + * - ERROR: ADC registers are not de-initialized + */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) +{ + ErrorStatus status = SUCCESS; + + __IO uint32_t timeout_cpu_cycles = 0UL; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + /* Disable ADC instance if not already disabled. */ + if (LL_ADC_IsEnabled(ADCx) == 1UL) + { + /* Set ADC group regular trigger source to SW start to ensure to not */ + /* have an external trigger event occurring during the conversion stop */ + /* ADC disable process. */ + LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); + + /* Stop potential ADC conversion on going on ADC group regular. */ + if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) + { + if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) + { + LL_ADC_REG_StopConversion(ADCx); + } + } + + /* Wait for ADC conversions are effectively stopped */ + timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; + while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL) + { + timeout_cpu_cycles--; + if (timeout_cpu_cycles == 0UL) + { + /* Time-out error */ + status = ERROR; + break; + } + } + + /* Disable the ADC instance */ + LL_ADC_Disable(ADCx); + + /* Wait for ADC instance is effectively disabled */ + timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; + while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) + { + timeout_cpu_cycles--; + if (timeout_cpu_cycles == 0UL) + { + /* Time-out error */ + status = ERROR; + break; + } + } + } + + /* Check whether ADC state is compliant with expected state */ + if (READ_BIT(ADCx->CR, + (ADC_CR_ADSTP | ADC_CR_ADSTART + | ADC_CR_ADDIS | ADC_CR_ADEN) + ) + == 0UL) + { + /* ========== Reset ADC registers ========== */ + /* Reset register IER */ + CLEAR_BIT(ADCx->IER, + (LL_ADC_IT_ADRDY + | LL_ADC_IT_EOC + | LL_ADC_IT_EOS + | LL_ADC_IT_OVR + | LL_ADC_IT_EOSMP + | LL_ADC_IT_AWD1 + | LL_ADC_IT_AWD2 + | LL_ADC_IT_AWD3 + | LL_ADC_IT_EOCAL + | LL_ADC_IT_CCRDY + ) + ); + + /* Reset register ISR */ + SET_BIT(ADCx->ISR, + (LL_ADC_FLAG_ADRDY + | LL_ADC_FLAG_EOC + | LL_ADC_FLAG_EOS + | LL_ADC_FLAG_OVR + | LL_ADC_FLAG_EOSMP + | LL_ADC_FLAG_AWD1 + | LL_ADC_FLAG_AWD2 + | LL_ADC_FLAG_AWD3 + | LL_ADC_FLAG_EOCAL + | LL_ADC_FLAG_CCRDY + ) + ); + + /* Reset register CR */ + /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ + /* "read-set": no direct reset applicable. */ + CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN); + + /* Reset register CFGR1 */ + CLEAR_BIT(ADCx->CFGR1, + (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN + | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD + | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES + | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) + ); + + /* Reset register CFGR2 */ + /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ + /* already done above. */ + CLEAR_BIT(ADCx->CFGR2, + (ADC_CFGR2_CKMODE + | ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR + | ADC_CFGR2_OVSE) + ); + + /* Reset register SMPR */ + CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL); + + /* Reset register TR1 */ + MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1); + + /* Reset register TR2 */ + MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2); + + /* Reset register TR3 */ + MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3); + + /* Reset register CHSELR */ + CLEAR_BIT(ADCx->CHSELR, + (ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16 + | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 + | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 + | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 + | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0) + ); + + /* Wait for ADC channel configuration ready */ + timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES; + while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL) + { + timeout_cpu_cycles--; + if (timeout_cpu_cycles == 0UL) + { + /* Time-out error */ + status = ERROR; + break; + } + } + + /* Clear flag ADC channel configuration ready */ + LL_ADC_ClearFlag_CCRDY(ADCx); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable */ + + /* Reset register CALFACT */ + CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT); + + } + else + { + /* ADC instance is in an unknown state */ + /* Need to performing a hard reset of ADC instance, using high level */ + /* clock source RCC ADC reset. */ + /* Caution: On this STM32 series, if several ADC instances are available */ + /* on the selected device, RCC ADC reset will reset */ + /* all ADC instances belonging to the common ADC instance. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, some other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular sequencer: + * Depending on the sequencer mode (refer to + * function @ref LL_ADC_REG_SetSequencerConfigurable() ): + * - map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_REG_SetSequencerRanks(); + * - map channel on rank corresponding to channel number. + * Refer to function @ref LL_ADC_REG_SetSequencerChannels(); + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetSamplingTimeCommonChannels(); + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock)); + assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); + assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); + assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if (LL_ADC_IsEnabled(ADCx) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC instance */ + /* - Set ADC data resolution */ + /* - Set ADC conversion data alignment */ + /* - Set ADC low power mode */ + MODIFY_REG(ADCx->CFGR1, + ADC_CFGR1_RES + | ADC_CFGR1_ALIGN + | ADC_CFGR1_WAIT + | ADC_CFGR1_AUTOFF + , + ADC_InitStruct->Resolution + | ADC_InitStruct->DataAlignment + | ADC_InitStruct->LowPowerMode + ); + + MODIFY_REG(ADCx->CFGR2, + ADC_CFGR2_CKMODE + , + ADC_InitStruct->Clock + ); + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Set each @ref LL_ADC_InitTypeDef field to default value. + * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) +{ + /* Set ADC_InitStruct fields to default values */ + /* Set fields of ADC instance */ + ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; + ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; + ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; + ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; + +} + +/** + * @brief Initialize some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note Before using this function, ADC group regular sequencer + * must be configured: refer to function + * @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note After using this function, other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular sequencer: + * Depending on the sequencer mode (refer to + * function @ref LL_ADC_REG_SetSequencerConfigurable() ): + * - map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_REG_SetSequencerRanks(); + * - map channel on rank corresponding to channel number. + * Refer to function @ref LL_ADC_REG_SetSequencerChannels(); + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetSamplingTimeCommonChannels(); + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); + assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); + assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); + assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); + + if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED) + { + assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); + } + + if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED) + || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + ) + { + assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + + /* ADC group regular continuous mode and discontinuous mode */ + /* can not be enabled simultenaeously */ + assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); + } + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if (LL_ADC_IsEnabled(ADCx) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC group regular */ + /* - Set ADC group regular trigger source */ + /* - Set ADC group regular sequencer length */ + /* - Set ADC group regular sequencer discontinuous mode */ + /* - Set ADC group regular continuous mode */ + /* - Set ADC group regular conversion data transfer: no transfer or */ + /* transfer by DMA, and DMA requests mode */ + /* - Set ADC group regular overrun behavior */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ + /* setting of trigger source to SW start. */ + if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED) + || (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + ) + { + /* Case of sequencer mode fixed + or sequencer length >= 2 ranks with sequencer mode fully configurable: + discontinuous mode configured */ + MODIFY_REG(ADCx->CFGR1, + ADC_CFGR1_EXTSEL + | ADC_CFGR1_EXTEN + | ADC_CFGR1_DISCEN + | ADC_CFGR1_CONT + | ADC_CFGR1_DMAEN + | ADC_CFGR1_DMACFG + | ADC_CFGR1_OVRMOD + , + ADC_REG_InitStruct->TriggerSource + | ADC_REG_InitStruct->SequencerDiscont + | ADC_REG_InitStruct->ContinuousMode + | ADC_REG_InitStruct->DMATransfer + | ADC_REG_InitStruct->Overrun + ); + } + else + { + /* Case of sequencer mode fully configurable + and sequencer length 1 rank (sequencer disabled): + discontinuous mode discarded (fixed to disable) */ + MODIFY_REG(ADCx->CFGR1, + ADC_CFGR1_EXTSEL + | ADC_CFGR1_EXTEN + | ADC_CFGR1_DISCEN + | ADC_CFGR1_CONT + | ADC_CFGR1_DMAEN + | ADC_CFGR1_DMACFG + | ADC_CFGR1_OVRMOD + , + ADC_REG_InitStruct->TriggerSource + | LL_ADC_REG_SEQ_DISCONT_DISABLE + | ADC_REG_InitStruct->ContinuousMode + | ADC_REG_InitStruct->DMATransfer + | ADC_REG_InitStruct->Overrun + ); + } + + /* Set ADC group regular sequencer length */ + if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED) + { + LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); + } + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. + * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +{ + /* Set ADC_REG_InitStruct fields to default values */ + /* Set fields of ADC group regular */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ + /* setting of trigger source to SW start. */ + ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; + ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; + ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; + ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_dma.c (revision 3) @@ -0,0 +1,369 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_dma.c + * @author MCD Application Team + * @brief DMA LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_ll_dma.h" +#include "stm32g0xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup DMA_LL_Private_Macros + * @{ + */ +#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) + +#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ + ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) + +#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ + ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) + +#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ + ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) + +#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) + +#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) + +#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) + +#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_MAX_REQ) + +#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ + ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ + ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ + ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) + +#if defined(DMA2) +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ + (((INSTANCE) == DMA2) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5)))) +#else /* DMA1 */ +#if defined(DMA1_Channel7) +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7)))) +#else +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5)))) +#endif +#endif /* DMA2 */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the DMA registers to their default reset values. + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_ALL + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are de-initialized + * - ERROR: DMA registers are not de-initialized + */ +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) +{ + ErrorStatus status = SUCCESS; + + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL)); + + if (Channel == LL_DMA_CHANNEL_ALL) + { + if (DMAx == DMA1) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); + } +#if defined(DMA2) + else if (DMAx == DMA2) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); + } +#endif + else + { + status = ERROR; + } + } + else + { + DMA_Channel_TypeDef *tmp; + + tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Disable the selected DMAx_Channely */ + CLEAR_BIT(tmp->CCR, DMA_CCR_EN); + + /* Reset DMAx_Channely control register */ + WRITE_REG(tmp->CCR, 0U); + + /* Reset DMAx_Channely remaining bytes register */ + WRITE_REG(tmp->CNDTR, 0U); + + /* Reset DMAx_Channely peripheral address register */ + WRITE_REG(tmp->CPAR, 0U); + + /* Reset DMAx_Channely memory address register */ + WRITE_REG(tmp->CMAR, 0U); + + /* Reset Request register field for DMAx Channel */ + LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM); + + if (Channel == LL_DMA_CHANNEL_1) + { + /* Reset interrupt pending bits for DMAx Channel1 */ + LL_DMA_ClearFlag_GI1(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_2) + { + /* Reset interrupt pending bits for DMAx Channel2 */ + LL_DMA_ClearFlag_GI2(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_3) + { + /* Reset interrupt pending bits for DMAx Channel3 */ + LL_DMA_ClearFlag_GI3(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_4) + { + /* Reset interrupt pending bits for DMAx Channel4 */ + LL_DMA_ClearFlag_GI4(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_5) + { + /* Reset interrupt pending bits for DMAx Channel5 */ + LL_DMA_ClearFlag_GI5(DMAx); + } +#if defined(DMA1_Channel6) + else if (Channel == LL_DMA_CHANNEL_6) + { + /* Reset interrupt pending bits for DMAx Channel6 */ + LL_DMA_ClearFlag_GI6(DMAx); + } +#endif +#if defined(DMA1_Channel7) + else if (Channel == LL_DMA_CHANNEL_7) + { + /* Reset interrupt pending bits for DMAx Channel7 */ + LL_DMA_ClearFlag_GI7(DMAx); + } +#endif + else + { + status = ERROR; + } + } + + return status; +} + +/** + * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : + * @arg @ref __LL_DMA_GET_INSTANCE + * @arg @ref __LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are initialized + * - ERROR: Not applicable + */ +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Check the DMA parameters from DMA_InitStruct */ + assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); + assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); + assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); + assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); + assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); + assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); + assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); + assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest)); + assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); + + /*---------------------------- DMAx CCR Configuration ------------------------ + * Configure DMAx_Channely: data transfer direction, data transfer mode, + * peripheral and memory increment mode, + * data size alignment and priority level with parameters : + * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits + * - Mode: DMA_CCR_CIRC bit + * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit + * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit + * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits + * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits + * - Priority: DMA_CCR_PL[1:0] bits + */ + LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ + DMA_InitStruct->Mode | \ + DMA_InitStruct->PeriphOrM2MSrcIncMode | \ + DMA_InitStruct->MemoryOrM2MDstIncMode | \ + DMA_InitStruct->PeriphOrM2MSrcDataSize | \ + DMA_InitStruct->MemoryOrM2MDstDataSize | \ + DMA_InitStruct->Priority); + + /*-------------------------- DMAx CMAR Configuration ------------------------- + * Configure the memory or destination base address with parameter : + * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits + */ + LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); + + /*-------------------------- DMAx CPAR Configuration ------------------------- + * Configure the peripheral or source base address with parameter : + * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits + */ + LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); + + /*--------------------------- DMAx CNDTR Configuration ----------------------- + * Configure the peripheral base address with parameter : + * - NbData: DMA_CNDTR_NDT[15:0] bits + */ + LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); + + /*--------------------------- DMAMUXx CCR Configuration ---------------------- + * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter : + * - PeriphRequest: DMA_CxCR[7:0] bits + */ + LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_DMA_InitTypeDef field to default value. + * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval None + */ +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Set DMA_InitStruct fields to default values */ + DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; + DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; + DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; + DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + DMA_InitStruct->NbData = 0x00000000U; + DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQ_MEM2MEM; + DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c =================================================================== --- ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c (revision 3) +++ ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Src/stm32g0xx_ll_rcc.c (revision 3) @@ -0,0 +1,1349 @@ +/** + ****************************************************************************** + * @file stm32g0xx_ll_rcc.c + * @author MCD Application Team + * @brief RCC LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g0xx_ll_rcc.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ +/** @addtogroup STM32G0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @addtogroup RCC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Macros + * @{ + */ +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) +#elif defined(STM32G081xx) || defined(STM32G071xx) || defined(STM32G070xx) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) +#else +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART1_CLKSOURCE) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(LPUART1) && defined(LPUART2) +#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_LPUART2_CLKSOURCE)) +#elif defined(LPUART1) +#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) +#endif /* LPUART1 && LPUART2 */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE)) +#else +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(LPTIM1) || defined(LPTIM2) +#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE)) +#endif /* LPTIM1 || LPTIM2 */ + +#if defined(RNG) +#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) +#endif /* RNG */ + +#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE)) + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE)) +#else +#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE)) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(CEC) +#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) +#endif /* CEC */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(FDCAN1) || defined(FDCAN2) +#define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE)) +#endif /* FDCAN1 || FDCAN2 */ + +#if defined(RCC_CCIPR_TIM1SEL) && defined(RCC_CCIPR_TIM15SEL) +#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_TIM15_CLKSOURCE)) +#elif defined(RCC_CCIPR_TIM1SEL) +#define IS_LL_RCC_TIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_TIM1_CLKSOURCE)) +#endif /* RCC_CCIPR_TIM1SEL */ + + + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_LL_Private_Functions RCC Private functions + * @{ + */ +uint32_t RCC_GetSystemClockFreq(void); +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_PLL_GetFreqDomain_SYS(void); +uint32_t RCC_PLL_GetFreqDomain_ADC(void); +uint32_t RCC_PLL_GetFreqDomain_I2S1(void); +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +uint32_t RCC_PLL_GetFreqDomain_I2S2(void); +uint32_t RCC_PLL_GetFreqDomain_USB(void); +uint32_t RCC_PLL_GetFreqDomain_FDCAN(void); +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ +uint32_t RCC_PLL_GetFreqDomain_RNG(void); +uint32_t RCC_PLL_GetFreqDomain_TIM1(void); +uint32_t RCC_PLL_GetFreqDomain_TIM15(void); +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_LL_EF_Init + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB and APB1 prescaler set to 1. + * - CSS, MCO OFF + * - All interrupts disabled + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RCC registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RCC_DeInit(void) +{ + /* Set HSION bit and wait for HSI READY bit */ + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + {} + + /* Set HSITRIM bits to reset value*/ + LL_RCC_HSI_SetCalibTrimming(0x40U); + + /* Reset CFGR register */ + LL_RCC_WriteReg(CFGR, 0x00000000U); + + /* Reset whole CR register but HSI in 2 steps in case HSEBYP is set */ + LL_RCC_WriteReg(CR, RCC_CR_HSION); + while (LL_RCC_HSE_IsReady() != 0U) + {} + LL_RCC_WriteReg(CR, RCC_CR_HSION); + + /* Wait for PLL READY bit to be reset */ + while (LL_RCC_PLL_IsReady() != 0U) + {} + + /* Reset PLLCFGR register */ + LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos); + + /* Disable all interrupts */ + LL_RCC_WriteReg(CIER, 0x00000000U); + + /* Clear all interrupts flags */ + LL_RCC_WriteReg(CICR, 0xFFFFFFFFU); + + return SUCCESS; +} + +/** + * @} + */ + +/** @addtogroup RCC_LL_EF_Get_Freq + * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + * and different peripheral clocks available on the device. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE divided by HSI division factor(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) + * or HSI_VALUE(**) multiplied/divided by the PLL factors. + * @note (**) HSI_VALUE is a constant defined in this file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in this file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * @note The result of this function could be incorrect when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * @{ + */ + +/** + * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function + * must be called to update structure fields. Otherwise, any + * configuration based on this function will be incorrect. + * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies + * @retval None + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) +{ + /* Get SYSCLK frequency */ + RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); +} + +/** + * @brief Return USARTx clock frequency + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART3_CLKSOURCE + * @retval USART clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) +{ + uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); + + if (USARTxSource == LL_RCC_USART1_CLKSOURCE) + { + /* USART1CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#if defined(RCC_CCIPR_USART2SEL) + else if (USARTxSource == LL_RCC_USART2_CLKSOURCE) + { + /* USART2CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CCIPR_USART2SEL */ +#if defined(RCC_CCIPR_USART3SEL) + else if (USARTxSource == LL_RCC_USART3_CLKSOURCE) + { + /* USART3CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CCIPR_USART3SEL */ + else + { + /* nothing to do */ + } + return usart_frequency; +} + +/** + * @brief Return I2Cx clock frequency + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @retval I2C clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready + */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) +{ + uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + + if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) + { + /* I2C1 CLK clock frequency */ + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + i2c_frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ + default: + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#if defined(RCC_CCIPR_I2C2SEL) + else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE) + { + /* I2C2 CLK clock frequency */ + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + i2c_frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */ + default: + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CCIPR_I2C2SEL */ + else + { + } + + return i2c_frequency; +} + +/** + * @brief Return I2Sx clock frequency + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE + * @retval I2S clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready + */ +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) +{ + uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); + + if (I2SxSource == LL_RCC_I2S1_CLKSOURCE) + { + /* I2S1 CLK clock frequency */ + switch (LL_RCC_GetI2SClockSource(I2SxSource)) + { + case LL_RCC_I2S1_CLKSOURCE_HSI: /* I2S1 Clock is HSI */ + i2s_frequency = HSI_VALUE; + break; + + case LL_RCC_I2S1_CLKSOURCE_PLL: /* I2S1 Clock is PLL"P" */ + if (LL_RCC_PLL_IsReady() == 1U) + { + i2s_frequency = RCC_PLL_GetFreqDomain_I2S1(); + } + break; + + + case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */ + i2s_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_I2S1_CLKSOURCE_SYSCLK: /* I2S1 Clock is System Clock */ + default: + i2s_frequency = RCC_GetSystemClockFreq(); + break; + } + } +#if defined(RCC_CCIPR2_I2S2SEL) + else if (I2SxSource == LL_RCC_I2S2_CLKSOURCE) + { + /* I2S2 CLK clock frequency */ + switch (LL_RCC_GetI2SClockSource(I2SxSource)) + { + case LL_RCC_I2S2_CLKSOURCE_HSI: /* I2S2 Clock is HSI */ + i2s_frequency = HSI_VALUE; + break; + + case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL"P" */ + if (LL_RCC_PLL_IsReady() == 1U) + { + i2s_frequency = RCC_PLL_GetFreqDomain_I2S2(); + } + break; + + case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */ + i2s_frequency = EXTERNAL_CLOCK_VALUE; + break; + + case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /* I2S2 Clock is System Clock */ + default: + i2s_frequency = RCC_GetSystemClockFreq(); + break; + } + } +#endif /* RCC_CCIPR2_I2S2SEL */ + else + { + } + return i2s_frequency; +} + +#if defined(LPUART1) || defined(LPUART2) +/** + * @brief Return LPUARTx clock frequency + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @arg @ref LL_RCC_LPUART2_CLKSOURCE (*) + * @retval LPUART clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + * (*) feature not available on all devices + */ +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) +{ + uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource)); + + if (LPUARTxSource == LL_RCC_LPUART1_CLKSOURCE) + { + /* LPUART1CLK clock frequency */ + switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) + { + case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ + lpuart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + lpuart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + lpuart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */ + default: + lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#if defined(LPUART2) + else if (LPUARTxSource == LL_RCC_LPUART2_CLKSOURCE) + { + /* LPUART2CLK clock frequency */ + switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) + { + case LL_RCC_LPUART2_CLKSOURCE_SYSCLK: /* LPUART2 Clock is System Clock */ + lpuart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_LPUART2_CLKSOURCE_HSI: /* LPUART2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + lpuart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPUART2_CLKSOURCE_LSE: /* LPUART2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + lpuart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPUART2_CLKSOURCE_PCLK1: /* LPUART2 Clock is PCLK1 */ + default: + lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* LPUART2 */ + else + { + } + + return lpuart_frequency; +} +#endif /* LPUART1 */ + +#if defined(LPTIM1) && defined(LPTIM2) +/** + * @brief Return LPTIMx clock frequency + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @retval LPTIM clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready + */ +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) +{ + uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); + + if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) + { + /* LPTIM1CLK clock frequency */ + switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + { + case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ + if (LL_RCC_LSI_IsReady() == 1U) + { + lptim_frequency = LSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + lptim_frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + lptim_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ + default: + lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + else + { + /* LPTIM2CLK clock frequency */ + switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + { + case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */ + if (LL_RCC_LSI_IsReady() == 1U) + { + lptim_frequency = LSI_VALUE; + } + break; + + case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() == 1U) + { + lptim_frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + lptim_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */ + default: + lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + + return lptim_frequency; +} +#endif /* LPTIM1 && LPTIM2 */ + +#if defined(RCC_CCIPR_TIM1SEL) || defined(RCC_CCIPR_TIM15SEL) +/** + * @brief Return TIMx clock frequency + * @param TIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM1_CLKSOURCE + * @if defined(STM32G081xx) + * @arg @ref LL_RCC_TIM15_CLKSOURCE + * @endif + * @retval TIMx clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource) +{ + uint32_t tim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_TIM_CLKSOURCE(TIMxSource)); + + if (TIMxSource == LL_RCC_TIM1_CLKSOURCE) + { + /* TIM1CLK clock frequency */ + switch (LL_RCC_GetTIMClockSource(TIMxSource)) + { + case LL_RCC_TIM1_CLKSOURCE_PLL: /* TIM1 Clock is PLLQ */ + if (LL_RCC_PLL_IsReady() == 1U) + { + tim_frequency = RCC_PLL_GetFreqDomain_TIM1(); + } + break; + + case LL_RCC_TIM1_CLKSOURCE_PCLK1: /* TIM1 Clock is PCLK1 */ + default: + tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#if defined(TIM15) + else + { + if (TIMxSource == LL_RCC_TIM15_CLKSOURCE) + { + /* TIM15CLK clock frequency */ + switch (LL_RCC_GetTIMClockSource(TIMxSource)) + { + case LL_RCC_TIM15_CLKSOURCE_PLL: /* TIM1 Clock is PLLQ */ + if (LL_RCC_PLL_IsReady() == 1U) + { + tim_frequency = RCC_PLL_GetFreqDomain_TIM15(); + } + break; + + case LL_RCC_TIM15_CLKSOURCE_PCLK1: /* TIM15 Clock is PCLK1 */ + default: + tim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + } +#endif /* TIM15 */ + return tim_frequency; +} +#endif /* RCC_CCIPR_TIM1SEL && RCC_CCIPR_TIM15SEL */ + + +#if defined(RNG) +/** + * @brief Return RNGx clock frequency + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval RNG clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLL is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) +{ + uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + uint32_t rngdiv; + + /* Check parameter */ + assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource)); + + /* RNGCLK clock frequency */ + switch (LL_RCC_GetRNGClockSource(RNGxSource)) + { + case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */ + if (LL_RCC_PLL_IsReady() == 1U) + { + rng_frequency = RCC_PLL_GetFreqDomain_RNG(); + rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos)); + rng_frequency = (rng_frequency / rngdiv); + } + break; + + case LL_RCC_RNG_CLKSOURCE_HSI_DIV8: /* HSI clock divided by 8 used as RNG clock source */ + rng_frequency = HSI_VALUE / 8U; + rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos)); + rng_frequency = (rng_frequency / rngdiv); + break; + case LL_RCC_RNG_CLKSOURCE_SYSCLK: /* SYSCLK clock used as RNG clock source */ + rng_frequency = RCC_GetSystemClockFreq(); + rngdiv = (1UL << ((READ_BIT(RCC->CCIPR, RCC_CCIPR_RNGDIV)) >> RCC_CCIPR_RNGDIV_Pos)); + rng_frequency = (rng_frequency / rngdiv); + break; + + case LL_RCC_RNG_CLKSOURCE_NONE: /* No clock used as RNG clock source */ + default: + rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + + } + + return rng_frequency; +} +#endif /* RNG */ + +#if defined(CEC) +/** + * @brief Return CEC clock frequency + * @param CECxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval CEC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) +{ + uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); + + /* CECCLK clock frequency */ + switch (LL_RCC_GetCECClockSource(CECxSource)) + { + case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + cec_frequency = LSE_VALUE; + } + break; + + case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */ + default: + if (LL_RCC_HSI_IsReady() == 1U) + { + cec_frequency = (HSI_VALUE / 488U); + } + break; + } + + return cec_frequency; +} +#endif /* CEC */ + +#if defined(FDCAN1) || defined(FDCAN2) +/** + * @brief Return FDCANx clock frequency + * @param FDCANxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_FDCAN_CLKSOURCE + * @retval FDCANx clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready + */ +uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource) +{ + uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource)); + + /* FDCANCLK clock frequency */ + switch (LL_RCC_GetFDCANClockSource(FDCANxSource)) + { + case LL_RCC_FDCAN_CLKSOURCE_PLL: /* FDCAN Clock is PLL "Q" Osc. */ + if (LL_RCC_PLL_IsReady() == 1U) + { + fdcan_frequency = RCC_PLL_GetFreqDomain_FDCAN(); + } + break; + + case LL_RCC_FDCAN_CLKSOURCE_HSE: /* FDCAN Clock is HSE Osc. */ + if (LL_RCC_HSE_IsReady() == 1U) + { + fdcan_frequency = HSE_VALUE; + } + break; + + case LL_RCC_FDCAN_CLKSOURCE_PCLK1: /* FDCAN Clock is PCLK1 */ + default: + fdcan_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + + return fdcan_frequency; +} +#endif /* FDCAN1 || FDCAN2 */ + +/** + * @brief Return ADCx clock frequency + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval ADC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLL is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) +{ + uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource)); + + /* ADCCLK clock frequency */ + switch (LL_RCC_GetADCClockSource(ADCxSource)) + { + case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ + adc_frequency = RCC_GetSystemClockFreq(); + break; + case LL_RCC_ADC_CLKSOURCE_HSI : /* HSI clock used as ADC clock source */ + adc_frequency = HSI_VALUE; + break; + + case LL_RCC_ADC_CLKSOURCE_PLL: /* PLLP clock used as ADC clock source */ + if (LL_RCC_PLL_IsReady() == 1U) + { + adc_frequency = RCC_PLL_GetFreqDomain_ADC(); + } + break; + default: + adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + + return adc_frequency; +} + +/** + * @brief Return RTC clock frequency + * @retval RTC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetRTCClockFreq(void) +{ + uint32_t rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* RTCCLK clock frequency */ + switch (LL_RCC_GetRTCClockSource()) + { + case LL_RCC_RTC_CLKSOURCE_LSE: /* LSE clock used as RTC clock source */ + if (LL_RCC_LSE_IsReady() == 1U) + { + rtc_frequency = LSE_VALUE; + } + break; + + case LL_RCC_RTC_CLKSOURCE_LSI: /* LSI clock used as RTC clock source */ + if (LL_RCC_LSI_IsReady() == 1U) + { + rtc_frequency = LSI_VALUE; + } + break; + + case LL_RCC_RTC_CLKSOURCE_HSE_DIV32: /* HSE clock used as ADC clock source */ + rtc_frequency = HSE_VALUE / 32U; + break; + + case LL_RCC_RTC_CLKSOURCE_NONE: /* No clock used as RTC clock source */ + default: + rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + + return rtc_frequency; +} + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Return USBx clock frequency + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval USB clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) +{ + uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); + + /* USBCLK clock frequency */ + switch (LL_RCC_GetUSBClockSource(USBxSource)) + { +#if defined(RCC_HSI48_SUPPORT) + case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 used as USB clock source */ + if (LL_RCC_HSI48_IsReady() != 0U) + { + usb_frequency = HSI48_VALUE; + } + break; +#endif /* RCC_HSI48_SUPPORT */ + + case LL_RCC_USB_CLKSOURCE_HSE: /* HSE used as USB clock source */ + if (LL_RCC_HSE_IsReady() != 0U) + { + usb_frequency = HSE_VALUE; + } + break; + + case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + if (LL_RCC_PLL_IsReady() != 0U) + { + usb_frequency = RCC_PLL_GetFreqDomain_USB(); + } + break; + + default: + usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + + return usb_frequency; +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx) */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_LL_Private_Functions + * @{ + */ + +/** + * @brief Return SYSTEM clock frequency + * @retval SYSTEM clock frequency (in Hz) + */ +uint32_t RCC_GetSystemClockFreq(void) +{ + uint32_t frequency; + uint32_t hsidiv; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ + frequency = RCC_PLL_GetFreqDomain_SYS(); + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + default: + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); + frequency = (HSI_VALUE / hsidiv); + break; + } + + return frequency; +} + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} +/** + * @brief Return PLL clock frequency used for system domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_SYS(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); +} +/** + * @brief Return PLL clock frequency used for ADC domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_ADC(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + ADC Domain clock = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); +} + +#if defined(FDCAN1) || defined(FDCAN2) +/** + * @brief Return PLL clock frequency used for FDCAN domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_FDCAN(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN + + FDCAN Domain clock = PLL_VCO / PLLQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_FDCAN_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +} +#endif /* FDCAN1 || FDCAN2 */ + +/** + * @brief Return PLL clock frequency used for I2S1 domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_I2S1(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + I2S1 Domain clock = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_I2S1_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); +} + +#if defined(RCC_CCIPR2_I2S2SEL) +/** + * @brief Return PLL clock frequency used for I2S2 domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_I2S2(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + I2S2 Domain clock = PLL_VCO / PLLP + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_I2S2_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); +} +#endif /* RCC_CCIPR2_I2S2SEL */ + +#if defined(RNG) +/** + * @brief Return PLL clock frequency used for RNG domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_RNG(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN + + RNG Domain clock = PLL_VCO / PLLQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_RNG_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +} +#endif /* RNG */ + +#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx) +/** + * @brief Return PLL clock frequency used for USB domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_USB(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN + + RNG Domain clock = PLL_VCO / PLLQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_USB_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +} +#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */ + +#if defined(RCC_PLLQ_SUPPORT) +/** + * @brief Return PLL clock frequency used for TIM1 domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_TIM1(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN + + TIM1 Domain clock = PLL_VCO / PLLQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_TIM1_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +} +#endif /* RCC_PLLQ_SUPPORT */ + +#if defined(RCC_PLLQ_SUPPORT) && defined(TIM15) +/** + * @brief Return PLL clock frequency used for TIM15 domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_TIM15(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN + + TIM15 Domain clock = PLL_VCO / PLLQ + */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_TIM15_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); +} +#endif /* RCC_PLLQ_SUPPORT && TIM15 */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/Output/Debug/Exe/cellMon.ind =================================================================== --- ecs_cellMon/firmware/Output/Debug/Exe/cellMon.ind (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Exe/cellMon.ind (revision 3) @@ -0,0 +1,52 @@ +"Output/Debug/Obj/cellMon/system_stm32g0xx.o" +"Output/Debug/Obj/cellMon/dma.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_adc.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_adc_ex.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_comp.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_cortex.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_dac.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_dac_ex.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_dma.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_dma_ex.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_exti.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_flash.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_flash_ex.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_gpio.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_pwr.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_pwr_ex.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_rcc.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_rcc_ex.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_tim.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_tim_ex.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_uart.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_uart_ex.o" +"Output/Debug/Obj/cellMon/stm32g0xx_ll_adc.o" +"Output/Debug/Obj/cellMon/stm32g0xx_ll_dma.o" +"Output/Debug/Obj/cellMon/stm32g0xx_ll_rcc.o" +"Output/Debug/Obj/cellMon/adc.o" +"Output/Debug/Obj/cellMon/comp.o" +"Output/Debug/Obj/cellMon/dac.o" +"Output/Debug/Obj/cellMon/gpio.o" +"Output/Debug/Obj/cellMon/main.o" +"Output/Debug/Obj/cellMon/stm32g0xx_hal_msp.o" +"Output/Debug/Obj/cellMon/stm32g0xx_it.o" +"Output/Debug/Obj/cellMon/tim.o" +"Output/Debug/Obj/cellMon/usart.o" +"Output/Debug/Obj/cellMon/balancer.o" +"Output/Debug/Obj/cellMon/bms.o" +"Output/Debug/Obj/cellMon/eeprom.o" +"Output/Debug/Obj/cellMon/led.o" +"Output/Debug/Obj/cellMon/meas.o" +"Output/Debug/Obj/cellMon/modbus.o" +"Output/Debug/Obj/cellMon/output.o" +"Output/Debug/Obj/cellMon/sysdata.o" +"Output/Debug/Obj/cellMon/template.o" +"Output/Debug/Obj/cellMon/SEGGER_THUMB_Startup.o" +"Output/Debug/Obj/cellMon/STM32G07x_Vectors.o" +"Output/Debug/Obj/cellMon/STM32G0xx_Startup.o" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 7.12a/lib/libc_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 7.12a/lib/SEGGER_crtinit_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 7.12a/lib/prinops_rtt_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 7.12a/lib/heapops_basic_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 7.12a/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_balanced.a" Index: ecs_cellMon/firmware/Output/Debug/Exe/cellMon.map =================================================================== --- ecs_cellMon/firmware/Output/Debug/Exe/cellMon.map (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Exe/cellMon.map (revision 3) @@ -0,0 +1,2392 @@ +*********************************************************************************************** +*** *** +*** LINK INFORMATION *** +*** *** +*********************************************************************************************** + +Linker version: + + SEGGER ARM Linker 4.38.2 compiled Mar 14 2023 20:07:24 + Copyright (c) 2017-2022 SEGGER Microcontroller GmbH www.segger.com + + +*********************************************************************************************** +*** *** +*** MODULE SUMMARY *** +*** *** +*********************************************************************************************** + +Memory use by input file: + + Object File RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + adc.o 468 192 + balancer.o 1 216 381 4 20 + bms.o 1 536 207 4 20 + comp.o 360 96 + dac.o 176 20 + dma.o 48 + eeprom.o 2 084 271 128 + gpio.o 320 + led.o 512 32 + main.o 1 236 334 580 + meas.o 488 117 32 + modbus.o 3 214 191 + output.o 80 + SEGGER_THUMB_Startup.o 20 + STM32G07x_Vectors.o 248 + stm32g0xx_hal.o 348 101 5 4 + stm32g0xx_hal_adc.o 5 340 105 + stm32g0xx_hal_adc_ex.o 332 108 + stm32g0xx_hal_comp.o 1 572 106 + stm32g0xx_hal_cortex.o 452 108 + stm32g0xx_hal_dac.o 1 280 105 + stm32g0xx_hal_dma.o 1 448 105 + stm32g0xx_hal_flash.o 696 107 28 + stm32g0xx_hal_flash_ex.o 384 110 + stm32g0xx_hal_gpio.o 1 744 106 + stm32g0xx_hal_msp.o 64 + stm32g0xx_hal_pwr_ex.o 152 108 + stm32g0xx_hal_rcc.o 3 260 105 + stm32g0xx_hal_rcc_ex.o 1 444 108 + stm32g0xx_hal_tim.o 6 658 105 + stm32g0xx_hal_tim_ex.o 936 108 + stm32g0xx_hal_uart.o 5 642 130 + stm32g0xx_hal_uart_ex.o 1 204 109 + stm32g0xx_it.o 96 + STM32G0xx_Startup.o 8 + sysdata.o 60 156 312 + system_stm32g0xx.o 388 96 4 + tim.o 384 76 + usart.o 348 144 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (39 objects) 46 246 3 431 173 1 684 + --------------------------------------------- ---------- ---------- ---------- ---------- + heapops_basic_v6m_t_le_eabi_balanced.a 20 4 + libc_v6m_t_le_eabi_balanced.a 6 806 792 20 4 + prinops_rtt_v6m_t_le_eabi_balanced.a 512 26 12 1 220 + SEGGER_crtinit_v6m_t_le_eabi_balanced.a 130 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (4 archives) 7 468 818 32 1 228 + --------------------------------------------- ---------- ---------- ---------- ---------- + Linker created (shared data, fills, blocks): 56 837 3 072 + ============================================= ========== ========== ========== ========== + Total: 53 714 61 086 205 5 984 + ============================================= ========== ========== ========== ========== + +Memory use by archive member: + + Archive member RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + __SEGGER_RTL_vfprintf_short_float_long.o (libc_v6m_t_le_eabi_balanced.a) + 3 400 35 + fileops.o (libc_v6m_t_le_eabi_balanced.a) 52 + floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 1 626 + floatops.o (libc_v6m_t_le_eabi_balanced.a) 496 + heapops_basic.o (heapops_basic_v6m_t_le_eabi_balanced.a) + 20 4 + intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 368 + intops.o (libc_v6m_t_le_eabi_balanced.a) 8 + mbops.o (libc_v6m_t_le_eabi_balanced.a) 188 541 20 4 + prinops.o (libc_v6m_t_le_eabi_balanced.a) 416 192 + prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 64 12 12 + SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 130 + SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 448 26 1 208 + strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 52 + strops.o (libc_v6m_t_le_eabi_balanced.a) 128 + utilops.o (libc_v6m_t_le_eabi_balanced.a) 72 24 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (15 members from 4 archives) 7 468 818 32 1 228 + Objects (39 files) 46 246 3 431 173 1 684 + Linker created (shared data, fills, blocks): 56 837 3 072 + ============================================= ========== ========== ========== ========== + Total: 53 714 61 086 205 5 984 + ============================================= ========== ========== ========== ========== + +Memory use by linker: + + Description RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + Filling 56 721 + Initialization table 112 + Integrity check 4 + Memory for block 'heap' 1 024 + Memory for block 'stack' 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (linker created): 56 837 3 072 + --------------------------------------------- ---------- ---------- ---------- ---------- + Objects (39 files) 46 246 3 431 173 1 684 + Archives (4 files) 7 468 818 32 1 228 + ============================================= ========== ========== ========== ========== + Total: 53 714 61 086 205 5 984 + ============================================= ========== ========== ========== ========== + + +*********************************************************************************************** +*** *** +*** SECTION DETAIL *** +*** *** +*********************************************************************************************** + +Sections by address: + + Range Symbol or [section] Name Size Al Init Ac Object File + ----------------- ------------------------- ---------- -- ---- -- ----------- + 08003000-080030bf _vectors 192 512 + Code RX STM32G07x_Vectors.o + 080030c0-0800315f __SEGGER_RTL_ipow10 160 8 Cnst RO prinops.o (libc_v6m_t_le_eabi_balanced.a) + 08003160-0800316f SystemInit 16 4 Code RX system_stm32g0xx.o + 08003170-080032e3 SystemCoreClockUpdate 372 4 Code RX system_stm32g0xx.o + 080032e4-080032f7 _start 20 4 Code RX SEGGER_THUMB_Startup.o + 080032f8-08003337 AHBPrescTable 64 4 Cnst RO system_stm32g0xx.o + 08003338-08003357 APBPrescTable 32 4 Cnst RO system_stm32g0xx.o + 08003358-08003387 MX_DMA_Init 48 4 Code RX dma.o + 08003388-080033bf HAL_Init 56 4 Code RX stm32g0xx_hal.o + 080033c0-08003437 HAL_InitTick 120 4 Code RX stm32g0xx_hal.o + 08003438-0800344f HAL_IncTick 24 4 Code RX stm32g0xx_hal.o + 08003450-0800345b HAL_GetTick 12 4 Code RX stm32g0xx_hal.o + 0800345c-08003497 HAL_Delay 60 4 Code RX stm32g0xx_hal.o + 08003498-080034e3 HAL_SYSCFG_StrobeDBattpinsConfig + 76 4 Code RX stm32g0xx_hal.o + 080034e4-08003c1f HAL_ADC_Init 1 852 4 Code RX stm32g0xx_hal_adc.o + 08003c20-08003c3f LL_ADC_EnableInternalRegulator + 32 4 Code RX stm32g0xx_hal_adc.o + 08003c40-08003d1f ADC_Enable 224 4 Code RX stm32g0xx_hal_adc.o + 08003d20-08003d3b LL_ADC_REG_StartConversion + 28 4 Code RX stm32g0xx_hal_adc.o + 08003d3c-08003e57 HAL_ADC_Start_DMA 284 4 Code RX stm32g0xx_hal_adc.o + 08003e58-08003e73 LL_ADC_Disable 28 4 Code RX stm32g0xx_hal_adc.o + 08003e74-080040c3 HAL_ADC_IRQHandler 592 4 Code RX stm32g0xx_hal_adc.o + 080040c4-080046ab HAL_ADC_ConfigChannel 1 512 4 Code RX stm32g0xx_hal_adc.o + 080046ac-080046c7 LL_ADC_REG_SetSequencerChAdd + 28 4 Code RX stm32g0xx_hal_adc.o + 080046c8-080046ef LL_ADC_SetChannelSamplingTime + 40 4 Code RX stm32g0xx_hal_adc.o + 080046f0-0800470f LL_ADC_REG_SetSequencerChRem + 32 4 Code RX stm32g0xx_hal_adc.o + 08004710-0800472b LL_ADC_Enable 28 4 Code RX stm32g0xx_hal_adc.o + 0800472c-08004833 HAL_ADCEx_Calibration_Start + 264 4 Code RX stm32g0xx_hal_adc_ex.o + 08004834-08004cbf HAL_COMP_Init 1 164 4 Code RX stm32g0xx_hal_comp.o + 08004cc0-08004cd7 LL_EXTI_EnableRisingTrig_0_31 + 24 4 Code RX stm32g0xx_hal_comp.o + 08004cd8-08004cef LL_EXTI_DisableRisingTrig_0_31 + 24 4 Code RX stm32g0xx_hal_comp.o + 08004cf0-08004d07 LL_EXTI_EnableFallingTrig_0_31 + 24 4 Code RX stm32g0xx_hal_comp.o + 08004d08-08004d1f LL_EXTI_DisableFallingTrig_0_31 + 24 4 Code RX stm32g0xx_hal_comp.o + 08004d20-08004d33 LL_EXTI_ClearRisingFlag_0_31 + 20 4 Code RX stm32g0xx_hal_comp.o + 08004d34-08004d47 LL_EXTI_ClearFallingFlag_0_31 + 20 4 Code RX stm32g0xx_hal_comp.o + 08004d48-08004d5f LL_EXTI_EnableEvent_0_31 24 4 Code RX stm32g0xx_hal_comp.o + 08004d60-08004d77 LL_EXTI_DisableEvent_0_31 24 4 Code RX stm32g0xx_hal_comp.o + 08004d78-08004d8f LL_EXTI_EnableIT_0_31 24 4 Code RX stm32g0xx_hal_comp.o + 08004d90-08004da7 LL_EXTI_DisableIT_0_31 24 4 Code RX stm32g0xx_hal_comp.o + 08004da8-08004e57 HAL_COMP_Start 176 4 Code RX stm32g0xx_hal_comp.o + 08004e58-08004e87 HAL_NVIC_SetPriority 48 4 Code RX stm32g0xx_hal_cortex.o + 08004e88-08004f07 __NVIC_SetPriority 128 4 Code RX stm32g0xx_hal_cortex.o + 08004f08-08004f37 HAL_NVIC_EnableIRQ 48 4 Code RX stm32g0xx_hal_cortex.o + 08004f38-08004f5f __NVIC_EnableIRQ 40 4 Code RX stm32g0xx_hal_cortex.o + 08004f60-08004f8f HAL_NVIC_DisableIRQ 48 4 Code RX stm32g0xx_hal_cortex.o + 08004f90-08004fbf __NVIC_DisableIRQ 48 4 Code RX stm32g0xx_hal_cortex.o + 08004fc0-0800500b SysTick_Config 76 4 Code RX stm32g0xx_hal_cortex.o + 0800500c-0800506f HAL_DAC_Init 100 4 Code RX stm32g0xx_hal_dac.o + 08005070-08005123 HAL_DAC_Start 180 4 Code RX stm32g0xx_hal_dac.o + 08005124-080051bb HAL_DAC_SetValue 152 4 Code RX stm32g0xx_hal_dac.o + 080051bc-0800550b HAL_DAC_ConfigChannel 848 4 Code RX stm32g0xx_hal_dac.o + 0800550c-0800577b HAL_DMA_Init 624 4 Code RX stm32g0xx_hal_dma.o + 0800577c-080057bf DMA_CalcDMAMUXChannelBaseAndMask + 68 4 Code RX stm32g0xx_hal_dma.o + 080057c0-080057f7 DMA_CalcDMAMUXRequestGenBaseAndMask + 56 4 Code RX stm32g0xx_hal_dma.o + 080057f8-08005867 DMA_SetConfig 112 4 Code RX stm32g0xx_hal_dma.o + 08005868-08005973 HAL_DMA_Start_IT 268 4 Code RX stm32g0xx_hal_dma.o + 08005974-08005ab3 HAL_DMA_IRQHandler 320 4 Code RX stm32g0xx_hal_dma.o + 08005ab4-08005bbf HAL_FLASH_Program 268 4 Code RX stm32g0xx_hal_flash.o + 08005bc0-08005c5b FLASH_WaitForLastOperation + 156 4 Code RX stm32g0xx_hal_flash.o + 08005c5c-08005c87 FLASH_Program_DoubleWord 44 4 Code RX stm32g0xx_hal_flash.o + 08005c88-08005ccb HAL_FLASH_Unlock 68 4 Code RX stm32g0xx_hal_flash.o + 08005ccc-08005cf7 HAL_FLASH_Lock 44 4 Code RX stm32g0xx_hal_flash.o + 08005cf8-08005de3 HAL_FLASHEx_Erase 236 4 Code RX stm32g0xx_hal_flash_ex.o + 08005de4-08005e1b FLASH_MassErase 56 4 Code RX stm32g0xx_hal_flash_ex.o + 08005e1c-08005e77 FLASH_PageErase 92 4 Code RX stm32g0xx_hal_flash_ex.o + 08005e78-0800628f HAL_GPIO_Init 1 048 4 Code RX stm32g0xx_hal_gpio.o + 08006290-08006457 HAL_GPIO_DeInit 456 4 Code RX stm32g0xx_hal_gpio.o + 08006458-0800649f HAL_GPIO_ReadPin 72 4 Code RX stm32g0xx_hal_gpio.o + 080064a0-08006503 HAL_GPIO_WritePin 100 4 Code RX stm32g0xx_hal_gpio.o + 08006504-08006547 HAL_GPIO_TogglePin 68 4 Code RX stm32g0xx_hal_gpio.o + 08006548-080065df HAL_PWREx_ControlVoltageScaling + 152 4 Code RX stm32g0xx_hal_pwr_ex.o + 080065e0-08006e03 HAL_RCC_OscConfig 2 084 4 Code RX stm32g0xx_hal_rcc.o + 08006e04-08007153 HAL_RCC_ClockConfig 848 4 Code RX stm32g0xx_hal_rcc.o + 08007154-08007257 HAL_RCC_GetSysClockFreq 260 4 Code RX stm32g0xx_hal_rcc.o + 08007258-08007263 HAL_RCC_GetHCLKFreq 12 4 Code RX stm32g0xx_hal_rcc.o + 08007264-0800728b HAL_RCC_GetPCLK1Freq 40 4 Code RX stm32g0xx_hal_rcc.o + 0800728c-0800729b LL_RCC_GetAPB1Prescaler 16 4 Code RX stm32g0xx_hal_rcc.o + 0800729c-0800783f HAL_RCCEx_PeriphCLKConfig 1 444 4 Code RX stm32g0xx_hal_rcc_ex.o + 08007840-080079e3 HAL_TIM_Base_Init 420 4 Code RX stm32g0xx_hal_tim.o + 080079e4-08007ad7 TIM_Base_SetConfig 244 4 Code RX stm32g0xx_hal_tim.o + 08007ad8-08007ba7 TIM_CCxChannelCmd 208 4 Code RX stm32g0xx_hal_tim.o + 08007ba8-08007d53 HAL_TIM_IC_Init 428 4 Code RX stm32g0xx_hal_tim.o + 08007d54-0800803f HAL_TIM_IC_Start 748 4 Code RX stm32g0xx_hal_tim.o + 08008040-080082d7 HAL_TIM_IC_ConfigChannel 664 4 Code RX stm32g0xx_hal_tim.o + 080082d8-0800838b TIM_TI1_SetConfig 180 4 Code RX stm32g0xx_hal_tim.o + 0800838c-0800893f HAL_TIM_ConfigClockSource 1 460 4 Code RX stm32g0xx_hal_tim.o + 08008940-0800896f TIM_ITRx_SetConfig 48 4 Code RX stm32g0xx_hal_tim.o + 08008970-08008acb HAL_TIM_SlaveConfigSynchro + 348 4 Code RX stm32g0xx_hal_tim.o + 08008acc-08008e8b TIM_SlaveTimer_SetConfig 960 4 Code RX stm32g0xx_hal_tim.o + 08008e8c-08009013 HAL_TIM_ReadCapturedValue 392 4 Code RX stm32g0xx_hal_tim.o + 08009014-0800928b HAL_TIMEx_MasterConfigSynchronization + 632 4 Code RX stm32g0xx_hal_tim_ex.o + 0800928c-080093bb HAL_TIMEx_TISelection 304 4 Code RX stm32g0xx_hal_tim_ex.o + 080093bc-08009a6b UART_SetConfig 1 712 4 Code RX stm32g0xx_hal_uart.o + 08009a6c-08009d2f UART_AdvFeatureConfig 708 4 Code RX stm32g0xx_hal_uart.o + 08009d30-08009dc7 UART_CheckIdleState 152 4 Code RX stm32g0xx_hal_uart.o + 08009dc8-08009e93 HAL_UART_DeInit 204 4 Code RX stm32g0xx_hal_uart.o + 08009e94-08009fcb HAL_UART_Transmit_IT 312 4 Code RX stm32g0xx_hal_uart.o + 08009fcc-0800a057 UART_TxISR_16BIT_FIFOEN 140 4 Code RX stm32g0xx_hal_uart.o + 0800a058-0800a0b7 UART_TxISR_16BIT 96 4 Code RX stm32g0xx_hal_uart.o + 0800a0b8-0800a227 UART_Start_Receive_IT 368 4 Code RX stm32g0xx_hal_uart.o + 0800a228-0800a40b UART_RxISR_16BIT_FIFOEN 484 4 Code RX stm32g0xx_hal_uart.o + 0800a40c-0800a5eb UART_RxISR_8BIT_FIFOEN 480 4 Code RX stm32g0xx_hal_uart.o + 0800a5ec-0800a747 HAL_RS485Ex_Init 348 4 Code RX stm32g0xx_hal_uart_ex.o + 0800a748-0800a7ef UARTEx_SetNbDataToProcess 168 4 Code RX stm32g0xx_hal_uart_ex.o + 0800a7f0-0800a897 HAL_UARTEx_DisableFifoMode + 168 4 Code RX stm32g0xx_hal_uart_ex.o + 0800a898-0800a99b HAL_UARTEx_SetTxFifoThreshold + 260 4 Code RX stm32g0xx_hal_uart_ex.o + 0800a99c-0800aa9f HAL_UARTEx_SetRxFifoThreshold + 260 4 Code RX stm32g0xx_hal_uart_ex.o + 0800aaa0-0800ab7f MX_ADC1_Init 224 4 Code RX adc.o + 0800ab80-0800ac73 HAL_ADC_MspInit 244 4 Code RX adc.o + 0800ac74-0800acb7 MX_COMP1_Init 68 4 Code RX comp.o + 0800acb8-0800acfb MX_COMP2_Init 68 4 Code RX comp.o + 0800acfc-0800addb HAL_COMP_MspInit 224 4 Code RX comp.o + 0800addc-0800ae23 MX_DAC1_Init 72 4 Code RX dac.o + 0800ae24-0800ae8b HAL_DAC_MspInit 104 4 Code RX dac.o + 0800ae8c-0800afcb MX_GPIO_Init 320 4 Code RX gpio.o + 0800afcc-0800b2af main 740 4 Code RX main.o + 0800b2b0-0800b333 SystemClock_Config 132 4 Code RX main.o + 0800b334-0800b34f __NVIC_SystemReset 28 4 Code RX main.o + 0800b350-0800b38f applyMBParameter 64 4 Code RX main.o + 0800b390-0800b3db resetCounters 76 4 Code RX main.o + 0800b3dc-0800b42b resetMinMaxValues 80 4 Code RX main.o + 0800b42c-0800b47f mb_save_lock_key 84 4 Code RX main.o + 0800b480-0800b49b assert_failed 28 4 Code RX main.o + 0800b49c-0800b4db HAL_MspInit 64 4 Code RX stm32g0xx_hal_msp.o + 0800b4dc-0800b4eb DMA1_Channel1_IRQHandler 16 4 Code RX stm32g0xx_it.o + 0800b4ec-0800b4fb ADC1_COMP_IRQHandler 16 4 Code RX stm32g0xx_it.o + 0800b4fc-0800b50b USART1_IRQHandler 16 4 Code RX stm32g0xx_it.o + 0800b50c-0800b51b USART3_USART4_LPUART1_IRQHandler + 16 4 Code RX stm32g0xx_it.o + 0800b51c-0800b62b MX_TIM1_Init 272 4 Code RX tim.o + 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EEPROM_ResetLogData 0x0800C949 260 4 Code Gb eeprom.o + EEPROM_fullRestore 0x0800C371 220 4 Code Gb eeprom.o + EEPROM_isFirstStart 0x0800C2B9 80 4 Code Gb eeprom.o + EEPROM_readConfig 0x0800C44D 424 4 Code Gb eeprom.o + EEPROM_readLogData 0x0800CA4D 144 4 Code Gb eeprom.o + EEPROM_storeConfig 0x0800C5F5 556 4 Code Gb eeprom.o + EEPROM_storeLogData 0x0800C821 296 4 Code Gb eeprom.o + EXTI0_1_IRQHandler 0x0800F34F 2 Code Wk STM32G07x_Vectors.o + EXTI2_3_IRQHandler 0x0800F351 2 Code Wk STM32G07x_Vectors.o + EXTI4_15_IRQHandler 0x0800F353 2 Code Wk STM32G07x_Vectors.o + Error_Handler 0x0800FFAD 4 2 Code Gb main.o + FLASH_IRQHandler 0x0800F34B 2 Code Wk STM32G07x_Vectors.o + FLASH_MassErase 0x08005DE5 56 4 Code Lc stm32g0xx_hal_flash_ex.o + FLASH_PageErase 0x08005E1D 92 4 Code Gb stm32g0xx_hal_flash_ex.o + FLASH_Program_DoubleWord 0x08005C5D 44 4 Code Lc stm32g0xx_hal_flash.o + FLASH_Program_Fast 0x20000C31 116 4 Code Lc stm32g0xx_hal_flash.o + FLASH_Program_Fast__TT_veneer_T16_LDR_BX + 0x08005BB1 4 Code Lc [ Linker created ] + FLASH_WaitForLastOperation + 0x08005BC1 156 4 Code Gb stm32g0xx_hal_flash.o + HAL_ADCEx_Calibration_Start + 0x0800472D 264 4 Code Gb stm32g0xx_hal_adc_ex.o + HAL_ADCEx_ChannelConfigReadyCallback + 0x0800FC05 8 2 Code Wk stm32g0xx_hal_adc_ex.o + HAL_ADCEx_EndOfSamplingCallback + 0x0800FBFD 8 2 Code Wk stm32g0xx_hal_adc_ex.o + HAL_ADCEx_LevelOutOfWindow2Callback + 0x0800FBED 8 2 Code Wk stm32g0xx_hal_adc_ex.o + HAL_ADCEx_LevelOutOfWindow3Callback + 0x0800FBF5 8 2 Code Wk stm32g0xx_hal_adc_ex.o + HAL_ADC_ConfigChannel 0x080040C5 1 512 4 Code Gb stm32g0xx_hal_adc.o + HAL_ADC_ConvCpltCallback 0x0800CEA5 20 4 Code Gb meas.o + HAL_ADC_ConvHalfCpltCallback + 0x0800FBA5 8 2 Code Wk stm32g0xx_hal_adc.o + HAL_ADC_ErrorCallback 0x0800FB9D 8 2 Code Wk stm32g0xx_hal_adc.o + HAL_ADC_IRQHandler 0x08003E75 592 4 Code Gb stm32g0xx_hal_adc.o + HAL_ADC_Init 0x080034E5 1 852 4 Code Gb stm32g0xx_hal_adc.o + HAL_ADC_LevelOutOfWindowCallback + 0x0800FB85 8 2 Code Wk stm32g0xx_hal_adc.o + HAL_ADC_MspInit 0x0800AB81 244 4 Code Gb adc.o + HAL_ADC_Start_DMA 0x08003D3D 284 4 Code Gb stm32g0xx_hal_adc.o + HAL_COMP_Init 0x08004835 1 164 4 Code Gb stm32g0xx_hal_comp.o + HAL_COMP_MspInit 0x0800ACFD 224 4 Code Gb comp.o + HAL_COMP_Start 0x08004DA9 176 4 Code Gb stm32g0xx_hal_comp.o + HAL_DAC_ConfigChannel 0x080051BD 848 4 Code Gb stm32g0xx_hal_dac.o + HAL_DAC_Init 0x0800500D 100 4 Code Gb stm32g0xx_hal_dac.o + HAL_DAC_MspInit 0x0800AE25 104 4 Code Gb dac.o + HAL_DAC_SetValue 0x08005125 152 4 Code Gb stm32g0xx_hal_dac.o + HAL_DAC_Start 0x08005071 180 4 Code Gb stm32g0xx_hal_dac.o + HAL_DMA_IRQHandler 0x08005975 320 4 Code Gb stm32g0xx_hal_dma.o + HAL_DMA_Init 0x0800550D 624 4 Code Gb stm32g0xx_hal_dma.o + HAL_DMA_Start_IT 0x08005869 268 4 Code Gb stm32g0xx_hal_dma.o + HAL_Delay 0x0800345D 60 4 Code Wk stm32g0xx_hal.o + HAL_FLASHEx_Erase 0x08005CF9 236 4 Code Gb stm32g0xx_hal_flash_ex.o + HAL_FLASH_Lock 0x08005CCD 44 4 Code Gb stm32g0xx_hal_flash.o + HAL_FLASH_Program 0x08005AB5 252 4 Code Gb stm32g0xx_hal_flash.o + HAL_FLASH_Unlock 0x08005C89 68 4 Code Gb stm32g0xx_hal_flash.o + HAL_GPIO_DeInit 0x08006291 456 4 Code Gb stm32g0xx_hal_gpio.o + HAL_GPIO_Init 0x08005E79 1 048 4 Code Gb stm32g0xx_hal_gpio.o + HAL_GPIO_ReadPin 0x08006459 72 4 Code Gb stm32g0xx_hal_gpio.o + HAL_GPIO_TogglePin 0x08006505 68 4 Code Gb stm32g0xx_hal_gpio.o + HAL_GPIO_WritePin 0x080064A1 100 4 Code Gb stm32g0xx_hal_gpio.o + HAL_GetTick 0x08003451 12 4 Code Wk stm32g0xx_hal.o + HAL_IncTick 0x08003439 24 4 Code Wk stm32g0xx_hal.o + HAL_Init 0x08003389 56 4 Code Gb stm32g0xx_hal.o + HAL_InitTick 0x080033C1 120 4 Code Wk stm32g0xx_hal.o + HAL_MspInit 0x0800B49D 64 4 Code Gb stm32g0xx_hal_msp.o + HAL_NVIC_DisableIRQ 0x08004F61 48 4 Code Gb stm32g0xx_hal_cortex.o + HAL_NVIC_EnableIRQ 0x08004F09 48 4 Code Gb stm32g0xx_hal_cortex.o + HAL_NVIC_SetPriority 0x08004E59 48 4 Code Gb stm32g0xx_hal_cortex.o + HAL_PWREx_ControlVoltageScaling + 0x08006549 152 4 Code Gb stm32g0xx_hal_pwr_ex.o + HAL_RCCEx_PeriphCLKConfig 0x0800729D 1 444 4 Code Gb stm32g0xx_hal_rcc_ex.o + HAL_RCC_ClockConfig 0x08006E05 848 4 Code Gb stm32g0xx_hal_rcc.o + HAL_RCC_GetHCLKFreq 0x08007259 12 4 Code Gb stm32g0xx_hal_rcc.o + HAL_RCC_GetPCLK1Freq 0x08007265 40 4 Code Gb stm32g0xx_hal_rcc.o + HAL_RCC_GetSysClockFreq 0x08007155 260 4 Code Gb stm32g0xx_hal_rcc.o + HAL_RCC_OscConfig 0x080065E1 2 084 4 Code Gb stm32g0xx_hal_rcc.o + HAL_RS485Ex_Init 0x0800A5ED 348 4 Code Gb stm32g0xx_hal_uart_ex.o + HAL_SYSCFG_StrobeDBattpinsConfig + 0x08003499 76 4 Code Gb stm32g0xx_hal.o + HAL_SYSTICK_Config 0x0800FC0D 16 2 Code Gb stm32g0xx_hal_cortex.o + HAL_TIMEx_MasterConfigSynchronization + 0x08009015 632 4 Code Gb stm32g0xx_hal_tim_ex.o + HAL_TIMEx_TISelection 0x0800928D 304 4 Code Gb stm32g0xx_hal_tim_ex.o + HAL_TIM_Base_Init 0x08007841 420 4 Code Gb stm32g0xx_hal_tim.o + HAL_TIM_Base_MspInit 0x0800B62D 112 4 Code Gb tim.o + HAL_TIM_ConfigClockSource 0x0800838D 1 460 4 Code Gb stm32g0xx_hal_tim.o + HAL_TIM_IC_ConfigChannel 0x08008041 664 4 Code Gb stm32g0xx_hal_tim.o + HAL_TIM_IC_Init 0x08007BA9 428 4 Code Gb stm32g0xx_hal_tim.o + HAL_TIM_IC_MspInit 0x0800FC1D 8 2 Code Wk stm32g0xx_hal_tim.o + HAL_TIM_IC_Start 0x08007D55 748 4 Code Gb stm32g0xx_hal_tim.o + HAL_TIM_ReadCapturedValue 0x08008E8D 392 4 Code Gb stm32g0xx_hal_tim.o + HAL_TIM_SlaveConfigSynchro + 0x08008971 348 4 Code Gb stm32g0xx_hal_tim.o + HAL_UARTEx_DisableFifoMode + 0x0800A7F1 168 4 Code Gb stm32g0xx_hal_uart_ex.o + HAL_UARTEx_RxEventCallback + 0x0800FE2D 12 2 Code Wk stm32g0xx_hal_uart.o + HAL_UARTEx_SetRxFifoThreshold + 0x0800A99D 260 4 Code Gb stm32g0xx_hal_uart_ex.o + HAL_UARTEx_SetTxFifoThreshold + 0x0800A899 260 4 Code Gb stm32g0xx_hal_uart_ex.o + HAL_UART_DeInit 0x08009DC9 204 4 Code Gb stm32g0xx_hal_uart.o + HAL_UART_ErrorCallback 0x0800FE25 8 2 Code Wk stm32g0xx_hal_uart.o + HAL_UART_MspDeInit 0x0800B7BD 60 4 Code Gb usart.o + HAL_UART_MspInit 0x0800B719 164 4 Code Gb usart.o + HAL_UART_Receive_IT 0x0800F643 146 2 Code Gb stm32g0xx_hal_uart.o + HAL_UART_RxCpltCallback 0x0800FE41 8 2 Code Wk stm32g0xx_hal_uart.o + HAL_UART_Transmit_IT 0x08009E95 312 4 Code Gb stm32g0xx_hal_uart.o + HAL_UART_TxCpltCallback 0x0800FE39 8 2 Code Wk stm32g0xx_hal_uart.o + HardFault_Handler 0x0800F6D7 2 2 Code Gb stm32g0xx_it.o + I2C1_IRQHandler 0x0800F36F 2 Code Wk STM32G07x_Vectors.o + I2C2_IRQHandler 0x0800F371 2 Code Wk STM32G07x_Vectors.o + LED_ErrorExec 0x0800CB9D 116 4 Code Gb led.o + LED_ErrorOff 0x0800CB11 52 4 Code Gb led.o + LED_ErrorOn 0x0800CADD 52 4 Code Gb led.o + LED_ErrorStartBlink 0x0800CB45 88 4 Code Gb led.o + LED_Exec 0x0800FFC9 12 2 Code Gb led.o + LED_FunctionExec 0x0800CC75 92 4 Code Gb led.o + LED_FunctionSetTimes 0x0800CC5D 24 4 Code Gb led.o + LED_FunctionStartBlink 0x0800CC11 76 4 Code Gb led.o + LL_ADC_Disable 0x08003E59 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_Enable 0x08004711 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_EnableInternalRegulator + 0x08003C21 32 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_GetCommonPathInternalCh + 0x0800F439 18 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_IsCalibrationOnGoing + 0x0800FBD9 20 2 Code Lc stm32g0xx_hal_adc_ex.o + LL_ADC_IsDisableOngoing 0x0800F44B 18 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_IsEnabled 0x0800FA29 16 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_IsEnabled 0x0800FBC9 16 2 Code Lc stm32g0xx_hal_adc_ex.o + LL_ADC_IsInternalRegulatorEnabled + 0x0800FA15 20 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_GetDMATransfer 0x0800FB8D 16 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_IsConversionOngoing + 0x0800F37D 18 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_IsTriggerSourceSWStart + 0x0800F3B5 22 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_SetSequencerChAdd + 0x080046AD 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_SetSequencerChRem + 0x080046F1 32 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_SetSequencerRanks + 0x0800F40B 46 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_StartConversion + 0x08003D21 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_SetChannelSamplingTime + 0x080046C9 40 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_SetCommonPathInternalCh + 0x0800FBAD 28 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_SetSamplingTimeCommonChannels + 0x0800F38F 38 2 Code Lc stm32g0xx_hal_adc.o + LL_EXTI_ClearFallingFlag_0_31 + 0x08004D35 20 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_ClearRisingFlag_0_31 + 0x08004D21 20 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_DisableEvent_0_31 0x08004D61 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_DisableFallingTrig_0_31 + 0x08004D09 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_DisableIT_0_31 0x08004D91 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_DisableRisingTrig_0_31 + 0x08004CD9 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_EnableEvent_0_31 0x08004D49 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_EnableFallingTrig_0_31 + 0x08004CF1 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_EnableIT_0_31 0x08004D79 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_EnableRisingTrig_0_31 + 0x08004CC1 24 4 Code Lc stm32g0xx_hal_comp.o + LL_RCC_GetAPB1Prescaler 0x0800728D 16 4 Code Lc stm32g0xx_hal_rcc.o + MEAS_Exec 0x0800CD49 96 4 Code Gb meas.o + MEAS_Init 0x0800CCD1 120 4 Code Gb meas.o + MODBUS_UART_IRQHandler 0x0800D121 640 4 Code Gb modbus.o + MX_ADC1_Init 0x0800AAA1 224 4 Code Gb adc.o + MX_COMP1_Init 0x0800AC75 68 4 Code Gb comp.o + MX_COMP2_Init 0x0800ACB9 68 4 Code Gb comp.o + MX_DAC1_Init 0x0800ADDD 72 4 Code Gb dac.o + MX_DMA_Init 0x08003359 48 4 Code Gb dma.o + MX_GPIO_Init 0x0800AE8D 320 4 Code Gb gpio.o + MX_TIM1_Init 0x0800B51D 272 4 Code Gb tim.o + MX_USART1_UART_Init 0x0800B69D 124 4 Code Gb usart.o + NMI_Handler 0x0800F6D5 2 2 Code Gb stm32g0xx_it.o + OUTPUT_LVP_Disable 0x0800D869 20 4 Code Gb output.o + OUTPUT_LVP_Enable 0x0800D841 20 4 Code Gb output.o + OUTPUT_OVP_Disable 0x0800D855 20 4 Code Gb output.o + OUTPUT_OVP_Enable 0x0800D82D 20 4 Code Gb output.o + PVD_IRQHandler 0x0800F347 2 Code Wk STM32G07x_Vectors.o + PendSV_Handler 0x0800F6DB 2 2 Code Gb stm32g0xx_it.o + RCC_IRQHandler 0x0800F34D 2 Code Wk STM32G07x_Vectors.o + RS485_ModbusEx_Init 0x0800CF8D 404 4 Code Lc modbus.o + RTC_STAMP_IRQHandler 0x0800F349 2 Code Wk STM32G07x_Vectors.o + Reset_Handler 0x0800FA0D 2 Code Gb STM32G0xx_Startup.o + SEGGER_RTT_Write 0x0800F169 52 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + SEGGER_RTT_WriteNoLock 0x0800F0E5 132 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + SPI1_IRQHandler 0x0800F373 2 Code Wk STM32G07x_Vectors.o + SPI2_IRQHandler 0x0800F375 2 Code Wk STM32G07x_Vectors.o + SVC_Handler 0x0800F6D9 2 2 Code Gb stm32g0xx_it.o + SYSDATA_Init 0x0800D87D 60 4 Code Gb sysdata.o + SysTick_Config 0x08004FC1 76 4 Code Lc stm32g0xx_hal_cortex.o + SysTick_Handler 0x0800FFB1 8 2 Code Gb stm32g0xx_it.o + SystemClock_Config 0x0800B2B1 132 4 Code Gb main.o + SystemCoreClockUpdate 0x08003171 372 4 Code Gb system_stm32g0xx.o + SystemInit 0x08003161 16 4 Code Gb system_stm32g0xx.o + TIM14_IRQHandler 0x0800F367 2 Code Wk STM32G07x_Vectors.o + TIM15_IRQHandler 0x0800F369 2 Code Wk STM32G07x_Vectors.o + TIM16_IRQHandler 0x0800F36B 2 Code Wk STM32G07x_Vectors.o + TIM17_IRQHandler 0x0800F36D 2 Code Wk STM32G07x_Vectors.o + TIM1_BRK_UP_TRG_COMP_IRQHandler + 0x0800F35B 2 Code Wk STM32G07x_Vectors.o + TIM1_CC_IRQHandler 0x0800F35D 2 Code Wk STM32G07x_Vectors.o + TIM2_IRQHandler 0x0800F35F 2 Code Wk STM32G07x_Vectors.o + TIM3_IRQHandler 0x0800F361 2 Code Wk STM32G07x_Vectors.o + TIM6_DAC_LPTIM1_IRQHandler + 0x0800F363 2 Code Wk STM32G07x_Vectors.o + TIM7_LPTIM2_IRQHandler 0x0800F365 2 Code Wk STM32G07x_Vectors.o + TIM_Base_SetConfig 0x080079E5 244 4 Code Gb stm32g0xx_hal_tim.o + TIM_CCxChannelCmd 0x08007AD9 208 4 Code Gb stm32g0xx_hal_tim.o + TIM_ETR_SetConfig 0x0800F53D 54 2 Code Gb stm32g0xx_hal_tim.o + TIM_ITRx_SetConfig 0x08008941 48 4 Code Lc stm32g0xx_hal_tim.o + TIM_SlaveTimer_SetConfig 0x08008ACD 960 4 Code Lc stm32g0xx_hal_tim.o + TIM_TI1_ConfigInputStage 0x0800FC91 80 2 Code Lc stm32g0xx_hal_tim.o + TIM_TI1_SetConfig 0x080082D9 180 4 Code Gb stm32g0xx_hal_tim.o + TIM_TI2_ConfigInputStage 0x0800FCE1 84 2 Code Lc stm32g0xx_hal_tim.o + TIM_TI2_SetConfig 0x0800F45D 110 2 Code Lc stm32g0xx_hal_tim.o + TIM_TI3_SetConfig 0x0800FC25 108 2 Code Lc stm32g0xx_hal_tim.o + TIM_TI4_SetConfig 0x0800F4CB 114 2 Code Lc stm32g0xx_hal_tim.o + UARTEx_SetNbDataToProcess 0x0800A749 168 4 Code Lc stm32g0xx_hal_uart_ex.o + UART_AdvFeatureConfig 0x08009A6D 708 4 Code Gb stm32g0xx_hal_uart.o + UART_CheckIdleState 0x08009D31 152 4 Code Gb stm32g0xx_hal_uart.o + UART_EndTransmit_IT 0x0800F6DD 42 2 Code Lc modbus.o + UART_RxISR_16BIT 0x0800FE49 180 2 Code Lc stm32g0xx_hal_uart.o + UART_RxISR_16BIT_FIFOEN 0x0800A229 484 4 Code Lc stm32g0xx_hal_uart.o + UART_RxISR_8BIT 0x0800FEFD 176 2 Code Lc stm32g0xx_hal_uart.o + UART_RxISR_8BIT_FIFOEN 0x0800A40D 480 4 Code Lc stm32g0xx_hal_uart.o + UART_SetConfig 0x080093BD 1 712 4 Code Gb stm32g0xx_hal_uart.o + UART_Start_Receive_IT 0x0800A0B9 368 4 Code Gb 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----- ---- -- ----------- + 0x08003161 SystemInit 16 4 Code Gb system_stm32g0xx.o + 0x08003171 SystemCoreClockUpdate 372 4 Code Gb system_stm32g0xx.o + 0x080032E5 _start 14 4 Code Gb SEGGER_THUMB_Startup.o + 0x080032EF __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + 0x080032F3 exit 2 4 Code Gb SEGGER_THUMB_Startup.o + 0x08003359 MX_DMA_Init 48 4 Code Gb dma.o + 0x08003389 HAL_Init 56 4 Code Gb stm32g0xx_hal.o + 0x080033C1 HAL_InitTick 120 4 Code Wk stm32g0xx_hal.o + 0x08003439 HAL_IncTick 24 4 Code Wk stm32g0xx_hal.o + 0x08003451 HAL_GetTick 12 4 Code Wk stm32g0xx_hal.o + 0x0800345D HAL_Delay 60 4 Code Wk stm32g0xx_hal.o + 0x08003499 HAL_SYSCFG_StrobeDBattpinsConfig + 76 4 Code Gb stm32g0xx_hal.o + 0x080034E5 HAL_ADC_Init 1 852 4 Code Gb stm32g0xx_hal_adc.o + 0x08003C21 LL_ADC_EnableInternalRegulator + 32 4 Code Lc stm32g0xx_hal_adc.o + 0x08003C41 ADC_Enable 224 4 Code Gb stm32g0xx_hal_adc.o + 0x08003D21 LL_ADC_REG_StartConversion + 28 4 Code Lc stm32g0xx_hal_adc.o + 0x08003D3D HAL_ADC_Start_DMA 284 4 Code Gb stm32g0xx_hal_adc.o + 0x08003E59 LL_ADC_Disable 28 4 Code Lc stm32g0xx_hal_adc.o + 0x08003E75 HAL_ADC_IRQHandler 592 4 Code Gb stm32g0xx_hal_adc.o + 0x080040C5 HAL_ADC_ConfigChannel 1 512 4 Code Gb stm32g0xx_hal_adc.o + 0x080046AD LL_ADC_REG_SetSequencerChAdd + 28 4 Code Lc stm32g0xx_hal_adc.o + 0x080046C9 LL_ADC_SetChannelSamplingTime + 40 4 Code Lc stm32g0xx_hal_adc.o + 0x080046F1 LL_ADC_REG_SetSequencerChRem + 32 4 Code Lc stm32g0xx_hal_adc.o + 0x08004711 LL_ADC_Enable 28 4 Code Lc stm32g0xx_hal_adc.o + 0x0800472D HAL_ADCEx_Calibration_Start + 264 4 Code Gb stm32g0xx_hal_adc_ex.o + 0x08004835 HAL_COMP_Init 1 164 4 Code Gb stm32g0xx_hal_comp.o + 0x08004CC1 LL_EXTI_EnableRisingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004CD9 LL_EXTI_DisableRisingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004CF1 LL_EXTI_EnableFallingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D09 LL_EXTI_DisableFallingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D21 LL_EXTI_ClearRisingFlag_0_31 + 20 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D35 LL_EXTI_ClearFallingFlag_0_31 + 20 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D49 LL_EXTI_EnableEvent_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D61 LL_EXTI_DisableEvent_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D79 LL_EXTI_EnableIT_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D91 LL_EXTI_DisableIT_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004DA9 HAL_COMP_Start 176 4 Code Gb stm32g0xx_hal_comp.o + 0x08004E59 HAL_NVIC_SetPriority 48 4 Code Gb stm32g0xx_hal_cortex.o + 0x08004E89 __NVIC_SetPriority 128 4 Code Lc stm32g0xx_hal_cortex.o + 0x08004F09 HAL_NVIC_EnableIRQ 48 4 Code Gb stm32g0xx_hal_cortex.o + 0x08004F39 __NVIC_EnableIRQ 40 4 Code Lc stm32g0xx_hal_cortex.o + 0x08004F61 HAL_NVIC_DisableIRQ 48 4 Code Gb stm32g0xx_hal_cortex.o + 0x08004F91 __NVIC_DisableIRQ 48 4 Code Lc stm32g0xx_hal_cortex.o + 0x08004FC1 SysTick_Config 76 4 Code Lc stm32g0xx_hal_cortex.o + 0x0800500D HAL_DAC_Init 100 4 Code Gb stm32g0xx_hal_dac.o + 0x08005071 HAL_DAC_Start 180 4 Code Gb stm32g0xx_hal_dac.o + 0x08005125 HAL_DAC_SetValue 152 4 Code Gb stm32g0xx_hal_dac.o + 0x080051BD HAL_DAC_ConfigChannel 848 4 Code Gb stm32g0xx_hal_dac.o + 0x0800550D HAL_DMA_Init 624 4 Code Gb stm32g0xx_hal_dma.o + 0x0800577D DMA_CalcDMAMUXChannelBaseAndMask + 68 4 Code Lc stm32g0xx_hal_dma.o + 0x080057C1 DMA_CalcDMAMUXRequestGenBaseAndMask + 56 4 Code Lc stm32g0xx_hal_dma.o + 0x080057F9 DMA_SetConfig 112 4 Code Lc stm32g0xx_hal_dma.o + 0x08005869 HAL_DMA_Start_IT 268 4 Code Gb stm32g0xx_hal_dma.o + 0x08005975 HAL_DMA_IRQHandler 320 4 Code Gb stm32g0xx_hal_dma.o + 0x08005AB5 HAL_FLASH_Program 252 4 Code Gb stm32g0xx_hal_flash.o + 0x08005BB1 FLASH_Program_Fast__TT_veneer_T16_LDR_BX + 4 Code Lc [ Linker created ] + 0x08005BC1 FLASH_WaitForLastOperation + 156 4 Code Gb stm32g0xx_hal_flash.o + 0x08005C5D FLASH_Program_DoubleWord 44 4 Code Lc stm32g0xx_hal_flash.o + 0x08005C89 HAL_FLASH_Unlock 68 4 Code Gb stm32g0xx_hal_flash.o + 0x08005CCD HAL_FLASH_Lock 44 4 Code Gb stm32g0xx_hal_flash.o + 0x08005CF9 HAL_FLASHEx_Erase 236 4 Code Gb stm32g0xx_hal_flash_ex.o + 0x08005DE5 FLASH_MassErase 56 4 Code Lc stm32g0xx_hal_flash_ex.o + 0x08005E1D FLASH_PageErase 92 4 Code Gb stm32g0xx_hal_flash_ex.o + 0x08005E79 HAL_GPIO_Init 1 048 4 Code Gb stm32g0xx_hal_gpio.o + 0x08006291 HAL_GPIO_DeInit 456 4 Code Gb stm32g0xx_hal_gpio.o + 0x08006459 HAL_GPIO_ReadPin 72 4 Code Gb stm32g0xx_hal_gpio.o + 0x080064A1 HAL_GPIO_WritePin 100 4 Code Gb stm32g0xx_hal_gpio.o + 0x08006505 HAL_GPIO_TogglePin 68 4 Code Gb stm32g0xx_hal_gpio.o + 0x08006549 HAL_PWREx_ControlVoltageScaling + 152 4 Code Gb stm32g0xx_hal_pwr_ex.o + 0x080065E1 HAL_RCC_OscConfig 2 084 4 Code Gb stm32g0xx_hal_rcc.o + 0x08006E05 HAL_RCC_ClockConfig 848 4 Code Gb stm32g0xx_hal_rcc.o + 0x08007155 HAL_RCC_GetSysClockFreq 260 4 Code Gb stm32g0xx_hal_rcc.o + 0x08007259 HAL_RCC_GetHCLKFreq 12 4 Code Gb stm32g0xx_hal_rcc.o + 0x08007265 HAL_RCC_GetPCLK1Freq 40 4 Code Gb stm32g0xx_hal_rcc.o + 0x0800728D LL_RCC_GetAPB1Prescaler 16 4 Code Lc stm32g0xx_hal_rcc.o + 0x0800729D HAL_RCCEx_PeriphCLKConfig 1 444 4 Code Gb stm32g0xx_hal_rcc_ex.o + 0x08007841 HAL_TIM_Base_Init 420 4 Code Gb stm32g0xx_hal_tim.o + 0x080079E5 TIM_Base_SetConfig 244 4 Code Gb stm32g0xx_hal_tim.o + 0x08007AD9 TIM_CCxChannelCmd 208 4 Code Gb stm32g0xx_hal_tim.o + 0x08007BA9 HAL_TIM_IC_Init 428 4 Code Gb stm32g0xx_hal_tim.o + 0x08007D55 HAL_TIM_IC_Start 748 4 Code Gb stm32g0xx_hal_tim.o + 0x08008041 HAL_TIM_IC_ConfigChannel 664 4 Code Gb stm32g0xx_hal_tim.o + 0x080082D9 TIM_TI1_SetConfig 180 4 Code Gb stm32g0xx_hal_tim.o + 0x0800838D HAL_TIM_ConfigClockSource 1 460 4 Code Gb stm32g0xx_hal_tim.o + 0x08008941 TIM_ITRx_SetConfig 48 4 Code Lc stm32g0xx_hal_tim.o + 0x08008971 HAL_TIM_SlaveConfigSynchro + 348 4 Code Gb stm32g0xx_hal_tim.o + 0x08008ACD TIM_SlaveTimer_SetConfig 960 4 Code Lc stm32g0xx_hal_tim.o + 0x08008E8D HAL_TIM_ReadCapturedValue 392 4 Code Gb stm32g0xx_hal_tim.o + 0x08009015 HAL_TIMEx_MasterConfigSynchronization + 632 4 Code Gb stm32g0xx_hal_tim_ex.o + 0x0800928D HAL_TIMEx_TISelection 304 4 Code Gb stm32g0xx_hal_tim_ex.o + 0x080093BD UART_SetConfig 1 712 4 Code Gb stm32g0xx_hal_uart.o + 0x08009A6D UART_AdvFeatureConfig 708 4 Code Gb stm32g0xx_hal_uart.o + 0x08009D31 UART_CheckIdleState 152 4 Code Gb stm32g0xx_hal_uart.o + 0x08009DC9 HAL_UART_DeInit 204 4 Code Gb stm32g0xx_hal_uart.o + 0x08009E95 HAL_UART_Transmit_IT 312 4 Code Gb stm32g0xx_hal_uart.o + 0x08009FCD UART_TxISR_16BIT_FIFOEN 140 4 Code Lc stm32g0xx_hal_uart.o + 0x0800A059 UART_TxISR_16BIT 96 4 Code Lc stm32g0xx_hal_uart.o + 0x0800A0B9 UART_Start_Receive_IT 368 4 Code Gb stm32g0xx_hal_uart.o + 0x0800A229 UART_RxISR_16BIT_FIFOEN 484 4 Code Lc stm32g0xx_hal_uart.o + 0x0800A40D UART_RxISR_8BIT_FIFOEN 480 4 Code Lc stm32g0xx_hal_uart.o + 0x0800A5ED HAL_RS485Ex_Init 348 4 Code Gb stm32g0xx_hal_uart_ex.o + 0x0800A749 UARTEx_SetNbDataToProcess 168 4 Code Lc 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0x0800B481 assert_failed 28 4 Code Gb main.o + 0x0800B49D HAL_MspInit 64 4 Code Gb stm32g0xx_hal_msp.o + 0x0800B4DD DMA1_Channel1_IRQHandler 16 4 Code Gb stm32g0xx_it.o + 0x0800B4ED ADC1_COMP_IRQHandler 16 4 Code Gb stm32g0xx_it.o + 0x0800B4FD USART1_IRQHandler 16 4 Code Gb stm32g0xx_it.o + 0x0800B50D USART3_USART4_LPUART1_IRQHandler + 16 4 Code Gb stm32g0xx_it.o + 0x0800B51D MX_TIM1_Init 272 4 Code Gb tim.o + 0x0800B62D HAL_TIM_Base_MspInit 112 4 Code Gb tim.o + 0x0800B69D MX_USART1_UART_Init 124 4 Code Gb usart.o + 0x0800B719 HAL_UART_MspInit 164 4 Code Gb usart.o + 0x0800B7BD HAL_UART_MspDeInit 60 4 Code Gb usart.o + 0x0800B7F9 BALANCER_Init 192 4 Code Gb balancer.o + 0x0800B8B9 BALANCER_Exec 924 4 Code Gb balancer.o + 0x0800BC55 BALANCER_SetStartImpulse 100 4 Code Gb balancer.o + 0x0800BCB9 calculateSetpoints 208 4 Code Gb bms.o + 0x0800BD89 BMS_Exec 1 328 4 Code Gb bms.o + 0x0800C2B9 EEPROM_isFirstStart 80 4 Code Gb eeprom.o + 0x0800C309 getEEPROMData 104 4 Code Lc eeprom.o + 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HAL_TIM_Base_Init 420 4 Code Gb stm32g0xx_hal_tim.o + RS485_ModbusEx_Init 404 4 Code Lc modbus.o + __aeabi_dmul_aux 394 2 Code Lc floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_TIM_ReadCapturedValue 392 4 Code Gb stm32g0xx_hal_tim.o + SystemCoreClockUpdate 372 4 Code Gb system_stm32g0xx.o + UART_Start_Receive_IT 368 4 Code Gb stm32g0xx_hal_uart.o + mbSlaveWriteMultipleRegisters + 352 4 Code Gb modbus.o + HAL_RS485Ex_Init 348 4 Code Gb stm32g0xx_hal_uart_ex.o + HAL_TIM_SlaveConfigSynchro + 348 4 Code Gb stm32g0xx_hal_tim.o + HAL_DMA_IRQHandler 320 4 Code Gb stm32g0xx_hal_dma.o + MX_GPIO_Init 320 4 Code Gb gpio.o + HAL_UART_Transmit_IT 312 4 Code Gb stm32g0xx_hal_uart.o + __aeabi_fadd 308 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_TIMEx_TISelection 304 4 Code Gb stm32g0xx_hal_tim_ex.o + mbSlaveWriteSingleRegister + 304 4 Code Gb modbus.o + EEPROM_storeLogData 296 4 Code Gb eeprom.o + HAL_ADC_Start_DMA 284 4 Code Gb stm32g0xx_hal_adc.o + fmodf 280 4 Code Wk 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208 4 Code Gb stm32g0xx_hal_tim.o + calculateSetpoints 208 4 Code Gb bms.o + HAL_UART_DeInit 204 4 Code Gb stm32g0xx_hal_uart.o + BALANCER_Init 192 4 Code Gb balancer.o + __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_DAC_Start 180 4 Code Gb stm32g0xx_hal_dac.o + TIM_TI1_SetConfig 180 4 Code Gb stm32g0xx_hal_tim.o + UART_RxISR_16BIT 180 2 Code Lc stm32g0xx_hal_uart.o + HAL_COMP_Start 176 4 Code Gb stm32g0xx_hal_comp.o + UART_RxISR_8BIT 176 2 Code Lc stm32g0xx_hal_uart.o + ADC_DMAConvCplt 168 2 Code Lc stm32g0xx_hal_adc.o + HAL_UARTEx_DisableFifoMode + 168 4 Code Gb stm32g0xx_hal_uart_ex.o + UARTEx_SetNbDataToProcess 168 4 Code Lc stm32g0xx_hal_uart_ex.o + ADC_Disable 164 2 Code Gb stm32g0xx_hal_adc.o + HAL_UART_MspInit 164 4 Code Gb usart.o + __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + FLASH_WaitForLastOperation + 156 4 Code Gb stm32g0xx_hal_flash.o + HAL_DAC_SetValue 152 4 Code Gb stm32g0xx_hal_dac.o + HAL_PWREx_ControlVoltageScaling + 152 4 Code Gb stm32g0xx_hal_pwr_ex.o + UART_CheckIdleState 152 4 Code Gb stm32g0xx_hal_uart.o + __aeabi_fdiv 148 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_UART_Receive_IT 146 2 Code Gb stm32g0xx_hal_uart.o + EEPROM_readLogData 144 4 Code Gb eeprom.o + UART_TxISR_16BIT_FIFOEN 140 4 Code Lc stm32g0xx_hal_uart.o + mbInit 140 2 Code Gb modbus.o + mbSlaveCheckModbusRtuQuery + 140 4 Code Gb modbus.o + __SEGGER_RTL_putc 138 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + SEGGER_RTT_WriteNoLock 132 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + SystemClock_Config 132 4 Code Gb main.o + __NVIC_SetPriority 128 4 Code Lc stm32g0xx_hal_cortex.o + strnlen 128 4 Code Wk strops.o (libc_v6m_t_le_eabi_balanced.a) + UART_TxISR_8BIT_FIFOEN 126 2 Code Lc stm32g0xx_hal_uart.o + MX_USART1_UART_Init 124 4 Code Gb usart.o + HAL_InitTick 120 4 Code Wk stm32g0xx_hal.o + MEAS_Init 120 4 Code Gb meas.o + vfprintf_l 120 4 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + FLASH_Program_Fast 116 4 Code Lc stm32g0xx_hal_flash.o + LED_ErrorExec 116 4 Code Gb led.o + mbCrc16 116 4 Code Gb modbus.o + mbSlaveProcessPdu 116 2 Code Gb modbus.o + TIM_TI4_SetConfig 114 2 Code Lc stm32g0xx_hal_tim.o + DMA_SetConfig 112 4 Code Lc stm32g0xx_hal_dma.o + HAL_TIM_Base_MspInit 112 4 Code Gb tim.o + TIM_TI2_SetConfig 110 2 Code Lc stm32g0xx_hal_tim.o + TIM_TI3_SetConfig 108 2 Code Lc stm32g0xx_hal_tim.o + UART_TxISR_8BIT 108 2 Code Lc modbus.o + HAL_DAC_MspInit 104 4 Code Gb dac.o + _WriteBlocking 104 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + getEEPROMData 104 4 Code Lc eeprom.o + BALANCER_SetStartImpulse 100 4 Code Gb balancer.o + HAL_DAC_Init 100 4 Code Gb stm32g0xx_hal_dac.o + HAL_GPIO_WritePin 100 4 Code Gb stm32g0xx_hal_gpio.o + __aeabi_d2f 98 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + MEAS_Exec 96 4 Code Gb meas.o + UART_TxISR_16BIT 96 4 Code Lc stm32g0xx_hal_uart.o + mbSlaveProcessRtuQuery 96 2 Code Gb modbus.o + FLASH_PageErase 92 4 Code Gb stm32g0xx_hal_flash_ex.o + LED_FunctionExec 92 4 Code Gb led.o + calcCellTemperature 92 4 Code Gb meas.o + LED_ErrorStartBlink 88 4 Code Gb led.o + floorf 88 4 Code Wk floatops.o (libc_v6m_t_le_eabi_balanced.a) + TIM_TI2_ConfigInputStage 84 2 Code Lc stm32g0xx_hal_tim.o + _DoInit 84 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + mb_save_lock_key 84 4 Code Gb main.o + UART_TxISR_8BIT 82 2 Code Lc stm32g0xx_hal_uart.o + EEPROM_isFirstStart 80 4 Code Gb eeprom.o + TIM_TI1_ConfigInputStage 80 2 Code Lc stm32g0xx_hal_tim.o + resetMinMaxValues 80 4 Code Gb main.o + HAL_SYSCFG_StrobeDBattpinsConfig + 76 4 Code Gb stm32g0xx_hal.o + LED_FunctionStartBlink 76 4 Code Gb led.o + SysTick_Config 76 4 Code Lc stm32g0xx_hal_cortex.o + resetCounters 76 4 Code Gb main.o + _WriteNoCheck 74 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + HAL_GPIO_ReadPin 72 4 Code Gb stm32g0xx_hal_gpio.o + MX_DAC1_Init 72 4 Code Gb dac.o + __SEGGER_RTL_pow10f 72 4 Code Gb utilops.o (libc_v6m_t_le_eabi_balanced.a) + mbCheckCrc16 72 2 Code Gb modbus.o + DMA_CalcDMAMUXChannelBaseAndMask + 68 4 Code Lc stm32g0xx_hal_dma.o + HAL_FLASH_Unlock 68 4 Code Gb stm32g0xx_hal_flash.o + HAL_GPIO_TogglePin 68 4 Code Gb stm32g0xx_hal_gpio.o + MX_COMP1_Init 68 4 Code Gb comp.o + MX_COMP2_Init 68 4 Code Gb comp.o + mbAppendCrc16 68 2 Code Gb modbus.o + HAL_MspInit 64 4 Code Gb stm32g0xx_hal_msp.o + __aeabi_f2ulz 64 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + applyMBParameter 64 4 Code Gb main.o + calcBalancerCurrent 64 4 Code Gb meas.o + HAL_Delay 60 4 Code Wk stm32g0xx_hal.o + HAL_UART_MspDeInit 60 4 Code Gb usart.o + SYSDATA_Init 60 4 Code Gb sysdata.o + calcCellVoltageFiltered 60 4 Code Gb meas.o + mbSlaveResponseException 58 2 Code Gb modbus.o + DMA_CalcDMAMUXRequestGenBaseAndMask + 56 4 Code Lc stm32g0xx_hal_dma.o + FLASH_MassErase 56 4 Code Lc stm32g0xx_hal_flash_ex.o + HAL_Init 56 4 Code Gb stm32g0xx_hal.o + __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + ldexpf 56 2 Code Wk floatops.o (libc_v6m_t_le_eabi_balanced.a) + TIM_ETR_SetConfig 54 2 Code Gb stm32g0xx_hal_tim.o + LED_ErrorOff 52 4 Code Gb led.o + LED_ErrorOn 52 4 Code Gb led.o + SEGGER_RTT_Write 52 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + __SEGGER_init_pack 52 2 Code Wk SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + fwrite 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_fcmpge 50 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_NVIC_DisableIRQ 48 4 Code Gb stm32g0xx_hal_cortex.o + HAL_NVIC_EnableIRQ 48 4 Code Gb stm32g0xx_hal_cortex.o + HAL_NVIC_SetPriority 48 4 Code Gb stm32g0xx_hal_cortex.o + MX_DMA_Init 48 4 Code Gb dma.o + TIM_ITRx_SetConfig 48 4 Code Lc stm32g0xx_hal_tim.o + __NVIC_DisableIRQ 48 4 Code Lc stm32g0xx_hal_cortex.o + __SEGGER_RTL_X_file_stat 48 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + LL_ADC_REG_SetSequencerRanks + 46 2 Code Lc stm32g0xx_hal_adc.o + __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_fcmpgt 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_fcmplt 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + FLASH_Program_DoubleWord 44 4 Code Lc stm32g0xx_hal_flash.o + HAL_FLASH_Lock 44 4 Code Gb stm32g0xx_hal_flash.o + __SEGGER_RTL_ascii_mbtowc 44 2 Code Gb mbops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ul2f 44 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + ADC_DMAError 42 2 Code Lc stm32g0xx_hal_adc.o + UART_EndTransmit_IT 42 2 Code Lc modbus.o + HAL_RCC_GetPCLK1Freq 40 4 Code Gb stm32g0xx_hal_rcc.o + LL_ADC_SetChannelSamplingTime + 40 4 Code Lc stm32g0xx_hal_adc.o + __NVIC_EnableIRQ 40 4 Code Lc stm32g0xx_hal_cortex.o + printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + LL_ADC_SetSamplingTimeCommonChannels + 38 2 Code Lc stm32g0xx_hal_adc.o + __aeabi_i2f 38 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + mbSend 38 2 Code Gb modbus.o + __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + calcCellVoltageUnfiltered 36 4 Code Gb meas.o + frexpf 36 2 Code Wk floatops.o (libc_v6m_t_le_eabi_balanced.a) + LL_ADC_EnableInternalRegulator + 32 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_SetSequencerChRem + 32 4 Code Lc stm32g0xx_hal_adc.o + __aeabi_fcmpeq 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + LL_ADC_Disable 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_Enable 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_SetSequencerChAdd + 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_StartConversion + 28 4 Code Lc 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stm32g0xx_hal_comp.o + LL_EXTI_DisableRisingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_EnableEvent_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_EnableFallingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_EnableIT_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_EnableRisingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + __SEGGER_RTL_current_locale + 24 4 Code Gb mbops.o (libc_v6m_t_le_eabi_balanced.a) + ADC_DMAHalfConvCplt 22 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_IsTriggerSourceSWStart + 22 2 Code Lc stm32g0xx_hal_adc.o + __SEGGER_RTL_pre_padding 22 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + mbClearRxFrame 22 2 Code Gb modbus.o + HAL_ADC_ConvCpltCallback 20 4 Code Gb meas.o + LL_ADC_IsCalibrationOnGoing + 20 2 Code Lc stm32g0xx_hal_adc_ex.o + LL_ADC_IsInternalRegulatorEnabled + 20 2 Code Lc stm32g0xx_hal_adc.o + LL_EXTI_ClearFallingFlag_0_31 + 20 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_ClearRisingFlag_0_31 + 20 4 Code Lc stm32g0xx_hal_comp.o + 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HAL_NVIC_EnableIRQ 48 4 Code RX stm32g0xx_hal_cortex.o + 08004f08-08004f2f __NVIC_EnableIRQ 40 4 Code RX stm32g0xx_hal_cortex.o + 08004f30-08004f5f HAL_NVIC_DisableIRQ 48 4 Code RX stm32g0xx_hal_cortex.o + 08004f60-08004f8f __NVIC_DisableIRQ 48 4 Code RX stm32g0xx_hal_cortex.o + 08004f90-08004fdb SysTick_Config 76 4 Code RX stm32g0xx_hal_cortex.o + 08004fdc-0800503f HAL_DAC_Init 100 4 Code RX stm32g0xx_hal_dac.o + 08005040-080050f3 HAL_DAC_Start 180 4 Code RX stm32g0xx_hal_dac.o + 080050f4-0800518b HAL_DAC_SetValue 152 4 Code RX stm32g0xx_hal_dac.o + 0800518c-080054db HAL_DAC_ConfigChannel 848 4 Code RX stm32g0xx_hal_dac.o + 080054dc-0800574b HAL_DMA_Init 624 4 Code RX stm32g0xx_hal_dma.o + 0800574c-0800578f DMA_CalcDMAMUXChannelBaseAndMask + 68 4 Code RX stm32g0xx_hal_dma.o + 08005790-080057c7 DMA_CalcDMAMUXRequestGenBaseAndMask + 56 4 Code RX stm32g0xx_hal_dma.o + 080057c8-08005837 DMA_SetConfig 112 4 Code RX stm32g0xx_hal_dma.o + 08005838-08005943 HAL_DMA_Start_IT 268 4 Code RX stm32g0xx_hal_dma.o + 08005944-08005a83 HAL_DMA_IRQHandler 320 4 Code RX stm32g0xx_hal_dma.o + 08005a84-08005b8f HAL_FLASH_Program 268 4 Code RX stm32g0xx_hal_flash.o + 08005b90-08005c2b FLASH_WaitForLastOperation + 156 4 Code RX stm32g0xx_hal_flash.o + 08005c2c-08005c57 FLASH_Program_DoubleWord 44 4 Code RX stm32g0xx_hal_flash.o + 08005c58-08005c9b HAL_FLASH_Unlock 68 4 Code RX stm32g0xx_hal_flash.o + 08005c9c-08005cc7 HAL_FLASH_Lock 44 4 Code RX stm32g0xx_hal_flash.o + 08005cc8-08005db3 HAL_FLASHEx_Erase 236 4 Code RX stm32g0xx_hal_flash_ex.o + 08005db4-08005deb FLASH_MassErase 56 4 Code RX stm32g0xx_hal_flash_ex.o + 08005dec-08005e47 FLASH_PageErase 92 4 Code RX stm32g0xx_hal_flash_ex.o + 08005e48-0800625f HAL_GPIO_Init 1 048 4 Code RX stm32g0xx_hal_gpio.o + 08006260-08006427 HAL_GPIO_DeInit 456 4 Code RX stm32g0xx_hal_gpio.o + 08006428-0800646f HAL_GPIO_ReadPin 72 4 Code RX stm32g0xx_hal_gpio.o + 08006470-080064d3 HAL_GPIO_WritePin 100 4 Code RX stm32g0xx_hal_gpio.o + 080064d4-08006517 HAL_GPIO_TogglePin 68 4 Code RX stm32g0xx_hal_gpio.o + 08006518-080065af HAL_PWREx_ControlVoltageScaling + 152 4 Code RX stm32g0xx_hal_pwr_ex.o + 080065b0-08006dd3 HAL_RCC_OscConfig 2 084 4 Code RX stm32g0xx_hal_rcc.o + 08006dd4-08007123 HAL_RCC_ClockConfig 848 4 Code RX stm32g0xx_hal_rcc.o + 08007124-08007227 HAL_RCC_GetSysClockFreq 260 4 Code RX stm32g0xx_hal_rcc.o + 08007228-08007233 HAL_RCC_GetHCLKFreq 12 4 Code RX stm32g0xx_hal_rcc.o + 08007234-0800725b HAL_RCC_GetPCLK1Freq 40 4 Code RX stm32g0xx_hal_rcc.o + 0800725c-0800726b LL_RCC_GetAPB1Prescaler 16 4 Code RX stm32g0xx_hal_rcc.o + 0800726c-0800780f HAL_RCCEx_PeriphCLKConfig 1 444 4 Code RX stm32g0xx_hal_rcc_ex.o + 08007810-080079b3 HAL_TIM_Base_Init 420 4 Code RX stm32g0xx_hal_tim.o + 080079b4-08007aa7 TIM_Base_SetConfig 244 4 Code RX stm32g0xx_hal_tim.o + 08007aa8-08007b77 TIM_CCxChannelCmd 208 4 Code RX stm32g0xx_hal_tim.o + 08007b78-08007d23 HAL_TIM_IC_Init 428 4 Code RX stm32g0xx_hal_tim.o + 08007d24-0800800f HAL_TIM_IC_Start 748 4 Code RX stm32g0xx_hal_tim.o + 08008010-080082a7 HAL_TIM_IC_ConfigChannel 664 4 Code RX stm32g0xx_hal_tim.o + 080082a8-0800835b TIM_TI1_SetConfig 180 4 Code RX stm32g0xx_hal_tim.o + 0800835c-0800890f HAL_TIM_ConfigClockSource 1 460 4 Code RX stm32g0xx_hal_tim.o + 08008910-0800893f TIM_ITRx_SetConfig 48 4 Code RX stm32g0xx_hal_tim.o + 08008940-08008a9b HAL_TIM_SlaveConfigSynchro + 348 4 Code RX stm32g0xx_hal_tim.o + 08008a9c-08008e5b TIM_SlaveTimer_SetConfig 960 4 Code RX stm32g0xx_hal_tim.o + 08008e5c-08008fe3 HAL_TIM_ReadCapturedValue 392 4 Code RX stm32g0xx_hal_tim.o + 08008fe4-0800925b HAL_TIMEx_MasterConfigSynchronization + 632 4 Code RX stm32g0xx_hal_tim_ex.o + 0800925c-0800938b HAL_TIMEx_TISelection 304 4 Code RX stm32g0xx_hal_tim_ex.o + 0800938c-08009a3b UART_SetConfig 1 712 4 Code RX stm32g0xx_hal_uart.o + 08009a3c-08009cff UART_AdvFeatureConfig 708 4 Code RX stm32g0xx_hal_uart.o + 08009d00-08009d97 UART_CheckIdleState 152 4 Code RX stm32g0xx_hal_uart.o + 08009d98-08009e63 HAL_UART_DeInit 204 4 Code RX stm32g0xx_hal_uart.o + 08009e64-08009f9b HAL_UART_Transmit_IT 312 4 Code RX stm32g0xx_hal_uart.o + 08009f9c-0800a027 UART_TxISR_16BIT_FIFOEN 140 4 Code RX stm32g0xx_hal_uart.o + 0800a028-0800a087 UART_TxISR_16BIT 96 4 Code RX stm32g0xx_hal_uart.o + 0800a088-0800a1f7 UART_Start_Receive_IT 368 4 Code RX stm32g0xx_hal_uart.o + 0800a1f8-0800a3db UART_RxISR_16BIT_FIFOEN 484 4 Code RX stm32g0xx_hal_uart.o + 0800a3dc-0800a5bb UART_RxISR_8BIT_FIFOEN 480 4 Code RX stm32g0xx_hal_uart.o + 0800a5bc-0800a717 HAL_RS485Ex_Init 348 4 Code RX stm32g0xx_hal_uart_ex.o + 0800a718-0800a7bf UARTEx_SetNbDataToProcess 168 4 Code RX stm32g0xx_hal_uart_ex.o + 0800a7c0-0800a867 HAL_UARTEx_DisableFifoMode + 168 4 Code RX stm32g0xx_hal_uart_ex.o + 0800a868-0800a96b HAL_UARTEx_SetTxFifoThreshold + 260 4 Code RX stm32g0xx_hal_uart_ex.o + 0800a96c-0800aa6f HAL_UARTEx_SetRxFifoThreshold + 260 4 Code RX stm32g0xx_hal_uart_ex.o + 0800aa70-0800aa9f MX_DMA_Init 48 4 Code RX dma.o + 0800aaa0-0800ab7f MX_ADC1_Init 224 4 Code RX adc.o + 0800ab80-0800ac73 HAL_ADC_MspInit 244 4 Code RX adc.o + 0800ac74-0800acb7 MX_COMP1_Init 68 4 Code RX comp.o + 0800acb8-0800acfb MX_COMP2_Init 68 4 Code RX comp.o + 0800acfc-0800addb HAL_COMP_MspInit 224 4 Code RX comp.o + 0800addc-0800ae23 MX_DAC1_Init 72 4 Code RX dac.o + 0800ae24-0800ae8b HAL_DAC_MspInit 104 4 Code RX dac.o + 0800ae8c-0800afab MX_GPIO_Init 288 4 Code RX gpio.o + 0800afac-0800b28f main 740 4 Code RX main.o + 0800b290-0800b313 SystemClock_Config 132 4 Code RX main.o + 0800b314-0800b32f __NVIC_SystemReset 28 4 Code RX main.o + 0800b330-0800b36f applyMBParameter 64 4 Code RX main.o + 0800b370-0800b3bb resetCounters 76 4 Code RX main.o + 0800b3bc-0800b40b resetMinMaxValues 80 4 Code RX main.o + 0800b40c-0800b45f mb_save_lock_key 84 4 Code RX main.o + 0800b460-0800b47b assert_failed 28 4 Code RX main.o + 0800b47c-0800b4bb HAL_MspInit 64 4 Code RX stm32g0xx_hal_msp.o + 0800b4bc-0800b4cb DMA1_Channel1_IRQHandler 16 4 Code RX stm32g0xx_it.o + 0800b4cc-0800b4db ADC1_COMP_IRQHandler 16 4 Code RX stm32g0xx_it.o + 0800b4dc-0800b4eb USART1_IRQHandler 16 4 Code RX stm32g0xx_it.o + 0800b4ec-0800b4fb USART3_USART4_LPUART1_IRQHandler + 16 4 Code RX stm32g0xx_it.o + 0800b4fc-0800b577 MX_USART1_UART_Init 124 4 Code RX usart.o + 0800b578-0800b61b HAL_UART_MspInit 164 4 Code RX usart.o + 0800b61c-0800b657 HAL_UART_MspDeInit 60 4 Code RX usart.o + 0800b658-0800b767 MX_TIM1_Init 272 4 Code RX tim.o + 0800b768-0800b7d7 HAL_TIM_Base_MspInit 112 4 Code RX tim.o + 0800b7d8-0800b7ff LED_ErrorOn 40 4 Code RX led.o + 0800b800-0800b823 LED_ErrorOff 36 4 Code RX led.o + 0800b824-0800b86f LED_ErrorStartBlink 76 4 Code RX led.o + 0800b870-0800b8cb LED_ErrorExec 92 4 Code RX led.o + 0800b8cc-0800b917 LED_FunctionStartBlink 76 4 Code RX led.o + 0800b918-0800b92f LED_FunctionSetTimes 24 4 Code RX led.o + 0800b930-0800b98b LED_FunctionExec 92 4 Code RX led.o + 0800b98c-0800b99f OUTPUT_OVP_Enable 20 4 Code RX output.o + 0800b9a0-0800b9b3 OUTPUT_LVP_Enable 20 4 Code RX output.o + 0800b9b4-0800b9c7 OUTPUT_OVP_Disable 20 4 Code RX output.o + 0800b9c8-0800b9db OUTPUT_LVP_Disable 20 4 Code RX output.o + 0800b9dc-0800ba53 MEAS_Init 120 4 Code RX meas.o + 0800ba54-0800bab3 MEAS_Exec 96 4 Code RX meas.o + 0800bab4-0800baf3 calcBalancerCurrent 64 4 Code RX meas.o + 0800baf4-0800bb2b calcCellVoltageFiltered 56 4 Code RX meas.o + 0800bb2c-0800bb4b calcCellVoltageUnfiltered 32 4 Code RX meas.o + 0800bb4c-0800bba7 calcCellTemperature 92 4 Code RX meas.o + 0800bba8-0800bbbb HAL_ADC_ConvCpltCallback 20 4 Code RX meas.o + 0800bbbc-0800bbf7 SYSDATA_Init 60 4 Code RX sysdata.o + 0800bbf8-0800bcb7 BALANCER_Init 192 4 Code RX balancer.o + 0800bcb8-0800c053 BALANCER_Exec 924 4 Code RX balancer.o + 0800c054-0800c0b7 BALANCER_SetStartImpulse 100 4 Code RX balancer.o + 0800c0b8-0800c18b mbUartInit 212 4 Code RX modbus.o + 0800c18c-0800c31f RS485_ModbusEx_Init 404 4 Code RX modbus.o + 0800c320-0800c59f MODBUS_UART_IRQHandler 640 4 Code RX modbus.o + 0800c5a0-0800c613 mbCrc16 116 4 Code RX modbus.o + 0800c614-0800c69f mbSlaveCheckModbusRtuQuery + 140 4 Code RX modbus.o + 0800c6a0-0800c79b mbSlaveReadHoldingRegisters + 252 4 Code RX modbus.o + 0800c79c-0800c8cb mbSlaveWriteSingleRegister + 304 4 Code RX modbus.o + 0800c8cc-0800ca2b mbSlaveWriteMultipleRegisters + 352 4 Code RX modbus.o + 0800ca2c-0800cafb calculateSetpoints 208 4 Code RX bms.o + 0800cafc-0800d02b BMS_Exec 1 328 4 Code RX bms.o + 0800d02c-0800d07b EEPROM_isFirstStart 80 4 Code RX eeprom.o + 0800d07c-0800d0e3 getEEPROMData 104 4 Code RX eeprom.o + 0800d0e4-0800d1bf EEPROM_fullRestore 220 4 Code RX eeprom.o + 0800d1c0-0800d367 EEPROM_readConfig 424 4 Code RX eeprom.o + 0800d368-0800d593 EEPROM_storeConfig 556 4 Code RX eeprom.o + 0800d594-0800d6bb EEPROM_storeLogData 296 4 Code RX eeprom.o + 0800d6bc-0800d7bf EEPROM_ResetLogData 260 4 Code RX eeprom.o + 0800d7c0-0800d84f EEPROM_readLogData 144 4 Code RX eeprom.o + 0800d850-0800d983 __aeabi_fadd 308 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800d984-0800d993 __aeabi_fsub 16 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800d994-0800da4b __aeabi_fmul 184 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800da4c-0800dadf __aeabi_fdiv 148 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800dae0-0800daff __aeabi_fcmpeq 32 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800db00-0800db33 __aeabi_fcmpge 52 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800db34-0800db63 __aeabi_fcmpgt 48 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800db64-0800db93 __aeabi_fcmplt 48 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800db94-0800dbb7 __aeabi_f2uiz 36 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800dbb8-0800dbe7 __aeabi_d2uiz 48 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800dbe8-0800dc27 __aeabi_f2ulz 64 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800dc28-0800dc4f __aeabi_i2f 40 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800dc50-0800dc6f __aeabi_ui2f 32 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800dc70-0800dc8b __aeabi_ui2d 28 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800dc8c-0800dcbb __aeabi_ul2f 48 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800dcbc-0800dd1f __aeabi_d2f 100 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800dd20-0800de23 fmodf 260 4 Code RX floatops.o (libc_v6m_t_le_eabi_balanced.a) + 0800de24-0800de7b floorf 88 4 Code RX floatops.o (libc_v6m_t_le_eabi_balanced.a) + 0800de7c-0800deab __aeabi_lmul 48 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800deac-0800deeb __aeabi_idiv 64 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800deec-0800defb __aeabi_idivmod 16 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800defc-0800df33 __aeabi_uidiv 56 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800df34-0800df43 __aeabi_uidivmod 16 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800df44-0800dfe3 __aeabi_uldivmod 160 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800dfe4-0800dfeb __aeabi_idiv0 8 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800dfec-0800e003 __SEGGER_RTL_current_locale + 24 4 Code RX mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0800e004-0800e01f __SEGGER_RTL_ascii_isctype + 28 4 Code RX mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0800e020-0800e03b __SEGGER_RTL_ascii_iswctype + 28 4 Code RX mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0800e03c-0800e04b strlen 16 4 Code RX strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800e04c-0800e05b memcpy 16 4 Code RX strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800e05c-0800e06f __aeabi_memclr 20 4 Code RX strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800e070-0800e0ef strnlen 128 4 Code RX strops.o (libc_v6m_t_le_eabi_balanced.a) + 0800e0f0-0800e133 __SEGGER_RTL_pow10f 68 4 Code RX utilops.o (libc_v6m_t_le_eabi_balanced.a) + 0800e134-0800e1ab vfprintf_l 120 4 Code RX prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0800e1ac-0800e1d3 printf 40 4 Code RX prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0800e1d4-0800eeeb __SEGGER_RTL_vfprintf_short_float_long + 3 352 4 Code RX __SEGGER_RTL_vfprintf_short_float_long.o (libc_v6m_t_le_eabi_balanced.a) + 0800eeec-0800ef1b __SEGGER_RTL_X_file_stat 48 4 Code RX prinops_rtt.o (prinops_rtt_v6m_little.a) + 0800ef1c-0800ef1f __SEGGER_RTL_X_file_bufsize + 4 4 Code RX prinops_rtt.o (prinops_rtt_v6m_little.a) + 0800ef20-0800ef2b __SEGGER_RTL_X_file_write 12 4 Code RX prinops_rtt.o (prinops_rtt_v6m_little.a) + 0800ef2c-0800ef83 _DoInit 88 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_little.a) + 0800ef84-0800efcf _WriteNoCheck 76 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_little.a) + 0800efd0-0800f037 _WriteBlocking 104 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_little.a) + 0800f038-0800f0bb SEGGER_RTT_WriteNoLock 132 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_little.a) + 0800f0bc-0800f0ef SEGGER_RTT_Write 52 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_little.a) + 0800f0f0-0800f103 __SEGGER_RTL_init_heap 20 4 Code RX heapops_basic.o (heapops_basic_v6m_little.a) + 0800f104-0800f143 defaultEepromData 64 4 Cnst RO eeprom.o + 0800f144-0800f14f __SEGGER_RTL_c_locale 12 4 Cnst RO mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0800f150-0800f16f __SEGGER_RTL_codeset_ascii + 32 4 Cnst RO mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0800f170-0800f1c7 __SEGGER_RTL_c_locale_data + 88 4 Cnst RO mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0800f1c8-0800f1df __SEGGER_RTL_aPower2f 24 4 Cnst RO utilops.o (libc_v6m_t_le_eabi_balanced.a) + 0800f1e0-0800f1f7 __SEGGER_init_heap 24 4 Code RX SEGGER_crtinit_v6m_little.o + 0800f1f8-0800f1fb [.init_array] 4 4 ---- -- STM32G0xx_Startup.o + 0800f1fc-0800f204 [.rodata._DoInit.str1.4] 9 4 Cnst RO SEGGER_RTT.o (prinops_rtt_v6m_little.a) + 0800f205-0800f27b [.rodata..L.str] 119 1 Cnst RO stm32g0xx_hal_flash.o + 0800f27c-0800f28c _aInitStr.0 17 4 Cnst RO SEGGER_RTT.o (prinops_rtt_v6m_little.a) + 0800f28d-0800f2a3 [.rodata..L.str.4] 23 1 Cnst RO main.o + 0800f2a4-0800f2a5 WWDG_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800f2a6-0800f2a7 PVD_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800f2a8-0800f2a9 RTC_STAMP_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800f2aa-0800f2ab FLASH_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800f2ac-0800f2ad RCC_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800f2ae-0800f2af EXTI0_1_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800f2b0-0800f2b1 EXTI2_3_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800f2b2-0800f2b3 EXTI4_15_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800f2b4-0800f2b5 UCPD1_UCPD2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800f2b6-0800f2b7 DMA_Channel2_3_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800f2b8-0800f2b9 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__SEGGER_RTL_heap_globals 4 4 Zero ZI heapops_basic.o (heapops_basic_v6m_little.a) + 20000b50-20000b53 BMS_Exec.ledErrorBlinkState + 4 4 Zero ZI bms.o + 20000b54-20000b5b aADCxConvertedData 8 2 Zero ZI meas.o + 20000b5c-20000b5d savedLockKey 2 2 Zero ZI main.o + 20000b5e-20000b5f keyAccepted 2 2 Zero ZI main.o + 20000b60-20000b73 __SEGGER_RTL_global_locale + 20 4 Init RW mbops.o (libc_v6m_t_le_eabi_balanced.a) + 20000b74-20000b77 uwTickPrio 4 4 Init RW stm32g0xx_hal.o + 20000b78-20000b7b stdout 4 4 Init RW prinops_rtt.o (prinops_rtt_v6m_little.a) + 20000b7c-20000b7f stdin 4 4 Init RW prinops_rtt.o (prinops_rtt_v6m_little.a) + 20000b80-20000b83 stderr 4 4 Init RW prinops_rtt.o (prinops_rtt_v6m_little.a) + 20000b84-20000b87 initRefresh 4 4 Init RW bms.o + 20000b88-20000b8b balancerRegulationCounter 4 4 Init RW balancer.o + 20000b8c-20000b8f SystemCoreClock 4 4 Init RW system_stm32g0xx.o + 20000b90-20000c2b accessModeTable 156 1 Init RW sysdata.o + 20000c2c-20000c2c uwTickFreq 1 1 Init RW stm32g0xx_hal.o + 20000c2d-20000c2f ( UNUSED .=.+3 ) 3 - ---- - - + 20000c30-20000ca3 FLASH_Program_Fast 116 4 Code RX stm32g0xx_hal_flash.o + 20000ca4-20000ca7 ( UNUSED .=.+4 ) 4 - ---- - - + 20000ca8-200010a7 [.bss.block.heap] 1 024 8 None ZI [ Linker created ] + 200010a8-200077ff ( UNUSED .=.+26456 ) 26 456 - ---- - - + 20007800-20007fff [.bss.block.stack] 2 048 8 None ZI [ Linker created ] + + +*********************************************************************************************** +*** *** +*** SYMBOL LIST *** +*** *** +*********************************************************************************************** + +Function symbols by name: + + Symbol name Address Size Align Type Bd Object File + ------------------------- ---------- ---------- ----- ---- -- ----------- + ADC1_COMP_IRQHandler 0x0800B4CD 16 4 Code Gb stm32g0xx_it.o + ADC_COMP_IRQHandler 0x0800FF6F 8 2 Code Gb stm32g0xx_it.o + ADC_DMAConvCplt 0x0800FA8B 168 2 Code Lc stm32g0xx_hal_adc.o + ADC_DMAError 0x0800F341 42 2 Code Lc stm32g0xx_hal_adc.o + ADC_DMAHalfConvCplt 0x0800F32B 22 2 Code Lc stm32g0xx_hal_adc.o + ADC_Disable 0x0800F9E7 164 2 Code Gb stm32g0xx_hal_adc.o + ADC_Enable 0x08003C11 224 4 Code Gb stm32g0xx_hal_adc.o + AES_RNG_IRQHandler 0x0800F2DB 2 Code Wk STM32G07x_Vectors.o + BALANCER_Exec 0x0800BCB9 924 4 Code Gb balancer.o + BALANCER_Init 0x0800BBF9 192 4 Code Gb balancer.o + BALANCER_SetStartImpulse 0x0800C055 100 4 Code Gb balancer.o + BMS_Exec 0x0800CAFD 1 328 4 Code Gb bms.o + CEC_IRQHandler 0x0800F2D9 2 Code Wk STM32G07x_Vectors.o + DMA1_Channel1_IRQHandler 0x0800B4BD 16 4 Code Gb stm32g0xx_it.o + DMA_CalcDMAMUXChannelBaseAndMask + 0x0800574D 68 4 Code Lc stm32g0xx_hal_dma.o + DMA_CalcDMAMUXRequestGenBaseAndMask + 0x08005791 56 4 Code Lc stm32g0xx_hal_dma.o + DMA_Channel1_IRQHandler 0x0800FF67 8 2 Code Gb stm32g0xx_it.o + DMA_Channel2_3_IRQHandler 0x0800F2B7 2 Code Wk STM32G07x_Vectors.o + DMA_Channel4_5_6_7_IRQHandler + 0x0800F2B9 2 Code Wk STM32G07x_Vectors.o + DMA_SetConfig 0x080057C9 112 4 Code Lc stm32g0xx_hal_dma.o + EEPROM_ResetLogData 0x0800D6BD 260 4 Code Gb eeprom.o + EEPROM_fullRestore 0x0800D0E5 220 4 Code Gb eeprom.o + EEPROM_isFirstStart 0x0800D02D 80 4 Code Gb eeprom.o + EEPROM_readConfig 0x0800D1C1 424 4 Code Gb eeprom.o + EEPROM_readLogData 0x0800D7C1 144 4 Code Gb eeprom.o + EEPROM_storeConfig 0x0800D369 556 4 Code Gb eeprom.o + EEPROM_storeLogData 0x0800D595 296 4 Code Gb eeprom.o + EXTI0_1_IRQHandler 0x0800F2AF 2 Code Wk STM32G07x_Vectors.o + EXTI2_3_IRQHandler 0x0800F2B1 2 Code Wk STM32G07x_Vectors.o + EXTI4_15_IRQHandler 0x0800F2B3 2 Code Wk STM32G07x_Vectors.o + Error_Handler 0x0800FF5B 4 2 Code Gb main.o + FLASH_IRQHandler 0x0800F2AB 2 Code Wk STM32G07x_Vectors.o + FLASH_MassErase 0x08005DB5 56 4 Code Lc stm32g0xx_hal_flash_ex.o + FLASH_PageErase 0x08005DED 92 4 Code Gb stm32g0xx_hal_flash_ex.o + FLASH_Program_DoubleWord 0x08005C2D 44 4 Code Lc stm32g0xx_hal_flash.o + FLASH_Program_Fast 0x20000C31 116 4 Code Lc stm32g0xx_hal_flash.o + FLASH_Program_Fast__TT_veneer_T16_LDR_BX + 0x08005B81 4 Code Lc [ Linker created ] + FLASH_WaitForLastOperation + 0x08005B91 156 4 Code Gb stm32g0xx_hal_flash.o + HAL_ADCEx_Calibration_Start + 0x080046FD 264 4 Code Gb stm32g0xx_hal_adc_ex.o + HAL_ADCEx_ChannelConfigReadyCallback + 0x0800FBB3 8 2 Code Wk stm32g0xx_hal_adc_ex.o + HAL_ADCEx_EndOfSamplingCallback + 0x0800FBAB 8 2 Code Wk stm32g0xx_hal_adc_ex.o + HAL_ADCEx_LevelOutOfWindow2Callback + 0x0800FB9B 8 2 Code Wk stm32g0xx_hal_adc_ex.o + HAL_ADCEx_LevelOutOfWindow3Callback + 0x0800FBA3 8 2 Code Wk stm32g0xx_hal_adc_ex.o + HAL_ADC_ConfigChannel 0x08004095 1 512 4 Code Gb stm32g0xx_hal_adc.o + HAL_ADC_ConvCpltCallback 0x0800BBA9 20 4 Code Gb meas.o + HAL_ADC_ConvHalfCpltCallback + 0x0800FB53 8 2 Code Wk stm32g0xx_hal_adc.o + HAL_ADC_ErrorCallback 0x0800FB4B 8 2 Code Wk stm32g0xx_hal_adc.o + HAL_ADC_IRQHandler 0x08003E45 592 4 Code Gb stm32g0xx_hal_adc.o + HAL_ADC_Init 0x080034B5 1 852 4 Code Gb stm32g0xx_hal_adc.o + HAL_ADC_LevelOutOfWindowCallback + 0x0800FB33 8 2 Code Wk stm32g0xx_hal_adc.o + HAL_ADC_MspInit 0x0800AB81 244 4 Code Gb adc.o + HAL_ADC_Start_DMA 0x08003D0D 284 4 Code Gb stm32g0xx_hal_adc.o + HAL_COMP_Init 0x08004805 1 164 4 Code Gb stm32g0xx_hal_comp.o + HAL_COMP_MspInit 0x0800ACFD 224 4 Code Gb comp.o + HAL_COMP_Start 0x08004D79 176 4 Code Gb stm32g0xx_hal_comp.o + HAL_DAC_ConfigChannel 0x0800518D 848 4 Code Gb stm32g0xx_hal_dac.o + HAL_DAC_Init 0x08004FDD 100 4 Code Gb stm32g0xx_hal_dac.o + HAL_DAC_MspInit 0x0800AE25 104 4 Code Gb dac.o + HAL_DAC_SetValue 0x080050F5 152 4 Code Gb stm32g0xx_hal_dac.o + HAL_DAC_Start 0x08005041 180 4 Code Gb stm32g0xx_hal_dac.o + HAL_DMA_IRQHandler 0x08005945 320 4 Code Gb stm32g0xx_hal_dma.o + HAL_DMA_Init 0x080054DD 624 4 Code Gb stm32g0xx_hal_dma.o + HAL_DMA_Start_IT 0x08005839 268 4 Code Gb stm32g0xx_hal_dma.o + HAL_Delay 0x0800342D 60 4 Code Wk stm32g0xx_hal.o + HAL_FLASHEx_Erase 0x08005CC9 236 4 Code Gb stm32g0xx_hal_flash_ex.o + HAL_FLASH_Lock 0x08005C9D 44 4 Code Gb stm32g0xx_hal_flash.o + HAL_FLASH_Program 0x08005A85 252 4 Code Gb stm32g0xx_hal_flash.o + HAL_FLASH_Unlock 0x08005C59 68 4 Code Gb stm32g0xx_hal_flash.o + HAL_GPIO_DeInit 0x08006261 456 4 Code Gb stm32g0xx_hal_gpio.o + HAL_GPIO_Init 0x08005E49 1 048 4 Code Gb stm32g0xx_hal_gpio.o + HAL_GPIO_ReadPin 0x08006429 72 4 Code Gb stm32g0xx_hal_gpio.o + HAL_GPIO_TogglePin 0x080064D5 68 4 Code Gb stm32g0xx_hal_gpio.o + HAL_GPIO_WritePin 0x08006471 100 4 Code Gb stm32g0xx_hal_gpio.o + HAL_GetTick 0x08003421 12 4 Code Wk stm32g0xx_hal.o + HAL_IncTick 0x08003409 24 4 Code Wk stm32g0xx_hal.o + HAL_Init 0x08003359 56 4 Code Gb stm32g0xx_hal.o + HAL_InitTick 0x08003391 120 4 Code Wk stm32g0xx_hal.o + HAL_MspInit 0x0800B47D 64 4 Code Gb stm32g0xx_hal_msp.o + HAL_NVIC_DisableIRQ 0x08004F31 48 4 Code Gb stm32g0xx_hal_cortex.o + HAL_NVIC_EnableIRQ 0x08004ED9 48 4 Code Gb stm32g0xx_hal_cortex.o + HAL_NVIC_SetPriority 0x08004E29 48 4 Code Gb stm32g0xx_hal_cortex.o + HAL_PWREx_ControlVoltageScaling + 0x08006519 152 4 Code Gb stm32g0xx_hal_pwr_ex.o + HAL_RCCEx_PeriphCLKConfig 0x0800726D 1 444 4 Code Gb stm32g0xx_hal_rcc_ex.o + HAL_RCC_ClockConfig 0x08006DD5 848 4 Code Gb stm32g0xx_hal_rcc.o + HAL_RCC_GetHCLKFreq 0x08007229 12 4 Code Gb stm32g0xx_hal_rcc.o + HAL_RCC_GetPCLK1Freq 0x08007235 40 4 Code Gb stm32g0xx_hal_rcc.o + HAL_RCC_GetSysClockFreq 0x08007125 260 4 Code Gb stm32g0xx_hal_rcc.o + HAL_RCC_OscConfig 0x080065B1 2 084 4 Code Gb stm32g0xx_hal_rcc.o + HAL_RS485Ex_Init 0x0800A5BD 348 4 Code Gb stm32g0xx_hal_uart_ex.o + HAL_SYSCFG_StrobeDBattpinsConfig + 0x08003469 76 4 Code Gb stm32g0xx_hal.o + HAL_SYSTICK_Config 0x0800FBBB 16 2 Code Gb stm32g0xx_hal_cortex.o + HAL_TIMEx_MasterConfigSynchronization + 0x08008FE5 632 4 Code Gb stm32g0xx_hal_tim_ex.o + HAL_TIMEx_TISelection 0x0800925D 304 4 Code Gb stm32g0xx_hal_tim_ex.o + HAL_TIM_Base_Init 0x08007811 420 4 Code Gb stm32g0xx_hal_tim.o + HAL_TIM_Base_MspInit 0x0800B769 112 4 Code Gb tim.o + HAL_TIM_ConfigClockSource 0x0800835D 1 460 4 Code Gb stm32g0xx_hal_tim.o + HAL_TIM_IC_ConfigChannel 0x08008011 664 4 Code Gb stm32g0xx_hal_tim.o + HAL_TIM_IC_Init 0x08007B79 428 4 Code Gb stm32g0xx_hal_tim.o + HAL_TIM_IC_MspInit 0x0800FBCB 8 2 Code Wk stm32g0xx_hal_tim.o + HAL_TIM_IC_Start 0x08007D25 748 4 Code Gb stm32g0xx_hal_tim.o + HAL_TIM_ReadCapturedValue 0x08008E5D 392 4 Code Gb stm32g0xx_hal_tim.o + HAL_TIM_SlaveConfigSynchro + 0x08008941 348 4 Code Gb stm32g0xx_hal_tim.o + HAL_UARTEx_DisableFifoMode + 0x0800A7C1 168 4 Code Gb stm32g0xx_hal_uart_ex.o + HAL_UARTEx_RxEventCallback + 0x0800FDDB 12 2 Code Wk stm32g0xx_hal_uart.o + HAL_UARTEx_SetRxFifoThreshold + 0x0800A96D 260 4 Code Gb stm32g0xx_hal_uart_ex.o + HAL_UARTEx_SetTxFifoThreshold + 0x0800A869 260 4 Code Gb stm32g0xx_hal_uart_ex.o + HAL_UART_DeInit 0x08009D99 204 4 Code Gb stm32g0xx_hal_uart.o + HAL_UART_ErrorCallback 0x0800FDD3 8 2 Code Wk stm32g0xx_hal_uart.o + HAL_UART_MspDeInit 0x0800B61D 60 4 Code Gb usart.o + HAL_UART_MspInit 0x0800B579 164 4 Code Gb usart.o + HAL_UART_Receive_IT 0x0800F5A3 146 2 Code Gb stm32g0xx_hal_uart.o + HAL_UART_RxCpltCallback 0x0800FDEF 8 2 Code Wk stm32g0xx_hal_uart.o + HAL_UART_Transmit_IT 0x08009E65 312 4 Code Gb stm32g0xx_hal_uart.o + HAL_UART_TxCpltCallback 0x0800FDE7 8 2 Code Wk stm32g0xx_hal_uart.o + HardFault_Handler 0x0800F637 2 2 Code Gb stm32g0xx_it.o + I2C1_IRQHandler 0x0800F2CF 2 Code Wk STM32G07x_Vectors.o + I2C2_IRQHandler 0x0800F2D1 2 Code Wk STM32G07x_Vectors.o + LED_ErrorExec 0x0800B871 92 4 Code Gb led.o + LED_ErrorOff 0x0800B801 36 4 Code Gb led.o + LED_ErrorOn 0x0800B7D9 40 4 Code Gb led.o + LED_ErrorStartBlink 0x0800B825 76 4 Code Gb led.o + LED_Exec 0x0800FF77 12 2 Code Gb led.o + LED_FunctionExec 0x0800B931 92 4 Code Gb led.o + LED_FunctionSetTimes 0x0800B919 24 4 Code Gb led.o + LED_FunctionStartBlink 0x0800B8CD 76 4 Code Gb led.o + LL_ADC_Disable 0x08003E29 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_Enable 0x080046E1 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_EnableInternalRegulator + 0x08003BF1 32 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_GetCommonPathInternalCh + 0x0800F399 18 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_IsCalibrationOnGoing + 0x0800FB87 20 2 Code Lc stm32g0xx_hal_adc_ex.o + LL_ADC_IsDisableOngoing 0x0800F3AB 18 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_IsEnabled 0x0800F9D7 16 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_IsEnabled 0x0800FB77 16 2 Code Lc stm32g0xx_hal_adc_ex.o + LL_ADC_IsInternalRegulatorEnabled + 0x0800F9C3 20 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_GetDMATransfer 0x0800FB3B 16 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_IsConversionOngoing + 0x0800F2DD 18 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_IsTriggerSourceSWStart + 0x0800F315 22 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_SetSequencerChAdd + 0x0800467D 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_SetSequencerChRem + 0x080046C1 32 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_SetSequencerRanks + 0x0800F36B 46 2 Code Lc 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(libc_v6m_t_le_eabi_balanced.a) + getEEPROMData 0x0800D07D 104 4 Code Lc eeprom.o + ldexpf 0x08010223 56 2 Code Wk floatops.o (libc_v6m_t_le_eabi_balanced.a) + main 0x0800AFAD 740 4 Code Gb main.o + mbAppendCrc16 0x080100C3 68 2 Code Gb modbus.o + mbCheckCrc16 0x0801007B 72 2 Code Gb modbus.o + mbClearRxFrame 0x0800F69F 22 2 Code Gb modbus.o + mbClearTxBuffer 0x0800F68D 18 2 Code Gb modbus.o + mbCrc16 0x0800C5A1 116 4 Code Gb modbus.o + mbGetFrameComplete 0x08010107 16 2 Code Gb modbus.o + mbInit 0x0800FF83 140 2 Code Gb modbus.o + mbSend 0x0800F667 38 2 Code Gb modbus.o + mbSlaveCheckModbusRtuQuery + 0x0800C615 140 4 Code Gb modbus.o + mbSlaveProcessPdu 0x08010177 116 2 Code Gb modbus.o + mbSlaveProcessRtuQuery 0x08010117 96 2 Code Gb modbus.o + mbSlaveReadHoldingRegisters + 0x0800C6A1 252 4 Code Gb modbus.o + mbSlaveResponseException 0x0800F6B5 58 2 Code Gb modbus.o + mbSlaveWriteMultipleRegisters + 0x0800C8CD 352 4 Code Gb modbus.o + mbSlaveWriteSingleRegister + 0x0800C79D 304 4 Code Gb modbus.o + mbUartInit 0x0800C0B9 212 4 Code Gb modbus.o + mb_save_lock_key 0x0800B40D 84 4 Code Gb main.o + memcpy 0x0800E04D 14 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + memset 0x0800E065 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + printf 0x0800E1AD 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + resetCounters 0x0800B371 76 4 Code Gb main.o + resetMinMaxValues 0x0800B3BD 80 4 Code Gb main.o + reset_handler 0x0800F9BB 2 Code Gb STM32G0xx_Startup.o + strlen 0x0800E03D 14 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + strnlen 0x0800E071 128 4 Code Wk strops.o (libc_v6m_t_le_eabi_balanced.a) + vfprintf 0x0800F9A1 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + vfprintf_l 0x0800E135 120 4 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + +Function symbols by address: + + Address Symbol name Size Align Type Bd Object File + ---------- ------------------------- ---------- ----- ---- -- ----------- + 0x08003161 SystemInit 16 4 Code Gb system_stm32g0xx.o + 0x08003171 SystemCoreClockUpdate 372 4 Code Gb system_stm32g0xx.o + 0x080032E5 _start 14 4 Code Gb SEGGER_THUMB_Startup.o + 0x080032EF __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + 0x080032F3 exit 2 4 Code Gb SEGGER_THUMB_Startup.o + 0x08003359 HAL_Init 56 4 Code Gb stm32g0xx_hal.o + 0x08003391 HAL_InitTick 120 4 Code Wk stm32g0xx_hal.o + 0x08003409 HAL_IncTick 24 4 Code Wk stm32g0xx_hal.o + 0x08003421 HAL_GetTick 12 4 Code Wk stm32g0xx_hal.o + 0x0800342D HAL_Delay 60 4 Code Wk stm32g0xx_hal.o + 0x08003469 HAL_SYSCFG_StrobeDBattpinsConfig + 76 4 Code Gb stm32g0xx_hal.o + 0x080034B5 HAL_ADC_Init 1 852 4 Code Gb stm32g0xx_hal_adc.o + 0x08003BF1 LL_ADC_EnableInternalRegulator + 32 4 Code Lc stm32g0xx_hal_adc.o + 0x08003C11 ADC_Enable 224 4 Code Gb stm32g0xx_hal_adc.o + 0x08003CF1 LL_ADC_REG_StartConversion + 28 4 Code Lc stm32g0xx_hal_adc.o + 0x08003D0D HAL_ADC_Start_DMA 284 4 Code Gb stm32g0xx_hal_adc.o + 0x08003E29 LL_ADC_Disable 28 4 Code Lc stm32g0xx_hal_adc.o + 0x08003E45 HAL_ADC_IRQHandler 592 4 Code Gb stm32g0xx_hal_adc.o + 0x08004095 HAL_ADC_ConfigChannel 1 512 4 Code Gb stm32g0xx_hal_adc.o + 0x0800467D LL_ADC_REG_SetSequencerChAdd + 28 4 Code Lc stm32g0xx_hal_adc.o + 0x08004699 LL_ADC_SetChannelSamplingTime + 40 4 Code Lc stm32g0xx_hal_adc.o + 0x080046C1 LL_ADC_REG_SetSequencerChRem + 32 4 Code Lc stm32g0xx_hal_adc.o + 0x080046E1 LL_ADC_Enable 28 4 Code Lc stm32g0xx_hal_adc.o + 0x080046FD HAL_ADCEx_Calibration_Start + 264 4 Code Gb stm32g0xx_hal_adc_ex.o + 0x08004805 HAL_COMP_Init 1 164 4 Code Gb stm32g0xx_hal_comp.o + 0x08004C91 LL_EXTI_EnableRisingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004CA9 LL_EXTI_DisableRisingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004CC1 LL_EXTI_EnableFallingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004CD9 LL_EXTI_DisableFallingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004CF1 LL_EXTI_ClearRisingFlag_0_31 + 20 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D05 LL_EXTI_ClearFallingFlag_0_31 + 20 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D19 LL_EXTI_EnableEvent_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D31 LL_EXTI_DisableEvent_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D49 LL_EXTI_EnableIT_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D61 LL_EXTI_DisableIT_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + 0x08004D79 HAL_COMP_Start 176 4 Code Gb stm32g0xx_hal_comp.o + 0x08004E29 HAL_NVIC_SetPriority 48 4 Code Gb stm32g0xx_hal_cortex.o + 0x08004E59 __NVIC_SetPriority 128 4 Code Lc stm32g0xx_hal_cortex.o + 0x08004ED9 HAL_NVIC_EnableIRQ 48 4 Code Gb stm32g0xx_hal_cortex.o + 0x08004F09 __NVIC_EnableIRQ 40 4 Code Lc stm32g0xx_hal_cortex.o + 0x08004F31 HAL_NVIC_DisableIRQ 48 4 Code Gb stm32g0xx_hal_cortex.o + 0x08004F61 __NVIC_DisableIRQ 48 4 Code Lc stm32g0xx_hal_cortex.o + 0x08004F91 SysTick_Config 76 4 Code Lc stm32g0xx_hal_cortex.o + 0x08004FDD HAL_DAC_Init 100 4 Code Gb stm32g0xx_hal_dac.o + 0x08005041 HAL_DAC_Start 180 4 Code Gb stm32g0xx_hal_dac.o + 0x080050F5 HAL_DAC_SetValue 152 4 Code Gb stm32g0xx_hal_dac.o + 0x0800518D HAL_DAC_ConfigChannel 848 4 Code Gb stm32g0xx_hal_dac.o + 0x080054DD HAL_DMA_Init 624 4 Code Gb stm32g0xx_hal_dma.o + 0x0800574D DMA_CalcDMAMUXChannelBaseAndMask + 68 4 Code Lc stm32g0xx_hal_dma.o + 0x08005791 DMA_CalcDMAMUXRequestGenBaseAndMask + 56 4 Code Lc stm32g0xx_hal_dma.o + 0x080057C9 DMA_SetConfig 112 4 Code Lc stm32g0xx_hal_dma.o + 0x08005839 HAL_DMA_Start_IT 268 4 Code Gb stm32g0xx_hal_dma.o + 0x08005945 HAL_DMA_IRQHandler 320 4 Code Gb stm32g0xx_hal_dma.o + 0x08005A85 HAL_FLASH_Program 252 4 Code Gb stm32g0xx_hal_flash.o + 0x08005B81 FLASH_Program_Fast__TT_veneer_T16_LDR_BX + 4 Code Lc [ Linker created ] + 0x08005B91 FLASH_WaitForLastOperation + 156 4 Code Gb stm32g0xx_hal_flash.o + 0x08005C2D FLASH_Program_DoubleWord 44 4 Code Lc stm32g0xx_hal_flash.o + 0x08005C59 HAL_FLASH_Unlock 68 4 Code Gb stm32g0xx_hal_flash.o + 0x08005C9D HAL_FLASH_Lock 44 4 Code Gb stm32g0xx_hal_flash.o + 0x08005CC9 HAL_FLASHEx_Erase 236 4 Code Gb stm32g0xx_hal_flash_ex.o + 0x08005DB5 FLASH_MassErase 56 4 Code Lc stm32g0xx_hal_flash_ex.o + 0x08005DED FLASH_PageErase 92 4 Code Gb stm32g0xx_hal_flash_ex.o + 0x08005E49 HAL_GPIO_Init 1 048 4 Code Gb stm32g0xx_hal_gpio.o + 0x08006261 HAL_GPIO_DeInit 456 4 Code Gb stm32g0xx_hal_gpio.o + 0x08006429 HAL_GPIO_ReadPin 72 4 Code Gb stm32g0xx_hal_gpio.o + 0x08006471 HAL_GPIO_WritePin 100 4 Code Gb stm32g0xx_hal_gpio.o + 0x080064D5 HAL_GPIO_TogglePin 68 4 Code Gb stm32g0xx_hal_gpio.o + 0x08006519 HAL_PWREx_ControlVoltageScaling + 152 4 Code Gb stm32g0xx_hal_pwr_ex.o + 0x080065B1 HAL_RCC_OscConfig 2 084 4 Code Gb stm32g0xx_hal_rcc.o + 0x08006DD5 HAL_RCC_ClockConfig 848 4 Code Gb stm32g0xx_hal_rcc.o + 0x08007125 HAL_RCC_GetSysClockFreq 260 4 Code Gb stm32g0xx_hal_rcc.o + 0x08007229 HAL_RCC_GetHCLKFreq 12 4 Code Gb stm32g0xx_hal_rcc.o + 0x08007235 HAL_RCC_GetPCLK1Freq 40 4 Code Gb stm32g0xx_hal_rcc.o + 0x0800725D LL_RCC_GetAPB1Prescaler 16 4 Code Lc stm32g0xx_hal_rcc.o + 0x0800726D HAL_RCCEx_PeriphCLKConfig 1 444 4 Code Gb stm32g0xx_hal_rcc_ex.o + 0x08007811 HAL_TIM_Base_Init 420 4 Code Gb stm32g0xx_hal_tim.o + 0x080079B5 TIM_Base_SetConfig 244 4 Code Gb stm32g0xx_hal_tim.o + 0x08007AA9 TIM_CCxChannelCmd 208 4 Code Gb stm32g0xx_hal_tim.o + 0x08007B79 HAL_TIM_IC_Init 428 4 Code Gb stm32g0xx_hal_tim.o + 0x08007D25 HAL_TIM_IC_Start 748 4 Code Gb stm32g0xx_hal_tim.o + 0x08008011 HAL_TIM_IC_ConfigChannel 664 4 Code Gb stm32g0xx_hal_tim.o + 0x080082A9 TIM_TI1_SetConfig 180 4 Code Gb stm32g0xx_hal_tim.o + 0x0800835D HAL_TIM_ConfigClockSource 1 460 4 Code Gb stm32g0xx_hal_tim.o + 0x08008911 TIM_ITRx_SetConfig 48 4 Code Lc stm32g0xx_hal_tim.o + 0x08008941 HAL_TIM_SlaveConfigSynchro + 348 4 Code Gb stm32g0xx_hal_tim.o + 0x08008A9D TIM_SlaveTimer_SetConfig 960 4 Code Lc stm32g0xx_hal_tim.o + 0x08008E5D HAL_TIM_ReadCapturedValue 392 4 Code Gb stm32g0xx_hal_tim.o + 0x08008FE5 HAL_TIMEx_MasterConfigSynchronization + 632 4 Code Gb stm32g0xx_hal_tim_ex.o + 0x0800925D HAL_TIMEx_TISelection 304 4 Code Gb stm32g0xx_hal_tim_ex.o + 0x0800938D UART_SetConfig 1 712 4 Code Gb stm32g0xx_hal_uart.o + 0x08009A3D UART_AdvFeatureConfig 708 4 Code Gb stm32g0xx_hal_uart.o + 0x08009D01 UART_CheckIdleState 152 4 Code Gb stm32g0xx_hal_uart.o + 0x08009D99 HAL_UART_DeInit 204 4 Code Gb stm32g0xx_hal_uart.o + 0x08009E65 HAL_UART_Transmit_IT 312 4 Code Gb stm32g0xx_hal_uart.o + 0x08009F9D UART_TxISR_16BIT_FIFOEN 140 4 Code Lc stm32g0xx_hal_uart.o + 0x0800A029 UART_TxISR_16BIT 96 4 Code Lc stm32g0xx_hal_uart.o + 0x0800A089 UART_Start_Receive_IT 368 4 Code Gb stm32g0xx_hal_uart.o + 0x0800A1F9 UART_RxISR_16BIT_FIFOEN 484 4 Code Lc stm32g0xx_hal_uart.o + 0x0800A3DD UART_RxISR_8BIT_FIFOEN 480 4 Code Lc stm32g0xx_hal_uart.o + 0x0800A5BD HAL_RS485Ex_Init 348 4 Code Gb stm32g0xx_hal_uart_ex.o + 0x0800A719 UARTEx_SetNbDataToProcess 168 4 Code Lc stm32g0xx_hal_uart_ex.o + 0x0800A7C1 HAL_UARTEx_DisableFifoMode + 168 4 Code Gb stm32g0xx_hal_uart_ex.o + 0x0800A869 HAL_UARTEx_SetTxFifoThreshold + 260 4 Code Gb stm32g0xx_hal_uart_ex.o + 0x0800A96D HAL_UARTEx_SetRxFifoThreshold + 260 4 Code Gb stm32g0xx_hal_uart_ex.o + 0x0800AA71 MX_DMA_Init 48 4 Code Gb dma.o + 0x0800AAA1 MX_ADC1_Init 224 4 Code Gb adc.o + 0x0800AB81 HAL_ADC_MspInit 244 4 Code Gb adc.o + 0x0800AC75 MX_COMP1_Init 68 4 Code Gb comp.o + 0x0800ACB9 MX_COMP2_Init 68 4 Code Gb comp.o + 0x0800ACFD HAL_COMP_MspInit 224 4 Code Gb comp.o + 0x0800ADDD MX_DAC1_Init 72 4 Code Gb dac.o + 0x0800AE25 HAL_DAC_MspInit 104 4 Code Gb dac.o + 0x0800AE8D MX_GPIO_Init 288 4 Code Gb gpio.o + 0x0800AFAD main 740 4 Code Gb main.o + 0x0800B291 SystemClock_Config 132 4 Code Gb main.o + 0x0800B315 __NVIC_SystemReset 28 4 Code Lc main.o + 0x0800B331 applyMBParameter 64 4 Code Gb main.o + 0x0800B371 resetCounters 76 4 Code Gb main.o + 0x0800B3BD resetMinMaxValues 80 4 Code Gb main.o + 0x0800B40D mb_save_lock_key 84 4 Code Gb main.o + 0x0800B461 assert_failed 28 4 Code Gb main.o + 0x0800B47D HAL_MspInit 64 4 Code Gb stm32g0xx_hal_msp.o + 0x0800B4BD DMA1_Channel1_IRQHandler 16 4 Code Gb stm32g0xx_it.o + 0x0800B4CD ADC1_COMP_IRQHandler 16 4 Code Gb stm32g0xx_it.o + 0x0800B4DD USART1_IRQHandler 16 4 Code Gb stm32g0xx_it.o + 0x0800B4ED USART3_USART4_LPUART1_IRQHandler + 16 4 Code Gb stm32g0xx_it.o + 0x0800B4FD MX_USART1_UART_Init 124 4 Code Gb usart.o + 0x0800B579 HAL_UART_MspInit 164 4 Code Gb usart.o + 0x0800B61D HAL_UART_MspDeInit 60 4 Code Gb usart.o + 0x0800B659 MX_TIM1_Init 272 4 Code Gb tim.o + 0x0800B769 HAL_TIM_Base_MspInit 112 4 Code Gb tim.o + 0x0800B7D9 LED_ErrorOn 40 4 Code Gb led.o + 0x0800B801 LED_ErrorOff 36 4 Code Gb led.o + 0x0800B825 LED_ErrorStartBlink 76 4 Code Gb led.o + 0x0800B871 LED_ErrorExec 92 4 Code Gb led.o + 0x0800B8CD LED_FunctionStartBlink 76 4 Code Gb led.o + 0x0800B919 LED_FunctionSetTimes 24 4 Code Gb led.o + 0x0800B931 LED_FunctionExec 92 4 Code Gb led.o + 0x0800B98D OUTPUT_OVP_Enable 20 4 Code Gb output.o + 0x0800B9A1 OUTPUT_LVP_Enable 20 4 Code Gb output.o + 0x0800B9B5 OUTPUT_OVP_Disable 20 4 Code Gb output.o + 0x0800B9C9 OUTPUT_LVP_Disable 20 4 Code Gb output.o + 0x0800B9DD MEAS_Init 120 4 Code Gb meas.o + 0x0800BA55 MEAS_Exec 96 4 Code Gb meas.o + 0x0800BAB5 calcBalancerCurrent 64 4 Code Gb meas.o + 0x0800BAF5 calcCellVoltageFiltered 56 4 Code Gb meas.o + 0x0800BB2D calcCellVoltageUnfiltered 32 4 Code Gb meas.o + 0x0800BB4D calcCellTemperature 92 4 Code Gb meas.o + 0x0800BBA9 HAL_ADC_ConvCpltCallback 20 4 Code Gb meas.o + 0x0800BBBD SYSDATA_Init 60 4 Code Gb sysdata.o + 0x0800BBF9 BALANCER_Init 192 4 Code Gb balancer.o + 0x0800BCB9 BALANCER_Exec 924 4 Code Gb balancer.o + 0x0800C055 BALANCER_SetStartImpulse 100 4 Code Gb balancer.o + 0x0800C0B9 mbUartInit 212 4 Code Gb modbus.o + 0x0800C18D RS485_ModbusEx_Init 404 4 Code Lc modbus.o + 0x0800C321 MODBUS_UART_IRQHandler 640 4 Code Gb modbus.o + 0x0800C5A1 mbCrc16 116 4 Code Gb modbus.o + 0x0800C615 mbSlaveCheckModbusRtuQuery + 140 4 Code Gb modbus.o + 0x0800C6A1 mbSlaveReadHoldingRegisters + 252 4 Code Gb modbus.o + 0x0800C79D mbSlaveWriteSingleRegister + 304 4 Code Gb modbus.o + 0x0800C8CD mbSlaveWriteMultipleRegisters + 352 4 Code Gb modbus.o + 0x0800CA2D calculateSetpoints 208 4 Code Gb bms.o + 0x0800CAFD BMS_Exec 1 328 4 Code Gb bms.o + 0x0800D02D EEPROM_isFirstStart 80 4 Code Gb eeprom.o + 0x0800D07D getEEPROMData 104 4 Code Lc eeprom.o + 0x0800D0E5 EEPROM_fullRestore 220 4 Code Gb eeprom.o + 0x0800D1C1 EEPROM_readConfig 424 4 Code Gb eeprom.o + 0x0800D369 EEPROM_storeConfig 556 4 Code Gb eeprom.o + 0x0800D595 EEPROM_storeLogData 296 4 Code Gb eeprom.o + 0x0800D6BD EEPROM_ResetLogData 260 4 Code Gb eeprom.o + 0x0800D7C1 EEPROM_readLogData 144 4 Code Gb eeprom.o + 0x0800D851 __aeabi_fadd 308 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800D985 __aeabi_fsub 10 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800D995 __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DA4D __aeabi_fdiv 148 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DAE1 __aeabi_fcmpeq 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DB01 __aeabi_fcmpge 50 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DB35 __aeabi_fcmpgt 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DB65 __aeabi_fcmplt 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DB95 __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DBB9 __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DBE9 __aeabi_f2ulz 64 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DC29 __aeabi_i2f 38 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DC51 __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DC71 __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DC8D __aeabi_ul2f 44 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DCBD __aeabi_d2f 98 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DD21 fmodf 260 4 Code Wk floatops.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DE25 floorf 88 4 Code Wk floatops.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DE7D __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DEAD __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DEED __aeabi_idivmod 14 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DEFD __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DF35 __aeabi_uidivmod 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DF45 __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DFE5 __aeabi_idiv0 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800DFED __SEGGER_RTL_current_locale + 24 4 Code Gb mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800E005 __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800E021 __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800E03D strlen 14 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800E04D memcpy 14 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800E04D __aeabi_memcpy8 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800E04D __aeabi_memcpy4 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800E04D __aeabi_memcpy 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800E05D __aeabi_memclr8 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800E05D __aeabi_memclr4 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800E05D __aeabi_memclr 20 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0x0800E05F __aeabi_memset8 4 Code Wk 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symbols by descending size: + + Symbol name Size Align Type Bd Object File + ------------------------- ---------- ----- ---- -- ----------- + __SEGGER_RTL_vfprintf 3 352 4 Code Gb __SEGGER_RTL_vfprintf_short_float_long.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_vfprintf_short_float_long + 3 352 4 Code Gb __SEGGER_RTL_vfprintf_short_float_long.o (libc_v6m_t_le_eabi_balanced.a) + HAL_RCC_OscConfig 2 084 4 Code Gb stm32g0xx_hal_rcc.o + HAL_ADC_Init 1 852 4 Code Gb stm32g0xx_hal_adc.o + UART_SetConfig 1 712 4 Code Gb stm32g0xx_hal_uart.o + HAL_ADC_ConfigChannel 1 512 4 Code Gb stm32g0xx_hal_adc.o + HAL_TIM_ConfigClockSource 1 460 4 Code Gb stm32g0xx_hal_tim.o + HAL_RCCEx_PeriphCLKConfig 1 444 4 Code Gb stm32g0xx_hal_rcc_ex.o + BMS_Exec 1 328 4 Code Gb bms.o + HAL_COMP_Init 1 164 4 Code Gb stm32g0xx_hal_comp.o + HAL_GPIO_Init 1 048 4 Code Gb stm32g0xx_hal_gpio.o + TIM_SlaveTimer_SetConfig 960 4 Code Lc stm32g0xx_hal_tim.o + BALANCER_Exec 924 4 Code Gb balancer.o + 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stm32g0xx_hal_uart.o + BALANCER_Init 192 4 Code Gb balancer.o + __aeabi_fmul 182 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_DAC_Start 180 4 Code Gb stm32g0xx_hal_dac.o + TIM_TI1_SetConfig 180 4 Code Gb stm32g0xx_hal_tim.o + UART_RxISR_16BIT 180 2 Code Lc stm32g0xx_hal_uart.o + HAL_COMP_Start 176 4 Code Gb stm32g0xx_hal_comp.o + UART_RxISR_8BIT 176 2 Code Lc stm32g0xx_hal_uart.o + ADC_DMAConvCplt 168 2 Code Lc stm32g0xx_hal_adc.o + HAL_UARTEx_DisableFifoMode + 168 4 Code Gb stm32g0xx_hal_uart_ex.o + UARTEx_SetNbDataToProcess 168 4 Code Lc stm32g0xx_hal_uart_ex.o + ADC_Disable 164 2 Code Gb stm32g0xx_hal_adc.o + HAL_UART_MspInit 164 4 Code Gb usart.o + __aeabi_uldivmod 160 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + FLASH_WaitForLastOperation + 156 4 Code Gb stm32g0xx_hal_flash.o + HAL_DAC_SetValue 152 4 Code Gb stm32g0xx_hal_dac.o + HAL_PWREx_ControlVoltageScaling + 152 4 Code Gb stm32g0xx_hal_pwr_ex.o + UART_CheckIdleState 152 4 Code Gb stm32g0xx_hal_uart.o + __aeabi_fdiv 148 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_UART_Receive_IT 146 2 Code Gb stm32g0xx_hal_uart.o + EEPROM_readLogData 144 4 Code Gb eeprom.o + __SEGGER_RTL_putc 142 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + UART_TxISR_16BIT_FIFOEN 140 4 Code Lc stm32g0xx_hal_uart.o + mbInit 140 2 Code Gb modbus.o + mbSlaveCheckModbusRtuQuery + 140 4 Code Gb modbus.o + SEGGER_RTT_WriteNoLock 132 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_little.a) + SystemClock_Config 132 4 Code Gb main.o + __NVIC_SetPriority 128 4 Code Lc stm32g0xx_hal_cortex.o + strnlen 128 4 Code Wk strops.o (libc_v6m_t_le_eabi_balanced.a) + UART_TxISR_8BIT_FIFOEN 126 2 Code Lc stm32g0xx_hal_uart.o + MX_USART1_UART_Init 124 4 Code Gb usart.o + HAL_InitTick 120 4 Code Wk stm32g0xx_hal.o + MEAS_Init 120 4 Code Gb meas.o + vfprintf_l 120 4 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + FLASH_Program_Fast 116 4 Code Lc stm32g0xx_hal_flash.o + mbCrc16 116 4 Code Gb modbus.o + mbSlaveProcessPdu 116 2 Code Gb modbus.o + TIM_TI4_SetConfig 114 2 Code Lc stm32g0xx_hal_tim.o + DMA_SetConfig 112 4 Code Lc stm32g0xx_hal_dma.o + HAL_TIM_Base_MspInit 112 4 Code Gb tim.o + TIM_TI2_SetConfig 110 2 Code Lc stm32g0xx_hal_tim.o + TIM_TI3_SetConfig 108 2 Code Lc stm32g0xx_hal_tim.o + UART_TxISR_8BIT 108 2 Code Lc modbus.o + HAL_DAC_MspInit 104 4 Code Gb dac.o + _WriteBlocking 104 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_little.a) + getEEPROMData 104 4 Code Lc eeprom.o + BALANCER_SetStartImpulse 100 4 Code Gb balancer.o + HAL_DAC_Init 100 4 Code Gb stm32g0xx_hal_dac.o + HAL_GPIO_WritePin 100 4 Code Gb stm32g0xx_hal_gpio.o + __aeabi_d2f 98 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + MEAS_Exec 96 4 Code Gb meas.o + UART_TxISR_16BIT 96 4 Code Lc stm32g0xx_hal_uart.o + mbSlaveProcessRtuQuery 96 2 Code Gb modbus.o + FLASH_PageErase 92 4 Code Gb stm32g0xx_hal_flash_ex.o + LED_ErrorExec 92 4 Code Gb led.o + LED_FunctionExec 92 4 Code Gb led.o + calcCellTemperature 92 4 Code Gb meas.o + _DoInit 88 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_little.a) + floorf 88 4 Code Wk floatops.o (libc_v6m_t_le_eabi_balanced.a) + TIM_TI2_ConfigInputStage 84 2 Code Lc stm32g0xx_hal_tim.o + mb_save_lock_key 84 4 Code Gb main.o + UART_TxISR_8BIT 82 2 Code Lc stm32g0xx_hal_uart.o + EEPROM_isFirstStart 80 4 Code Gb eeprom.o + TIM_TI1_ConfigInputStage 80 2 Code Lc stm32g0xx_hal_tim.o + resetMinMaxValues 80 4 Code Gb main.o + HAL_SYSCFG_StrobeDBattpinsConfig + 76 4 Code Gb stm32g0xx_hal.o + LED_ErrorStartBlink 76 4 Code Gb led.o + LED_FunctionStartBlink 76 4 Code Gb led.o + SysTick_Config 76 4 Code Lc stm32g0xx_hal_cortex.o + resetCounters 76 4 Code Gb main.o + _WriteNoCheck 74 4 Code Lc SEGGER_RTT.o (prinops_rtt_v6m_little.a) + __SEGGER_RTL_float32_normalize + 74 2 Code Lc floatops.o (libc_v6m_t_le_eabi_balanced.a) + HAL_GPIO_ReadPin 72 4 Code Gb stm32g0xx_hal_gpio.o + MX_DAC1_Init 72 4 Code Gb dac.o + mbCheckCrc16 72 2 Code Gb modbus.o + DMA_CalcDMAMUXChannelBaseAndMask + 68 4 Code Lc stm32g0xx_hal_dma.o + HAL_FLASH_Unlock 68 4 Code Gb stm32g0xx_hal_flash.o + HAL_GPIO_TogglePin 68 4 Code Gb stm32g0xx_hal_gpio.o + MX_COMP1_Init 68 4 Code Gb comp.o + MX_COMP2_Init 68 4 Code Gb comp.o + __SEGGER_RTL_pow10f 68 4 Code Gb utilops.o (libc_v6m_t_le_eabi_balanced.a) + mbAppendCrc16 68 2 Code Gb modbus.o + HAL_MspInit 64 4 Code Gb stm32g0xx_hal_msp.o + __aeabi_f2ulz 64 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_idiv 64 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + applyMBParameter 64 4 Code Gb main.o + calcBalancerCurrent 64 4 Code Gb meas.o + HAL_Delay 60 4 Code Wk stm32g0xx_hal.o + HAL_UART_MspDeInit 60 4 Code Gb usart.o + SYSDATA_Init 60 4 Code Gb sysdata.o + mbSlaveResponseException 58 2 Code Gb modbus.o + DMA_CalcDMAMUXRequestGenBaseAndMask + 56 4 Code Lc stm32g0xx_hal_dma.o + FLASH_MassErase 56 4 Code Lc stm32g0xx_hal_flash_ex.o + HAL_Init 56 4 Code Gb stm32g0xx_hal.o + __aeabi_uidiv 56 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + calcCellVoltageFiltered 56 4 Code Gb meas.o + ldexpf 56 2 Code Wk floatops.o (libc_v6m_t_le_eabi_balanced.a) + TIM_ETR_SetConfig 54 2 Code Gb stm32g0xx_hal_tim.o + SEGGER_RTT_Write 52 4 Code Gb SEGGER_RTT.o (prinops_rtt_v6m_little.a) + __SEGGER_init_pack 52 2 Code Wk SEGGER_crtinit_v6m_little.o + fwrite 52 2 Code Wk fileops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_fcmpge 50 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_NVIC_DisableIRQ 48 4 Code Gb stm32g0xx_hal_cortex.o + HAL_NVIC_EnableIRQ 48 4 Code Gb stm32g0xx_hal_cortex.o + HAL_NVIC_SetPriority 48 4 Code Gb stm32g0xx_hal_cortex.o + MX_DMA_Init 48 4 Code Gb dma.o + TIM_ITRx_SetConfig 48 4 Code Lc stm32g0xx_hal_tim.o + __NVIC_DisableIRQ 48 4 Code Lc stm32g0xx_hal_cortex.o + __SEGGER_RTL_X_file_stat 48 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_little.a) + LL_ADC_REG_SetSequencerRanks + 46 2 Code Lc stm32g0xx_hal_adc.o + __aeabi_d2uiz 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_fcmpgt 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_fcmplt 46 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_lmul 46 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + FLASH_Program_DoubleWord 44 4 Code Lc stm32g0xx_hal_flash.o + HAL_FLASH_Lock 44 4 Code Gb stm32g0xx_hal_flash.o + __SEGGER_RTL_ascii_mbtowc 44 2 Code Gb mbops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ul2f 44 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + ADC_DMAError 42 2 Code Lc stm32g0xx_hal_adc.o + UART_EndTransmit_IT 42 2 Code Lc modbus.o + HAL_RCC_GetPCLK1Freq 40 4 Code Gb stm32g0xx_hal_rcc.o + LED_ErrorOn 40 4 Code Gb led.o + LL_ADC_SetChannelSamplingTime + 40 4 Code Lc stm32g0xx_hal_adc.o + __NVIC_EnableIRQ 40 4 Code Lc stm32g0xx_hal_cortex.o + printf 40 4 Code Wk prinops.o (libc_v6m_t_le_eabi_balanced.a) + LL_ADC_SetSamplingTimeCommonChannels + 38 2 Code Lc stm32g0xx_hal_adc.o + __aeabi_i2f 38 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + mbSend 38 2 Code Gb modbus.o + LED_ErrorOff 36 4 Code Gb led.o + __aeabi_f2uiz 36 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + frexpf 36 2 Code Wk floatops.o (libc_v6m_t_le_eabi_balanced.a) + LL_ADC_EnableInternalRegulator + 32 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_SetSequencerChRem + 32 4 Code Lc stm32g0xx_hal_adc.o + calcCellVoltageUnfiltered 32 4 Code Gb meas.o + __aeabi_fcmpeq 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ui2f 30 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + LL_ADC_Disable 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_Enable 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_SetSequencerChAdd + 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_StartConversion + 28 4 Code Lc stm32g0xx_hal_adc.o + LL_ADC_SetCommonPathInternalCh + 28 2 Code Lc stm32g0xx_hal_adc.o + __NVIC_SystemReset 28 4 Code Lc main.o + __SEGGER_RTL_ascii_isctype + 28 4 Code Lc mbops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_iswctype + 28 4 Code Lc mbops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_print_padding + 28 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_ui2d 28 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + assert_failed 28 4 Code Gb main.o + __SEGGER_RTL_prin_flush 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + vfprintf 26 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + HAL_IncTick 24 4 Code Wk stm32g0xx_hal.o + LED_FunctionSetTimes 24 4 Code Gb led.o + LL_EXTI_DisableEvent_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_DisableFallingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_DisableIT_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_DisableRisingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_EnableEvent_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_EnableFallingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_EnableIT_0_31 24 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_EnableRisingTrig_0_31 + 24 4 Code Lc stm32g0xx_hal_comp.o + __SEGGER_RTL_current_locale + 24 4 Code Gb mbops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_init_ctors 24 4 Code Wk SEGGER_crtinit_v6m_little.o + ADC_DMAHalfConvCplt 22 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_IsTriggerSourceSWStart + 22 2 Code Lc stm32g0xx_hal_adc.o + __SEGGER_RTL_pre_padding 22 2 Code Gb prinops.o (libc_v6m_t_le_eabi_balanced.a) + mbClearRxFrame 22 2 Code Gb modbus.o + HAL_ADC_ConvCpltCallback 20 4 Code Gb meas.o + LL_ADC_IsCalibrationOnGoing + 20 2 Code Lc stm32g0xx_hal_adc_ex.o + LL_ADC_IsInternalRegulatorEnabled + 20 2 Code Lc stm32g0xx_hal_adc.o + LL_EXTI_ClearFallingFlag_0_31 + 20 4 Code Lc stm32g0xx_hal_comp.o + LL_EXTI_ClearRisingFlag_0_31 + 20 4 Code Lc stm32g0xx_hal_comp.o + OUTPUT_LVP_Disable 20 4 Code Gb output.o + OUTPUT_LVP_Enable 20 4 Code Gb output.o + OUTPUT_OVP_Disable 20 4 Code Gb output.o + OUTPUT_OVP_Enable 20 4 Code Gb output.o + __SEGGER_RTL_init_heap 20 4 Code Wk heapops_basic.o (heapops_basic_v6m_little.a) + __aeabi_memclr 20 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + LL_ADC_GetCommonPathInternalCh + 18 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_IsDisableOngoing 18 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_REG_IsConversionOngoing + 18 2 Code Lc stm32g0xx_hal_adc.o + __SEGGER_RTL_float32_isnan + 18 2 Code Wk floatops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_init_zero 18 2 Code Wk SEGGER_crtinit_v6m_little.o + mbClearTxBuffer 18 2 Code Gb modbus.o + ADC1_COMP_IRQHandler 16 4 Code Gb stm32g0xx_it.o + DMA1_Channel1_IRQHandler 16 4 Code Gb stm32g0xx_it.o + HAL_SYSTICK_Config 16 2 Code Gb stm32g0xx_hal_cortex.o + LL_ADC_IsEnabled 16 2 Code Lc stm32g0xx_hal_adc.o + LL_ADC_IsEnabled 16 2 Code Lc stm32g0xx_hal_adc_ex.o + LL_ADC_REG_GetDMATransfer 16 2 Code Lc stm32g0xx_hal_adc.o + LL_RCC_GetAPB1Prescaler 16 4 Code Lc stm32g0xx_hal_rcc.o + SystemInit 16 4 Code Gb system_stm32g0xx.o + USART1_IRQHandler 16 4 Code Gb stm32g0xx_it.o + USART3_USART4_LPUART1_IRQHandler + 16 4 Code Gb stm32g0xx_it.o + __SEGGER_RTL_ascii_wctomb 16 2 Code Gb mbops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_stream_write 16 2 Code Lc prinops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_init_heap 16 4 Code Wk SEGGER_crtinit_v6m_little.o + __aeabi_uidivmod 16 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + mbGetFrameComplete 16 2 Code Gb modbus.o + __SEGGER_RTL_float32_isinf + 14 2 Code Wk floatops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_idivmod 14 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + _start 14 4 Code Gb SEGGER_THUMB_Startup.o + memcpy 14 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + strlen 14 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + HAL_GetTick 12 4 Code Wk stm32g0xx_hal.o + HAL_RCC_GetHCLKFreq 12 4 Code Gb stm32g0xx_hal_rcc.o + HAL_UARTEx_RxEventCallback + 12 2 Code Wk stm32g0xx_hal_uart.o + LED_Exec 12 2 Code Gb led.o + __SEGGER_RTL_ascii_tolower + 12 2 Code Lc mbops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_toupper + 12 2 Code Lc mbops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_towlower + 12 2 Code Lc mbops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_ascii_towupper + 12 2 Code Lc mbops.o (libc_v6m_t_le_eabi_balanced.a) + __SEGGER_RTL_X_file_write 10 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_little.a) + __aeabi_fsub 10 4 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + ADC_COMP_IRQHandler 8 2 Code Gb stm32g0xx_it.o + DMA_Channel1_IRQHandler 8 2 Code Gb stm32g0xx_it.o + HAL_ADCEx_ChannelConfigReadyCallback + 8 2 Code Wk stm32g0xx_hal_adc_ex.o + HAL_ADCEx_EndOfSamplingCallback + 8 2 Code Wk stm32g0xx_hal_adc_ex.o + HAL_ADCEx_LevelOutOfWindow2Callback + 8 2 Code Wk stm32g0xx_hal_adc_ex.o + HAL_ADCEx_LevelOutOfWindow3Callback + 8 2 Code Wk stm32g0xx_hal_adc_ex.o + HAL_ADC_ConvHalfCpltCallback + 8 2 Code Wk stm32g0xx_hal_adc.o + HAL_ADC_ErrorCallback 8 2 Code Wk stm32g0xx_hal_adc.o + HAL_ADC_LevelOutOfWindowCallback + 8 2 Code Wk stm32g0xx_hal_adc.o + HAL_TIM_IC_MspInit 8 2 Code Wk stm32g0xx_hal_tim.o + HAL_UART_ErrorCallback 8 2 Code Wk stm32g0xx_hal_uart.o + HAL_UART_RxCpltCallback 8 2 Code Wk stm32g0xx_hal_uart.o + HAL_UART_TxCpltCallback 8 2 Code Wk stm32g0xx_hal_uart.o + SysTick_Handler 8 2 Code Gb stm32g0xx_it.o + abs 8 2 Code Wk intops.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_idiv0 6 4 Code Wk intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + Error_Handler 4 2 Code Gb main.o + __SEGGER_RTL_X_file_bufsize + 4 4 Code Gb prinops_rtt.o (prinops_rtt_v6m_little.a) + __SEGGER_RTL_float32_signbit + 4 2 Code Wk floatops.o (libc_v6m_t_le_eabi_balanced.a) + HardFault_Handler 2 2 Code Gb stm32g0xx_it.o + NMI_Handler 2 2 Code Gb stm32g0xx_it.o + PendSV_Handler 2 2 Code Gb stm32g0xx_it.o + SVC_Handler 2 2 Code Gb stm32g0xx_it.o + exit 2 4 Code Gb SEGGER_THUMB_Startup.o + AES_RNG_IRQHandler 2 Code Wk STM32G07x_Vectors.o + CEC_IRQHandler 2 Code Wk STM32G07x_Vectors.o + DMA_Channel2_3_IRQHandler 2 Code Wk STM32G07x_Vectors.o + DMA_Channel4_5_6_7_IRQHandler + 2 Code Wk STM32G07x_Vectors.o + EXTI0_1_IRQHandler 2 Code Wk STM32G07x_Vectors.o + EXTI2_3_IRQHandler 2 Code Wk STM32G07x_Vectors.o + EXTI4_15_IRQHandler 2 Code Wk STM32G07x_Vectors.o + FLASH_IRQHandler 2 Code Wk STM32G07x_Vectors.o + FLASH_Program_Fast__TT_veneer_T16_LDR_BX + 4 Code Lc [ Linker created ] + I2C1_IRQHandler 2 Code Wk STM32G07x_Vectors.o + I2C2_IRQHandler 2 Code Wk STM32G07x_Vectors.o + PVD_IRQHandler 2 Code Wk STM32G07x_Vectors.o + RCC_IRQHandler 2 Code Wk STM32G07x_Vectors.o + RTC_STAMP_IRQHandler 2 Code Wk STM32G07x_Vectors.o + Reset_Handler 2 Code Gb STM32G0xx_Startup.o + SPI1_IRQHandler 2 Code Wk STM32G07x_Vectors.o + SPI2_IRQHandler 2 Code Wk STM32G07x_Vectors.o + TIM14_IRQHandler 2 Code Wk STM32G07x_Vectors.o + TIM15_IRQHandler 2 Code Wk STM32G07x_Vectors.o + TIM16_IRQHandler 2 Code Wk STM32G07x_Vectors.o + TIM17_IRQHandler 2 Code Wk STM32G07x_Vectors.o + TIM1_BRK_UP_TRG_COMP_IRQHandler + 2 Code Wk STM32G07x_Vectors.o + TIM1_CC_IRQHandler 2 Code Wk STM32G07x_Vectors.o + TIM2_IRQHandler 2 Code Wk STM32G07x_Vectors.o + TIM3_IRQHandler 2 Code Wk STM32G07x_Vectors.o + TIM6_DAC_LPTIM1_IRQHandler + 2 Code Wk STM32G07x_Vectors.o + TIM7_LPTIM2_IRQHandler 2 Code Wk STM32G07x_Vectors.o + UCPD1_UCPD2_IRQHandler 2 Code Wk STM32G07x_Vectors.o + USART2_IRQHandler 2 Code Wk STM32G07x_Vectors.o + WWDG_IRQHandler 2 Code Wk STM32G07x_Vectors.o + __SEGGER_init_done 4 Code Gb SEGGER_THUMB_Startup.o + __aeabi_dmul 2 Code Wk floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_memclr4 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_memclr8 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy4 4 Code Wk strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + __aeabi_memcpy8 4 Code Wk strasmops_arm.o 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+*********************************************************************************************** +*** *** +*** LINK SUMMARY *** +*** *** +*********************************************************************************************** + +Memory breakdown: + + 53 616 bytes read-only code + + 61 184 bytes read-only data = 114 800 bytes read-only (total) + 6 189 bytes read-write data + +Region summary: + + Name Range Size Used Unused Alignment Loss + ---------- ----------------- ----------- ------------------- ------------------- ------------------- + 08003000-0801efff 114 688 114 688 100.00% 0 0.00% 0 0.00% + RAM 20000000-20007fff 32 768 6 305 19.24% 26 463 80.76% 0 0.00% + +Link complete: 0 errors, 0 warnings, 0 remarks Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/SEGGER_THUMB_Startup.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/SEGGER_THUMB_Startup.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/SEGGER_THUMB_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/cellMon/SEGGER_THUMB_Startup.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\SEGGER_THUMB_Startup.s Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/STM32G07x_Vectors.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/STM32G07x_Vectors.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/STM32G07x_Vectors.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/cellMon/STM32G07x_Vectors.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\Source\STM32G07x_Vectors.s Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/STM32G0xx_Startup.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/STM32G0xx_Startup.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/STM32G0xx_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/cellMon/STM32G0xx_Startup.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\Source\STM32G0xx_Startup.s Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/adc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/adc.d (revision 3) @@ -0,0 +1,48 @@ +Output/Debug/Obj/cellMon/adc.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\adc.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/balancer.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/balancer.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/balancer.d (revision 3) @@ -0,0 +1,56 @@ +Output/Debug/Obj/cellMon/balancer.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\balancer.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\balancer.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\led.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/bms.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/bms.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/bms.d (revision 3) @@ -0,0 +1,55 @@ +Output/Debug/Obj/cellMon/bms.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\bms.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\bms.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\output.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\led.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\eeprom.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/comp.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/comp.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/comp.d (revision 3) @@ -0,0 +1,48 @@ +Output/Debug/Obj/cellMon/comp.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\comp.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/dac.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/dac.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/dac.d (revision 3) @@ -0,0 +1,48 @@ +Output/Debug/Obj/cellMon/dac.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\dac.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/dma.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/dma.d (revision 3) @@ -0,0 +1,48 @@ +Output/Debug/Obj/cellMon/dma.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\dma.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/eeprom.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/eeprom.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/eeprom.d (revision 3) @@ -0,0 +1,53 @@ +Output/Debug/Obj/cellMon/eeprom.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\eeprom.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\eeprom.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\string.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/gpio.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/gpio.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/gpio.d (revision 3) @@ -0,0 +1,48 @@ +Output/Debug/Obj/cellMon/gpio.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\gpio.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/led.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/led.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/led.d (revision 3) @@ -0,0 +1,48 @@ +Output/Debug/Obj/cellMon/led.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\led.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\led.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/main.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/main.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/main.d (revision 3) @@ -0,0 +1,64 @@ +Output/Debug/Obj/cellMon/main.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\main.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\usart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\led.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\output.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\meas.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\balancer.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\eeprom.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\bms.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdio.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/meas.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/meas.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/meas.d (revision 3) @@ -0,0 +1,53 @@ +Output/Debug/Obj/cellMon/meas.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\meas.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\meas.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\adc.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/modbus.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/modbus.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/modbus.d (revision 3) @@ -0,0 +1,51 @@ +Output/Debug/Obj/cellMon/modbus.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\modbus.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdio.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/output.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/output.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/output.d (revision 3) @@ -0,0 +1,48 @@ +Output/Debug/Obj/cellMon/output.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\output.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\output.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_adc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_adc.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_adc.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_adc_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_adc_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_adc_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_adc_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_comp.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_comp.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_comp.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_comp.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_comp.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_cortex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_cortex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_cortex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_cortex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cortex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_dac.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_dac.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_dac.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_dac.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dac.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_dac_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_dac_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_dac_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_dac_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dac_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_dma.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_dma.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_dma.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_dma_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_dma_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_dma_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_dma_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_exti.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_exti.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_exti.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_exti.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_exti.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_flash.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_flash.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_flash.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_flash.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_flash_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_flash_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_flash_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_flash_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_gpio.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_gpio.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_gpio.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_gpio.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_gpio.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_msp.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_msp.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_msp.d (revision 3) @@ -0,0 +1,47 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_msp.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\stm32g0xx_hal_msp.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_pwr.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_pwr.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_pwr.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_pwr.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_pwr_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_pwr_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_pwr_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_pwr_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_rcc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_rcc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_rcc.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_rcc.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_rcc_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_rcc_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_rcc_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_rcc_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_tim.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_tim.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_tim.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_tim.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_tim_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_tim_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_tim_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_tim_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_uart.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_uart.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_uart.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_uart.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_uart_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_uart_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_hal_uart_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/stm32g0xx_hal_uart_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_it.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_it.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_it.d (revision 3) @@ -0,0 +1,50 @@ +Output/Debug/Obj/cellMon/stm32g0xx_it.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\stm32g0xx_it.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_it.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_ll_adc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_ll_adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_ll_adc.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/cellMon/stm32g0xx_ll_adc.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_adc.c Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_ll_dma.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_ll_dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_ll_dma.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/cellMon/stm32g0xx_ll_dma.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_dma.c Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_ll_rcc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_ll_rcc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/stm32g0xx_ll_rcc.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/cellMon/stm32g0xx_ll_rcc.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_rcc.c Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/sysdata.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/sysdata.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/sysdata.d (revision 3) @@ -0,0 +1,50 @@ +Output/Debug/Obj/cellMon/sysdata.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\sysdata.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/system_stm32g0xx.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/system_stm32g0xx.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/system_stm32g0xx.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/cellMon/system_stm32g0xx.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Source\system_stm32g0xx.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/template.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/template.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/template.d (revision 3) @@ -0,0 +1,3 @@ +Output/Debug/Obj/cellMon/template.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\template.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\template.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/tim.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/tim.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/tim.d (revision 3) @@ -0,0 +1,48 @@ +Output/Debug/Obj/cellMon/tim.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\tim.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/cellMon/usart.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/cellMon/usart.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/cellMon/usart.d (revision 3) @@ -0,0 +1,48 @@ +Output/Debug/Obj/cellMon/usart.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\usart.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\usart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/start.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/start.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/start.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/lipro1-6_v2_main/start.o: \ + D\:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\start.s Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/start_PP.s =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/start_PP.s (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/start_PP.s (revision 3) @@ -0,0 +1,15 @@ +# 1 "D:\\projekte\\ecs_lipro\\branches\\lipro1-6_v2\\firmware\\start.s" +# 1 "" +# 1 "" +# 1 "D:\\projekte\\ecs_lipro\\branches\\lipro1-6_v2\\firmware\\start.s" +# 51 "D:\\projekte\\ecs_lipro\\branches\\lipro1-6_v2\\firmware\\start.s" + .syntax unified + .global _start + .text + + .thumb_func +_start: + ldr r0, =#0x12345678 +loop: + adds r0, r0, #1 + b loop Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_adc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_adc.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_adc.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_adc_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_adc_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_adc_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_adc_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_comp.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_comp.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_comp.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_comp.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_comp.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_cortex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_cortex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_cortex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_cortex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cortex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dac.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dac.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dac.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dac.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dac.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dac_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dac_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dac_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dac_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dac_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dma.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dma.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dma.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dma_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dma_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dma_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_dma_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_exti.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_exti.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_exti.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_exti.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_exti.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_flash.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_flash.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_flash.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_flash.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_flash_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_flash_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_flash_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_flash_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_gpio.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_gpio.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_gpio.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_gpio.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_gpio.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_pwr.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_pwr.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_pwr.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_pwr.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_pwr_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_pwr_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_pwr_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_pwr_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_rcc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_rcc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_rcc.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_rcc.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_rcc_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_rcc_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_rcc_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_rcc_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_tim.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_tim.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_tim.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_tim.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_tim_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_tim_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_tim_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_tim_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_uart.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_uart.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_uart.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_uart.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_uart_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_uart_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_uart_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_hal_uart_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\__SEGGER_RTL_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 5.40\segger-rtl\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_ll_adc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_ll_adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_ll_adc.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_ll_adc.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_adc.c Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_ll_dma.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_ll_dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_ll_dma.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/lipro1-6_v2_main/stm32g0xx_ll_dma.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_dma.c Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/SEGGER_THUMB_Startup.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/SEGGER_THUMB_Startup.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/SEGGER_THUMB_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/lipro1_6_v2_main/SEGGER_THUMB_Startup.o: \ + D\:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\SEGGER_THUMB_Startup.s Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/STM32G07x_Vectors.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/STM32G07x_Vectors.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/STM32G07x_Vectors.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/lipro1_6_v2_main/STM32G07x_Vectors.o: \ + D\:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\Source\STM32G07x_Vectors.s Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/STM32G0xx_Startup.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/STM32G0xx_Startup.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/STM32G0xx_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/lipro1_6_v2_main/STM32G0xx_Startup.o: \ + D\:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\Source\STM32G0xx_Startup.s Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/adc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/adc.d (revision 3) @@ -0,0 +1,51 @@ +Output/Debug/Obj/lipro1_6_v2_main/adc.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Src\adc.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/balancer.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/balancer.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/balancer.d (revision 3) @@ -0,0 +1,61 @@ +Output/Debug/Obj/lipro1_6_v2_main/balancer.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\src\balancer.c \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdio.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\balancer.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\led.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/bms.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/bms.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/bms.d (revision 3) @@ -0,0 +1,60 @@ +Output/Debug/Obj/lipro1_6_v2_main/bms.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\src\bms.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\bms.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\output.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\led.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\eeprom.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/comp.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/comp.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/comp.d (revision 3) @@ -0,0 +1,51 @@ +Output/Debug/Obj/lipro1_6_v2_main/comp.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Src\comp.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/dac.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/dac.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/dac.d (revision 3) @@ -0,0 +1,51 @@ +Output/Debug/Obj/lipro1_6_v2_main/dac.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Src\dac.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/dma.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/dma.d (revision 3) @@ -0,0 +1,51 @@ +Output/Debug/Obj/lipro1_6_v2_main/dma.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Src\dma.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/eeprom.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/eeprom.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/eeprom.d (revision 3) @@ -0,0 +1,59 @@ +Output/Debug/Obj/lipro1_6_v2_main/eeprom.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\src\eeprom.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\eeprom.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdio.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\string.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\string.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/gpio.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/gpio.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/gpio.d (revision 3) @@ -0,0 +1,51 @@ +Output/Debug/Obj/lipro1_6_v2_main/gpio.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Src\gpio.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/led.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/led.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/led.d (revision 3) @@ -0,0 +1,51 @@ +Output/Debug/Obj/lipro1_6_v2_main/led.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\src\led.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\led.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/lipro1_6_v2_main.ind =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/lipro1_6_v2_main.ind (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/lipro1_6_v2_main.ind (revision 3) @@ -0,0 +1,53 @@ +"Output/Debug/Obj/lipro1_6_v2_main/system_stm32g0xx.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc_ex.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_comp.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_cortex.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac_ex.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma_ex.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_exti.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash_ex.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_gpio.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr_ex.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc_ex.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim_ex.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart_ex.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_adc.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_dma.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_rcc.o" +"Output/Debug/Obj/lipro1_6_v2_main/dma.o" +"Output/Debug/Obj/lipro1_6_v2_main/adc.o" +"Output/Debug/Obj/lipro1_6_v2_main/comp.o" +"Output/Debug/Obj/lipro1_6_v2_main/dac.o" +"Output/Debug/Obj/lipro1_6_v2_main/gpio.o" +"Output/Debug/Obj/lipro1_6_v2_main/main.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_msp.o" +"Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_it.o" +"Output/Debug/Obj/lipro1_6_v2_main/usart.o" +"Output/Debug/Obj/lipro1_6_v2_main/tim.o" +"Output/Debug/Obj/lipro1_6_v2_main/led.o" +"Output/Debug/Obj/lipro1_6_v2_main/template.o" +"Output/Debug/Obj/lipro1_6_v2_main/output.o" +"Output/Debug/Obj/lipro1_6_v2_main/meas.o" +"Output/Debug/Obj/lipro1_6_v2_main/sysdata.o" +"Output/Debug/Obj/lipro1_6_v2_main/balancer.o" +"Output/Debug/Obj/lipro1_6_v2_main/modbus.o" +"Output/Debug/Obj/lipro1_6_v2_main/bms.o" +"Output/Debug/Obj/lipro1_6_v2_main/eeprom.o" +"Output/Debug/Obj/lipro1_6_v2_main/SEGGER_THUMB_Startup.o" +"Output/Debug/Obj/lipro1_6_v2_main/STM32G0xx_Startup.o" +"Output/Debug/Obj/lipro1_6_v2_main/STM32G07x_Vectors.o" +"C:/Users/ecs/AppData/Local/SEGGER/SEGGER Embedded Studio/v3/packages/libraries/libcxx/lib/libcxx_noexcept_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 6.34a/lib/libc_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 6.34a/lib/SEGGER_crtinit_v6m_little.o" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 6.34a/lib/prinops_rtt_v6m_little.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 6.34a/lib/heapops_basic_v6m_little.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 6.34a/lib/heapops_disable_interrupts_locking_v6m_little.a" Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/main.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/main.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/main.d (revision 3) @@ -0,0 +1,69 @@ +Output/Debug/Obj/lipro1_6_v2_main/main.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Src\main.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\usart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\led.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\output.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\meas.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\balancer.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\eeprom.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\bms.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdio.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/meas.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/meas.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/meas.d (revision 3) @@ -0,0 +1,58 @@ +Output/Debug/Obj/lipro1_6_v2_main/meas.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\src\meas.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\meas.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\adc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdbool.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/modbus.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/modbus.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/modbus.d (revision 3) @@ -0,0 +1,56 @@ +Output/Debug/Obj/lipro1_6_v2_main/modbus.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\src\modbus.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\sysdata.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdio.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/output.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/output.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/output.d (revision 3) @@ -0,0 +1,51 @@ +Output/Debug/Obj/lipro1_6_v2_main/output.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\src\output.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\output.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_comp.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_comp.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_comp.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_comp.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_comp.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_cortex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_cortex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_cortex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_cortex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cortex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dac.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dac_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_exti.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_exti.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_exti.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_exti.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_exti.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_gpio.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_gpio.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_gpio.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_gpio.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_gpio.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_msp.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_msp.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_msp.d (revision 3) @@ -0,0 +1,50 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_msp.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Src\stm32g0xx_hal_msp.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart_ex.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_it.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_it.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_it.d (revision 3) @@ -0,0 +1,54 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_it.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Src\stm32g0xx_it.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_it.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdbool.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_adc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_adc.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_adc.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_adc.c Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_dma.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_dma.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_dma.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_dma.c Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_rcc.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_rcc.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_rcc.d (revision 3) @@ -0,0 +1,2 @@ +Output/Debug/Obj/lipro1_6_v2_main/stm32g0xx_ll_rcc.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_rcc.c Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/sysdata.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/sysdata.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/sysdata.d (revision 3) @@ -0,0 +1,54 @@ +Output/Debug/Obj/lipro1_6_v2_main/sysdata.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\src\sysdata.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdbool.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/system_stm32g0xx.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/system_stm32g0xx.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/system_stm32g0xx.d (revision 3) @@ -0,0 +1,49 @@ +Output/Debug/Obj/lipro1_6_v2_main/system_stm32g0xx.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Source\system_stm32g0xx.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/template.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/template.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/template.d (revision 3) @@ -0,0 +1,3 @@ +Output/Debug/Obj/lipro1_6_v2_main/template.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\template.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\template.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/tim.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/tim.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/tim.d (revision 3) @@ -0,0 +1,51 @@ +Output/Debug/Obj/lipro1_6_v2_main/tim.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Src\tim.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/usart.d =================================================================== --- ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/usart.d (revision 3) +++ ecs_cellMon/firmware/Output/Debug/Obj/lipro1_6_v2_main/usart.d (revision 3) @@ -0,0 +1,51 @@ +Output/Debug/Obj/lipro1_6_v2_main/usart.o: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Src\usart.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\usart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Exe/cellMon.hex =================================================================== --- ecs_cellMon/firmware/Output/Release/Exe/cellMon.hex (revision 3) +++ ecs_cellMon/firmware/Output/Release/Exe/cellMon.hex (revision 3) @@ -0,0 +1,7296 @@ +:020000040800F2 +:1030000000800020F3B600086DB400086FB400081B +:1030100000000000000000000000000000000000B0 +:1030200000000000000000000000000071B4000873 +:10303000000000000000000073B40008C987000809 +:1030400011B3000813B3000815B3000817B3000844 +:1030500019B300081BB300081DB300081FB3000814 +:1030600021B30008D987000823B3000825B300085E +:10307000C988000827B3000829B300082BB300084B +:103080002DB300082FB3000831B3000833B3000894 +:1030900035B3000837B3000839B300083BB3000864 +:1030A0003DB300083FB3000841B300084BB7000828 +:1030B00043B3000853B7000845B3000847B30008FE +:1030C00001000000000000000A00000000000000F5 +:1030D0006400000000000000E803000000000000A1 +:1030E0001027000000000000A08601000000000082 +:1030F00040420F0000000000809698000000000091 +:1031000000E1F5050000000000CA9A3B0000000045 +:1031100000E40B540200000000E8764817000000AD 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+:10EF9000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF81 +:10EFA000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF71 +:10EFB000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF61 +:10EFC000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF51 +:10EFD000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF41 +:10EFE000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF31 +:0CEFF000FFFFFFFFFFFFFFFFFFFFFFFF21 +:04EFFC00187F071D56 +:040000050800B6F346 +:00000001FF Index: ecs_cellMon/firmware/Output/Release/Exe/cellMon.ind =================================================================== --- ecs_cellMon/firmware/Output/Release/Exe/cellMon.ind (revision 3) +++ ecs_cellMon/firmware/Output/Release/Exe/cellMon.ind (revision 3) @@ -0,0 +1,52 @@ +"Output/Release/Obj/cellMon/system_stm32g0xx.bc" +"Output/Release/Obj/cellMon/dma.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_adc.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_adc_ex.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_comp.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_cortex.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_dac.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_dac_ex.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_dma.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_dma_ex.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_exti.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_flash.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_flash_ex.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_gpio.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_pwr.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_pwr_ex.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_rcc.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_rcc_ex.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_tim.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_tim_ex.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_uart.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_uart_ex.bc" +"Output/Release/Obj/cellMon/stm32g0xx_ll_adc.bc" +"Output/Release/Obj/cellMon/stm32g0xx_ll_dma.bc" +"Output/Release/Obj/cellMon/stm32g0xx_ll_rcc.bc" +"Output/Release/Obj/cellMon/adc.bc" +"Output/Release/Obj/cellMon/comp.bc" +"Output/Release/Obj/cellMon/dac.bc" +"Output/Release/Obj/cellMon/gpio.bc" +"Output/Release/Obj/cellMon/main.bc" +"Output/Release/Obj/cellMon/stm32g0xx_hal_msp.bc" +"Output/Release/Obj/cellMon/stm32g0xx_it.bc" +"Output/Release/Obj/cellMon/tim.bc" +"Output/Release/Obj/cellMon/usart.bc" +"Output/Release/Obj/cellMon/balancer.bc" +"Output/Release/Obj/cellMon/bms.bc" +"Output/Release/Obj/cellMon/eeprom.bc" +"Output/Release/Obj/cellMon/led.bc" +"Output/Release/Obj/cellMon/meas.bc" +"Output/Release/Obj/cellMon/modbus.bc" +"Output/Release/Obj/cellMon/output.bc" +"Output/Release/Obj/cellMon/sysdata.bc" +"Output/Release/Obj/cellMon/template.bc" +"Output/Release/Obj/cellMon/SEGGER_THUMB_Startup.o" +"Output/Release/Obj/cellMon/STM32G07x_Vectors.o" +"Output/Release/Obj/cellMon/STM32G0xx_Startup.o" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 7.12a/lib/libc_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 7.12a/lib/SEGGER_crtinit_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 7.12a/lib/prinops_rtt_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 7.12a/lib/heapops_basic_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 7.12a/lib/heapops_disable_interrupts_locking_v6m_t_le_eabi_balanced.a" Index: ecs_cellMon/firmware/Output/Release/Exe/cellMon.map =================================================================== --- ecs_cellMon/firmware/Output/Release/Exe/cellMon.map (revision 3) +++ ecs_cellMon/firmware/Output/Release/Exe/cellMon.map (revision 3) @@ -0,0 +1,1402 @@ +*********************************************************************************************** +*** *** +*** LINK INFORMATION *** +*** *** +*********************************************************************************************** + +Linker version: + + SEGGER ARM Linker 4.38.2 compiled Mar 14 2023 20:07:24 + Copyright (c) 2017-2022 SEGGER Microcontroller GmbH www.segger.com + + +*********************************************************************************************** +*** *** +*** MODULE SUMMARY *** +*** *** +*********************************************************************************************** + +Memory use by input file: + + Object File RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + cellMon_lto.o 26 788 2 818 164 1 660 + SEGGER_THUMB_Startup.o 20 + STM32G07x_Vectors.o 248 + STM32G0xx_Startup.o 8 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (4 objects) 27 064 2 818 164 1 660 + --------------------------------------------- ---------- ---------- ---------- ---------- + heapops_basic_v6m_t_le_eabi_balanced.a 20 4 + libc_v6m_t_le_eabi_balanced.a 6 766 792 20 4 + prinops_rtt_v6m_t_le_eabi_balanced.a 512 26 12 1 220 + SEGGER_crtinit_v6m_t_le_eabi_balanced.a 130 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (4 archives) 7 428 818 32 1 228 + --------------------------------------------- ---------- ---------- ---------- ---------- + Linker created (shared data, fills, blocks): 76 556 3 072 + ============================================= ========== ========== ========== ========== + Total: 34 492 80 192 196 5 960 + ============================================= ========== ========== ========== ========== + +Memory use by archive member: + + Archive member RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + __SEGGER_RTL_vfprintf_short_float_long.o (libc_v6m_t_le_eabi_balanced.a) + 3 400 35 + fileops.o (libc_v6m_t_le_eabi_balanced.a) 52 + floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 1 586 + floatops.o (libc_v6m_t_le_eabi_balanced.a) 496 + heapops_basic.o (heapops_basic_v6m_t_le_eabi_balanced.a) + 20 4 + intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 368 + intops.o (libc_v6m_t_le_eabi_balanced.a) 8 + mbops.o (libc_v6m_t_le_eabi_balanced.a) 188 541 20 4 + prinops.o (libc_v6m_t_le_eabi_balanced.a) 416 192 + prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 64 12 12 + SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 130 + SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 448 26 1 208 + strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 52 + strops.o (libc_v6m_t_le_eabi_balanced.a) 128 + utilops.o (libc_v6m_t_le_eabi_balanced.a) 72 24 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (15 members from 4 archives) 7 428 818 32 1 228 + Objects (4 files) 27 064 2 818 164 1 660 + Linker created (shared data, fills, blocks): 76 556 3 072 + ============================================= ========== ========== ========== ========== + Total: 34 492 80 192 196 5 960 + ============================================= ========== ========== ========== ========== + +Memory use by linker: + + Description RX Code RO Data RW Data ZI Data + --------------------------------------------- ---------- ---------- ---------- ---------- + Filling 76 448 + Initialization table 104 + Integrity check 4 + Memory for block 'heap' 1 024 + Memory for block 'stack' 2 048 + --------------------------------------------- ---------- ---------- ---------- ---------- + Subtotal (linker created): 76 556 3 072 + --------------------------------------------- ---------- ---------- ---------- ---------- + Objects (4 files) 27 064 2 818 164 1 660 + Archives (4 files) 7 428 818 32 1 228 + ============================================= ========== ========== ========== ========== + Total: 34 492 80 192 196 5 960 + ============================================= ========== ========== ========== ========== + + +*********************************************************************************************** +*** *** +*** SECTION DETAIL *** +*** *** +*********************************************************************************************** + +Sections by address: + + Range Symbol or [section] Name Size Al Init Ac Object File + ----------------- ------------------------- ---------- -- ---- -- ----------- + 08003000-080030bf _vectors 192 512 + Code RX STM32G07x_Vectors.o + 080030c0-0800315f __SEGGER_RTL_ipow10 160 8 Cnst RO prinops.o (libc_v6m_t_le_eabi_balanced.a) + 08003160-08003173 _start 20 4 Code RX SEGGER_THUMB_Startup.o + 08003174-08003183 SystemInit 16 4 Code RX cellMon_lto.o + 08003184-08003213 SystemCoreClockUpdate 144 4 Code RX cellMon_lto.o + 08003214-08003287 ADC_DMAConvCplt 116 4 Code RX cellMon_lto.o + 08003288-080036db HAL_ADC_ConfigChannel 1 108 4 Code RX cellMon_lto.o + 080036dc-08003acf HAL_COMP_Init 1 012 4 Code RX cellMon_lto.o + 08003ad0-08003b87 HAL_COMP_Start 184 4 Code RX cellMon_lto.o + 08003b88-08003cf7 HAL_FLASH_Program 368 4 Code RX cellMon_lto.o + 08003cf8-08003ebb HAL_FLASHEx_Erase 452 4 Code RX cellMon_lto.o + 08003ebc-0800417f HAL_GPIO_Init 708 4 Code RX cellMon_lto.o + 08004180-08004397 HAL_TIM_IC_Start 536 4 Code RX cellMon_lto.o + 08004398-080045ef HAL_TIM_IC_ConfigChannel 600 4 Code RX cellMon_lto.o + 080045f0-08004ae7 UART_SetConfig 1 272 4 Code RX cellMon_lto.o + 08004ae8-08004cdf UART_AdvFeatureConfig 504 4 Code RX cellMon_lto.o + 08004ce0-08004dcb UART_CheckIdleState 236 4 Code RX cellMon_lto.o + 08004dcc-08004e27 UART_TxISR_16BIT_FIFOEN 92 4 Code RX cellMon_lto.o + 08004e28-08004e6b UART_TxISR_16BIT 68 4 Code RX cellMon_lto.o + 08004e6c-08004fa7 UART_RxISR_8BIT_FIFOEN 316 4 Code RX cellMon_lto.o + 08004fa8-080050eb UART_RxISR_16BIT_FIFOEN 324 4 Code RX cellMon_lto.o + 080050ec-080087c7 main 14 044 4 Code RX cellMon_lto.o + 080087c8-080087d7 SysTick_Handler 16 4 Code RX cellMon_lto.o + 080087d8-080088c7 DMA_Channel1_IRQHandler 240 4 Code RX cellMon_lto.o + 080088c8-08008a9f ADC_COMP_IRQHandler 472 4 Code RX cellMon_lto.o + 08008aa0-08008c73 EEPROM_fullRestore 468 4 Code RX cellMon_lto.o + 08008c74-08008f1f EEPROM_readConfig 684 4 Code RX cellMon_lto.o + 08008f20-08009197 EEPROM_storeConfig 632 4 Code RX cellMon_lto.o + 08009198-0800931b EEPROM_storeLogData 388 4 Code RX cellMon_lto.o + 0800931c-08009613 mbInit 760 4 Code RX cellMon_lto.o + 08009614-0800988b MODBUS_UART_IRQHandler 632 4 Code RX cellMon_lto.o + 0800988c-080099bf __aeabi_fadd 308 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 080099c0-080099cf __aeabi_fsub 16 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 080099d0-08009a87 __aeabi_fmul 184 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009a88-08009b1b __aeabi_fdiv 148 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009b1c-08009b3b __aeabi_fcmpeq 32 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009b3c-08009b6f __aeabi_fcmpge 52 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009b70-08009b9f __aeabi_fcmpgt 48 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009ba0-08009bcf __aeabi_fcmplt 48 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009bd0-08009bf3 __aeabi_f2uiz 36 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009bf4-08009c23 __aeabi_d2uiz 48 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009c24-08009c63 __aeabi_f2ulz 64 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009c64-08009c83 __aeabi_ui2f 32 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009c84-08009c9f __aeabi_ui2d 28 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009ca0-08009ccf __aeabi_ul2f 48 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009cd0-08009d33 __aeabi_d2f 100 4 Code RX floatasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009d34-08009e4b fmodf 280 4 Code RX floatops.o (libc_v6m_t_le_eabi_balanced.a) + 08009e4c-08009ea3 floorf 88 4 Code RX floatops.o (libc_v6m_t_le_eabi_balanced.a) + 08009ea4-08009ed3 __aeabi_lmul 48 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009ed4-08009f13 __aeabi_idiv 64 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009f14-08009f23 __aeabi_idivmod 16 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009f24-08009f5b __aeabi_uidiv 56 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009f5c-08009f6b __aeabi_uidivmod 16 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 08009f6c-0800a00b __aeabi_uldivmod 160 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800a00c-0800a013 __aeabi_idiv0 8 4 Code RX intasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800a014-0800a02b __SEGGER_RTL_current_locale + 24 4 Code RX mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0800a02c-0800a047 __SEGGER_RTL_ascii_isctype + 28 4 Code RX mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0800a048-0800a063 __SEGGER_RTL_ascii_iswctype + 28 4 Code RX mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0800a064-0800a073 strlen 16 4 Code RX strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800a074-0800a083 memcpy 16 4 Code RX strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800a084-0800a097 __aeabi_memclr 20 4 Code RX strasmops_arm.o (libc_v6m_t_le_eabi_balanced.a) + 0800a098-0800a117 strnlen 128 4 Code RX strops.o (libc_v6m_t_le_eabi_balanced.a) + 0800a118-0800a15f __SEGGER_RTL_pow10f 72 4 Code RX utilops.o (libc_v6m_t_le_eabi_balanced.a) + 0800a160-0800a1d7 vfprintf_l 120 4 Code RX prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0800a1d8-0800a1ff printf 40 4 Code RX prinops.o (libc_v6m_t_le_eabi_balanced.a) + 0800a200-0800af47 __SEGGER_RTL_vfprintf_short_float_long + 3 400 4 Code RX __SEGGER_RTL_vfprintf_short_float_long.o (libc_v6m_t_le_eabi_balanced.a) + 0800af48-0800af77 __SEGGER_RTL_X_file_stat 48 4 Code RX prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0800af78-0800af7b __SEGGER_RTL_X_file_bufsize + 4 4 Code RX prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0800af7c-0800af87 __SEGGER_RTL_X_file_write 12 4 Code RX prinops_rtt.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0800af88-0800afdb _DoInit 84 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0800afdc-0800b027 _WriteNoCheck 76 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0800b028-0800b08f _WriteBlocking 104 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0800b090-0800b113 SEGGER_RTT_WriteNoLock 132 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0800b114-0800b147 SEGGER_RTT_Write 52 4 Code RX SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0800b148-0800b15b __SEGGER_RTL_init_heap 20 4 Code RX heapops_basic.o (heapops_basic_v6m_t_le_eabi_balanced.a) + 0800b15c-0800b19b AHBPrescTable 64 4 Cnst RO cellMon_lto.o + 0800b19c-0800b1bb APBPrescTable 32 4 Cnst RO cellMon_lto.o + 0800b1bc-0800b1cb [.rodata..Lswitch.table.UART_SetConfig.2] + 16 4 Cnst RO cellMon_lto.o + 0800b1cc-0800b20b defaultEepromData 64 4 Cnst RO cellMon_lto.o + 0800b20c-0800b21b [.rodata..Lswitch.table.HAL_TIM_IC_Start] + 16 4 Cnst RO cellMon_lto.o + 0800b21c-0800b227 __SEGGER_RTL_c_locale 12 4 Cnst RO mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0800b228-0800b247 __SEGGER_RTL_codeset_ascii + 32 4 Cnst RO mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0800b248-0800b29f __SEGGER_RTL_c_locale_data + 88 4 Cnst RO mbops.o (libc_v6m_t_le_eabi_balanced.a) + 0800b2a0-0800b2b7 __SEGGER_RTL_aPower2f 24 4 Cnst RO utilops.o (libc_v6m_t_le_eabi_balanced.a) + 0800b2b8-0800b2cf __SEGGER_init_heap 24 4 Code RX SEGGER_crtinit.o (SEGGER_crtinit_v6m_t_le_eabi_balanced.a) + 0800b2d0-0800b2d8 [.rodata.libc._DoInit.str1.4] + 9 4 Cnst RO SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0800b2d9-0800b2ef [.rodata..L.str.4] 23 1 Cnst RO cellMon_lto.o + 0800b2f0-0800b300 _aInitStr.0 17 4 Cnst RO SEGGER_RTT.o (prinops_rtt_v6m_t_le_eabi_balanced.a) + 0800b301-0800b30f [.rodata..L.str.6] 15 1 Cnst RO cellMon_lto.o + 0800b310-0800b311 WWDG_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800b312-0800b313 PVD_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800b314-0800b315 RTC_STAMP_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800b316-0800b317 FLASH_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800b318-0800b319 RCC_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800b31a-0800b31b EXTI0_1_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800b31c-0800b31d EXTI2_3_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800b31e-0800b31f EXTI4_15_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800b320-0800b321 UCPD1_UCPD2_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800b322-0800b323 DMA_Channel2_3_IRQHandler 2 2 Code RX STM32G07x_Vectors.o + 0800b324-0800b325 DMA_Channel4_5_6_7_IRQHandler + 2 2 Code RX STM32G07x_Vectors.o + 0800b326-0800b327 TIM1_BRK_UP_TRG_COMP_IRQHandler + 2 2 Code RX STM32G07x_Vectors.o + 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created ] + + +*********************************************************************************************** +*** *** +*** SYMBOL LIST *** +*** *** +*********************************************************************************************** + +Function symbols by name: + + Symbol name Address Size Align Type Bd Object File + ------------------------- ---------- ---------- ----- ---- -- ----------- + ADC_COMP_IRQHandler 0x080088C9 472 4 Code Gb cellMon_lto.o + ADC_DMAConvCplt 0x08003215 116 4 Code Lc cellMon_lto.o + ADC_DMAError 0x0800B6FB 20 2 Code Lc cellMon_lto.o + ADC_DMAHalfConvCplt 0x0800B349 2 2 Code Lc cellMon_lto.o + AES_RNG_IRQHandler 0x0800B347 2 Code Wk STM32G07x_Vectors.o + CEC_IRQHandler 0x0800B345 2 Code Wk STM32G07x_Vectors.o + DMA_Channel1_IRQHandler 0x080087D9 240 4 Code Gb cellMon_lto.o + DMA_Channel2_3_IRQHandler 0x0800B323 2 Code Wk STM32G07x_Vectors.o + DMA_Channel4_5_6_7_IRQHandler + 0x0800B325 2 Code Wk STM32G07x_Vectors.o + EEPROM_fullRestore 0x08008AA1 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ecs_cellMon/firmware/Output/Release/Obj/cellMon/adc.d (revision 3) @@ -0,0 +1,48 @@ +Output/Release/Obj/cellMon/adc.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\adc.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ 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7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\balancer.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\led.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/bms.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/bms.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/bms.d (revision 3) @@ -0,0 +1,55 @@ +Output/Release/Obj/cellMon/bms.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\bms.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\bms.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\output.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\led.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\eeprom.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/comp.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/comp.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/comp.d (revision 3) @@ -0,0 +1,48 @@ +Output/Release/Obj/cellMon/comp.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\comp.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/dac.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/dac.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/dac.d (revision 3) @@ -0,0 +1,48 @@ +Output/Release/Obj/cellMon/dac.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\dac.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/dma.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/dma.d (revision 3) @@ -0,0 +1,48 @@ +Output/Release/Obj/cellMon/dma.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\dma.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/eeprom.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/eeprom.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/eeprom.d (revision 3) @@ -0,0 +1,53 @@ +Output/Release/Obj/cellMon/eeprom.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\eeprom.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\eeprom.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\string.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/gpio.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/gpio.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/gpio.d (revision 3) @@ -0,0 +1,48 @@ +Output/Release/Obj/cellMon/gpio.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\gpio.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/led.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/led.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/led.d (revision 3) @@ -0,0 +1,48 @@ +Output/Release/Obj/cellMon/led.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\led.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\led.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/main.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/main.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/main.d (revision 3) @@ -0,0 +1,64 @@ +Output/Release/Obj/cellMon/main.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\main.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\usart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\led.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\output.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\meas.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\balancer.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\eeprom.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\bms.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdio.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/meas.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/meas.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/meas.d (revision 3) @@ -0,0 +1,53 @@ +Output/Release/Obj/cellMon/meas.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\meas.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\meas.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\adc.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/modbus.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/modbus.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/modbus.d (revision 3) @@ -0,0 +1,51 @@ +Output/Release/Obj/cellMon/modbus.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\modbus.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdio.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/output.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/output.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/output.d (revision 3) @@ -0,0 +1,48 @@ +Output/Release/Obj/cellMon/output.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\output.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\output.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_adc.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_adc.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_adc.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_adc_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_adc_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_adc_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_adc_ex.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_comp.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_comp.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_comp.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_comp.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_comp.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_cortex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_cortex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_cortex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_cortex.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cortex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_dac.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_dac.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_dac.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_dac.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dac.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_dac_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_dac_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_dac_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_dac_ex.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dac_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_dma.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_dma.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_dma.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_dma_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_dma_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_dma_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_dma_ex.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_exti.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_exti.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_exti.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_exti.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_exti.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_flash.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_flash.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_flash.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_flash.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_flash_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_flash_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_flash_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_flash_ex.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_gpio.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_gpio.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_gpio.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_gpio.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_gpio.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_msp.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_msp.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_msp.d (revision 3) @@ -0,0 +1,47 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_msp.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\stm32g0xx_hal_msp.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_pwr.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_pwr.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_pwr.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_pwr.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_pwr_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_pwr_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_pwr_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_pwr_ex.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_rcc.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_rcc.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_rcc.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_rcc.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_rcc_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_rcc_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_rcc_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_rcc_ex.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_tim.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_tim.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_tim.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_tim.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_tim_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_tim_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_tim_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_tim_ex.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_uart.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_uart.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_uart.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_uart.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_uart_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_uart_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_hal_uart_ex.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/stm32g0xx_hal_uart_ex.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart_ex.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_it.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_it.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_it.d (revision 3) @@ -0,0 +1,50 @@ +Output/Release/Obj/cellMon/stm32g0xx_it.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\stm32g0xx_it.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_it.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_ll_adc.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_ll_adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_ll_adc.d (revision 3) @@ -0,0 +1,2 @@ +Output/Release/Obj/cellMon/stm32g0xx_ll_adc.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_adc.c Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_ll_dma.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_ll_dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_ll_dma.d (revision 3) @@ -0,0 +1,2 @@ +Output/Release/Obj/cellMon/stm32g0xx_ll_dma.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_dma.c Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_ll_rcc.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_ll_rcc.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/stm32g0xx_ll_rcc.d (revision 3) @@ -0,0 +1,2 @@ +Output/Release/Obj/cellMon/stm32g0xx_ll_rcc.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_rcc.c Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/sysdata.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/sysdata.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/sysdata.d (revision 3) @@ -0,0 +1,50 @@ +Output/Release/Obj/cellMon/sysdata.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\sysdata.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdbool.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/system_stm32g0xx.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/system_stm32g0xx.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/system_stm32g0xx.d (revision 3) @@ -0,0 +1,46 @@ +Output/Release/Obj/cellMon/system_stm32g0xx.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Source\system_stm32g0xx.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/template.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/template.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/template.d (revision 3) @@ -0,0 +1,3 @@ +Output/Release/Obj/cellMon/template.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\src\template.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Inc\template.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/tim.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/tim.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/tim.d (revision 3) @@ -0,0 +1,48 @@ +Output/Release/Obj/cellMon/tim.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\tim.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/cellMon/usart.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/cellMon/usart.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/cellMon/usart.d (revision 3) @@ -0,0 +1,48 @@ +Output/Release/Obj/cellMon/usart.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Src\usart.c \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\usart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 7.12a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/SEGGER_THUMB_Startup.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/SEGGER_THUMB_Startup.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/SEGGER_THUMB_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Output/Release/Obj/lipro1_6_v2_main/SEGGER_THUMB_Startup.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\SEGGER_THUMB_Startup.s Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/STM32G07x_Vectors.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/STM32G07x_Vectors.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/STM32G07x_Vectors.d (revision 3) @@ -0,0 +1,2 @@ +Output/Release/Obj/lipro1_6_v2_main/STM32G07x_Vectors.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\Source\STM32G07x_Vectors.s Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/STM32G0xx_Startup.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/STM32G0xx_Startup.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/STM32G0xx_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Output/Release/Obj/lipro1_6_v2_main/STM32G0xx_Startup.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\Source\STM32G0xx_Startup.s Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/adc.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/adc.d (revision 3) @@ -0,0 +1,51 @@ +Output/Release/Obj/lipro1_6_v2_main/adc.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\adc.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/balancer.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/balancer.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/balancer.d (revision 3) @@ -0,0 +1,61 @@ +Output/Release/Obj/lipro1_6_v2_main/balancer.bc: \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\src\balancer.c \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdio.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\__SEGGER_RTL_Arm_Conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\balancer.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stddef.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.34a\include\stdbool.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_greenPowerPack\ecs_cellMon\lipro1-6_v2\firmware\Inc\led.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/bms.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/bms.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/bms.d (revision 3) @@ -0,0 +1,60 @@ +Output/Release/Obj/lipro1_6_v2_main/bms.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\bms.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\bms.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdbool.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\output.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\led.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\eeprom.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/comp.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/comp.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/comp.d (revision 3) @@ -0,0 +1,51 @@ +Output/Release/Obj/lipro1_6_v2_main/comp.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\comp.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/dac.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/dac.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/dac.d (revision 3) @@ -0,0 +1,51 @@ +Output/Release/Obj/lipro1_6_v2_main/dac.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\dac.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/dma.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/dma.d (revision 3) @@ -0,0 +1,51 @@ +Output/Release/Obj/lipro1_6_v2_main/dma.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\dma.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/eeprom.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/eeprom.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/eeprom.d (revision 3) @@ -0,0 +1,59 @@ +Output/Release/Obj/lipro1_6_v2_main/eeprom.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\eeprom.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\eeprom.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdbool.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdio.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\string.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\string.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/gpio.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/gpio.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/gpio.d (revision 3) @@ -0,0 +1,51 @@ +Output/Release/Obj/lipro1_6_v2_main/gpio.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\gpio.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/led.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/led.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/led.d (revision 3) @@ -0,0 +1,51 @@ +Output/Release/Obj/lipro1_6_v2_main/led.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\led.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\led.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/lipro1_6_v2_main.ind =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/lipro1_6_v2_main.ind (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/lipro1_6_v2_main.ind (revision 3) @@ -0,0 +1,53 @@ +"Output/Release/Obj/lipro1_6_v2_main/system_stm32g0xx.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc_ex.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_comp.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_cortex.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac_ex.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma_ex.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_exti.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash_ex.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_gpio.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr_ex.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc_ex.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim_ex.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart_ex.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_adc.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_dma.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_rcc.bc" +"Output/Release/Obj/lipro1_6_v2_main/dma.bc" +"Output/Release/Obj/lipro1_6_v2_main/adc.bc" +"Output/Release/Obj/lipro1_6_v2_main/comp.bc" +"Output/Release/Obj/lipro1_6_v2_main/dac.bc" +"Output/Release/Obj/lipro1_6_v2_main/gpio.bc" +"Output/Release/Obj/lipro1_6_v2_main/main.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_msp.bc" +"Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_it.bc" +"Output/Release/Obj/lipro1_6_v2_main/usart.bc" +"Output/Release/Obj/lipro1_6_v2_main/tim.bc" +"Output/Release/Obj/lipro1_6_v2_main/led.bc" +"Output/Release/Obj/lipro1_6_v2_main/template.bc" +"Output/Release/Obj/lipro1_6_v2_main/output.bc" +"Output/Release/Obj/lipro1_6_v2_main/meas.bc" +"Output/Release/Obj/lipro1_6_v2_main/sysdata.bc" +"Output/Release/Obj/lipro1_6_v2_main/balancer.bc" +"Output/Release/Obj/lipro1_6_v2_main/modbus.bc" +"Output/Release/Obj/lipro1_6_v2_main/bms.bc" +"Output/Release/Obj/lipro1_6_v2_main/eeprom.bc" +"Output/Release/Obj/lipro1_6_v2_main/SEGGER_THUMB_Startup.o" +"Output/Release/Obj/lipro1_6_v2_main/STM32G0xx_Startup.o" +"Output/Release/Obj/lipro1_6_v2_main/STM32G07x_Vectors.o" +"C:/Users/ecs/AppData/Local/SEGGER/SEGGER Embedded Studio/v3/packages/libraries/libcxx/lib/libcxx_noexcept_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 6.34a/lib/libc_v6m_t_le_eabi_balanced.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 6.34a/lib/SEGGER_crtinit_v6m_little.o" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 6.34a/lib/prinops_rtt_v6m_little.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 6.34a/lib/heapops_basic_v6m_little.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 6.34a/lib/heapops_disable_interrupts_locking_v6m_little.a" Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/main.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/main.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/main.d (revision 3) @@ -0,0 +1,69 @@ +Output/Release/Obj/lipro1_6_v2_main/main.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\main.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\usart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\led.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\output.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\meas.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdbool.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\balancer.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\eeprom.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\bms.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdio.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/meas.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/meas.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/meas.d (revision 3) @@ -0,0 +1,58 @@ +Output/Release/Obj/lipro1_6_v2_main/meas.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\meas.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\meas.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\adc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdbool.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/modbus.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/modbus.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/modbus.d (revision 3) @@ -0,0 +1,56 @@ +Output/Release/Obj/lipro1_6_v2_main/modbus.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\modbus.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdbool.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdio.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/output.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/output.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/output.d (revision 3) @@ -0,0 +1,51 @@ +Output/Release/Obj/lipro1_6_v2_main/output.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\output.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\output.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_adc_ex.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_comp.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_comp.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_comp.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_comp.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_comp.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_cortex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_cortex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_cortex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_cortex.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cortex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dac.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dac_ex.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dac_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_dma_ex.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_exti.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_exti.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_exti.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_exti.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_exti.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_flash_ex.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_gpio.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_gpio.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_gpio.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_gpio.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_gpio.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_msp.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_msp.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_msp.d (revision 3) @@ -0,0 +1,50 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_msp.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\stm32g0xx_hal_msp.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_pwr_ex.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_rcc_ex.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_tim_ex.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart_ex.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart_ex.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_hal_uart_ex.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_it.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_it.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_it.d (revision 3) @@ -0,0 +1,54 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_it.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\stm32g0xx_it.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_it.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdbool.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_adc.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_adc.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_adc.d (revision 3) @@ -0,0 +1,2 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_adc.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_adc.c Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_dma.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_dma.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_dma.d (revision 3) @@ -0,0 +1,2 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_dma.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_dma.c Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_rcc.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_rcc.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_rcc.d (revision 3) @@ -0,0 +1,2 @@ +Output/Release/Obj/lipro1_6_v2_main/stm32g0xx_ll_rcc.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_rcc.c Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/sysdata.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/sysdata.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/sysdata.d (revision 3) @@ -0,0 +1,54 @@ +Output/Release/Obj/lipro1_6_v2_main/sysdata.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\sysdata.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdbool.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdbool.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/system_stm32g0xx.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/system_stm32g0xx.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/system_stm32g0xx.d (revision 3) @@ -0,0 +1,49 @@ +Output/Release/Obj/lipro1_6_v2_main/system_stm32g0xx.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Source\system_stm32g0xx.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/template.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/template.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/template.d (revision 3) @@ -0,0 +1,3 @@ +Output/Release/Obj/lipro1_6_v2_main/template.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\template.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\template.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/tim.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/tim.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/tim.d (revision 3) @@ -0,0 +1,51 @@ +Output/Release/Obj/lipro1_6_v2_main/tim.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\tim.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/usart.d =================================================================== --- ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/usart.d (revision 3) +++ ecs_cellMon/firmware/Output/Release/Obj/lipro1_6_v2_main/usart.d (revision 3) @@ -0,0 +1,51 @@ +Output/Release/Obj/lipro1_6_v2_main/usart.bc: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\usart.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\usart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stdint.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\__config \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_ConfDefaults.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Conf.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\__SEGGER_RTL_Arm_Conf.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Users\zed\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\libraries\libcxx\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 6.32\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/SEGGER_THUMB_Startup.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/SEGGER_THUMB_Startup.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/SEGGER_THUMB_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Output/lipro1_6_v2_main\ Release/Obj/SEGGER_THUMB_Startup.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\SEGGER_THUMB_Startup.s Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/STM32G07x_Vectors.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/STM32G07x_Vectors.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/STM32G07x_Vectors.d (revision 3) @@ -0,0 +1,2 @@ +Output/lipro1_6_v2_main\ Release/Obj/STM32G07x_Vectors.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\Source\STM32G07x_Vectors.s Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/STM32G0xx_Startup.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/STM32G0xx_Startup.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/STM32G0xx_Startup.d (revision 3) @@ -0,0 +1,2 @@ +Output/lipro1_6_v2_main\ Release/Obj/STM32G0xx_Startup.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\Source\STM32G0xx_Startup.s Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/adc.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/adc.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/adc.d (revision 3) @@ -0,0 +1,46 @@ +Output/lipro1_6_v2_main Release/Obj/adc.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\adc.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/balancer.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/balancer.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/balancer.d (revision 3) @@ -0,0 +1,52 @@ +Output/lipro1_6_v2_main Release/Obj/balancer.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\balancer.c \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\balancer.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\comp.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/bms.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/bms.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/bms.d (revision 3) @@ -0,0 +1,49 @@ +Output/lipro1_6_v2_main Release/Obj/bms.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\bms.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\bms.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\output.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\led.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/comp.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/comp.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/comp.d (revision 3) @@ -0,0 +1,46 @@ +Output/lipro1_6_v2_main Release/Obj/comp.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\comp.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/dac.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/dac.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/dac.d (revision 3) @@ -0,0 +1,46 @@ +Output/lipro1_6_v2_main Release/Obj/dac.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\dac.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/dma.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/dma.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/dma.d (revision 3) @@ -0,0 +1,46 @@ +Output/lipro1_6_v2_main Release/Obj/dma.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\dma.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/eeprom.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/eeprom.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/eeprom.d (revision 3) @@ -0,0 +1,50 @@ +Output/lipro1_6_v2_main Release/Obj/eeprom.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\eeprom.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\eeprom.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdbool.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdio.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\string.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/gpio.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/gpio.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/gpio.d (revision 3) @@ -0,0 +1,46 @@ +Output/lipro1_6_v2_main Release/Obj/gpio.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\gpio.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/led.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/led.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/led.d (revision 3) @@ -0,0 +1,46 @@ +Output/lipro1_6_v2_main Release/Obj/led.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\led.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\led.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/lipro1_6_v2_main.ind =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/lipro1_6_v2_main.ind (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/lipro1_6_v2_main.ind (revision 3) @@ -0,0 +1,54 @@ +"Output/lipro1_6_v2_main Release/Obj/system_stm32g0xx.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_adc.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_adc_ex.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_comp.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_cortex.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dac.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dac_ex.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dma.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dma_ex.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_exti.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_flash.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_flash_ex.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_gpio.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_pwr.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_pwr_ex.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_rcc.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_rcc_ex.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_tim.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_tim_ex.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_uart.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_uart_ex.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_adc.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_dma.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_rcc.o" +"Output/lipro1_6_v2_main Release/Obj/dma.o" +"Output/lipro1_6_v2_main Release/Obj/adc.o" +"Output/lipro1_6_v2_main Release/Obj/comp.o" +"Output/lipro1_6_v2_main Release/Obj/dac.o" +"Output/lipro1_6_v2_main Release/Obj/gpio.o" +"Output/lipro1_6_v2_main Release/Obj/main.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_msp.o" +"Output/lipro1_6_v2_main Release/Obj/stm32g0xx_it.o" +"Output/lipro1_6_v2_main Release/Obj/usart.o" +"Output/lipro1_6_v2_main Release/Obj/tim.o" +"Output/lipro1_6_v2_main Release/Obj/led.o" +"Output/lipro1_6_v2_main Release/Obj/template.o" +"Output/lipro1_6_v2_main Release/Obj/output.o" +"Output/lipro1_6_v2_main Release/Obj/meas.o" +"Output/lipro1_6_v2_main Release/Obj/sysdata.o" +"Output/lipro1_6_v2_main Release/Obj/balancer.o" +"Output/lipro1_6_v2_main Release/Obj/modbus.o" +"Output/lipro1_6_v2_main Release/Obj/bms.o" +"Output/lipro1_6_v2_main Release/Obj/eeprom.o" +"Output/lipro1_6_v2_main Release/Obj/SEGGER_THUMB_Startup.o" +"Output/lipro1_6_v2_main Release/Obj/STM32G0xx_Startup.o" +"Output/lipro1_6_v2_main Release/Obj/STM32G07x_Vectors.o" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libdebugio_mempoll_v6m_t_le_eabi.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libm_v6m_t_le_eabi.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libc_v6m_t_le_eabi.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libcpp_v6m_t_le_eabi.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libdebugio_v6m_t_le_eabi.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libvfprintf_v6m_t_le_eabi.o" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libvfscanf_v6m_t_le_eabi.o" Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/lipro1_6_v2_main_link.ind =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/lipro1_6_v2_main_link.ind (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/lipro1_6_v2_main_link.ind (revision 3) @@ -0,0 +1,10 @@ +"Output/lipro1_6_v2_main Release/Obj/SEGGER_THUMB_Startup.o" +"Output/lipro1_6_v2_main Release/Obj/STM32G0xx_Startup.o" +"Output/lipro1_6_v2_main Release/Obj/STM32G07x_Vectors.o" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libdebugio_mempoll_v6m_t_le_eabi.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libm_v6m_t_le_eabi.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libc_v6m_t_le_eabi.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libcpp_v6m_t_le_eabi.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libdebugio_v6m_t_le_eabi.a" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libvfprintf_v6m_t_le_eabi.o" +"C:/Program Files/SEGGER/SEGGER Embedded Studio for ARM 4.52c/lib/libvfscanf_v6m_t_le_eabi.o" Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/main.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/main.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/main.d (revision 3) @@ -0,0 +1,64 @@ +Output/lipro1_6_v2_main Release/Obj/main.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\main.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\usart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\led.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\output.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\meas.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\balancer.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdbool.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\eeprom.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\bms.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdio.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/meas.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/meas.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/meas.d (revision 3) @@ -0,0 +1,50 @@ +Output/lipro1_6_v2_main Release/Obj/meas.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\meas.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\meas.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/modbus.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/modbus.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/modbus.d (revision 3) @@ -0,0 +1,50 @@ +Output/lipro1_6_v2_main Release/Obj/modbus.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\modbus.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdbool.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdio.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/output.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/output.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/output.d (revision 3) @@ -0,0 +1,46 @@ +Output/lipro1_6_v2_main Release/Obj/output.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\output.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\output.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_adc.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_adc.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_adc.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_adc.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_adc_ex.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_adc_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_adc_ex.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_adc_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_adc_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_comp.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_comp.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_comp.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_comp.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_comp.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_cortex.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_cortex.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_cortex.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_cortex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_cortex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dac.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dac.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dac.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dac.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dac.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dac_ex.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dac_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dac_ex.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dac_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dac_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dma.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dma.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dma.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dma.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dma_ex.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dma_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dma_ex.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_dma_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_dma_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_exti.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_exti.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_exti.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_exti.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_exti.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_flash.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_flash.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_flash.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_flash.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_flash_ex.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_flash_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_flash_ex.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_flash_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_flash_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_gpio.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_gpio.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_gpio.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_gpio.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_gpio.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_msp.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_msp.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_msp.d (revision 3) @@ -0,0 +1,45 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_msp.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\stm32g0xx_hal_msp.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_pwr.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_pwr.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_pwr.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_pwr.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_pwr_ex.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_pwr_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_pwr_ex.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_pwr_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_pwr_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_rcc.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_rcc.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_rcc.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_rcc.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_rcc_ex.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_rcc_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_rcc_ex.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_rcc_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_rcc_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_tim.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_tim.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_tim.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_tim.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_tim_ex.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_tim_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_tim_ex.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_tim_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_tim_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_uart.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_uart.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_uart.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_uart.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_uart_ex.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_uart_ex.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_uart_ex.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_hal_uart_ex.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_hal_uart_ex.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_it.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_it.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_it.d (revision 3) @@ -0,0 +1,49 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_it.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\stm32g0xx_it.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_it.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\modbus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdbool.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_adc.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_adc.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_adc.d (revision 3) @@ -0,0 +1,2 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_adc.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_adc.c Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_dma.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_dma.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_dma.d (revision 3) @@ -0,0 +1,2 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_dma.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_dma.c Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_rcc.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_rcc.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_rcc.d (revision 3) @@ -0,0 +1,2 @@ +Output/lipro1_6_v2_main Release/Obj/stm32g0xx_ll_rcc.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Src\stm32g0xx_ll_rcc.c Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/sysdata.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/sysdata.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/sysdata.d (revision 3) @@ -0,0 +1,46 @@ +Output/lipro1_6_v2_main Release/Obj/sysdata.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\sysdata.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\sysdata.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/system_stm32g0xx.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/system_stm32g0xx.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/system_stm32g0xx.d (revision 3) @@ -0,0 +1,44 @@ +Output/lipro1_6_v2_main Release/Obj/system_stm32g0xx.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Source\system_stm32g0xx.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/template.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/template.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/template.d (revision 3) @@ -0,0 +1,3 @@ +Output/lipro1_6_v2_main Release/Obj/template.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\src\template.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Inc\template.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/tim.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/tim.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/tim.d (revision 3) @@ -0,0 +1,46 @@ +Output/lipro1_6_v2_main Release/Obj/tim.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\tim.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/usart.d =================================================================== --- ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/usart.d (revision 3) +++ ecs_cellMon/firmware/Output/lipro1_6_v2_main Release/Obj/usart.d (revision 3) @@ -0,0 +1,46 @@ +Output/lipro1_6_v2_main Release/Obj/usart.o: \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Src\usart.c \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\usart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\main.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Core\Inc\stm32g0xx_hal_conf.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_def.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\stm32g071xx.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\core_cm0plus.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stdint.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_version.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_compiler.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\cmsis_gcc.h \ + C:\Users\ecs\AppData\Local\SEGGER\SEGGER\ Embedded\ Studio\v3\packages\CMSIS_5\CMSIS\Core\Include\mpu_armv7.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\STM32G0xx\CMSIS\Device\Include\system_stm32g0xx.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\stddef.h \ + C:\Program\ Files\SEGGER\SEGGER\ Embedded\ Studio\ for\ ARM\ 4.52c\include\__crossworks.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_rcc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_rcc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_gpio_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dma.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_dmamux.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dma_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_cortex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_adc.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_adc_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_comp.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_ll_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_dac_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_exti.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_flash_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_pwr_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_tim_ex.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart.h \ + D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Drivers\STM32G0xx_HAL_Driver\Inc\stm32g0xx_hal_uart_ex.h Index: ecs_cellMon/firmware/SEGGER_THUMB_Startup.s =================================================================== --- ecs_cellMon/firmware/SEGGER_THUMB_Startup.s (revision 3) +++ ecs_cellMon/firmware/SEGGER_THUMB_Startup.s (revision 3) @@ -0,0 +1,281 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2021 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : SEGGER_THUMB_Startup.s +Purpose : Generic runtime init startup code for ARM CPUs running + in THUMB mode. + Designed to work with the SEGGER linker to produce + smallest possible executables. + + This file does not normally require any customization. + +Additional information: + Preprocessor Definitions + FULL_LIBRARY + If defined then + - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). + - the exit symbol is defined and executes on return from main. + - the exit symbol calls destructors, atexit functions and then + calls SEGGER_SEMIHOST_Exit(). + + If not defined then + - argc and argv are not valid (main is assumed to not take parameters) + - the exit symbol is defined, executes on return from main and + halts in a loop. +*/ + + .syntax unified + +/********************************************************************* +* +* Defines, configurable +* +********************************************************************** +*/ + +#ifndef APP_ENTRY_POINT + #define APP_ENTRY_POINT main +#endif + +#ifndef ARGSSPACE + #define ARGSSPACE 128 +#endif + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ +// +// Declare a label as function symbol (without switching sections) +// +.macro MARK_FUNC Name + .global \Name + .thumb_func + .code 16 +\Name: +.endm +// +// Declare a regular function. +// Functions from the startup are placed in the init section. +// +.macro START_FUNC Name + .section .init.\Name, "ax" + .global \Name + .balign 2 + .thumb_func + .code 16 +\Name: +.endm + +// +// Declare a weak function +// +.macro WEAK_FUNC Name + .section .init.\Name, "ax", %progbits + .global \Name + .weak \Name + .balign 2 + .thumb_func + .code 16 +\Name: +.endm + +// +// Mark the end of a function and calculate its size +// +.macro END_FUNC name + .size \name,.-\name +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern APP_ENTRY_POINT // typically main + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* _start +* +* Function description +* Entry point for the startup code. +* Usually called by the reset handler. +* Performs all initialisation, based on the entries in the +* linker-generated init table, then calls main(). +* It is device independent, so there should not be any need for an +* end-user to modify it. +* +* Additional information +* At this point, the stack pointer should already have been +* initialized +* - by hardware (such as on Cortex-M), +* - by the device-specific reset handler, +* - or by the debugger (such as for RAM Code). +*/ +#undef L +#define L(label) .L_start_##label + +START_FUNC _start + // + // Call linker init functions which in turn performs the following: + // * Perform segment init + // * Perform heap init (if used) + // * Call constructors of global Objects (if any exist) + // + ldr R4, =__SEGGER_init_table__ // Set table pointer to start of initialization table +L(RunInit): + ldr R0, [R4] // Get next initialization function from table + adds R4, R4, #4 // Increment table pointer to point to function arguments + blx R0 // Call initialization function + b L(RunInit) + // +MARK_FUNC __SEGGER_init_done + // + // Time to call main(), the application entry point. + // +#ifndef FULL_LIBRARY + // + // In a real embedded application ("Free-standing environment"), + // main() does not get any arguments, + // which means it is not necessary to init R0 and R1. + // + bl APP_ENTRY_POINT // Call to application entry point (usually main()) + +END_FUNC _start + // + // end of _start + // Fall-through to exit if main ever returns. + // +MARK_FUNC exit + // + // In a free-standing environment, if returned from application: + // Loop forever. + // + b . + .size exit,.-exit +#else + // + // In a hosted environment, + // we need to load R0 and R1 with argc and argv, in order to handle + // the command line arguments. + // This is required for some programs running under control of a + // debugger, such as automated tests. + // + movs R0, #ARGSSPACE + ldr R1, =__SEGGER_init_arg_data + bl SEGGER_SEMIHOST_GetArgs + ldr R1, =__SEGGER_init_arg_data + bl APP_ENTRY_POINT // Call to application entry point (usually main()) + bl exit // Call exit function + b . // If we unexpectedly return from exit, hang. +END_FUNC _start +#endif + // +#ifdef FULL_LIBRARY +/********************************************************************* +* +* exit +* +* Function description +* Exit of the system. +* Called on return from application entry point or explicit call +* to exit. +* +* Additional information +* In a hosted environment exit gracefully, by +* saving the return value, +* calling destructurs of global objects, +* calling registered atexit functions, +* and notifying the host/debugger. +*/ +#undef L +#define L(label) .L_exit_##label + +WEAK_FUNC exit + mov R5, R0 // Save the exit parameter/return result + // + // Call destructors + // + ldr R0, =__dtors_start__ // Pointer to destructor list + ldr R1, =__dtors_end__ +L(Loop): + cmp R0, R1 + beq L(End) // Reached end of destructor list? => Done + ldr R2, [R0] // Load current destructor address into R2 + adds R0, R0, #4 // Increment pointer + push {R0-R1} // Save R0 and R1 + blx R2 // Call destructor + pop {R0-R1} // Restore R0 and R1 + b L(Loop) +L(End): + // + // Call atexit functions + // + bl __SEGGER_RTL_execute_at_exit_fns + // + // Call debug_exit with return result/exit parameter + // + mov R0, R5 + bl SEGGER_SEMIHOST_Exit + // + // If execution is not terminated, loop forever + // +L(ExitLoop): + b L(ExitLoop) // Loop forever. +END_FUNC exit +#endif + +#ifdef FULL_LIBRARY + .bss +__SEGGER_init_arg_data: + .space ARGSSPACE + .size __SEGGER_init_arg_data, .-__SEGGER_init_arg_data + .type __SEGGER_init_arg_data, %object +#endif + +/*************************** End of file ****************************/ Index: ecs_cellMon/firmware/STM32G071C8Tx_FLASH.icf =================================================================== --- ecs_cellMon/firmware/STM32G071C8Tx_FLASH.icf (revision 3) +++ ecs_cellMon/firmware/STM32G071C8Tx_FLASH.icf (revision 3) @@ -0,0 +1,23 @@ +define memory with size = 4G; + +define symbol _estack = 0x20009000; +define region RAM = [0x20000000 size 0x9000]; +define region FLASH = [0x8000000 size 0x10000]; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block exidx { section .ARM.exidx, section .ARM.exidx.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, readwrite access { }; +do not initialize { section .non_init }; +initialize by copy { section .fast }; + +place in FLASH { section .isr_vector }; +keep { section .isr_vector }; +place in FLASH { section .init, section .init.*, section .text, section .text.*, section .rodata, section .rodata.*, section .segger.*, block exidx, block ctors, block dtors }; +place in RAM { section .data, section .data.*, section .RamFunc* }; +place in RAM { section .bss, section .bss.* }; +place in RAM { block heap, block tls, section .non_init, section .fast }; +define symbol __stack_end__ = _estack; Index: ecs_cellMon/firmware/STM32G071C8Tx_FLASH.ld =================================================================== --- ecs_cellMon/firmware/STM32G071C8Tx_FLASH.ld (revision 3) +++ ecs_cellMon/firmware/STM32G071C8Tx_FLASH.ld (revision 3) @@ -0,0 +1,189 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : Auto-generated by System Workbench for STM32 +** +** Abstract : Linker script for STM32G071C8Tx series +** 64Kbytes FLASH and 36Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2019 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20009000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x2000; /* required amount of heap */ +_Min_Stack_Size = 0x4000; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 36K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} + + Index: ecs_cellMon/firmware/STM32G071C8Tx_MemoryMap.xml =================================================================== --- ecs_cellMon/firmware/STM32G071C8Tx_MemoryMap.xml (revision 3) +++ ecs_cellMon/firmware/STM32G071C8Tx_MemoryMap.xml (revision 3) @@ -0,0 +1,5 @@ + + + + + Index: ecs_cellMon/firmware/STM32G07x_Registers.xml =================================================================== --- ecs_cellMon/firmware/STM32G07x_Registers.xml (revision 3) +++ ecs_cellMon/firmware/STM32G07x_Registers.xml (revision 3) @@ -0,0 +1,5861 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + Index: ecs_cellMon/firmware/STM32G0xx/CMSIS/Device/Include/stm32g070xx.h =================================================================== --- ecs_cellMon/firmware/STM32G0xx/CMSIS/Device/Include/stm32g070xx.h (revision 3) +++ ecs_cellMon/firmware/STM32G0xx/CMSIS/Device/Include/stm32g070xx.h (revision 3) @@ -0,0 +1,7639 @@ +/** + ****************************************************************************** + * @file stm32g070xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32g070xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g070xx + * @{ + */ + +#ifndef STM32G070xx_H +#define STM32G070xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1 /*!< STM32G0xx provides an MPU */ +#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< STM32G0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32g070xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */ + ADC1_IRQn = 12, /*!< ADC1 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM6_IRQn = 17, /*!< TIM6 global Interrupts */ + TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + USART3_4_IRQn = 29, /*!< USART3, USART4 globlal Interrupts */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32g0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x24--0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x34--0x38 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ + __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */ + uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ +} TAMP_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[25]; /*!< Reserved 0x1C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */ + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) +#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) +#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART4 ((USART_TypeDef *) USART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) + +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ +#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ +#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ +#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ +#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ +#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ +#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ +#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ +#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ +#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ +#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ +#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ +#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ + +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ + +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ + +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ + +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *******************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ********************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ********************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/******************************************************************************/ +/* */ +/* DMAMUX Controller */ +/* */ +/******************************************************************************/ +/******************** Bits definition for DMAMUX_CxCR register **************/ +#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U) +#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */ +#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */ +#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */ +#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */ +#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */ +#define DMAMUX_CxCR_SOIE_Pos (8U) +#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */ +#define DMAMUX_CxCR_EGE_Pos (9U) +#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */ +#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */ +#define DMAMUX_CxCR_SE_Pos (16U) +#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */ +#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */ +#define DMAMUX_CxCR_SPOL_Pos (17U) +#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */ +#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_CxCR_NBREQ_Pos (19U) +#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */ +#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */ +#define DMAMUX_CxCR_SYNC_ID_Pos (24U) +#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */ +#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */ +#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */ +#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */ +#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */ +#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */ +#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */ + +/******************* Bits definition for DMAMUX_CSR register **************/ +#define DMAMUX_CSR_SOF0_Pos (0U) +#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */ +#define DMAMUX_CSR_SOF1_Pos (1U) +#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */ +#define DMAMUX_CSR_SOF2_Pos (2U) +#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */ +#define DMAMUX_CSR_SOF3_Pos (3U) +#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */ +#define DMAMUX_CSR_SOF4_Pos (4U) +#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */ +#define DMAMUX_CSR_SOF5_Pos (5U) +#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */ +#define DMAMUX_CSR_SOF6_Pos (6U) +#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */ + +/******************** Bits definition for DMAMUX_CFR register **************/ +#define DMAMUX_CFR_CSOF0_Pos (0U) +#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */ +#define DMAMUX_CFR_CSOF1_Pos (1U) +#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */ +#define DMAMUX_CFR_CSOF2_Pos (2U) +#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */ +#define DMAMUX_CFR_CSOF3_Pos (3U) +#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */ +#define DMAMUX_CFR_CSOF4_Pos (4U) +#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */ +#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */ +#define DMAMUX_CFR_CSOF5_Pos (5U) +#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */ +#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */ +#define DMAMUX_CFR_CSOF6_Pos (6U) +#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */ +#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */ + +/******************** Bits definition for DMAMUX_RGxCR register ************/ +#define DMAMUX_RGxCR_SIG_ID_Pos (0U) +#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */ +#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */ +#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */ +#define DMAMUX_RGxCR_OIE_Pos (8U) +#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */ +#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */ +#define DMAMUX_RGxCR_GE_Pos (16U) +#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */ +#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */ +#define DMAMUX_RGxCR_GPOL_Pos (17U) +#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */ +#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */ +#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */ +#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */ +#define DMAMUX_RGxCR_GNBREQ_Pos (19U) +#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */ +#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */ +#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */ +#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */ +#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */ +#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */ +#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for DMAMUX_RGSR register **************/ +#define DMAMUX_RGSR_OF0_Pos (0U) +#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */ +#define DMAMUX_RGSR_OF1_Pos (1U) +#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */ +#define DMAMUX_RGSR_OF2_Pos (2U) +#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */ +#define DMAMUX_RGSR_OF3_Pos (3U) +#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */ + +/******************** Bits definition for DMAMUX_RGCFR register **************/ +#define DMAMUX_RGCFR_COF0_Pos (0U) +#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */ +#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */ +#define DMAMUX_RGCFR_COF1_Pos (1U) +#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */ +#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */ +#define DMAMUX_RGCFR_COF2_Pos (2U) +#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */ +#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */ +#define DMAMUX_RGCFR_COF3_Pos (3U) +#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */ +#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM19_Pos (19U) +#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ +#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ +#define EXTI_IMR1_IM20_Pos (20U) +#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ +#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */ +#define EXTI_IMR1_IM21_Pos (21U) +#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ +#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ +#define EXTI_IMR1_IM22_Pos (22U) +#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ +#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */ +#define EXTI_IMR1_IM23_Pos (23U) +#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ +#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ +#define EXTI_IMR1_IM24_Pos (24U) +#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ +#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ +#define EXTI_IMR1_IM25_Pos (25U) +#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ +#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ +#define EXTI_IMR1_IM26_Pos (26U) +#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ +#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */ +#define EXTI_IMR1_IM31_Pos (31U) +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ +#define EXTI_IMR1_IM_Pos (0U) +#define EXTI_IMR1_IM_Msk (0x86A8FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x86A8FFFFU */ +#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ + + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ +#define EXTI_EMR1_EM19_Pos (19U) +#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ +#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ +#define EXTI_EMR1_EM21_Pos (21U) +#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ +#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ +#define EXTI_EMR1_EM23_Pos (23U) +#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ +#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ +#define EXTI_EMR1_EM25_Pos (25U) +#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ +#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ +#define EXTI_EMR1_EM26_Pos (26U) +#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ +#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */ +#define EXTI_EMR1_EM31_Pos (31U) +#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ +#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +/* Note: No specific macro feature on this device */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk +#define FLASH_ACR_ICEN_Pos (9U) +#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ +#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk +#define FLASH_ACR_ICRST_Pos (11U) +#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk +#define FLASH_ACR_PROGEMPTY_Pos (16U) +#define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */ +#define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk + +/******************* Bits definition for FLASH_SR register ******************/ +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_OPERR_Pos (1U) +#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_PROGERR_Pos (3U) +#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_PGAERR_Pos (5U) +#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk +#define FLASH_SR_SIZERR_Pos (6U) +#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk +#define FLASH_SR_PGSERR_Pos (7U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_MISERR_Pos (8U) +#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */ +#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk +#define FLASH_SR_FASTERR_Pos (9U) +#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */ +#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY1_Pos (16U) +#define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk +#define FLASH_SR_CFGBSY_Pos (18U) +#define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */ +#define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk + +/******************* Bits definition for FLASH_CR register ******************/ +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER1_Pos (2U) +#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER1 FLASH_CR_MER1_Msk +#define FLASH_CR_PNB_Pos (3U) +#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_CR_PNB FLASH_CR_PNB_Msk +#define FLASH_CR_STRT_Pos (16U) +#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_CR_STRT FLASH_CR_STRT_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_FSTPG_Pos (18U) +#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */ +#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +/******************* Bits definition for FLASH_ECCR register ****************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk +#define FLASH_ECCR_SYSF_ECC_Pos (20U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk +#define FLASH_ECCR_ECCCIE_Pos (24U) +#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk + +/******************* Bits definition for FLASH_OPTR register ****************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk +#define FLASH_OPTR_nRST_STOP_Pos (13U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk +#define FLASH_OPTR_nRST_STDBY_Pos (14U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk +#define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) +#define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk +#define FLASH_OPTR_nBOOT_SEL_Pos (24U) +#define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk +#define FLASH_OPTR_nBOOT1_Pos (25U) +#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk +#define FLASH_OPTR_nBOOT0_Pos (26U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk + + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk +#define FLASH_WRP1AR_WRP1A_END_Pos (16U) +#define FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x003F0000 */ +#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000003F */ +#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk +#define FLASH_WRP1BR_WRP1B_END_Pos (16U) +#define FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x003F0000 */ +#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk + + + +/******************************************************************************/ +/* */ +/* General Purpose I/O */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG (IWDG) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*! */ +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_OUT2EN_Pos (31U) +#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ +#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */ +#define RTC_CR_TAMPALRM_TYPE_Pos (30U) +#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ +#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */ +#define RTC_CR_TAMPALRM_PU_Pos (29U) +#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ +#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */ +#define RTC_CR_TAMPOE_Pos (26U) +#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ +#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */ +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk + +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */ +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */ +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */ +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U +#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U +#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFLT_0 0x00000008U +#define TAMP_FLTCR_TAMPFLT_1 0x00000010U +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U +#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk + +/******************** Bits definition for TAMP_SR register ******************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ***************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ***************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ***************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ***************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G0 serie) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[21] interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos (1U) +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk /*!< RTC_WAKEUP -> exti[19] interrupt .... */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U) +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U) +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */ +#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) +#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ +#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) +#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ +#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) +#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ +#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) +#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ +#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) +#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */ +#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) +#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */ +#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) +#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */ +#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) +#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */ +#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) +#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */ +#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) +#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */ +#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) +#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ +#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */ +#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) +#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ +#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */ +#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) +#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ +#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */ +#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) +#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ +#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */ +#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) +#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ +#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */ +#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) +#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ +#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U) +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (3U) +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (4U) +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */ +#define SYSCFG_ITLINE12_SR_ADC_Pos (0U) +#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ +#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt */ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ +#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U) +#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g071xx + * @{ + */ + +#ifndef STM32G071xx_H +#define STM32G071xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1 /*!< STM32G0xx provides an MPU */ +#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< STM32G0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32g071xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt(EXTI line 16) */ + RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + UCPD1_2_IRQn = 8, /*!< UCPD1 and UCPD2 global Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts (combined with EXTI 17 & 18) */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM6_DAC_LPTIM1_IRQn = 17, /*!< TIM6, DAC and LPTIM1 global Interrupts */ + TIM7_LPTIM2_IRQn = 18, /*!< TIM7 and LPTIM2 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + USART3_4_LPUART1_IRQn = 29, /*!< USART3, USART4 and LPUART1 globlal Interrupts (combined with EXTI 28) */ + CEC_IRQn = 30, /*!< CEC Interrupt(combined with EXTI 27) */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32g0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief HDMI-CEC + */ +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ +} LPTIM_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ + __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */ + uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ +} TAMP_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[25]; /*!< Reserved 0x1C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ + +} UCPD_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */ + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM2_BASE (APBPERIPH_BASE + 0UL) +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) +#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define DAC1_BASE (APBPERIPH_BASE + 0x00007400UL) +#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL) /* Kept for legacy purpose */ +#define CEC_BASE (APBPERIPH_BASE + 0x00007800UL) +#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL) +#define LPUART1_BASE (APBPERIPH_BASE + 0x00008000UL) +#define LPTIM2_BASE (APBPERIPH_BASE + 0x00009400UL) +#define UCPD1_BASE (APBPERIPH_BASE + 0x0000A000UL) +#define UCPD2_BASE (APBPERIPH_BASE + 0x0000A400UL) +#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define VREFBUF_BASE (APBPERIPH_BASE + 0x00010030UL) +#define COMP1_BASE (SYSCFG_BASE + 0x0200UL) +#define COMP2_BASE (SYSCFG_BASE + 0x0204UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) +#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART4 ((USART_TypeDef *) USART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) + +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + + +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) +#define UCPD2 ((UCPD_TypeDef *) UCPD2_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ +#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ +#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ +#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ +#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ +#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ +#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ +#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ +#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ +#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ +#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ +#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ +#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */ + +/******************************************************************************/ +/* */ +/* HDMI-CEC (CEC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CEC_CR register *********************/ +#define CEC_CR_CECEN_Pos (0U) +#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */ +#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */ +#define CEC_CR_TXSOM_Pos (1U) +#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */ +#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */ +#define CEC_CR_TXEOM_Pos (2U) +#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */ +#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */ + +/******************* Bit definition for CEC_CFGR register *******************/ +#define CEC_CFGR_SFT_Pos (0U) +#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */ +#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */ +#define CEC_CFGR_RXTOL_Pos (3U) +#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */ +#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */ +#define CEC_CFGR_BRESTP_Pos (4U) +#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */ +#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */ +#define CEC_CFGR_BREGEN_Pos (5U) +#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */ +#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */ +#define CEC_CFGR_LBPEGEN_Pos (6U) +#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */ +#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */ +#define CEC_CFGR_BRDNOGEN_Pos (7U) +#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */ +#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */ +#define CEC_CFGR_SFTOPT_Pos (8U) +#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */ +#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */ +#define CEC_CFGR_OAR_Pos (16U) +#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */ +#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */ +#define CEC_CFGR_LSTN_Pos (31U) +#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */ +#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */ + +/******************* Bit definition for CEC_TXDR register *******************/ +#define CEC_TXDR_TXD_Pos (0U) +#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */ +#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ + +/******************* Bit definition for CEC_RXDR register *******************/ +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ + +/******************* Bit definition for CEC_ISR register ********************/ +#define CEC_ISR_RXBR_Pos (0U) +#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ +#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */ +#define CEC_ISR_RXEND_Pos (1U) +#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */ +#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */ +#define CEC_ISR_RXOVR_Pos (2U) +#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */ +#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */ +#define CEC_ISR_BRE_Pos (3U) +#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */ +#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */ +#define CEC_ISR_SBPE_Pos (4U) +#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */ +#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */ +#define CEC_ISR_LBPE_Pos (5U) +#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */ +#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */ +#define CEC_ISR_RXACKE_Pos (6U) +#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */ +#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */ +#define CEC_ISR_ARBLST_Pos (7U) +#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */ +#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */ +#define CEC_ISR_TXBR_Pos (8U) +#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */ +#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */ +#define CEC_ISR_TXEND_Pos (9U) +#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */ +#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */ +#define CEC_ISR_TXUDR_Pos (10U) +#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */ +#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */ +#define CEC_ISR_TXERR_Pos (11U) +#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */ +#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */ +#define CEC_ISR_TXACKE_Pos (12U) +#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */ +#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */ + +/******************* Bit definition for CEC_IER register ********************/ +#define CEC_IER_RXBRIE_Pos (0U) +#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */ +#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */ +#define CEC_IER_RXENDIE_Pos (1U) +#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */ +#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */ +#define CEC_IER_RXOVRIE_Pos (2U) +#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */ +#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */ +#define CEC_IER_BREIE_Pos (3U) +#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */ +#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */ +#define CEC_IER_SBPEIE_Pos (4U) +#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */ +#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/ +#define CEC_IER_LBPEIE_Pos (5U) +#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */ +#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */ +#define CEC_IER_RXACKEIE_Pos (6U) +#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */ +#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */ +#define CEC_IER_ARBLSTIE_Pos (7U) +#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */ +#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */ +#define CEC_IER_TXBRIE_Pos (8U) +#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */ +#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */ +#define CEC_IER_TXENDIE_Pos (9U) +#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */ +#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */ +#define CEC_IER_TXUDRIE_Pos (10U) +#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */ +#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */ +#define CEC_IER_TXERRIE_Pos (11U) +#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */ +#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */ +#define CEC_IER_TXACKEIE_Pos (12U) +#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */ +#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ +#define DAC_ADDITIONAL_TRIGGERS_SUPPORT + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_OUT2EN_Pos (31U) +#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ +#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */ +#define RTC_CR_TAMPALRM_TYPE_Pos (30U) +#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ +#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */ +#define RTC_CR_TAMPALRM_PU_Pos (29U) +#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ +#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */ +#define RTC_CR_TAMPOE_Pos (26U) +#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ +#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */ +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk + +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */ +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */ +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */ +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U +#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U +#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFLT_0 0x00000008U +#define TAMP_FLTCR_TAMPFLT_1 0x00000010U +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U +#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk + +/******************** Bits definition for TAMP_SR register ******************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ***************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ***************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ***************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ***************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G0 serie) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[16] Interrupt */ +#define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U) +#define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk /*!< TAMPER -> exti[21] interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos (1U) +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk /*!< RTC_WAKEUP -> exti[19] interrupt .... */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U) +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U) +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */ +#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) +#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ +#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) +#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ +#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) +#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ +#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) +#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ +#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) +#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */ +#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) +#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */ +#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) +#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */ +#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) +#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */ +#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) +#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */ +#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) +#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */ +#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) +#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ +#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */ +#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) +#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ +#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */ +#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) +#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ +#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */ +#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) +#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ +#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */ +#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) +#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ +#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */ +#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) +#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ +#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */ +#define SYSCFG_ITLINE8_SR_UCPD1_Pos (0U) +#define SYSCFG_ITLINE8_SR_UCPD1_Msk (0x1UL << SYSCFG_ITLINE8_SR_UCPD1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE8_SR_UCPD1 SYSCFG_ITLINE8_SR_UCPD1_Msk /*!< UCPD1 -> exti[32] Interrupt */ +#define SYSCFG_ITLINE8_SR_UCPD2_Pos (1U) +#define SYSCFG_ITLINE8_SR_UCPD2_Msk (0x1UL << SYSCFG_ITLINE8_SR_UCPD2_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE8_SR_UCPD2 SYSCFG_ITLINE8_SR_UCPD2_Msk /*!< UCPD2 -> exti[33] Interrupt */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U) +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (3U) +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (4U) +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */ +#define SYSCFG_ITLINE12_SR_ADC_Pos (0U) +#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ +#define SYSCFG_ITLINE12_SR_COMP1_Pos (1U) +#define SYSCFG_ITLINE12_SR_COMP1_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE12_SR_COMP1 SYSCFG_ITLINE12_SR_COMP1_Msk /*!< COMP1 Interrupt -> exti[17] */ +#define SYSCFG_ITLINE12_SR_COMP2_Pos (2U) +#define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[18] */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ +#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB SYSCFG_ITLINE15_SR_TIM2_GLB_Msk /*!< TIM2 GLB Interrupt */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_DAC_Pos (1U) +#define SYSCFG_ITLINE17_SR_DAC_Msk (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos (2U) +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk /*!< LPTIM1 -> exti[29] Interrupt */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */ +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos (1U) +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk /*!< LPTIM2 -> exti[30] Interrupt */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt */ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ +#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U) +#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos (2U) +#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE29_SR_LPUART1_GLB SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk /*!< LPUART1 GLB Interrupt -> exti[28] */ +#define SYSCFG_ITLINE30_SR_CEC_Pos (0U) +#define SYSCFG_ITLINE30_SR_CEC_Msk (0x1UL << SYSCFG_ITLINE30_SR_CEC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE30_SR_CEC SYSCFG_ITLINE30_SR_CEC_Msk /*!< CEC Interrupt-> exti[27] */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32g081xx + * @{ + */ + +#ifndef STM32G081xx_H +#define STM32G081xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1 /*!< STM32G0xx provides an MPU */ +#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< STM32G0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32g081xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt(EXTI line 16) */ + RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + UCPD1_2_IRQn = 8, /*!< UCPD1 and UCPD2 global Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts (combined with EXTI 17 & 18) */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM6_DAC_LPTIM1_IRQn = 17, /*!< TIM6, DAC and LPTIM1 global Interrupts */ + TIM7_LPTIM2_IRQn = 18, /*!< TIM7 and LPTIM2 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + USART3_4_LPUART1_IRQn = 29, /*!< USART3, USART4 and LPUART1 globlal Interrupts (combined with EXTI 28) */ + CEC_IRQn = 30, /*!< CEC Interrupt(combined with EXTI 27) */ + AES_RNG_IRQn = 31, /*!< AES & RNG Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_stm32g0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief HDMI-CEC + */ +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ +} LPTIM_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ + __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */ + uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */ + __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */ + uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ +} TAMP_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[25]; /*!< Reserved 0x1C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ +} AES_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ + +} UCPD_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */ + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ + +#define TIM2_BASE (APBPERIPH_BASE + 0UL) +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) +#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define DAC1_BASE (APBPERIPH_BASE + 0x00007400UL) +#define DAC_BASE (APBPERIPH_BASE + 0x00007400UL) /* Kept for legacy purpose */ +#define CEC_BASE (APBPERIPH_BASE + 0x00007800UL) +#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL) +#define LPUART1_BASE (APBPERIPH_BASE + 0x00008000UL) +#define LPTIM2_BASE (APBPERIPH_BASE + 0x00009400UL) +#define UCPD1_BASE (APBPERIPH_BASE + 0x0000A000UL) +#define UCPD2_BASE (APBPERIPH_BASE + 0x0000A400UL) +#define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define VREFBUF_BASE (APBPERIPH_BASE + 0x00010030UL) +#define COMP1_BASE (SYSCFG_BASE + 0x0200UL) +#define COMP2_BASE (SYSCFG_BASE + 0x0204UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL) +#define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */ +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBG_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE) +#define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + +#define RNG_BASE (AHBPERIPH_BASE + 0x00005000UL) +#define AES_BASE (AHBPERIPH_BASE + 0x00006000UL) + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x00000014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x00000018UL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) +#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/*!< Device Electronic Signature */ +#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */ +#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define TAMP ((TAMP_TypeDef *) TAMP_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART4 ((USART_TypeDef *) USART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) + +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define ADC (ADC1_COMMON) /* Kept for legacy purpose */ + +#define AES ((AES_TypeDef *) AES_BASE) +#define AES1 ((AES_TypeDef *) AES_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + +#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE) +#define UCPD2 ((UCPD_TypeDef *) UCPD2_BASE) + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE) + +#define DBG ((DBG_TypeDef *) DBG_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_CCRDY_Pos (13U) +#define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */ +#define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */ + +/* Legacy defines */ +#define ADC_ISR_EOSEQ (ADC_ISR_EOS) + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_CCRDYIE_Pos (13U) +#define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */ +#define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */ + +/* Legacy defines */ +#define ADC_IER_EOSEQIE (ADC_IER_EOSIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC_CFGR1_RES_Pos (3U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_AUTOFF_Pos (15U) +#define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/* Legacy defines */ +#define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT) + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_CKMODE_Pos (30U) +#define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR_SMPSEL18_Pos (26U) +#define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */ +#define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */ +#define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */ +#define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */ +#define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */ +#define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */ +#define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18U) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */ +#define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */ +#define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */ +#define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */ +#define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */ +#define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */ +#define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +#define ADC_CCR_LFMEN_Pos (25U) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */ + +/******************************************************************************/ +/* */ +/* HDMI-CEC (CEC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CEC_CR register *********************/ +#define CEC_CR_CECEN_Pos (0U) +#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */ +#define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */ +#define CEC_CR_TXSOM_Pos (1U) +#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */ +#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */ +#define CEC_CR_TXEOM_Pos (2U) +#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */ +#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */ + +/******************* Bit definition for CEC_CFGR register *******************/ +#define CEC_CFGR_SFT_Pos (0U) +#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */ +#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */ +#define CEC_CFGR_RXTOL_Pos (3U) +#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */ +#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */ +#define CEC_CFGR_BRESTP_Pos (4U) +#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */ +#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */ +#define CEC_CFGR_BREGEN_Pos (5U) +#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */ +#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */ +#define CEC_CFGR_LBPEGEN_Pos (6U) +#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */ +#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error gener. */ +#define CEC_CFGR_BRDNOGEN_Pos (7U) +#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */ +#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No Error generation */ +#define CEC_CFGR_SFTOPT_Pos (8U) +#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */ +#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */ +#define CEC_CFGR_OAR_Pos (16U) +#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */ +#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */ +#define CEC_CFGR_LSTN_Pos (31U) +#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */ +#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */ + +/******************* Bit definition for CEC_TXDR register *******************/ +#define CEC_TXDR_TXD_Pos (0U) +#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */ +#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */ + +/******************* Bit definition for CEC_RXDR register *******************/ +#define CEC_RXDR_RXD_Pos (0U) +#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */ +#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */ + +/******************* Bit definition for CEC_ISR register ********************/ +#define CEC_ISR_RXBR_Pos (0U) +#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */ +#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */ +#define CEC_ISR_RXEND_Pos (1U) +#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */ +#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */ +#define CEC_ISR_RXOVR_Pos (2U) +#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */ +#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */ +#define CEC_ISR_BRE_Pos (3U) +#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */ +#define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */ +#define CEC_ISR_SBPE_Pos (4U) +#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */ +#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */ +#define CEC_ISR_LBPE_Pos (5U) +#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */ +#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */ +#define CEC_ISR_RXACKE_Pos (6U) +#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */ +#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */ +#define CEC_ISR_ARBLST_Pos (7U) +#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */ +#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */ +#define CEC_ISR_TXBR_Pos (8U) +#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */ +#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */ +#define CEC_ISR_TXEND_Pos (9U) +#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */ +#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */ +#define CEC_ISR_TXUDR_Pos (10U) +#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */ +#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */ +#define CEC_ISR_TXERR_Pos (11U) +#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */ +#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */ +#define CEC_ISR_TXACKE_Pos (12U) +#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */ +#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */ + +/******************* Bit definition for CEC_IER register ********************/ +#define CEC_IER_RXBRIE_Pos (0U) +#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */ +#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */ +#define CEC_IER_RXENDIE_Pos (1U) +#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */ +#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */ +#define CEC_IER_RXOVRIE_Pos (2U) +#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */ +#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */ +#define CEC_IER_BREIE_Pos (3U) +#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */ +#define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */ +#define CEC_IER_SBPEIE_Pos (4U) +#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */ +#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable*/ +#define CEC_IER_LBPEIE_Pos (5U) +#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */ +#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */ +#define CEC_IER_RXACKEIE_Pos (6U) +#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */ +#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */ +#define CEC_IER_ARBLSTIE_Pos (7U) +#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */ +#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */ +#define CEC_IER_TXBRIE_Pos (8U) +#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */ +#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */ +#define CEC_IER_TXENDIE_Pos (9U) +#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */ +#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */ +#define CEC_IER_TXUDRIE_Pos (10U) +#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */ +#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */ +#define CEC_IER_TXERRIE_Pos (11U) +#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */ +#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */ +#define CEC_IER_TXACKEIE_Pos (12U) +#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */ +#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ + +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ + +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ + +#define AES_CR_CCFC_Pos (7U) +#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */ +#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC_Pos (8U) +#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */ +#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ +#define AES_CR_CCFIE_Pos (9U) +#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */ +#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */ +#define AES_CR_ERRIE_Pos (10U) +#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ +#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ + +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in last block of payload. */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ + +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ + +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +/* +* @brief Specific device feature definitions +*/ +#define DAC_ADDITIONAL_TRIGGERS_SUPPORT + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*! */ +#define RTC_ICSR_ALRBWF_Pos (1U) +#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */ +#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk +#define RTC_ICSR_ALRAWF_Pos (0U) +#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */ +#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */ + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_OUT2EN_Pos (31U) +#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */ +#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */ +#define RTC_CR_TAMPALRM_TYPE_Pos (30U) +#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */ +#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */ +#define RTC_CR_TAMPALRM_PU_Pos (29U) +#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */ +#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */ +#define RTC_CR_TAMPOE_Pos (26U) +#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */ +#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */ +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */ +#define RTC_CR_ITSE_Pos (24U) +#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */ +#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */ +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */ +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */ +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */ +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk + +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */ +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */ +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */ +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_0 0x00000001U +#define TAMP_FLTCR_TAMPFREQ_1 0x00000002U +#define TAMP_FLTCR_TAMPFREQ_2 0x00000004U +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFLT_0 0x00000008U +#define TAMP_FLTCR_TAMPFLT_1 0x00000010U +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPPRCH_0 0x00000020U +#define TAMP_FLTCR_TAMPPRCH_1 0x00000040U +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk + +/******************** Bits definition for TAMP_SR register ******************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ***************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ***************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ***************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ***************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/* + * @brief Specific device feature definitions (not present on all devices in the STM32G0 serie) + */ +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[16] Interrupt */ +#define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U) +#define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk /*!< TAMPER -> exti[21] interrupt */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos (1U) +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE2_SR_RTC_WAKEUP SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk /*!< RTC_WAKEUP -> exti[19] interrupt .... */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U) +#define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) +#define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U) +#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */ +#define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) +#define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ +#define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U) +#define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */ +#define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U) +#define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */ +#define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U) +#define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */ +#define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U) +#define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */ +#define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U) +#define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */ +#define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U) +#define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */ +#define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U) +#define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */ +#define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U) +#define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */ +#define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U) +#define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */ +#define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */ +#define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U) +#define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */ +#define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */ +#define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U) +#define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */ +#define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */ +#define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U) +#define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */ +#define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */ +#define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U) +#define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */ +#define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */ +#define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U) +#define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */ +#define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */ +#define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U) +#define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */ +#define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */ +#define SYSCFG_ITLINE8_SR_UCPD1_Pos (0U) +#define SYSCFG_ITLINE8_SR_UCPD1_Msk (0x1UL << SYSCFG_ITLINE8_SR_UCPD1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE8_SR_UCPD1 SYSCFG_ITLINE8_SR_UCPD1_Msk /*!< UCPD1 -> exti[32] Interrupt */ +#define SYSCFG_ITLINE8_SR_UCPD2_Pos (1U) +#define SYSCFG_ITLINE8_SR_UCPD2_Msk (0x1UL << SYSCFG_ITLINE8_SR_UCPD2_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE8_SR_UCPD2 SYSCFG_ITLINE8_SR_UCPD2_Msk /*!< UCPD2 -> exti[33] Interrupt */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U) +#define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U) +#define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) +#define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U) +#define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U) +#define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos (3U) +#define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH6 SYSCFG_ITLINE11_SR_DMA1_CH6_Msk /*!< DMA1 Channel 6 Interrupt */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos (4U) +#define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000010 */ +#define SYSCFG_ITLINE11_SR_DMA1_CH7 SYSCFG_ITLINE11_SR_DMA1_CH7_Msk /*!< DMA1 Channel 7 Interrupt */ +#define SYSCFG_ITLINE12_SR_ADC_Pos (0U) +#define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ +#define SYSCFG_ITLINE12_SR_COMP1_Pos (1U) +#define SYSCFG_ITLINE12_SR_COMP1_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP1_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE12_SR_COMP1 SYSCFG_ITLINE12_SR_COMP1_Msk /*!< COMP1 Interrupt -> exti[17] */ +#define SYSCFG_ITLINE12_SR_COMP2_Pos (2U) +#define SYSCFG_ITLINE12_SR_COMP2_Msk (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE12_SR_COMP2 SYSCFG_ITLINE12_SR_COMP2_Msk /*!< COMP2 Interrupt -> exti[18] */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U) +#define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U) +#define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U) +#define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U) +#define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */ +#define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */ +#define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U) +#define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos (0U) +#define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE15_SR_TIM2_GLB SYSCFG_ITLINE15_SR_TIM2_GLB_Msk /*!< TIM2 GLB Interrupt */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U) +#define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos (0U) +#define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE17_SR_TIM6_GLB SYSCFG_ITLINE17_SR_TIM6_GLB_Msk /*!< TIM6 GLB Interrupt */ +#define SYSCFG_ITLINE17_SR_DAC_Pos (1U) +#define SYSCFG_ITLINE17_SR_DAC_Msk (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE17_SR_DAC SYSCFG_ITLINE17_SR_DAC_Msk /*!< DAC Interrupt */ +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos (2U) +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE17_SR_LPTIM1_GLB SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk /*!< LPTIM1 -> exti[29] Interrupt */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos (0U) +#define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE18_SR_TIM7_GLB SYSCFG_ITLINE18_SR_TIM7_GLB_Msk /*!< TIM7 GLB Interrupt */ +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos (1U) +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE18_SR_LPTIM2_GLB SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk /*!< LPTIM2 -> exti[30] Interrupt */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U) +#define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos (0U) +#define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk (0x1UL << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE20_SR_TIM15_GLB SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U) +#define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U) +#define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U) +#define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U) +#define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt */ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */ +#define SYSCFG_ITLINE29_SR_USART3_GLB_Pos (0U) +#define SYSCFG_ITLINE29_SR_USART3_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE29_SR_USART3_GLB SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_USART4_GLB_Pos (1U) +#define SYSCFG_ITLINE29_SR_USART4_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE29_SR_USART4_GLB SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */ +#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos (2U) +#define SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos) /*!< 0x00000004 */ +#define SYSCFG_ITLINE29_SR_LPUART1_GLB SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk /*!< LPUART1 GLB Interrupt -> exti[28] */ +#define SYSCFG_ITLINE30_SR_CEC_Pos (0U) +#define SYSCFG_ITLINE30_SR_CEC_Msk (0x1UL << SYSCFG_ITLINE30_SR_CEC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE30_SR_CEC SYSCFG_ITLINE30_SR_CEC_Msk /*!< CEC Interrupt-> exti[27] */ +#define SYSCFG_ITLINE31_SR_RNG_Pos (0U) +#define SYSCFG_ITLINE31_SR_RNG_Msk (0x1UL << SYSCFG_ITLINE31_SR_RNG_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE31_SR_RNG SYSCFG_ITLINE31_SR_RNG_Msk /*!< RNG Interrupt */ +#define SYSCFG_ITLINE31_SR_AES_Pos (1U) +#define SYSCFG_ITLINE31_SR_AES_Msk (0x1UL << SYSCFG_ITLINE31_SR_AES_Pos) /*!< 0x00000002 */ +#define SYSCFG_ITLINE31_SR_AES SYSCFG_ITLINE31_SR_AES_Msk /*!< AES Interrupt */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.
+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx + * @{ + */ + +#ifndef STM32G0xx_H +#define STM32G0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32G0) +#define STM32G0 +#endif /* STM32G0 */ + +/* Uncomment the line below according to the target STM32G0 device used in your + application + */ + +#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) + /* #define STM32G070xx */ /*!< STM32G070xx Devices */ + /* #define STM32G071xx */ /*!< STM32G071xx Devices */ + /* #define STM32G081xx */ /*!< STM32G081xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number $VERSION$ + */ +#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32G0_CMSIS_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32G0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\ + |(__STM32G0_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32G0_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32G071xx) + #include "stm32g071xx.h" +#elif defined(STM32G081xx) + #include "stm32g081xx.h" +#elif defined(STM32G070xx) + #include "stm32g070xx.h" +#else + #error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/ +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32g0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32G0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/STM32G0xx/CMSIS/Device/Include/system_stm32g0xx.h =================================================================== --- ecs_cellMon/firmware/STM32G0xx/CMSIS/Device/Include/system_stm32g0xx.h (revision 3) +++ ecs_cellMon/firmware/STM32G0xx/CMSIS/Device/Include/system_stm32g0xx.h (revision 3) @@ -0,0 +1,106 @@ +/** + ****************************************************************************** + * @file system_stm32g0xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device System Source File for STM32G0xx devices. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef SYSTEM_STM32G0XX_H +#define SYSTEM_STM32G0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32G0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32G0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*SYSTEM_STM32G0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/STM32G0xx/CMSIS/Device/Source/system_stm32g0xx.c =================================================================== --- ecs_cellMon/firmware/STM32G0xx/CMSIS/Device/Source/system_stm32g0xx.c (revision 3) +++ ecs_cellMon/firmware/STM32G0xx/CMSIS/Device/Source/system_stm32g0xx.c (revision 3) @@ -0,0 +1,290 @@ +/** + ****************************************************************************** + * @file system_stm32g0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32g0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB Prescaler | 1 + *----------------------------------------------------------------------------- + * HSI Division factor | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * Require 48MHz for RNG | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32g0xx_system + * @{ + */ + +/** @addtogroup STM32G0xx_System_Private_Includes + * @{ + */ + +#include "stm32g0xx.h" + +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +#if !defined (LSI_VALUE) + #define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) + #define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/ +#endif /* LSE_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x3000U /*!< Vector Table base offset field. This value must be a multiple of 0x100. */ +//#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field. This value must be a multiple of 0x100. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000UL; + + const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL}; + const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL}; + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32G0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE + * + * - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp; + uint32_t pllvco; + uint32_t pllr; + uint32_t pllsource; + uint32_t pllm; + uint32_t hsidiv; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_LSI: /* LSI used as system clock */ + SystemCoreClock = LSI_VALUE; + break; + + case RCC_CFGR_SWS_LSE: /* LSE used as system clock */ + SystemCoreClock = LSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL; + + if(pllsource == 0x03UL) /* HSE used as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + else /* HSI used as PLL clock source */ + { + pllvco = (HSI_VALUE / pllm); + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL); + + SystemCoreClock = pllvco/pllr; + break; + + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + default: /* HSI used as system clock */ + hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos)); + SystemCoreClock = (HSI_VALUE/hsidiv); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ Index: ecs_cellMon/firmware/STM32G0xx/Scripts/STM32G0xx_Target.js =================================================================== --- ecs_cellMon/firmware/STM32G0xx/Scripts/STM32G0xx_Target.js (revision 3) +++ ecs_cellMon/firmware/STM32G0xx/Scripts/STM32G0xx_Target.js (revision 3) @@ -0,0 +1,50 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2019 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* conditions are met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this list of conditions and the following disclaimer. * +* * +* - Neither the name of SEGGER Microcontroller GmbH * +* nor the names of its contributors may be used to endorse or * +* promote products derived from this software without specific * +* prior written permission. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. * +* IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +*********************************************************************/ + +function Reset() { + TargetInterface.resetAndStop(); +} + +function EnableTrace(traceInterfaceType) { + // TODO: Enable trace +} + Index: ecs_cellMon/firmware/STM32G0xx/Source/STM32G07x_Vectors.s =================================================================== --- ecs_cellMon/firmware/STM32G0xx/Source/STM32G07x_Vectors.s (revision 3) +++ ecs_cellMon/firmware/STM32G0xx/Source/STM32G07x_Vectors.s (revision 3) @@ -0,0 +1,239 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2020 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : STM32G07x_Vectors.s +Purpose : Exception and interrupt vectors for STM32G07x devices. + +Additional information: + Preprocessor Definitions + __NO_EXTERNAL_INTERRUPTS + If defined, + the vector table will contain only the internal exceptions + and interrupts. + + __OPTIMIZATION_SMALL + If defined, + all weak definitions of interrupt handlers will share the + same implementation. + If not defined, + all weak definitions of interrupt handlers will be defined + with their own implementation. +*/ + .syntax unified + +/********************************************************************* +* +* Macros +* +********************************************************************** +*/ + +// +// Directly place a vector (word) in the vector table +// +.macro VECTOR Name= + .section .vectors, "ax" + .code 16 + .word \Name +.endm + +// +// Declare an exception handler with a weak definition +// +.macro EXC_HANDLER Name= + // + // Insert vector in vector table + // + .section .vectors, "ax" + .word \Name + // + // Insert dummy handler in init section + // + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +.endm + +// +// Declare an interrupt handler with a weak definition +// +.macro ISR_HANDLER Name= + // + // Insert vector in vector table + // + .section .vectors, "ax" + .word \Name + // + // Insert dummy handler in init section + // +#if defined(__OPTIMIZATION_SMALL) + .section .init, "ax" + .weak \Name + .thumb_set \Name,Dummy_Handler +#else + .section .init.\Name, "ax" + .thumb_func + .weak \Name + .balign 2 +\Name: + 1: b 1b // Endless loop +#endif +.endm + +// +// Place a reserved vector in vector table +// +.macro ISR_RESERVED + .section .vectors, "ax" + .word 0 +.endm + +// +// Place a reserved vector in vector table +// +.macro ISR_RESERVED_DUMMY + .section .vectors, "ax" + .word Dummy_Handler +.endm + +/********************************************************************* +* +* Externals +* +********************************************************************** +*/ + .extern __stack_end__ + .extern Reset_Handler + .extern HardFault_Handler + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ + +/********************************************************************* +* +* Setup of the vector table and weak definition of interrupt handlers +* +*/ + .section .vectors, "ax" + .code 16 + .balign 512 + .global _vectors +_vectors: + // + // Internal exceptions and interrupts + // + VECTOR __stack_end__ + VECTOR Reset_Handler + EXC_HANDLER NMI_Handler + VECTOR HardFault_Handler + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + ISR_RESERVED + EXC_HANDLER SVC_Handler + ISR_RESERVED + ISR_RESERVED + EXC_HANDLER PendSV_Handler + EXC_HANDLER SysTick_Handler + // + // External interrupts + // +#ifndef __NO_EXTERNAL_INTERRUPTS + ISR_HANDLER WWDG_IRQHandler + ISR_HANDLER PVD_IRQHandler + ISR_HANDLER RTC_STAMP_IRQHandler + ISR_HANDLER FLASH_IRQHandler + ISR_HANDLER RCC_IRQHandler + ISR_HANDLER EXTI0_1_IRQHandler + ISR_HANDLER EXTI2_3_IRQHandler + ISR_HANDLER EXTI4_15_IRQHandler + ISR_HANDLER UCPD1_UCPD2_IRQHandler + ISR_HANDLER DMA_Channel1_IRQHandler + ISR_HANDLER DMA_Channel2_3_IRQHandler + ISR_HANDLER DMA_Channel4_5_6_7_IRQHandler + ISR_HANDLER ADC_COMP_IRQHandler + ISR_HANDLER TIM1_BRK_UP_TRG_COMP_IRQHandler + ISR_HANDLER TIM1_CC_IRQHandler + ISR_HANDLER TIM2_IRQHandler + ISR_HANDLER TIM3_IRQHandler + ISR_HANDLER TIM6_DAC_LPTIM1_IRQHandler + ISR_HANDLER TIM7_LPTIM2_IRQHandler + ISR_HANDLER TIM14_IRQHandler + ISR_HANDLER TIM15_IRQHandler + ISR_HANDLER TIM16_IRQHandler + ISR_HANDLER TIM17_IRQHandler + ISR_HANDLER I2C1_IRQHandler + ISR_HANDLER I2C2_IRQHandler + ISR_HANDLER SPI1_IRQHandler + ISR_HANDLER SPI2_IRQHandler + ISR_HANDLER USART1_IRQHandler + ISR_HANDLER USART2_IRQHandler + ISR_HANDLER USART3_USART4_LPUART1_IRQHandler + ISR_HANDLER CEC_IRQHandler + ISR_HANDLER AES_RNG_IRQHandler +#endif + // + .section .vectors, "ax" +_vectors_end: + + +/********************************************************************* +* +* Dummy handler to be used for reserved interrupt vectors +* and weak implementation of interrupts. +* +*/ + .section .init.Dummy_Handler, "ax" + .thumb_func + .weak Dummy_Handler + .balign 2 +Dummy_Handler: + 1: b 1b // Endless loop + + +/*************************** End of file ****************************/ Index: ecs_cellMon/firmware/STM32G0xx/Source/STM32G0xx_Startup.s =================================================================== --- ecs_cellMon/firmware/STM32G0xx/Source/STM32G0xx_Startup.s (revision 3) +++ ecs_cellMon/firmware/STM32G0xx/Source/STM32G0xx_Startup.s (revision 3) @@ -0,0 +1,209 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2020 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** + +-------------------------- END-OF-HEADER ----------------------------- + +File : STM32G0xx_Startup.s +Purpose : Startup and exception handlers for STM32G0xx devices. + +Additional information: + Preprocessor Definitions + __NO_SYSTEM_INIT + If defined, + SystemInit is not called. + If not defined, + SystemInit is called. + SystemInit is usually supplied by the CMSIS files. + This file declares a weak implementation as fallback. + + __MEMORY_INIT + If defined, + MemoryInit is called after SystemInit. + void MemoryInit(void) can be implemented to enable external + memory controllers. + +*/ + + .syntax unified + +/********************************************************************* +* +* Global functions +* +********************************************************************** +*/ +/********************************************************************* +* +* Reset_Handler +* +* Function description +* Exception handler for reset. +* Generic bringup of a Cortex-M system. +* +* Additional information +* The stack pointer is expected to be initialized by hardware, +* i.e. read from vectortable[0]. +* For manual initialization add +* ldr R0, =__stack_end__ +* mov SP, R0 +*/ + .global reset_handler + .global Reset_Handler + .equ reset_handler, Reset_Handler + .section .init.Reset_Handler, "ax" + .balign 2 + .thumb_func +Reset_Handler: +#ifndef __NO_SYSTEM_INIT + // + // Call SystemInit + // + bl SystemInit +#endif +#ifdef __MEMORY_INIT + // + // Call MemoryInit + // + bl MemoryInit +#endif +#ifdef __VECTORS_IN_RAM + // + // Copy vector table (from Flash) to RAM + // + ldr R0, =__vectors_start__ + ldr R1, =__vectors_end__ + ldr R2, =__vectors_ram_start__ +1: + cmp R0, R1 + beq 2f + ldr R3, [R0] + str R3, [R2] + adds R0, R0, #4 + adds R2, R2, #4 + b 1b +2: +#endif + // + // Call runtime initialization, which calls main(). + // + bl _start + + // + // Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP, + // when there is no strong definition of SystemInit. + // + .weak SystemInit + // + // Place SystmeCoreClockUpdate in .init_array + // to be called after runtime initialization + // +#ifndef __NO_SYSTEM_INIT + .section .init_array, "aw" + .balign 4 + .word SystemCoreClockUpdate +#endif + +/********************************************************************* +* +* HardFault_Handler +* +* Function description +* Simple exception handler for HardFault. +* In case of a HardFault caused by BKPT instruction without +* debugger attached, return execution, otherwise stay in loop. +* +* Additional information +* The stack pointer is expected to be initialized by hardware, +* i.e. read from vectortable[0]. +* For manual initialization add +* ldr R0, =__stack_end__ +* mov SP, R0 +*/ + .weak HardFault_Handler + .section .init.HardFault_Handler, "ax" + .balign 2 + .thumb_func +HardFault_Handler: + // + // Check if HardFault is caused by BKPT instruction + // + ldr R1, =0xE000ED2C // Load NVIC_HFSR + ldr R2, [R1] + cmp R2, #0 // Check NVIC_HFSR[31] + +hfLoop: + bmi hfLoop // Not set? Stay in HardFault Handler. + // + // Continue execution after BKPT instruction + // +#if defined(__thumb__) && !defined(__thumb2__) + movs R0, #4 + mov R1, LR + tst R0, R1 // Check EXC_RETURN in Link register bit 2. + bne Uses_PSP + mrs R0, MSP // Stacking was using MSP. + b Pass_StackPtr +Uses_PSP: + mrs R0, PSP // Stacking was using PSP. +Pass_StackPtr: +#else + tst LR, #4 // Check EXC_RETURN[2] in link register to get the return stack + ite eq + mrseq R0, MSP // Frame stored on MSP + mrsne R0, PSP // Frame stored on PSP +#endif + // + // Reset HardFault Status + // +#if defined(__thumb__) && !defined(__thumb2__) + movs R3, #1 + lsls R3, R3, #31 + orrs R2, R3 + str R2, [R1] +#else + orr R2, R2, #0x80000000 + str R2, [R1] +#endif + // + // Adjust return address + // + ldr R1, [R0, #24] // Get stored PC from stack + adds R1, #2 // Adjust PC by 2 to skip current BKPT + str R1, [R0, #24] // Write back adjusted PC to stack + // + bx LR // Return + +/*************************** End of file ****************************/ Index: ecs_cellMon/firmware/STM32G0xx_Flash.icf =================================================================== --- ecs_cellMon/firmware/STM32G0xx_Flash.icf (revision 3) +++ ecs_cellMon/firmware/STM32G0xx_Flash.icf (revision 3) @@ -0,0 +1,120 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2020 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +********************************************************************** +-------------------------- END-OF-HEADER ----------------------------- + +File : STM32G0xx_Flash.icf +Purpose : STM32G0xx linker script for application placement in Flash, + for use with the SEGGER Linker. +*/ + +define memory with size = 4G; + +// +// Combined regions per memory type +// +define region FLASH = FLASH1; +define region RAM = RAM1; + +// +// Block definitions +// +define block vectors { section .vectors }; // Vector table section +define block vectors_ram { section .vectors_ram }; // Vector table section +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block exidx { section .ARM.exidx, section .ARM.exidx.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { }; +// +// Explicit initialization settings for sections +// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits +// +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs +do not initialize { block vectors_ram }; +initialize by copy with packing=auto { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .fast, section .fast.* }; // "RAM Code" sections +initialize by symbol __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by symbol __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. + +// +// Explicit placement in FLASHn +// +place in FLASH1 { section .FLASH1, section .FLASH1.* }; +// +// FLASH Placement +// +place at start of FLASH { block vectors }; // Vector table section +place in FLASH with minimum size order { section .init, section .init.*, // Init code section + section .init_rodata, section .init_rodata.*, // Init read-only section + section .text, section .text.*, // Code section + section .rodata, section .rodata.*, // Read-only data section + section .segger.*, // Auto-generated initialization + section .ARM.extab.*, // ARM exception table + block exidx, // ARM exception unwinding block + block ctors, // Constructors block + block dtors }; // Destructors block +place in FLASH { block tdata_load }; // Thread-local-storage load image + +// +// Explicit placement in RAMn +// +place in RAM1 { section .RAM1, section .RAM1.* }; +// +// RAM Placement +// +place at start of RAM { block vectors_ram }; +place in RAM { section .non_init, section .non_init.*, // No initialization section + section .no_init, section .no_init.*, // No initialization section, for backwards compatibility + section .noinit, section .noinit.*, // No initialization section, used by some SDKs/HALs + block tls }; // Thread-local-storage block +place in RAM with auto order { section .fast, section .fast.*, // "ramfunc" section + section .RamFunc*, // "ramfunc" section + section .data, section .data.*, // Initialized data section + section .bss, section .bss.* // Static data section + }; +place in RAM { block heap }; // Heap reserved block +place at end of RAM { block stack }; // Stack reserved block at the end + +define region CRC = [end(FLASH) - 4 size 4]; +define region APP = FLASH - CRC; +place in CRC { integrity check of APP with algorithm="CRC-32/STM32" fill=0xFF }; +fill APP with 0xFF; Index: ecs_cellMon/firmware/cellMon_Debug.jlink =================================================================== --- ecs_cellMon/firmware/cellMon_Debug.jlink (revision 3) +++ ecs_cellMon/firmware/cellMon_Debug.jlink (revision 3) @@ -0,0 +1,44 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x01 Index: ecs_cellMon/firmware/cellMon_Release.jlink =================================================================== --- ecs_cellMon/firmware/cellMon_Release.jlink (revision 3) +++ ecs_cellMon/firmware/cellMon_Release.jlink (revision 3) @@ -0,0 +1,44 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +RMWThreshold = 0x400 +Loaders="" +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF +[RAM] +VerifyDownload = 0x01 Index: ecs_cellMon/firmware/firmware.ioc =================================================================== --- ecs_cellMon/firmware/firmware.ioc (revision 3) +++ ecs_cellMon/firmware/firmware.ioc (revision 3) @@ -0,0 +1,289 @@ +#MicroXplorer Configuration settings - do not modify +ADC1.Channel-4\#ChannelRegularConversion=ADC_CHANNEL_5 +ADC1.Channel-5\#ChannelRegularConversion=ADC_CHANNEL_6 +ADC1.Channel-6\#ChannelRegularConversion=ADC_CHANNEL_7 +ADC1.Channel-7\#ChannelRegularConversion=ADC_CHANNEL_8 +ADC1.ClockPrescaler=ADC_CLOCK_ASYNC_DIV16 +ADC1.ContinuousConvMode=ENABLE +ADC1.DMAContinuousRequests=ENABLE +ADC1.EOCSelection=ADC_EOC_SEQ_CONV +ADC1.IPParameters=NbrOfConversionFlag,master,SelectedChannel,ContinuousConvMode,Sequencer,NbrOfConversion,Rank-4\#ChannelRegularConversion,Channel-4\#ChannelRegularConversion,SamplingTime-4\#ChannelRegularConversion,Rank-5\#ChannelRegularConversion,Channel-5\#ChannelRegularConversion,SamplingTime-5\#ChannelRegularConversion,Rank-6\#ChannelRegularConversion,Channel-6\#ChannelRegularConversion,SamplingTime-6\#ChannelRegularConversion,Rank-7\#ChannelRegularConversion,Channel-7\#ChannelRegularConversion,SamplingTime-7\#ChannelRegularConversion,DMAContinuousRequests,EOCSelection,LowPowerAutoWait,OversamplingMode,RightBitShift,Ratio,SamplingTimeCommon1,ClockPrescaler,Overrun,SamplingTimeCommon2 +ADC1.LowPowerAutoWait=DISABLE +ADC1.NbrOfConversion=4 +ADC1.NbrOfConversionFlag=1 +ADC1.Overrun=ADC_OVR_DATA_OVERWRITTEN +ADC1.OversamplingMode=ENABLE +ADC1.Rank-4\#ChannelRegularConversion=1 +ADC1.Rank-5\#ChannelRegularConversion=2 +ADC1.Rank-6\#ChannelRegularConversion=3 +ADC1.Rank-7\#ChannelRegularConversion=4 +ADC1.Ratio=ADC_OVERSAMPLING_RATIO_16 +ADC1.RightBitShift=ADC_RIGHTBITSHIFT_NONE +ADC1.SamplingTime-4\#ChannelRegularConversion=ADC_SAMPLINGTIME_COMMON_1 +ADC1.SamplingTime-5\#ChannelRegularConversion=ADC_SAMPLINGTIME_COMMON_1 +ADC1.SamplingTime-6\#ChannelRegularConversion=ADC_SAMPLINGTIME_COMMON_1 +ADC1.SamplingTime-7\#ChannelRegularConversion=ADC_SAMPLINGTIME_COMMON_1 +ADC1.SamplingTimeCommon1=ADC_SAMPLETIME_160CYCLES_5 +ADC1.SamplingTimeCommon2=ADC_SAMPLETIME_160CYCLES_5 +ADC1.SelectedChannel=ADC_CHANNEL_5|ADC_CHANNEL_6|ADC_CHANNEL_7|ADC_CHANNEL_8 +ADC1.Sequencer=FULLY_CONFIGURABLE +ADC1.master=1 +COMP1.Hysteresis=COMP_HYSTERESIS_HIGH +COMP1.IPParameters=TriggerMode,Hysteresis,OutputPol,Mode +COMP1.Mode=COMP_POWERMODE_HIGHSPEED +COMP1.OutputPol=COMP_OUTPUTPOL_INVERTED +COMP1.TriggerMode=COMP_TRIGGERMODE_NONE +COMP2.Hysteresis=COMP_HYSTERESIS_HIGH +COMP2.IPParameters=Hysteresis,TriggerMode,Mode +COMP2.Mode=COMP_POWERMODE_HIGHSPEED +COMP2.TriggerMode=COMP_TRIGGERMODE_NONE +DAC1.DAC_Channel-DAC_OUT1_ExtAndInt=DAC_CHANNEL_1 +DAC1.IPParameters=DAC_Channel-DAC_OUT1_ExtAndInt +Dma.ADC1.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.ADC1.0.EventEnable=DISABLE +Dma.ADC1.0.Instance=DMA1_Channel1 +Dma.ADC1.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD +Dma.ADC1.0.MemInc=DMA_MINC_ENABLE +Dma.ADC1.0.Mode=DMA_CIRCULAR +Dma.ADC1.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD +Dma.ADC1.0.PeriphInc=DMA_PINC_DISABLE +Dma.ADC1.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.ADC1.0.Priority=DMA_PRIORITY_LOW +Dma.ADC1.0.RequestNumber=1 +Dma.ADC1.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.ADC1.0.SignalID=NONE +Dma.ADC1.0.SyncEnable=DISABLE +Dma.ADC1.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.ADC1.0.SyncRequestNumber=1 +Dma.ADC1.0.SyncSignalID=NONE +Dma.Request0=ADC1 +Dma.RequestsNb=1 +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.Family=STM32G0 +Mcu.IP0=ADC1 +Mcu.IP1=COMP1 +Mcu.IP2=COMP2 +Mcu.IP3=DAC1 +Mcu.IP4=DMA +Mcu.IP5=NVIC +Mcu.IP6=RCC +Mcu.IP7=SYS +Mcu.IP8=TIM1 +Mcu.IP9=USART1 +Mcu.IPNb=10 +Mcu.Name=STM32G071C(6-8-B)Tx +Mcu.Package=LQFP48 +Mcu.Pin0=PF0-OSC_IN (PF0) +Mcu.Pin1=PF1-OSC_OUT (PF1) +Mcu.Pin10=PA8 +Mcu.Pin11=PA9 +Mcu.Pin12=PA10 +Mcu.Pin13=PA11 [PA9] +Mcu.Pin14=PA12 [PA10] +Mcu.Pin15=PA13 +Mcu.Pin16=PA14-BOOT0 +Mcu.Pin17=PD0 +Mcu.Pin18=PD1 +Mcu.Pin19=PD2 +Mcu.Pin2=PA1 +Mcu.Pin20=PD3 +Mcu.Pin21=PB5 +Mcu.Pin22=VP_COMP1_VS_DACOUT1 +Mcu.Pin23=VP_SYS_VS_Systick +Mcu.Pin24=VP_SYS_VS_DBSignals +Mcu.Pin25=VP_TIM1_VS_ControllerModeReset +Mcu.Pin26=VP_TIM1_VS_ClockSourceINT +Mcu.Pin27=VP_TIM1_VS_NoInput1 +Mcu.Pin28=VP_TIM1_VS_NoInput2 +Mcu.Pin3=PA2 +Mcu.Pin4=PA3 +Mcu.Pin5=PA4 +Mcu.Pin6=PA5 +Mcu.Pin7=PA6 +Mcu.Pin8=PA7 +Mcu.Pin9=PB0 +Mcu.PinsNb=29 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32G071C8Tx +MxCube.Version=6.2.0 +MxDb.Version=DB.6.0.20 +NVIC.ADC1_COMP_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true +PA1.GPIOParameters=GPIO_Label +PA1.GPIO_Label=COMP1_INP_I_SENSE +PA1.Mode=INP +PA1.Signal=COMP1_INP +PA10.GPIOParameters=GPIO_PuPd +PA10.GPIO_PuPd=GPIO_PULLUP +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA11\ [PA9].GPIOParameters=GPIO_Label +PA11\ [PA9].GPIO_Label=COMP1_OUT_I_PEAK +PA11\ [PA9].Locked=true +PA11\ [PA9].Mode=ExternalOutput +PA11\ [PA9].Signal=COMP1_OUT +PA12\ [PA10].GPIOParameters=GPIO_PuPd +PA12\ [PA10].GPIO_PuPd=GPIO_NOPULL +PA12\ [PA10].Mode=Hardware Flow Control (RS485) +PA12\ [PA10].Signal=USART1_DE +PA13.Mode=Serial_Wire +PA13.Signal=SYS_SWDIO +PA14-BOOT0.Mode=Serial_Wire +PA14-BOOT0.Signal=SYS_SWCLK +PA2.GPIOParameters=GPIO_Label +PA2.GPIO_Label=COMP2_INM_U_TR_SENSE +PA2.Mode=INM +PA2.Signal=COMP2_INM +PA3.GPIOParameters=GPIO_Label +PA3.GPIO_Label=COMP2_INP_U_TR_REF +PA3.Mode=INP +PA3.Signal=COMP2_INP +PA4.GPIOParameters=GPIO_Label +PA4.GPIO_Label=DAC1_OUT1_I_CTR_TP +PA4.Signal=COMP_DAC11_group +PA5.GPIOParameters=GPIO_Label +PA5.GPIO_Label=ADC1_IN5_I_SENSE_AVG +PA5.Mode=IN5 +PA5.Signal=ADC1_IN5 +PA6.GPIOParameters=GPIO_Label +PA6.GPIO_Label=ADC1_IN6_UIN_SENSE +PA6.Mode=IN6 +PA6.Signal=ADC1_IN6 +PA7.GPIOParameters=GPIO_Label +PA7.GPIO_Label=ADC1_IN7_TEMP_SENSE +PA7.Mode=IN7 +PA7.Signal=ADC1_IN7 +PA8.Signal=S_TIM1_CH1 +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB0.Mode=IN8 +PB0.Signal=ADC1_IN8 +PB5.GPIOParameters=GPIO_Label +PB5.GPIO_Label=COMP2_OUT_DISCHARGE +PB5.Locked=true +PB5.Mode=ExternalOutput +PB5.Signal=COMP2_OUT +PD0.GPIOParameters=GPIO_Label +PD0.GPIO_Label=LVP +PD0.Locked=true +PD0.Signal=GPIO_Output +PD1.GPIOParameters=GPIO_Label +PD1.GPIO_Label=OVP +PD1.Locked=true +PD1.Signal=GPIO_Output +PD2.GPIOParameters=GPIO_Label +PD2.GPIO_Label=LED_FUNC +PD2.Locked=true +PD2.Signal=GPIO_Output +PD3.GPIOParameters=GPIO_Label +PD3.GPIO_Label=LED_ERROR +PD3.Locked=true +PD3.Signal=GPIO_Output +PF0-OSC_IN\ (PF0).Mode=HSE-External-Oscillator +PF0-OSC_IN\ (PF0).Signal=RCC_OSC_IN +PF1-OSC_OUT\ (PF1).Mode=HSE-External-Oscillator +PF1-OSC_OUT\ (PF1).Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32G071C8Tx +ProjectManager.FirmwarePackage=STM32Cube FW_G0 V1.4.1 +ProjectManager.FreePins=true +ProjectManager.HalAssertFull=true +ProjectManager.HeapSize=0x2000 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain=SW4STM32 +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=firmware.ioc +ProjectManager.ProjectName=firmware +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x4000 +ProjectManager.TargetToolchain=SW4STM32 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_COMP1_Init-COMP1-false-HAL-true,6-MX_COMP2_Init-COMP2-false-HAL-true,7-MX_DAC1_Init-DAC1-false-HAL-true,8-MX_TIM1_Init-TIM1-false-HAL-true,9-MX_USART1_UART_Init-USART1-false-HAL-true +RCC.ADCFreq_Value=8000000 +RCC.AHBFreq_Value=8000000 +RCC.APBFreq_Value=8000000 +RCC.APBTimFreq_Value=8000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=8000000 +RCC.EXTERNAL_CLOCK_VALUE=48000 +RCC.FCLKCortexFreq_Value=8000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=8000000 +RCC.HSE_VALUE=8000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=8000000 +RCC.I2S1Freq_Value=8000000 +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APBFreq_Value,APBTimFreq_Value,CECFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2S1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,PWRFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIM15Freq_Value,TIM1Freq_Value,USART1Freq_Value,USART2Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value +RCC.LPTIM1Freq_Value=8000000 +RCC.LPTIM2Freq_Value=8000000 +RCC.LPUART1Freq_Value=8000000 +RCC.LSCOPinFreq_Value=32000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO1PinFreq_Value=8000000 +RCC.PLLN=16 +RCC.PLLPoutputFreq_Value=64000000 +RCC.PLLQoutputFreq_Value=64000000 +RCC.PLLRCLKFreq_Value=64000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.PWRFreq_Value=8000000 +RCC.SYSCLKFreq_VALUE=8000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_HSE +RCC.TIM15Freq_Value=8000000 +RCC.TIM1Freq_Value=8000000 +RCC.USART1Freq_Value=8000000 +RCC.USART2Freq_Value=8000000 +RCC.VCOInputFreq_Value=8000000 +RCC.VCOOutputFreq_Value=128000000 +SH.COMP_DAC11_group.0=DAC1_OUT1,DAC_OUT1_ExtAndInt +SH.COMP_DAC11_group.ConfNb=1 +SH.S_TIM1_CH1.0=TIM1_CH1,TriggerSource_TI1FP1 +SH.S_TIM1_CH1.ConfNb=1 +TIM1.Channel-Input_Capture1_from_TI1_REMAP_TIM1=TIM_CHANNEL_1 +TIM1.Channel-Input_Capture2_from_TI2_Remap_TIM1=TIM_CHANNEL_2 +TIM1.ICPolarity_CH1=TIM_INPUTCHANNELPOLARITY_FALLING +TIM1.IPParameters=Channel-Input_Capture1_from_TI1_REMAP_TIM1,Channel-Input_Capture2_from_TI2_Remap_TIM1,ICPolarity_CH1 +USART1.BaudRate=19200 +USART1.IPParameters=VirtualMode-Asynchronous,VirtualMode-Hardware Flow Control (RS485),BaudRate,WordLength,Parity +USART1.Parity=PARITY_EVEN +USART1.VirtualMode-Asynchronous=VM_ASYNC +USART1.VirtualMode-Hardware\ Flow\ Control\ (RS485)=VM_ASYNC +USART1.WordLength=WORDLENGTH_9B +VP_COMP1_VS_DACOUT1.Mode=INM_DACOUT1 +VP_COMP1_VS_DACOUT1.Signal=COMP1_VS_DACOUT1 +VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals +VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +VP_TIM1_VS_ClockSourceINT.Mode=Internal +VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT +VP_TIM1_VS_ControllerModeReset.Mode=Reset Mode +VP_TIM1_VS_ControllerModeReset.Signal=TIM1_VS_ControllerModeReset +VP_TIM1_VS_NoInput1.Mode=Input_Capture1_from_TI1_REMAP_TIM1 +VP_TIM1_VS_NoInput1.Signal=TIM1_VS_NoInput1 +VP_TIM1_VS_NoInput2.Mode=Input_Capture2_from_TI2_Remap_TIM1 +VP_TIM1_VS_NoInput2.Signal=TIM1_VS_NoInput2 +board=custom Index: ecs_cellMon/firmware/firmware.xml =================================================================== --- ecs_cellMon/firmware/firmware.xml (revision 3) +++ ecs_cellMon/firmware/firmware.xml (revision 3) @@ -0,0 +1,9 @@ + + + + firmware + STM32G071C8Tx + SWD + ST-LinkV2-1 + + Index: ecs_cellMon/firmware/firmware_Debug Internal.jlink =================================================================== --- ecs_cellMon/firmware/firmware_Debug Internal.jlink (revision 3) +++ ecs_cellMon/firmware/firmware_Debug Internal.jlink (revision 3) @@ -0,0 +1,40 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF Index: ecs_cellMon/firmware/inc/balancer.h =================================================================== --- ecs_cellMon/firmware/inc/balancer.h (revision 3) +++ ecs_cellMon/firmware/inc/balancer.h (revision 3) @@ -0,0 +1,77 @@ +/** + ****************************************************************************** + * @file balancer.h + * @author ECS - Falko Jahn + * @version V1.0.0 + * @date 03-Feb-2021 + * @brief Balancer Modul Treiber + * + * Beschreibung + * Dieses Modul enthält die notwendigen Funktionen zur Stuerung des + * DC/DC Converters (Flybackconverter) + * + * Starte timer zur Messung der Charge Time und der Charge Transfer Time + * Charge Time bedeutet die Zeit zum Aufbau des Magnedfeldes. Also vom Einschalten + * des Mosfets bis zum erreichen der Maximal Stroms. + * Charge Transfer Time bedeutet die Zeit bis das Magnetfeld über den Trafo auf + * auf der Sek. Seite entladen wurde. + * Wir können das dedektieren indem wir auf der Prim. Seite die zurück refklektierte Spannung messen. + * Die zurück reflektierte spannung am Mosfet Drain Ud ist nach dem ausschalten des MOSFETS zunächst: + * Ud = Uin + Uout / Wicklungsverhältniss + * Nach dem abmagentieseren ist die Spannung nur noch U= Uin. + * Das bedeutet der Comparator sollte im Idealfall genau zwischen diesen beiden Punkten detektieren + * Zu diesem Zweg wird die Eingangsspannung leicht erhöht auf den Komperator gegeben + * In der aktuellen Konfig mit Spannungsteiler 18k / 3k und Offset 2,5V über 18k + * müssen am ausgang mindestens ca. 7 anliegen um über die Triggerschwelle zu kommen + * Falls die minimale Ausgangsspannung kleiner werden soll, muss der Offset verringert werde + + ****************************************************************************** + */ +#ifndef __BALANCER_H +#define __BALANCER_H + + +//--- INCLUDEs ----------------------------------------------------------------- + +//--- GLOBALE TYPE DEFS -------------------------------------------------------- + +//--- GLOBALE DEFINES ---------------------------------------------------------- + + +//--- GLOBALE VARIABLEN PROTOTYPEN --------------------------------------------- + +//--- GLOBALE FUNKTIONS PROTOTYPEN --------------------------------------------- +/** + * @brief Init Funktion + + * + * Initialisiert die Komparatoren, damit der Flyback Konverter automatisch arbeitet + * Initialisiert den DAC. Über den DAC wierd der maximale Strom vorgegeben. + * Die beiden Flyback Trafos haben einen Sätigungsstrom von 10,2 A + * Daher darf der MAX Strom nicht mehr als ca. 20A betragen + * + * + * @param Keine + * + * @retval Kein + */ +void BALANCER_Init(void); + + +/** + * @brief Execute Funktion + * + * Muss periodisch aufgerufen werden. + * Prüft die Zellspannung. Ist die Zellspannung größer der aktuellen + * ausgleichsspannung, dann wird der Balancer Strom schrittweise erhöht. + * + * + * @param Keine + * + * @retval Kein + */ +void BALANCER_Exec(void); + + + +#endif Index: ecs_cellMon/firmware/inc/bms.h =================================================================== --- ecs_cellMon/firmware/inc/bms.h (revision 3) +++ ecs_cellMon/firmware/inc/bms.h (revision 3) @@ -0,0 +1,48 @@ +/** + ****************************************************************************** + * @file template.h + * @author ECS - MAX MUSTERMANN + * @version V1.0.0 + * @date 09-Sep-2015 + * @brief Muster Modul Treiber + * + * Beschreibung + * Dieses Modul enthält ein Musteraufbau einer Header Datei + * + * Achtung: + * Hinweis1 + * Hinweis2 + ****************************************************************************** + */ +#ifndef __BMS_H +#define __BMS_H + + +//--- INCLUDEs ----------------------------------------------------------------- + +//--- GLOBALE TYPE DEFS -------------------------------------------------------- + +//--- GLOBALE DEFINES ---------------------------------------------------------- + +//--- GLOBALE VARIABLEN PROTOTYPEN --------------------------------------------- + +//--- GLOBALE FUNKTIONS PROTOTYPEN --------------------------------------------- +/** + * @brief BMS Execute + * + * Beschreibung: + * Berechnete die aktullen Schwellwerte anhand der Temperatur und abhängig vom Standalone Wert + * Prüft ob LED's oder Asugänge geschaltet werden müssen * + * + * + * @param Keine + * + * @retval Kein + */ +void BMS_Exec(void); + + + + + +#endif Index: ecs_cellMon/firmware/inc/doku.h =================================================================== --- ecs_cellMon/firmware/inc/doku.h (revision 3) +++ ecs_cellMon/firmware/inc/doku.h (revision 3) @@ -0,0 +1,53 @@ +/* + +Anmerkungen zum Projekt + +1) +Zunächst wurde LPUART geplant, da dieser aber keinen interne Timeout besitzt, wurde zunächst auf USART3 gewechselt. +Dieser hatte aber bei diesem Chip auch nicht die notwendige Funktionalätät. Nur USART 1 und 2 sind voll ausgestattet. +Daher wird jetzt mit USART 1 geabeitet. + +2) +COMPARATOR muss auf Highspeed Mode, damit ist die deutlich besser. + + +3) +Wir arbeiten jetzt mit 8Mhz Takt, die Genauighkeit der Bestimmung der Sekundär Spannung war mit 64Mhz besser. Da der Timmer +besser aufklösen konnte. 8 Mhz scheint aber zu reichen und der Stromverbrauch sinkt enorm. (14mA --> 8mA) + +4) +Wir müssen die Sekundär Spannung bestimmern, damit wir die Kondensatoren beim ausfall der Sicherung auf der Last Seite +keiner zu hohen spannung aussetzen. Wir können nicht mehr rein, nach der Charge transfer Zeit wie beim alten LiPro gehen. +Da hier der Balancer Stufenlos eingeschaltet wird und bei geringem Ausgleichsstrom auch die Zeiten sehr kurz werden. + +5) +die Messung der Zeiten wurde zunächst mit Comparator Interrupts versucht. Doch nur mit 64Mhz CPU Takt war der Prozessor s +schnell genug um die Interrupts zu verarbeiten. Um den Takt trotzdem gering zu halten, wurden die Interrupts wieder deaktiviert. +Die Zeitmessung läuft jetzt über eine Clevere Konfiguration von Timer 1. +Jede Periode beginnt mit einer negativen Flanke des Comparators 1. Dies entspricht dem Strom Max Wert. +Der Zähler zählt von 0 an bis zum ausllösen des COMP1, dann speichert er den Zeitstemperl in Caputure Register 1 und führt einen Reset aus. +in der Zwischenzeit wird vom Comp 2 noch eine positve Flanke ausgelöst. Der Zeitstempel wird in Caputre Register 2 gespeichert. +Capure Register zwei representiert also die Zeit vom Abschalten des Comp1 (--> Mosfet aus) bis zum Ende der Demagnetiesierung des Trafo. Also der Charge +Trasfer Zeit. + +6)Gemessene übliche Zeiten und Messwerte +Uin Uout Iin Iout Pin Pout wirkungsgrad charge time charge transfer time summe[clocks] summe Zeit[s] f[Hz] +3 10 4,568 1,03 13,704 10,3 0,751605370694688 90 92 182 2,275E-05 43956,043956044 +3 30 6,57 0,52 19,71 15,6 0,791476407914764 92 36 128 1,6E-05 62500 +3 65 7,301 0,25 21,903 16,25 0,741907501255536 97 20 117 1,4625E-05 68376,0683760684 +4 10 4,12 1,27 16,48 12,7 0,770631067961165 72 100 172 2,15E-05 46511,6279069768 +4 30 6,573 0,64 26,292 19,2 0,730260155180283 72 35 107 1,3375E-05 74766,3551401869 +4 65 7,44 0,36 29,76 23,4 0,786290322580645 75 20 95 1,1875E-05 84210,5263157895 +5 10 3,832 1,48 19,16 14,8 0,772442588726514 60 105 165 2,0625E-05 48484,8484848485 +5 30 6,309 0,86 31,545 25,8 0,817879220161674 62 41 103 1,2875E-05 77669,9029126214 +5 65 7,628 0,47 38,14 30,55 0,800996329313057 64 22 86 1,075E-05 93023,2558139535 + + + + + + + + + +*/ Index: ecs_cellMon/firmware/inc/eeprom.h =================================================================== --- ecs_cellMon/firmware/inc/eeprom.h (revision 3) +++ ecs_cellMon/firmware/inc/eeprom.h (revision 3) @@ -0,0 +1,13 @@ +#include "stm32g0xx_hal.h" +#include "stdbool.h" +#include "sysdata.h" + +HAL_StatusTypeDef EEPROM_readConfig(sys_data_t * data); +HAL_StatusTypeDef EEPROM_storeConfig(sys_data_t * data, bool withSN, bool saveNewKey); +HAL_StatusTypeDef EEPROM_fullRestore(sys_data_t * data, bool keepSN); +HAL_StatusTypeDef EEPROM_factoryRestore(sys_data_t * data); +HAL_StatusTypeDef EEPROM_storeLogData(void); +HAL_StatusTypeDef EEPROM_readLogData(void); +HAL_StatusTypeDef EEPROM_ResetLogData(void); + +bool EEPROM_isFirstStart(void); Index: ecs_cellMon/firmware/inc/led.h =================================================================== --- ecs_cellMon/firmware/inc/led.h (revision 3) +++ ecs_cellMon/firmware/inc/led.h (revision 3) @@ -0,0 +1,58 @@ +/** + ****************************************************************************** + * @file led.h + * @author ECS - Falko Jahn + * @version V1.0.0 + * @date 29-Sep-2021 + * @brief Muster Modul Treiber + * + * Beschreibung + * Dieses Modul enthält ein Musteraufbau einer Header Datei + * + * Achtung: + * Hinweis1 + * Hinweis2 + ****************************************************************************** + */ +#ifndef __LED_H +#define __LED_H + + +//--- INCLUDEs ----------------------------------------------------------------- + +//--- GLOBALE TYPE DEFS -------------------------------------------------------- + +//--- GLOBALE DEFINES ---------------------------------------------------------- + +//--- GLOBALE VARIABLEN PROTOTYPEN --------------------------------------------- + +//--- GLOBALE FUNKTIONS PROTOTYPEN --------------------------------------------- +/** + * @brief LED Modul Init Funktion + * + * Beschreibung: + * Init Funktion + * + * @param Keine + * + * @retval Kein + */ +void LED_Init(void); + +void LED_ErrorOn(void); +void LED_ErrorOff(void); +void LED_ErrorToggle(void); +void LED_ErrorStartBlink(int ontime, int offtime); +void LED_Test(); +void LED_Exec(); + + +void LED_FunctionOn(void); +void LED_FunctionOff(void); +void LED_FunctionToggle(void); +void LED_FunctionStartBlink(int ontime, int offtime); +void LED_Test(); +void LED_Exec(); +void LED_FunctionSetTimes(int ontime, int offtime); + +#endif Index: ecs_cellMon/firmware/inc/meas.h =================================================================== --- ecs_cellMon/firmware/inc/meas.h (revision 3) +++ ecs_cellMon/firmware/inc/meas.h (revision 3) @@ -0,0 +1,58 @@ +/** + ****************************************************************************** + * @file meas.h + * @author ECS - Falko Jahn + * @version V1.0.0 + * @date 30-Jan-2021 + * @brief MEAS Modul Treiber + * + * Beschreibung + * Dieses Modul enthält die Funktionen zur Messung von + * Zelltemperatur, Zellspannung, ausgleichsstrom + * + * Achtung: + * Hinweis1 + * Hinweis2 + ****************************************************************************** + */ +#ifndef __MEAS_H +#define __MEAS_H + + +//--- INCLUDEs ----------------------------------------------------------------- + +//--- GLOBALE TYPE DEFS -------------------------------------------------------- + +//--- GLOBALE DEFINES ---------------------------------------------------------- + +//--- GLOBALE VARIABLEN PROTOTYPEN --------------------------------------------- + +//--- GLOBALE FUNKTIONS PROTOTYPEN --------------------------------------------- +/** + * @brief Init Funktion + * + * Beschreibung: + * Startet die ADC Messungen. + * Ergebnisse werden per DMA in die System Daten Struktur gespeichert. + * + * @param Keine + * + * @retval Kein + */ +void MEAS_Init(void); + + +/** + * @brief Execute Funktion + * + * Beschreibung: + * Prüft die Ergebnisse der ADC Wandlungen, Speichert Min und Max Werte * + * + * @param Keine + * + * @retval Kein + */ +void MEAS_Exec(void); + + +#endif Index: ecs_cellMon/firmware/inc/modbus.h =================================================================== --- ecs_cellMon/firmware/inc/modbus.h (revision 3) +++ ecs_cellMon/firmware/inc/modbus.h (revision 3) @@ -0,0 +1,164 @@ +/* + * modbus.h + * + * Created: 03.09.2012 08:39:40 + * Author: Falko + */ + + +#ifndef MODBUS_H_ +#define MODBUS_H_ + + #if MODBUS_SUPPORT == TRUE + + #include "stdint.h" + #include "stdbool.h" + #include "main.h" + + + //! brief Anzahl der Startbits, nach Modbus Spezifikation immer 1, stop bits werden aus den Einstellungen geladen + #define NUMBER_OF_STARTBITS 1 + + //! brief Anzahl der Datenbits, nach Modbus Spezifikation immer 8 + #define NUMBER_OF_DATABITS 8 + + //! brief Max Timeput zwischen zwei gesendeten char + #define TIMEOUT_BETWEEN_CHARACTERS 1.5 + + //! brief Timeput bei dem fertig gesendetes Frame erkannt wird + #define TIMEOUT_FRAME_COMPLETE 3.5 + + //! define der Größe der Ein- und Ausgangsbuffer + #define RXBUFFERSIZE 255 + #define TXBUFFERSIZE 255 + + #define FORWARD_DATA TRUE + #define SEND_TO_LOKALBUS 1 + #define RESPOND_TO_QUERY 2 + #define MODBUS_UART_PARITY_EVEN 'e' + #define MODBUS_UART_PARITY_ODD 'o' + #define MODBUS_UART_PARITY_NONE 'n' + + + typedef union bword + { + uint16_t w; + int16_t sw; + uint8_t lb; + int8_t slb; + uint8_t b[2]; + int8_t sb[2]; + } bword_t; + + + + + typedef enum + { + ACCESS_MODE_READ_ONLY, //Muss als erstes damit nicht initialisierte Register automatisch 0 = READ ONLY sind + ACCESS_MODE_READ_WRITE, + ACCESS_MODE_WRITE_PROTECTABLE, + } accessMode_t; + + typedef enum mb_error_codes_enum + { + MB_ERROR_NOTHING = 0, + MB_ERROR_TIMEOUT = 1, + MB_ERROR_CRC = 2, + MB_ERROR_SLAVE_ADRESS = 3, + MB_ERROR_FUNCTION_CODE = 4, + MB_ERROR_BYTE_COUNT = 5, + MB_ERROR_START_ADRESS = 6, + MB_ERROR_UART_PE = 7, //Parity + MB_ERROR_UART_NE = 8, //Noise + MB_ERROR_UART_FE = 9, //Frame + MB_ERROR_UART_ORE = 10, //Overrun + } + mb_error_codes_t; + + + + typedef enum + { + MB_QUERY_NOTHING, + MB_QUERY_READ_IDENT, + MB_QUERY_READ_DATA, + MB_QUERY_READ_LIPRO_DATA, + MB_QUERY_WRITE_LIPRO_BALANCER_VOLTAGE, + MB_QUERY_WRITE_BUTTONS, + MB_QUERY_GSM_GATEWAY, + MB_QUERY_REMOTEBUS_GATEWAY, + MB_QUERY_WRITE_TO_GC, + MB_QUERY_SEND_DEVICE_ADDRESS, + MB_QUERY_SEND_SAVE_COMMAND, + MB_QUERY_GATEWAY, + MB_QUERY_SEND_DATA + } + mb_status_t; + + + typedef struct + { + //TIM_HandleTypeDef * timer; // Timer config + //TIM_OC_InitTypeDef * timerOcConfig; // Zeiger auf TimerInit Struktur + UART_HandleTypeDef * uart; // Zeiger auf das Uart Modul + GPIO_TypeDef * driverEnableGPIO; // Zuständiger einschalt Port + uint16_t driverEnableGPIOPin; // Zuständiger einschalt Pin + uint32_t mb_t15_total_timer_ticks; // max timeout zwischen einzelnen char + uint32_t mb_t35_total_timer_ticks; // timeout frame complete + volatile bool mb_rx_frame_complete; // frame complete ja/nein + uint32_t response_timeout_counter; // antwort Timeout + // QUERY (Anfrage): + uint8_t last_query_slave_adress; // zugehörige Slave Andresse + uint8_t last_query_function_code; // function Code + bword_t last_query_start_adress; // start Adresse + bword_t last_query_number_of_register; // Anzahl der Register + bool last_query_timeout; // Timeout + bword_t last_query_tcp_id; // stack ID + mb_status_t current_query; // Zeiger auf Statusstruktur + uint8_t rx_buffer[RXBUFFERSIZE]; // Bufferarray Empfangen + uint8_t tx_buffer[TXBUFFERSIZE]; // Bufferarray Senden + uint32_t rx_head; // + uint32_t tx_head; // + volatile bool setTxLed; // status Led + volatile bool setRxLed; // status Led + accessMode_t* accessModeTable; + uint16_t* currentAccessState; + } + modbus_t; + + + + //Public Functions Modbus + + // Timer Interrupt erkennt Fehler bei Framekomplettierung + void mbTimerIsr (modbus_t * mb_data); + // Initialiserung des Moduls muss mit den passenden Parametern gefüllt werden + void mbInit(modbus_t * mb_data, uint32_t baudrate, uint32_t parityMode, UART_HandleTypeDef * usart, accessMode_t * accessModeTable, uint16_t * currentAccessState ); + // überprüft ob ein Frame komplett ist + bool mbGetFrameComplete (modbus_t * mb_data); + + void mbClearRxFrame (modbus_t * mb_data); + // handelt den Interrupt + void mbUartIsr (modbus_t* mb_data); + + + //Public Fuctions Modbus SLAVE + + // Umgang mit ankommenden Anfragen und Verarbeitung dieser + void mbSlaveProcessRtuQuery (modbus_t * mb_data); + // Bedeutung der Anfrage und wie mit dieser umgegangen werden soll + uint32_t mbSlaveCheckModbusRtuQuery (modbus_t * mb_data); + // Verarbeite eine Anfrage + uint32_t mbSlaveProcessPdu(modbus_t * mb_data, uint8_t * msg, uint32_t tx_position, uint8_t deviceID); + + //Public Fuctions Modbus MASTER + void mbMasterStartRtuReadHoldingRegister (uint8_t slave_adress, uint16_t start_adress, uint16_t number_of_registers, modbus_t * mb_data); + bool mbMasterGetTimeout (modbus_t * mb_data); + void mbMasterCheckResponseTimeout (modbus_t * mb_data); + mb_error_codes_t mbMasterCheckReadMultipleRegisterResponse (modbus_t * mb_data) ; + mb_error_codes_t check_write_multiple_register_response (modbus_t * mb_data) ; + void mb_start_rtu_write_multiple_register (uint8_t slave_adress, uint16_t adress, uint16_t * values, uint8_t number_of_registers, modbus_t * mb_data); + void MODBUS_UART_IRQHandler(UART_HandleTypeDef *huart); + #endif +#endif /* MODBUS_H_ */ Index: ecs_cellMon/firmware/inc/modbus_.h =================================================================== --- ecs_cellMon/firmware/inc/modbus_.h (revision 3) +++ ecs_cellMon/firmware/inc/modbus_.h (revision 3) @@ -0,0 +1,164 @@ +/* + * modbus.h + * + * Created: 03.09.2012 08:39:40 + * Author: Falko + */ + + +#ifndef MODBUS_H_ +#define MODBUS_H_ + + #if MODBUS_SUPPORT == TRUE + + #include "stdint.h" + #include "stdbool.h" + #include "main.h" + + + //! brief Anzahl der Startbits, nach Modbus Spezifikation immer 1, stop bits werden aus den Einstellungen geladen + #define NUMBER_OF_STARTBITS 1 + + //! brief Anzahl der Datenbits, nach Modbus Spezifikation immer 8 + #define NUMBER_OF_DATABITS 8 + + //! brief Max Timeput zwischen zwei gesendeten char + #define TIMEOUT_BETWEEN_CHARACTERS 1.5 + + //! brief Timeput bei dem fertig gesendetes Frame erkannt wird + #define TIMEOUT_FRAME_COMPLETE 3.5 + + //! define der Größe der Ein- und Ausgangsbuffer + #define RXBUFFERSIZE 255 + #define TXBUFFERSIZE 255 + + #define FORWARD_DATA TRUE + #define SEND_TO_LOKALBUS 1 + #define RESPOND_TO_QUERY 2 + #define MODBUS_UART_PARITY_EVEN 'e' + #define MODBUS_UART_PARITY_ODD 'o' + #define MODBUS_UART_PARITY_NONE 'n' + + + typedef union bword + { + uint16_t w; + int16_t sw; + uint8_t lb; + int8_t slb; + uint8_t b[2]; + int8_t sb[2]; + } bword_t; + + + + + typedef enum + { + ACCESS_MODE_READ_ONLY, //Muss als erstes damit nicht initialisierte Register automatisch 0 = READ ONLY sind + ACCESS_MODE_READ_WRITE, + ACCESS_MODE_WRITE_PROTECTABLE, + } accessMode_t; + + typedef enum mb_error_codes_enum + { + MB_ERROR_NOTHING = 0, + MB_ERROR_TIMEOUT = 1, + MB_ERROR_CRC = 2, + MB_ERROR_SLAVE_ADRESS = 3, + MB_ERROR_FUNCTION_CODE = 4, + MB_ERROR_BYTE_COUNT = 5, + MB_ERROR_START_ADRESS = 6, + MB_ERROR_UART_PE = 7, //Parity + MB_ERROR_UART_NE = 8, //Noise + MB_ERROR_UART_FE = 9, //Frame + MB_ERROR_UART_ORE = 10, //Overrun + } + mb_error_codes_t; + + + + typedef enum + { + MB_QUERY_NOTHING, + MB_QUERY_READ_IDENT, + MB_QUERY_READ_DATA, + MB_QUERY_READ_LIPRO_DATA, + MB_QUERY_WRITE_LIPRO_BALANCER_VOLTAGE, + MB_QUERY_WRITE_BUTTONS, + MB_QUERY_GSM_GATEWAY, + MB_QUERY_REMOTEBUS_GATEWAY, + MB_QUERY_WRITE_TO_GC, + MB_QUERY_SEND_DEVICE_ADDRESS, + MB_QUERY_SEND_SAVE_COMMAND, + MB_QUERY_GATEWAY, + MB_QUERY_SEND_DATA + } + mb_status_t; + + + typedef struct + { + //TIM_HandleTypeDef * timer; // Timer config + //TIM_OC_InitTypeDef * timerOcConfig; // Zeiger auf TimerInit Struktur + UART_HandleTypeDef * uart; // Zeiger auf das Uart Modul + GPIO_TypeDef * driverEnableGPIO; // Zuständiger einschalt Port + uint16_t driverEnableGPIOPin; // Zuständiger einschalt Pin + uint32_t mb_t15_total_timer_ticks; // max timeout zwischen einzelnen char + uint32_t mb_t35_total_timer_ticks; // timeout frame complete + volatile bool mb_rx_frame_complete; // frame complete ja/nein + uint32_t response_timeout_counter; // antwort Timeout + // QUERY (Anfrage): + uint8_t last_query_slave_adress; // zugehörige Slave Andresse + uint8_t last_query_function_code; // function Code + bword_t last_query_start_adress; // start Adresse + bword_t last_query_number_of_register; // Anzahl der Register + bool last_query_timeout; // Timeout + bword_t last_query_tcp_id; // stack ID + mb_status_t current_query; // Zeiger auf Statusstruktur + uint8_t rx_buffer[RXBUFFERSIZE]; // Bufferarray Empfangen + uint8_t tx_buffer[TXBUFFERSIZE]; // Bufferarray Senden + uint32_t rx_head; // + uint32_t tx_head; // + volatile bool setTxLed; // status Led + volatile bool setRxLed; // status Led + accessMode_t* accessModeTable; + uint16_t* currentAccessState; + } + modbus_t; + + + + //Public Functions Modbus + + // Timer Interrupt erkennt Fehler bei Framekomplettierung + void mbTimerIsr (modbus_t * mb_data); + // Initialiserung des Moduls muss mit den passenden Parametern gefüllt werden + void mbInit(modbus_t * mb_data, uint32_t baudrate, uint32_t parityMode, UART_HandleTypeDef * usart, accessMode_t * accessModeTable, uint16_t * currentAccessState ); + // überprüft ob ein Frame komplett ist + bool mbGetFrameComplete (modbus_t * mb_data); + + void mbClearRxFrame (modbus_t * mb_data); + // handelt den Interrupt + void mbUartIsr (modbus_t* mb_data); + + + //Public Fuctions Modbus SLAVE + + // Umgang mit ankommenden Anfragen und Verarbeitung dieser + void mbSlaveProcessRtuQuery (modbus_t * mb_data); + // Bedeutung der Anfrage und wie mit dieser umgegangen werden soll + uint32_t mbSlaveCheckModbusRtuQuery (modbus_t * mb_data); + // Verarbeite eine Anfrage + uint32_t mbSlaveProcessPdu(modbus_t * mb_data, uint8_t * msg, uint32_t tx_position, uint8_t deviceID); + + //Public Fuctions Modbus MASTER + void mbMasterStartRtuReadHoldingRegister (uint8_t slave_adress, uint16_t start_adress, uint16_t number_of_registers, modbus_t * mb_data); + bool mbMasterGetTimeout (modbus_t * mb_data); + void mbMasterCheckResponseTimeout (modbus_t * mb_data); + mb_error_codes_t mbMasterCheckReadMultipleRegisterResponse (modbus_t * mb_data) ; + mb_error_codes_t check_write_multiple_register_response (modbus_t * mb_data) ; + void mb_start_rtu_write_multiple_register (uint8_t slave_adress, uint16_t adress, uint16_t * values, uint8_t number_of_registers, modbus_t * mb_data); + void MODBUS_UART_IRQHandler(UART_HandleTypeDef *huart); + #endif +#endif /* MODBUS_H_ */ Index: ecs_cellMon/firmware/inc/output.h =================================================================== --- ecs_cellMon/firmware/inc/output.h (revision 3) +++ ecs_cellMon/firmware/inc/output.h (revision 3) @@ -0,0 +1,73 @@ +/** + ****************************************************************************** + * @file output.h + * @author ECS - Falko Jahn + * @version V1.0.0 + * @date 29 Jan 2021 + * @brief LVP OVP Ausgang + * + * Beschreibung + * Dieses Modul enthält die Funktionen zum steuern der Ausgänge: + * LVP + * OVP + ****************************************************************************** + */ +#ifndef __OUTPUT_H +#define __OUTPUT_H + + +//--- INCLUDEs ----------------------------------------------------------------- + +//--- GLOBALE TYPE DEFS -------------------------------------------------------- + +//--- GLOBALE DEFINES ---------------------------------------------------------- + +//--- GLOBALE VARIABLEN PROTOTYPEN --------------------------------------------- + +//--- GLOBALE FUNKTIONS PROTOTYPEN --------------------------------------------- +/** + * @brief OVP- Overvoltage Protection aktvieren + * + * Beschreibung: + * Der Ausgang und die LED werden abgeschalten um so das Laden zu verhindern + * @param Keine + * + * @retval Kein + */ +void OUTPUT_OVP_Enable(void); + +/** + * @brief LVP- Low Voltage Protection aktvieren + * + * Beschreibung: + * Der Ausgang und die LED werden abgeschalten um so das Entladen zu verhindern + * @param Keine + * + * @retval Kein + */ +void OUTPUT_LVP_Enable(void); + +/** + * @brief OVP- Overvoltage Protection deaktvieren + * + * Beschreibung: + * Der Ausgang und die LED werden eingeschaltet um so das Laden zu erlauben + * @param Keine + * + * @retval Kein + */ +void OUTPUT_OVP_Disable(void); + +/** + * @brief LVP- Low Voltage Protection deaktvieren + * + * Beschreibung: + * Der Ausgang und die LED werden eingeschaltet um so das Entladen zu erlauben + * @param Keine + * + * @retval Kein + */ +void OUTPUT_LVP_Disable(void); + + +#endif Index: ecs_cellMon/firmware/inc/sysdata.h =================================================================== --- ecs_cellMon/firmware/inc/sysdata.h (revision 3) +++ ecs_cellMon/firmware/inc/sysdata.h (revision 3) @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * @file sysdata.h + * @author ECS - Falko Jahn + * @version V1.0.0 + * @date 30-jan-2021 + * @brief System Daten + * + * Beschreibung + * enthält alle Systemdaten. Diese sind via modbus auslesbar und veränderbar + * + ****************************************************************************** + */ +#ifndef __SYSDATA_H +#define __SYSDATA_H + + +//--- INCLUDEs ----------------------------------------------------------------- +#include "main.h" +#include "modbus.h" + +//--- GLOBALE TYPE DEFS -------------------------------------------------------- + +// !!! Tabellenstruktur von LiPro1-x V2 als Vorlage !!! +typedef struct __attribute__ ((__packed__)) +{ + //---- GERÄTE INFORMATIONEN --- + uint16_t deviceTypeId; //0 + uint16_t reserved0; //1 Reserviert Alignement + uint32_t deviceSn; //2-3 Seriennummer + uint16_t fwMajor; //4 FW Versionsnummer + uint16_t fwMinor; //5 FW Versionsnummer + uint16_t fwRevision; //6 FW Versionsnummer + uint16_t reserved1; //7 RESERVIERT + + //--- GERÄTE PARAMETER ALLGEMEIN --- + uint32_t baudrate; //8-9 Baudraute + uint16_t parityMode; //10 Parity Mode 101 = 'e' = even, 111 = 'o' = odd, 110 = 'n' = none, default even + uint16_t stopBits; //11 Aktuell nicht ausgewert, automatische Auswahl nach Modbus standard abhängig vom Parity Mode + uint16_t slaveAddress; //12 Slave Adresse + uint16_t command; //13 Commnd + uint16_t reserved2[6]; //14-19 RESERVIERT + + //--- GERÄTE PARAMETER GERÄTE SPEZIFISCH --- + uint16_t ovpAlarm; //20 Gespeicherter Parameter: OVP Alarm Spannung in mV + uint16_t lvpAlarm; //21 Gespeicherter Parameter: LVP Alarm Spannung in mV + uint16_t ovpStart; //22 Gespeicherter Parameter: OVP Start Spannung in mV + uint16_t ovpStop; //23 Gespeicherter Parameter: OVP Stopp Spannung in mV + uint16_t lvpStart; //24 Gespeicherter Parameter: LVP Start Spannung in mV + uint16_t lvpStop; //25 Gespeicherter Parameter: LVP Stopp Spannung in mV + uint16_t vShutdownStart; //26 Gespeicherter Parameter: Unterspannungsabschaltung Start in mV + uint16_t vShutdownStop; //27 Gespeicherter Parameter: Unterspannungsabschaltung Stopp in mV + int16_t otShutdownStart; //28 Gespeicherter Parameter: Übertemperaturabschaltung Start in °C * 100 + int16_t otShutdownStop; //29 Gespeicherter Parameter: Übertemperaturabschaltung Stopp in °C * 100 + int16_t utpChargeStart; //30 Gespeicherter Parameter: Untertemperaturabschaltung Ladung Start in mV -- AB HIER NEUE PARAMETER --- + int16_t utpChargeStop; //31 Gespeicherter Parameter: Untertemperaturabschaltung Ladung Stopp in mV + int16_t utpDischargeStart; //32 Gespeicherter Parameter: Untertemperaturabschaltung Entladung Start in mV + int16_t utpDischargeStop; //33 Gespeicherter Parameter: Untertemperaturabschaltung Entladung Stopp in mV + uint16_t lvpTime; //34 Gespeicherter Parameter: LVP Verzögerung in s + uint16_t defaultBalVoltage; //35 Gespeicherter Parameter: Ausgleichsspannung Defaultwert in mV. Wird verwendet wenn kein Mastergerät vorhanden ist + int16_t refTemp; //36 Gespeicherter Parameter: Referenz Temperatur + int16_t ovpAlarmTempco; //37 Gespeicherter Parameter: Temperaturkompensation OVP Alarmspannung in mV / °C + int16_t lvpAlarmTempco; //38 Gespeicherter Parameter: Temperaturkompensation LVP ALarmspannung in mV / °C + int16_t ovpStartTempco; //39 Gespeicherter Parameter: Temperaturkompensation OVP Startspannung in mV / °C + int16_t ovpStopTempco; //40 Gespeicherter Parameter: Temperaturkompensation OVP Stoppspannung in mV / °C + int16_t lvpStartTempco; //41 Gespeicherter Parameter: Temperaturkompensation LVP Startspannung in mV / °C + int16_t lvpStopTempco; //42 Gespeicherter Parameter: Temperaturkompensation LVP Stoppspannung in mV / °C + int16_t vShutdownStartTempco; //43 Gespeicherter Parameter: Temperaturkompensation Unterspannungsabschaltung Start in mV / °C + int16_t vShutdownStopTempco; //44 Gespeicherter Parameter: Temperaturkompensation Unterspannungsabschaltung Stopp in mV / °C + int16_t balancerVoltageTempco; //45 Gespeicherter Parameter: Temperaturkompensation Ausgleichsspannung (Standalone Mode) in mV / °C + uint16_t balancerVoltageRemote; //46 Remote Setpoint Ausgleichsspannung, diese Register dient zur Steuerung der Balancerspannung von Mastergerät + uint16_t writeLocked; //47 1= (Einige) Register sind geschützt, 0 = Kein Schutz vorhanden + uint16_t keyAccepted; //48 1= lockKey is correct, gesperrte Register sind freigegeben zum beschreiben + uint16_t lockKey; //49 EINGABE ENTSPERR CODE + uint16_t newLockKey; //50 EINGABE NEUER Sperrcode + uint16_t reserved3[49]; //51-99 RESERVIERT + + // --- AKTUELLE DATEN ab Adresse 100 --- + uint16_t cellVoltage; //100 Zellspannung in mV + int16_t cellTemperature; //101 Zelltemperatur + int16_t balancerCurrent; //102 Aktueller Ausgleichsstrom in mA --> Neuer Istwert + uint16_t otShutdown; //103 Übertemperatur Shutdown Status, 0 = AUS, 1 = AKTIV + uint16_t utChargeShutdown; //104 Untertemperatur Ladung Shutdown Status, 0 = AUS, 1 = AKTIV + uint16_t utDischargeShutdown; //105 Untertemperatur Entladung Shutdown Status, 0 = AUS, 1 = AKTIV + uint16_t voltageShutdown; //106 Spannuns shutdown Status, 0 = AUS, 1 = AKTIV + uint16_t lvpDelayCounter; //107 Zähler bis Abschaltung LVP in Sekunden, ACHTUNG, EINHEIT GEÄNDERT IN SEKUNDEN + uint16_t balancerPower; //108 Nicht wirklich Power in Watt, sondern DAC Value von 0 bis MAX_DAC_VALUE, Achtung Bereich geändert + uint16_t mode; //109 Modus 0 = Autmatisch. Modus 1 = Manuelle Steuerung über Register 12 möglich + uint16_t lvpState; //110 Zustand Schaltausgang LVP, 0 = LVP aus, 1 = LVP aktiv (verzögert), 2 = LVP aktiv (unverzögert) + uint16_t ovpState; //111 Zustand Schaltausgang OVP, 0 = OVP aus, 1 = LVP aktiv + uint16_t maxVoltage; //112 Höchste Spannung seit letztem Reset + uint16_t minVoltage; //113 Niedrigste Spannung seit letztem Reset + int16_t maxTemperature; //114 Höchste Temperatur seit letztem Reset + int16_t minTemperature; //115 Niedrigste Temperatur seit letztem Reset + + // --- AKTUELLE BERECHNETE PARAMTER --- + uint16_t balancerVoltage; //116 Aktuelle Ausgleichsspannung + uint16_t ovpAlarmComp; //117 OVP Alarmspannung Temperatur kompensiert + uint16_t lvpAlarmComp; //118 LVP Alarmspannung Temperatur kompensiert + uint16_t ovpStartComp; //119 OVP Startspannung Temperatur kompensiert + uint16_t ovpStopComp; //120 OVP Stoppspannung Temperatur kompensiert + uint16_t lvpStartComp; //121 LVP Startspannung Temperatur kompensiert + uint16_t lvpStopComp; //122 LVP Stoppspannung Temperatur kompensiert + uint16_t vShutdownStartComp; //123 Spannungsabschaltung Start Temperatur kompensiert + uint16_t vShutdownStopComp; //124 Spannungsabschaltung Stopp Temperatur kompensiert + uint16_t balancerVoltageComp; //125 Ausgleichsspannung Temperatur kompensiert (wenn im Standalone Mode) + uint16_t masterMode; //126 Master modus dedektiert + uint16_t converterError; //127 Fehler DC / DC Converter + + // --- weitere historische Daten + uint16_t cycleCounter; //128 + uint16_t criticalUnderTempTime; //129 + uint16_t criticalOverTempTime; //130 + uint16_t criticalUnderVoltageTime; //131 + uint16_t criticalOverVoltageTime; //132 + uint16_t reserved6[17]; //133-149 RESERVIERT für weitere wichtige Daten + + // --- AKTUELLE BERECHNETE PARAMTER, Weniger Wichtig, für DEBUG Zwecke, normalerweise keine Übertragung notwendig --- + uint16_t chargeTime; //150 Interner Debbug Wert: Ladezeit DC DC Converter + uint16_t chargeTransferTime; //151 Interner Debbug Wert: Ladungstransfer Zeit DC DC Converter + uint16_t sekVoltage; //152 + uint16_t SekHvErrorCounter; //153 + uint16_t SekLvErrorCounter; //154 + uint16_t cellVoltageUnfiltered; //155 +}sys_data_struct_t; + +typedef union sys_data_union +{ + sys_data_struct_t s; + bword_t mb[sizeof( sys_data_struct_t) /2]; +} sys_data_t; + + +//--- GLOBALE DEFINES ---------------------------------------------------------- +#define CMD_NOCMD 0 +#define CMD_SAVE_PARAMETER_TO_EEPROM 1 +#define CMD_APPLY_MB_PARAMETER 2 +#define CMD_RESET_FACTORY 3 +#define CMD_RESET 4 +#define CMD_SAVE_LOCK_KEY 5 +#define CMD_RESET_COUNTERS 6 +#define CMD_RESET_MIN_MAX_VALUES 7 +#define CMD_SAVE_SN 12345 + + + + + +#define MB_BAUDRATE_DEFAULT 19200 // bit pro sekunde +#define MB_PARITY_MODE_DEFAULT 'e' // EVEN - GERADE +#define MB_STOPBIT_MODE_DEFAULT 1 +#define MB_SLAVE_ADDRESS_DEFAULT 1 +#define MB_MASTER_MODE_DEFAULT 0 +#define MIN_VOLTAGE_DEFAULT 65535 +#define MAX_VOLTAGE_DEFAULT 0 +#define MIN_TEMPERATURE_DEFAULT 32767 +#define MAX_TEMPERATURE_DEFAULT -32767 + + + +// ------ DEFAULT CELLPARAMETER ------ +#define OVP_ALARM_VOLTAGE_DEFAULT 3700 // [mV] +#define LVP_ALARM_VOLTAGE_DEFAULT 2800 // [mV] +#define OVP_START_VOLTAGE_DEFAULT 3650 // [mV] +#define OVP_STOPP_VOLTAGE_DEFAULT 3600 // [mV] +#define LVP_START_VOLTAGE_DEFAULT 2900 // [mV] +#define LVP_STOPP_VOLTAGE_DEFAULT 3200 // [mV] +#define BAL_VOLTAGE_DEFAULT 3600 // [mV] für 14,4 V Ladeschlussspannung +#define VOLTAGE_SHUTDOWN_START_VOLTAGE_DEFAULT 2500 // [mV] +#define VOLTAGE_SHUTDOWN_STOPP_VOLTAGE_DEFAULT 2600 // [mV] +#define OVERTEMPPROTECTION_START_DEFAULT 500 // [°C *10] +#define OVERTEMPPROTECTION_STOP_DEFAULT 450 // [°C *10] +#define UNDERTEMPPROTECTION_CHARGE_START_DEFAULT 50 // [°C *10] +#define UNDERTEMPPROTECTION_CHARGE_STOP_DEFAULT 70 // [°C *10] +#define UNDERTEMPPROTECTION_DISCHARGE_START_DEFAULT -150 // [°C *10] +#define UNDERTEMPPROTECTION_DISCHARGE_STOP_DEFAULT -100 // [°C *10] +#define LVP_TIME_DEFAULT 600 // s +#define BASIS_TEMP_DEFAULT 250 // 25°C +#define OVP_ALARM_TEMPCO_DEFAULT 0 // [mV / °C] +#define OVP_START_TEMPCO_DEFAULT 0 // [mV / °C] +#define OVP_STOPP_TEMPCO_DEFAULT 0 // [mV / °C] +#define LVP_ALARM_TEMPCO_DEFAULT 0 // [mV / °C] +#define LVP_START_TEMPCO_DEFAULT 0 // [mV / °C] +#define LVP_STOPP_TEMPCO_DEFAULT 0 // [mV / °C] +#define V_SHUTDOWN_START_TEMPCO_DEFAULT 0 // [mV / °C] +#define V_SHUTDOWN_STOPP_TEMPCO_DEFAULT 0 // [mV / °C] +#define BAL_TEMPCO_DEFAULT 0 // [mV / °C] + + +#define CONVERTER_ERROR_NONE 0 +#define CONVERTER_ERROR_OUTPUT_VOLT_TOO_HIGH 2 +#define CONVERTER_ERROR_OUTPUT_VOLT_TOO_LOW 3 +#define CONVERTER_ERROR_STARTUP_ERROR 4 + + +//--- GLOBALE VARIABLEN PROTOTYPEN --------------------------------------------- +extern sys_data_t sysData; + + +#define MIN_ADRESS 0 +#define MAX_ADRESS ((sizeof(sysData)/2)-1) + +extern accessMode_t accessModeTable[MAX_ADRESS+1]; + + +//--- GLOBALE FUNKTIONS PROTOTYPEN --------------------------------------------- +void SYSDATA_Init(void); + + + + +#endif Index: ecs_cellMon/firmware/inc/template.h =================================================================== --- ecs_cellMon/firmware/inc/template.h (revision 3) +++ ecs_cellMon/firmware/inc/template.h (revision 3) @@ -0,0 +1,49 @@ +/** + ****************************************************************************** + * @file template.h + * @author ECS - MAX MUSTERMANN + * @version V1.0.0 + * @date 09-Sep-2015 + * @brief Muster Modul Treiber + * + * Beschreibung + * Dieses Modul enthält ein Musteraufbau einer Header Datei + * + * Achtung: + * Hinweis1 + * Hinweis2 + ****************************************************************************** + */ +#ifndef __TEMPLATE_H +#define __TEMPLATE_H + + +//--- INCLUDEs ----------------------------------------------------------------- + +//--- GLOBALE TYPE DEFS -------------------------------------------------------- + +//--- GLOBALE DEFINES ---------------------------------------------------------- + +//--- GLOBALE VARIABLEN PROTOTYPEN --------------------------------------------- + +//--- GLOBALE FUNKTIONS PROTOTYPEN --------------------------------------------- +/** + * @brief Muster Funktion + * + * Beschreibung: + * ..... + * ..... + * + * @author ECS - MAX MUSTERMANN <-- Nur wenn abweichend von Modul Autor + * + * @param Keine + * + * @retval Kein + */ +void TEMPLATE_Init(void); + + + + + +#endif Index: ecs_cellMon/firmware/main (2).emSession =================================================================== --- ecs_cellMon/firmware/main (2).emSession (revision 3) +++ ecs_cellMon/firmware/main (2).emSession (revision 3) @@ -0,0 +1,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: ecs_cellMon/firmware/main.emProject =================================================================== --- ecs_cellMon/firmware/main.emProject (revision 3) +++ ecs_cellMon/firmware/main.emProject (revision 3) @@ -0,0 +1,170 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: ecs_cellMon/firmware/main.emSession =================================================================== --- ecs_cellMon/firmware/main.emSession (revision 3) +++ ecs_cellMon/firmware/main.emSession (revision 3) @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: ecs_cellMon/firmware/main_Debug (2).jlink =================================================================== --- ecs_cellMon/firmware/main_Debug (2).jlink (revision 3) +++ ecs_cellMon/firmware/main_Debug (2).jlink (revision 3) @@ -0,0 +1,40 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +WorkRAMSize = 0x8000 +WorkRAMAddr = 0x20000000 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF Index: ecs_cellMon/firmware/main_Debug.jlink =================================================================== --- ecs_cellMon/firmware/main_Debug.jlink (revision 3) +++ ecs_cellMon/firmware/main_Debug.jlink (revision 3) @@ -0,0 +1,40 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF Index: ecs_cellMon/firmware/main_Release.jlink =================================================================== --- ecs_cellMon/firmware/main_Release.jlink (revision 3) +++ ecs_cellMon/firmware/main_Release.jlink (revision 3) @@ -0,0 +1,40 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +MonModeVTableAddr = 0xFFFFFFFF +MonModeDebug = 0 +MaxNumAPs = 0 +LowPowerHandlingMode = 0 +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +EraseType = 0x00 +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="ARM7" +[GENERAL] +WorkRAMSize = 0x8000 +WorkRAMAddr = 0x20000000 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF Index: ecs_cellMon/firmware/src/balancer.c =================================================================== --- ecs_cellMon/firmware/src/balancer.c (revision 3) +++ ecs_cellMon/firmware/src/balancer.c (revision 3) @@ -0,0 +1,310 @@ +/** + ****************************************************************************** + * @file balancer.c + * @author ECS, Falko Jahn + * @version V1.0.0 + * @date 03.02.2021 + * @brief BALANCER Modul + * Beschreibung in Header + ****************************************************************************** + */ + +// --- INCLUDES ---------------------------------------------------------------- +#include +#include "balancer.h" +#include "main.h" +#include "sysdata.h" +#include "tim.h" +#include "dac.h" +#include "comp.h" +#include "led.h" + + +//--- GGF. EXTERNE VARIABLEN --------------------------------------------------- + +//--- LOKALE DEFINES - bitte hier dokumentieren -------------------------------- +//Imax = 20A +//Verstrkung = 100 +//Shunt = 0,001 Ohm +//U dac = Imax * Rshunt * Verstrkung --> 20 A * 0,001 Ohm * 100 = 2.0V +//Dac Value = Udac / (Uref / 4096) +//#define MAX_DAC_VALUE 3276 +//Zur Zeit reduzieren wir den max. Wert weil der Strommessverstrker langsam ist und zu spt den max Wert ausgibt +//Daher zur Zeit nur 1,7V statt 2.0V +#define MAX_DAC_VALUE 1500 //2300 + +//MAX Timer Value um nicht mehr laufenden DC DC Wandler zu erkennen +//gemessen 1500 Periode bei 5V/12 und Sysclock 64Mhz +//um Faktor 10 vergrert +#define MAX_TIMER_VALUE 500 + + + +#define MIN_OUTPUT_VOLTAGE 10000 //mV +#define MAX_OUTPUT_VOLTAGE 68000 //mv //Messgenauikeit ca. +- 2-3V +#define MAX_ERROR 100 // +#define RESTART_TIMEOUT 100 //ms +#define BALANCER_REGULATION_TIME 10 //Alle 10mS ein Schritt +#define CONVERTER_MIN_POWER 300 //300 von 3000 = 10% +//--- LOKALE TYPE DEFS - bitte hier dokumentieren------------------------------- + +//--- DEFINATIONEN GLOBALER VARIABLEN - Bitte in Header dokumentieren ---------- + +//--- LOKALE VARIABLEN - bitte hier dokumentieren ------------------------------ + +uint32_t restartCounter; +uint32_t startImpulsCounter; +uint32_t balancer_running; +uint32_t secondCounter; +uint32_t balancerRegulationCounter= BALANCER_REGULATION_TIME; +//--- LOKALE FUNKTIONS PROTOTYPEN ---------------------------------------------- +void BALANCER_SetStartImpulse(void); + +//--- LOKALE FUNKTIONEN - bitte hier dokumentieren ----------------------------- + +//--- GLOBALE FUNKTIONEN - bitte in Header dokumentieren------------------------ +void BALANCER_Init(void) +{ + + // Starte timer zur Messung der Charge Time und der Charge Transfer Time + // Charge Time bedeutet die Zeit zum Aufbau des Magnedfeldes. Also vom Einschalten + // des Mosfets bis zum erreichen der Maximal Stroms. + //HAL_TIM_Base_Start_IT(&htim16); + //HAL_TIM_Base_Start_IT(&htim17); + + HAL_TIM_IC_Start(&htim1,TIM_CHANNEL_1); + HAL_TIM_IC_Start(&htim1,TIM_CHANNEL_2); + + + + + + if (HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 0) != HAL_OK) + { + /* Setting value Error */ + printf("HAL_DAC_SetValue ERROR\n"); + return; + } + printf("HAL_DAC_SetValue OK\n"); + + + if (HAL_DAC_Start(&hdac1, DAC_CHANNEL_1) != HAL_OK) + { + /* Start Error */ + printf("HAL_DAC_Start ERROR\n"); + return; + } + printf("HAL_DAC_Start OK\n"); + + + //Comparator fr Strom + if(HAL_COMP_Start(&hcomp1) != HAL_OK) + { + /* Initialization Error */ + printf("HAL_COMP1_Start ERROR\n"); + return; + } + printf("HAL_COMP1_Start OK\n"); + + + //Comparator fr Charge Transfer + if(HAL_COMP_Start(&hcomp2) != HAL_OK) + { + /* Initialization Error */ + printf("HAL_COMP2_Start ERROR\n"); + return; + } + printf("HAL_COMP2_Start OK\n"); + printf("BALANCER_Init OK\n"); + +} +uint32_t counterValue; + +void BALANCER_Exec() +{ + uint32_t val1 = HAL_TIM_ReadCapturedValue(&htim1,TIM_CHANNEL_1); + uint32_t val2 = HAL_TIM_ReadCapturedValue(&htim1,TIM_CHANNEL_2); + + + //Val1 representiert die gesamte Periode von Ipeak Abschaltung zu Ipeak Abschaltung (falling edge comparator 1) + //Val2 Periode von Ipeak Abschaltung (falling edge comparator 1) bis zu ende charge transfer (comparartor 2 rising edge ) + uint32_t periodeTime = val1; + uint32_t chargeTransferTime = val2; + uint32_t chargeTime = periodeTime - chargeTransferTime; + uint32_t trafo = 2;// n2 / n1; + uint32_t usek = ((float)chargeTime / (float)chargeTransferTime) * trafo * sysData.s.cellVoltage; + sysData.s.chargeTime = chargeTime; + sysData.s.chargeTransferTime = chargeTransferTime; + sysData.s.sekVoltage = usek / 10; + + + //Wenn Balancer eingeschaltet + if (sysData.s.balancerPower > 0) + { + // ----- Prfe ob Flyback converter luft ----- + counterValue = __HAL_TIM_GET_COUNTER(&htim1); + if (( counterValue > MAX_TIMER_VALUE) && (sysData.s.converterError == CONVERTER_ERROR_NONE) ) + { + restartCounter++; + balancer_running=0; + } + else + { + if (restartCounter>0) restartCounter--; + } + + + if (restartCounter >= RESTART_TIMEOUT) + { + BALANCER_SetStartImpulse(); + restartCounter = 0; + balancer_running=1; + startImpulsCounter++; + } + else + { + + } + + if (startImpulsCounter > 10) + { + sysData.s.balancerPower=0; + HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 0); + sysData.s.converterError = CONVERTER_ERROR_STARTUP_ERROR; + printf("CONVERTER ERROR: CONVERTER_STARTUP ERROR!\n"); + startImpulsCounter = 0; + + } + + + secondCounter++; + if (secondCounter > 999) + { + if (startImpulsCounter > 0) startImpulsCounter--; + secondCounter = 0; + } + + + + // ----- Prfe ob Flyback converter Ausgangsspannung zu hoch ----- + if ((usek > MAX_OUTPUT_VOLTAGE) && (balancer_running == 1)) + { + sysData.s.SekHvErrorCounter++; + } + else + { + if (sysData.s.SekHvErrorCounter>0) sysData.s.SekHvErrorCounter--; + } + + if (sysData.s.SekHvErrorCounter > MAX_ERROR) + { + sysData.s.balancerPower=0; + HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 0); + sysData.s.converterError = CONVERTER_ERROR_OUTPUT_VOLT_TOO_HIGH; + printf("CONVERTER ERROR: CONVERTER_ERROR_OUTPUT_VOLT_TOO_HIGH\n"); + sysData.s.SekHvErrorCounter=0; + } + + // ----- Prfe ob Flyback converter Ausgangsspannung zu niedrig ----- + if ((usek < MIN_OUTPUT_VOLTAGE) && (balancer_running == 1)) + { + sysData.s.SekLvErrorCounter++; + } + else + { + if (sysData.s.SekLvErrorCounter>0) sysData.s.SekLvErrorCounter--; + } + + if (sysData.s.SekLvErrorCounter > MAX_ERROR) + { + sysData.s.balancerPower=0; + HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 0); + sysData.s.converterError = CONVERTER_ERROR_OUTPUT_VOLT_TOO_LOW; + printf("CONVERTER ERROR: CONVERTER_ERROR_OUTPUT_VOLT_TOO_LOW\n"); + sysData.s.SekLvErrorCounter=0; + } + } + else + { + //Balancer ist ausgeschaltet + sysData.s.sekVoltage=0; + } + + if (balancerRegulationCounter > 0) balancerRegulationCounter--; + + if ((sysData.s.mode == 0) && (balancerRegulationCounter == 0)) //AUTO MODE + { + balancerRegulationCounter = BALANCER_REGULATION_TIME; + if (sysData.s.cellVoltageUnfiltered > sysData.s.balancerVoltage) + { + if ((sysData.s.balancerPower < MAX_DAC_VALUE) && (sysData.s.converterError == CONVERTER_ERROR_NONE )) + { + sysData.s.balancerPower++; + if (sysData.s.balancerPower < CONVERTER_MIN_POWER ) + { + sysData.s.balancerPower = CONVERTER_MIN_POWER; + startImpulsCounter = 0; + } + HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, sysData.s.balancerPower); + } + } + if (sysData.s.cellVoltageUnfiltered < sysData.s.balancerVoltage) + { + if (sysData.s.balancerPower > 0) + { + sysData.s.balancerPower--; + if( sysData.s.balancerPower < CONVERTER_MIN_POWER) sysData.s.balancerPower = 0; + HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, sysData.s.balancerPower); + + } + } + } + + if (sysData.s.mode == 1) + { + if ((sysData.s.balancerPower < MAX_DAC_VALUE) && (sysData.s.converterError == CONVERTER_ERROR_NONE )) + { + HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_1, DAC_ALIGN_12B_R, sysData.s.balancerPower); + } + } + + + + if (sysData.s.balancerPower > 0) + { + LED_FunctionSetTimes(900,100); + } + else + { + LED_FunctionSetTimes(100,900); + } + + +} + + + + +void BALANCER_SetStartImpulse() +{ + + //Balancer arbeitet nicht. Schalte Ausgang von Comparator um auf normalen GPIO, + //setze ausgang auf 0, und schalte dann wieder auf Comparator, dadurch wird ein neuer Setz Impuls auf das Flip Flop gegeben. + printf("DC DC Wandler not running, start impuls\n"); + GPIO_InitTypeDef GPIO_InitStruct = {0}; + GPIO_InitStruct.Pin = COMP2_OUT_DISCHARGE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(COMP2_OUT_DISCHARGE_GPIO_Port, &GPIO_InitStruct); + HAL_GPIO_WritePin(COMP2_OUT_DISCHARGE_GPIO_Port, COMP2_OUT_DISCHARGE_Pin, GPIO_PIN_RESET); + + //Ausgang zurck auf Comparator + GPIO_InitStruct.Pin = COMP2_OUT_DISCHARGE_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF7_COMP2; + HAL_GPIO_Init(COMP2_OUT_DISCHARGE_GPIO_Port, &GPIO_InitStruct); + +} Index: ecs_cellMon/firmware/src/bms.c =================================================================== --- ecs_cellMon/firmware/src/bms.c (revision 3) +++ ecs_cellMon/firmware/src/bms.c (revision 3) @@ -0,0 +1,332 @@ +/** + ****************************************************************************** + * @file bms.c + * @author ECS, Falko Jahn + * @version V1.0.0 + * @date 03-Feb-2021 + * @brief BMS Modul + * Beschreibung in Header + ****************************************************************************** + */ + +// --- INCLUDES ---------------------------------------------------------------- +#include "bms.h" +#include "main.h" +#include "sysdata.h" +#include "output.h" +#include "led.h" +#include "stdio.h" +#include "eeprom.h" + +//--- GGF. EXTERNE VARIABLEN --------------------------------------------------- + +//--- LOKALE DEFINES - bitte hier dokumentieren -------------------------------- +#define LVP_TIME_INTERVALL 1000 //Einheit für Delay ist Sekunden, deshalb Zähler alle 1000ms hochzählen +#define MINUTE_TIME_INTERVALL 60000 +#define HOUR_TIME_INTERVALL (60UL * 60000UL) +//--- LOKALE TYPE DEFS - bitte hier dokumentieren------------------------------- + +//--- DEFINATIONEN GLOBALER VARIABLEN - Bitte in Header dokumentieren ---------- + +//--- LOKALE VARIABLEN - bitte hier dokumentieren ------------------------------ +uint32_t lastLvpDelayTime = 0; +uint32_t lastMinuteTime = 0; +uint32_t lastHourTime = 0; +uint32_t batteryState = 0; // 0 = discharged, 1 = charged +uint32_t initRefresh = 1; +//--- LOKALE FUNKTIONS PROTOTYPEN ---------------------------------------------- + + +//--- LOKALE FUNKTIONEN - bitte hier dokumentieren ----------------------------- +/** + * @brief Calculate Setpoints + * + * Beschreibung: + * Berechnete die aktullen Schwellwerte anhand der Temperatur + * + * + * + * @param Keine + * + * @retval Kein + */ +void calculateSetpoints() +{ + int32_t delta_t; + + delta_t = sysData.s.cellTemperature - sysData.s.refTemp; + delta_t /= 10; + + sysData.s.ovpAlarmComp = sysData.s.ovpAlarm + delta_t * sysData.s.ovpAlarmTempco; + sysData.s.lvpAlarmComp = sysData.s.lvpAlarm + delta_t * sysData.s.lvpAlarmTempco; + sysData.s.ovpStartComp = sysData.s.ovpStart + delta_t * sysData.s.ovpStartTempco; + sysData.s.ovpStopComp = sysData.s.ovpStop + delta_t * sysData.s.ovpStopTempco; + sysData.s.lvpStartComp = sysData.s.lvpStart + delta_t * sysData.s.lvpStartTempco; + sysData.s.lvpStopComp = sysData.s.lvpStop + delta_t * sysData.s.lvpStopTempco; + sysData.s.vShutdownStartComp = sysData.s.vShutdownStart + delta_t * sysData.s.vShutdownStartTempco; + sysData.s.vShutdownStopComp = sysData.s.vShutdownStop + delta_t * sysData.s.vShutdownStopTempco; + + sysData.s.balancerVoltageComp = sysData.s.defaultBalVoltage + delta_t * sysData.s.balancerVoltageTempco; + + + if (!sysData.s.masterMode) + { + sysData.s.balancerVoltage = sysData.s.balancerVoltageComp; + } + +} +//--- GLOBALE FUNKTIONEN - bitte in Header dokumentieren------------------------ +void BMS_Exec(void) +{ + calculateSetpoints(); + + + // ------------ Über Temperatur Überwachung ----------------------- + if (sysData.s.cellTemperature > sysData.s.otShutdownStart) + { + sysData.s.otShutdown = 1; + } + + if (sysData.s.cellTemperature < sysData.s.otShutdownStop) + { + sysData.s.otShutdown = 0; + } + + // ------------ Unter Temperatur Überwachung ----------------------- + if (sysData.s.cellTemperature < sysData.s.utpChargeStart) + { + sysData.s.utChargeShutdown = 1; + } + + if (sysData.s.cellTemperature > sysData.s.utpChargeStop) + { + sysData.s.utChargeShutdown = 0; + } + + if (sysData.s.cellTemperature < sysData.s.utpDischargeStart) + { + sysData.s.utDischargeShutdown = 1; + } + + if (sysData.s.cellTemperature > sysData.s.utpDischargeStop) + { + sysData.s.utDischargeShutdown = 0; + } + + // ------------ VOLTAGE SHUTDOWN Überwachung ----------------------- + if (sysData.s.cellVoltage < sysData.s.vShutdownStartComp) + { + sysData.s.voltageShutdown=1; + } + + if (sysData.s.cellVoltage > sysData.s.vShutdownStopComp) + { + sysData.s.voltageShutdown=0; + } + + + // -------------- OVP ---------------------------------------- + // Spannung zu hoch? Temperatur nicht OK? --> OVP Sicherheitsschleife öfffen! + if ((sysData.s.cellVoltage > sysData.s.ovpStartComp) || (sysData.s.otShutdown == 1 ) || (sysData.s.utChargeShutdown == 1 ) || (sysData.s.voltageShutdown == 1) ) + { + OUTPUT_OVP_Enable(); + sysData.s.ovpState = 1; + } + + // Spannung und Temperaturen wieder OK? --> OVP Sicherheitsschleife wieder schließen! + if ((sysData.s.cellVoltage < sysData.s.ovpStopComp) && (sysData.s.otShutdown == 0 ) && (sysData.s.utChargeShutdown == 0 ) && (sysData.s.voltageShutdown == 0) ) + { + OUTPUT_OVP_Disable(); + sysData.s.ovpState = 0; + } + + // LVP + // Spannung zu niedrig? --> lVP Sicherheitsschleife verzögert öfffen! + if (sysData.s.cellVoltage < sysData.s.lvpStartComp) + { + if (HAL_GetTick() >= lastLvpDelayTime + LVP_TIME_INTERVALL) + { + if (sysData.s.lvpDelayCounter < sysData.s.lvpTime) sysData.s.lvpDelayCounter++; //TODO : Prüfe Zeitzähler + lastLvpDelayTime = HAL_GetTick(); + } + } + + if ((sysData.s.lvpDelayCounter == sysData.s.lvpTime) || ( sysData.s.otShutdown == 1 ) || (sysData.s.utDischargeShutdown == 1)) + { + OUTPUT_LVP_Enable(); + sysData.s.lvpState = 1; + } + + + + // Spannung wieder OK? --> LVP Sicherheitsschleife wieder schließen! + if (sysData.s.cellVoltage > sysData.s.lvpStopComp) + { + sysData.s.lvpDelayCounter=0; + } + + if ((sysData.s.lvpDelayCounter == 0) && (sysData.s.otShutdown == 0 ) && (sysData.s.utDischargeShutdown == 0)) + { + OUTPUT_LVP_Disable(); + sysData.s.lvpState = 0; + } + + // ------------ ALARM LED ------------------------- + static uint32_t ledErrorBlinkState=0; + if (sysData.s.converterError == CONVERTER_ERROR_OUTPUT_VOLT_TOO_HIGH) + { + if (ledErrorBlinkState != 1) + { + LED_ErrorStartBlink(7000, 1000); // 7 sekunden + ledErrorBlinkState = 1; + } + + } + else if ((sysData.s.converterError == CONVERTER_ERROR_OUTPUT_VOLT_TOO_LOW) || (sysData.s.converterError == CONVERTER_ERROR_STARTUP_ERROR)) + { + if (ledErrorBlinkState != 2) + { + LED_ErrorStartBlink(5000, 1000); // 5 sekunden + ledErrorBlinkState = 2; + } + } + else if (sysData.s.otShutdown == 1) + { + if (ledErrorBlinkState != 3) + { + LED_ErrorStartBlink(3000, 1000); // 3 sekunden + ledErrorBlinkState = 3; + } + } + else if (sysData.s.cellVoltage > sysData.s.ovpAlarmComp) + { + if (ledErrorBlinkState != 4) + { + LED_ErrorStartBlink(1000, 1000); // 1 sekunden + ledErrorBlinkState = 4; + } + } + else if (sysData.s.cellVoltage < sysData.s.lvpAlarmComp) + { + if (ledErrorBlinkState != 5) + { + LED_ErrorStartBlink(150, 1000); // 0,15 sekunden + } + OUTPUT_LVP_Enable(); + sysData.s.lvpState = 2; + sysData.s.lvpDelayCounter= sysData.s.lvpTime; + ledErrorBlinkState = 5; + } + else + { + LED_ErrorOff(); + ledErrorBlinkState = 0; + } + + + + bool epromDataChanged = false; + //Neu: Implementierung Cycle counter + //Wenn Zelle leer war und jetzt wieder aufgeladen, dann Cycle Counter erhöhen + if ((batteryState == 0) && (sysData.s.cellVoltage >= sysData.s.ovpStopComp)) + { + batteryState = 1; + sysData.s.cycleCounter++; + printf("Batterie charged! Cyclecounter++!\n"); + epromDataChanged = true; + } + + // Batterie State auf entladen schalten, wenn Zelle leer + if ((batteryState == 1) && (sysData.s.cellVoltage <= sysData.s.lvpStopComp)) + { + printf("Batterie discharged!\n"); + batteryState = 0; + } + + + if ((HAL_GetTick() >= lastMinuteTime + MINUTE_TIME_INTERVALL) || initRefresh) + { + + initRefresh = 0; + lastMinuteTime = HAL_GetTick(); + printf("Minute Intervall checks!\n"); + + // Speicher Max und min werte + if (sysData.s.cellVoltage < sysData.s.minVoltage) + { + + sysData.s.minVoltage = sysData.s.cellVoltage; + epromDataChanged = true; + printf("New Min Voltage %d Saved\n", sysData.s.cellVoltage); + } + + if (sysData.s.cellVoltage > sysData.s.maxVoltage) + { + + sysData.s.maxVoltage = sysData.s.cellVoltage; + epromDataChanged = true; + printf("New Max Voltage %d Saved\n", sysData.s.cellVoltage); + } + + if (sysData.s.cellTemperature < sysData.s.minTemperature) + { + sysData.s.minTemperature = sysData.s.cellTemperature; + epromDataChanged = true; + printf("New Min Temp. %d Saved\n", sysData.s.cellTemperature); + } + + if (sysData.s.cellTemperature > sysData.s.maxTemperature) + { + sysData.s.maxTemperature = sysData.s.cellTemperature; + epromDataChanged = true; + printf("New Max Temp. %d Saved\n", sysData.s.cellTemperature); + } + + // Aufzeichnung kritischer Betriebsbedingungen + // Temperatur 5°C Über Abschalttemperatur (Default 50°C + 5°C = 55°C) + if ((sysData.s.cellTemperature > sysData.s.otShutdownStart + 50) && (sysData.s.criticalOverTempTime < 65535 )) + { + sysData.s.criticalOverTempTime++; + epromDataChanged = true; + printf("New Max Temp. %d Saved\n", sysData.s.cellTemperature); + } + + // Temperatur 5°C Unter LastAbschalttemperatur (Default -15°C + -5°C = -20°C) + if ((sysData.s.cellTemperature < sysData.s.utpDischargeStart - 50) && (sysData.s.criticalUnderTempTime < 65535 )) + { + sysData.s.criticalUnderTempTime++; + epromDataChanged = true; + } + + // Spannung unter lvp alarm + if ((sysData.s.cellVoltage < sysData.s.lvpAlarm - 100 ) && (sysData.s.criticalUnderVoltageTime < 65535 )) + { + sysData.s.criticalUnderVoltageTime++; + epromDataChanged = true; + } + + // Spannung über ovp alarm + if ((sysData.s.cellVoltage > sysData.s.ovpAlarm + 100 ) && (sysData.s.criticalOverVoltageTime < 65535 )) + { + sysData.s.criticalOverVoltageTime++; + epromDataChanged = true; + } + + } + + + + //Speicher Log Daten maximal jede Stunde, aber auch nur dann, wenn siche Werte, seit dem letztem mal geändert haben + if (HAL_GetTick() >= lastHourTime + HOUR_TIME_INTERVALL) + { + lastHourTime = HAL_GetTick(); + printf("Hour Intervall checks!\n"); + + if (epromDataChanged ) + { + EEPROM_storeLogData(); + epromDataChanged = false; + } + + } +} Index: ecs_cellMon/firmware/src/eeprom.c =================================================================== --- ecs_cellMon/firmware/src/eeprom.c (revision 3) +++ ecs_cellMon/firmware/src/eeprom.c (revision 3) @@ -0,0 +1,644 @@ +#include "eeprom.h" +#include "stdio.h" +#include "string.h" +/********************************************************/ + +// Eeprom state related defines + +/*****************EEPROM_EMULATOR************************/ + +typedef struct +{ + // Schnittstellenparameter + uint32_t baudrate; + uint16_t parityMode; + uint16_t stopBits; + uint16_t slaveAddress; + + // Cell Parameter + uint16_t ovpAlarm; + uint16_t lvpAlarm; + uint16_t ovpStart; + uint16_t ovpStop; + uint16_t lvpStart; + uint16_t lvpStop; + uint16_t vShutdownStart; + uint16_t vShutdownStop; + int16_t otShutdownStart; + int16_t otShutdownStop; + int16_t utpChargeStart; + int16_t utpChargeStop; + int16_t utpDischargeStart; + int16_t utpDischargeStop; + uint16_t lvpTime; + uint16_t defaultBalVoltage; + + // tempco + int16_t refTemp; + int16_t ovpAlarmTempco; + int16_t lvpAlarmTempco; + int16_t ovpStartTempco; + int16_t ovpStopTempco; + int16_t lvpStartTempco; + int16_t lvpStopTempco; + int16_t vShutdownStartTempco; + int16_t vShutdownStopTempco; + int16_t balancerVoltageTempco; + uint16_t lockKey; +}eeprom_data_t; + +typedef struct +{ + // Geräteinformation + uint32_t SN; + uint8_t deviceInfoWritten; + uint8_t resv[3]; +}device_info_t; + + +typedef struct +{ + // Eeprom Status Infos + uint32_t writeCounter; + uint16_t structureSize; + uint16_t revisionInfo; + uint8_t firstStartId; +}eeprom_state_t; + + +typedef struct +{ + // Eeprom Status Infos + uint16_t cycleCounter; + uint16_t minVoltage; + uint16_t maxVoltage; + int16_t minTemperature; + int16_t maxTemperature; + uint16_t criticalOverTempTime; + uint16_t criticalUnderTempTime; + uint16_t criticalOvervoltageTime; + uint16_t criticalUndervoltageTime; + +}log_data_t; + +// fasse zu einer Struktur zusammen um nachher einfach darauf zugreifen zu können +typedef struct +{ + eeprom_data_t changedData; + eeprom_state_t eepromState; + device_info_t deviceInfo; + log_data_t logData; +}eeprom_stored_data_t; + +// Flash related defines +#define USER_FLASH_BASE_ADRESS FLASH_BASE + +#define USER_FLASH_SIZE FLASH_SIZE +//#define USER_FLASH_END ((USER_FLASH_BASE_ADRESS + USER_FLASH_SIZE) - 1) +#define USER_FLASH_END (USER_FLASH_BASE_ADRESS + USER_FLASH_SIZE) +#define USER_FLASH_PAGE_SIZE (0x800) + +// Eeprom emulator related defines +#define NUMBER_OF_PAGES (2) +#define USER_EEPROM_BASE_ADRESS (USER_FLASH_END - (USER_FLASH_PAGE_SIZE * NUMBER_OF_PAGES)) + +// Data to store reated defines +#define SIZEOF_DEFAULT_EEPROM_DATA (sizeof(eeprom_data_t)) +#define SIZEOF_CHANGED_EEPROM_DATA (sizeof(eeprom_data_t)) +#define SIZEOF_DEVICE_INFO (sizeof(device_info_t)) +#define SIZEOF_EEPROM_STATE (sizeof(eeprom_state_t)) + +#define SIZE_OF_DATA_TO_STORE (SIZEOF_CHANGED_EEPROM_DATA + SIZEOF_DEVICE_INFO + SIZEOF_EEPROM_STATE) + +// Adress related defines +#define EEPROM_ADRESS_FIRST_START_ID (USER_EEPROM_BASE_ADRESS - 1 + SIZE_OF_DATA_TO_STORE - 1 - SIZEOF_DEVICE_INFO - 1 - 1) +#define FIRST_START_ID (1) + + +static uint32_t GetPage(uint32_t Address); +static HAL_StatusTypeDef getEEPROMData(uint32_t address, uint8_t * data, uint32_t len); + +// muss modulo 8 noch hinzufügen wg 8 byte alignement +static uint64_t eepromData[(SIZE_OF_DATA_TO_STORE / 8) + 1]; +static uint64_t eepromLogData[(sizeof(log_data_t) / 8) + 1]; +static FLASH_EraseInitTypeDef EraseInitStruct = {0}; + +extern uint16_t savedLockKey; + +static const eeprom_data_t defaultEepromData = +{ + // Schnittstellenparameter + MB_BAUDRATE_DEFAULT, + MB_PARITY_MODE_DEFAULT, + MB_STOPBIT_MODE_DEFAULT, /*uint16_t stopbitmode, reserviert;*/ + MB_SLAVE_ADDRESS_DEFAULT, /*uint16_t slave_adress;*/ + OVP_ALARM_VOLTAGE_DEFAULT, + LVP_ALARM_VOLTAGE_DEFAULT, + OVP_START_VOLTAGE_DEFAULT, + OVP_STOPP_VOLTAGE_DEFAULT, + LVP_START_VOLTAGE_DEFAULT, + LVP_STOPP_VOLTAGE_DEFAULT, + VOLTAGE_SHUTDOWN_START_VOLTAGE_DEFAULT, + VOLTAGE_SHUTDOWN_STOPP_VOLTAGE_DEFAULT, + OVERTEMPPROTECTION_START_DEFAULT, + OVERTEMPPROTECTION_STOP_DEFAULT, + UNDERTEMPPROTECTION_CHARGE_START_DEFAULT, + UNDERTEMPPROTECTION_CHARGE_STOP_DEFAULT, + UNDERTEMPPROTECTION_DISCHARGE_START_DEFAULT, + UNDERTEMPPROTECTION_DISCHARGE_STOP_DEFAULT, + LVP_TIME_DEFAULT, + BAL_VOLTAGE_DEFAULT, + BASIS_TEMP_DEFAULT, + OVP_ALARM_TEMPCO_DEFAULT, + LVP_ALARM_TEMPCO_DEFAULT, + OVP_START_TEMPCO_DEFAULT, + OVP_STOPP_TEMPCO_DEFAULT, + LVP_START_TEMPCO_DEFAULT, + LVP_STOPP_TEMPCO_DEFAULT, + V_SHUTDOWN_START_TEMPCO_DEFAULT, + V_SHUTDOWN_STOPP_TEMPCO_DEFAULT, + BAL_TEMPCO_DEFAULT, + 0, //Lockkey, Default keiner! +}; + +/** + * @brief Gets the page of a given address + * @param Addr: Address of the FLASH Memory + * @retval The page of a given address + */ +static uint32_t GetPage(uint32_t Addr) +{ + return (Addr - FLASH_BASE) / FLASH_PAGE_SIZE; +} + +static HAL_StatusTypeDef getEEPROMData(uint32_t address, uint8_t * data, uint32_t len) +{ + uint32_t i = 0; + uint8_t daten; + if((address + len) > USER_FLASH_END) + { + return HAL_ERROR; + } + for(i = 0; i < len; i ++) + { + data[i] = *((uint8_t *) (address + i)); + } + return HAL_OK; +} + +bool EEPROM_isFirstStart() +{ + + uint8_t firstStartCatcher; + if(getEEPROMData(EEPROM_ADRESS_FIRST_START_ID, (uint8_t *)&firstStartCatcher, 1) != HAL_OK) return HAL_ERROR; + if(firstStartCatcher != FIRST_START_ID) + { + printf ("First start detected\n"); + return true; + + } + else + { + printf ("previous config present\n"); + return false; + } +} + +HAL_StatusTypeDef EEPROM_fullRestore(sys_data_t * data, bool keepSN) +{ + eeprom_stored_data_t * dataToStore; + uint32_t PageError; + uint32_t Address; + uint32_t x; + + printf("EEPROM FULL RESTORE!\n"); + + /****************LESE_DEFAULT_WERTE************************/ + + dataToStore = (eeprom_stored_data_t *) eepromData; + + memcpy( (void *) &dataToStore->changedData, (void*) &defaultEepromData, sizeof(dataToStore->changedData)) ; + + + // Eeprom Status Infos + dataToStore->eepromState.writeCounter ++; + dataToStore->eepromState.structureSize = sizeof(eeprom_stored_data_t); + dataToStore->eepromState.revisionInfo = 0; + dataToStore->eepromState.firstStartId = FIRST_START_ID; + + /****************PAGE_LÖSCHEN********************/ + HAL_FLASH_Unlock(); + + // check for PG bit set if so clear bit + FLASH_WaitForLastOperation(1000); + if(READ_BIT(FLASH->CR, FLASH_CR_PG)) + { + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + } + + /* Fill EraseInit structure*/ + //Speicherung in vorletzter page, deshalb diese löschen. + //Log Daten kommen in die letzte page + EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; + EraseInitStruct.Page = FLASH_PAGE_NB - 2; //GetPage(USER_EEPROM_BASE_ADRESS); + EraseInitStruct.NbPages = 1; + + /* erase Sektoren daten d+rfen nicht im instuction cache liegen */ + if (HAL_FLASHEx_Erase(&EraseInitStruct, &PageError) != HAL_OK) + { + while (1) + { + // ERROR HAL_FLASH_GetError() kann info geben + } + } + + /****************IM_FLASH_SPEICHERN********************/ + + /* programmiere uint64_t */ + Address = USER_EEPROM_BASE_ADRESS; + x = 0; + while (Address < (USER_EEPROM_BASE_ADRESS + SIZE_OF_DATA_TO_STORE)) + { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, Address, eepromData[x]) == HAL_OK) + { + Address = Address + 8; + x ++; + } + else + { + /* Error occurred while writing data in Flash memory. + User can add here some code to deal with this error */ + while (1) + { + // ERROR + } + } + } + + /* Lock the Flash */ + HAL_FLASH_Lock(); + + /****************AUSLESEN_UND_PRÜFEN********************/ + + return EEPROM_readConfig(data); + + +} + + + +HAL_StatusTypeDef EEPROM_storeConfig(sys_data_t * data,bool withSN, bool saveNewKey) +{ + eeprom_stored_data_t * dataToStore; + uint32_t PageError; + uint32_t Address; + uint32_t x; + /****************LESE_WERTE_AUS_SYSDATA*********************/ + printf("EEPROM STORE CONFIG!\n"); + dataToStore = (eeprom_stored_data_t *) eepromData; + + // Schnittstellenparameter + dataToStore->changedData.baudrate = data->s.baudrate; + dataToStore->changedData.parityMode = data->s.parityMode; + dataToStore->changedData.stopBits = data->s.stopBits; + dataToStore->changedData.slaveAddress = data->s.slaveAddress; + + // Cell Parameter + dataToStore->changedData.ovpAlarm = data->s.ovpAlarm; + dataToStore->changedData.lvpAlarm = data->s.lvpAlarm; + dataToStore->changedData.ovpStart = data->s.ovpStart; + dataToStore->changedData.ovpStop = data->s.ovpStop; + dataToStore->changedData.lvpStart = data->s.lvpStart; + dataToStore->changedData.lvpStop = data->s.lvpStop; + dataToStore->changedData.vShutdownStart = data->s.vShutdownStart; + dataToStore->changedData.vShutdownStop = data->s.vShutdownStop; + dataToStore->changedData.otShutdownStart = data->s.otShutdownStart; + dataToStore->changedData.otShutdownStop = data->s.otShutdownStop; + dataToStore->changedData.utpChargeStart = data->s.utpChargeStart; + dataToStore->changedData.utpChargeStop = data->s.utpChargeStop; + dataToStore->changedData.utpDischargeStart = data->s.utpDischargeStart; + dataToStore->changedData.utpDischargeStop = data->s.utpDischargeStop; + dataToStore->changedData.lvpTime = data->s.lvpTime; + dataToStore->changedData.defaultBalVoltage = data->s.defaultBalVoltage; + + // tempco + dataToStore->changedData.refTemp = data->s.refTemp; + dataToStore->changedData.ovpAlarmTempco = data->s.ovpAlarmTempco; + dataToStore->changedData.lvpAlarmTempco = data->s.lvpAlarmTempco; + dataToStore->changedData.ovpStartTempco = data->s.ovpStartTempco; + dataToStore->changedData.ovpStopTempco = data->s.ovpStopTempco; + dataToStore->changedData.lvpStartTempco = data->s.lvpStartTempco; + dataToStore->changedData.lvpStopTempco = data->s.lvpStopTempco; + dataToStore->changedData.vShutdownStartTempco = data->s.vShutdownStartTempco; + dataToStore->changedData.vShutdownStopTempco = data->s.vShutdownStopTempco; + dataToStore->changedData.balancerVoltageTempco = data->s.balancerVoltageTempco; + + if (saveNewKey) + { + dataToStore->changedData.lockKey = data->s.newLockKey; + } + else + { + dataToStore->changedData.lockKey = savedLockKey; + } + + + // Eeprom Status Infos + dataToStore->eepromState.writeCounter ++ ; + dataToStore->eepromState.structureSize = sizeof(eeprom_stored_data_t); + dataToStore->eepromState.revisionInfo = 0; + dataToStore->eepromState.firstStartId = FIRST_START_ID; + + if (withSN) + { + printf("Writing SN!\n"); + dataToStore->deviceInfo.SN = data->s.deviceSn; + } + + /****************PAGE_LÖSCHEN********************/ + HAL_FLASH_Unlock(); + + // check for PG bit set if so clear bit + FLASH_WaitForLastOperation(1000); + if(READ_BIT(FLASH->CR, FLASH_CR_PG)) + { + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + } + + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; + EraseInitStruct.Page = FLASH_PAGE_NB - 2; + EraseInitStruct.NbPages = 1; + + /* erase Sektoren daten dürfen nicht im instuction cache liegen */ + if (HAL_FLASHEx_Erase(&EraseInitStruct, &PageError) != HAL_OK) + { + while (1) + { + // ERROR HAL_FLASH_GetError() kann info geben + } + } + + /****************IM_FLASH_SPEICHERN********************/ + + /* programmiere uint64_t */ + Address = USER_EEPROM_BASE_ADRESS; + x = 0; + while (Address < (USER_EEPROM_BASE_ADRESS + SIZE_OF_DATA_TO_STORE)) + { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, Address, eepromData[x]) == HAL_OK) + { + Address = Address + 8; + x ++; + } + else + { + /* Error occurred while writing data in Flash memory. + User can add here some code to deal with this error */ + while (1) + { + // ERROR + } + } + } + + /* Lock the Flash */ + HAL_FLASH_Lock(); + + /****************AUSLESEN_UND_PRÜFEN********************/ + + return EEPROM_readConfig(data); + + +} + +HAL_StatusTypeDef EEPROM_storeLogData() +{ + + uint32_t PageError; + uint32_t Address; + uint32_t x; + log_data_t * logData; + /****************LESE_WERTE_AUS_SYSDATA*********************/ + printf("EEPROM STORE LOG DATA!\n"); + + //Zeiger auf Resevierten Ram Speicher, der für das speichern der Daten zuständig ist + logData = (log_data_t *) eepromLogData; + logData->cycleCounter = sysData.s.cycleCounter; + logData->maxVoltage = sysData.s.maxVoltage; + logData->minVoltage = sysData.s.minVoltage; + logData->maxTemperature = sysData.s.maxTemperature; + logData->minTemperature = sysData.s.minTemperature; + logData->criticalOvervoltageTime = sysData.s.criticalOverVoltageTime; + logData->criticalUndervoltageTime = sysData.s.criticalUnderVoltageTime; + logData->criticalOverTempTime = sysData.s.criticalOverTempTime; + logData->criticalUnderTempTime = sysData.s.criticalUnderTempTime; + + + /****************PAGE_LÖSCHEN********************/ + HAL_FLASH_Unlock(); + + // check for PG bit set if so clear bit + FLASH_WaitForLastOperation(1000); + if(READ_BIT(FLASH->CR, FLASH_CR_PG)) + { + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + } + + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; + EraseInitStruct.Page = FLASH_PAGE_NB - 1; // Page löschen + EraseInitStruct.NbPages = 1; + + /* erase Sektoren daten dürfen nicht im instuction cache liegen */ + if (HAL_FLASHEx_Erase(&EraseInitStruct, &PageError) != HAL_OK) + { + printf("Error while deleting log data area in flash\n"); + return HAL_ERROR; + } + + /****************IM_FLASH_SPEICHERN********************/ + + /* programmiere uint64_t */ + uint32_t startAdress = USER_EEPROM_BASE_ADRESS + FLASH_PAGE_SIZE; + Address = startAdress; + x = 0; + while (Address < (startAdress + sizeof(log_data_t))) + { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, Address, eepromLogData[x]) == HAL_OK) + { + Address = Address + 8; + x ++; + } + else + { + printf("Error while saving data to flash\n"); + return HAL_ERROR; + } + } + + /* Lock the Flash */ + HAL_FLASH_Lock(); + + return HAL_OK; +} + + +HAL_StatusTypeDef EEPROM_ResetLogData() +{ + + uint32_t PageError; + uint32_t Address; + uint32_t x; + log_data_t * logData; + /****************LESE_WERTE_AUS_SYSDATA*********************/ + printf("EEPROM STORE LOG DATA!\n"); + + //Zeiger auf Resevierten Ram Speicher, der für das speichern der Daten zuständig ist + logData = (log_data_t *) eepromLogData; + logData->cycleCounter = 0; + logData->maxVoltage = 0; + logData->minVoltage = UINT16_MAX; + logData->maxTemperature = INT16_MIN; + logData->minTemperature = INT16_MAX; + logData->criticalOvervoltageTime = 0; + logData->criticalUndervoltageTime = 0; + logData->criticalOverTempTime = 0; + logData->criticalUnderTempTime = 0; + + + /****************PAGE_LÖSCHEN********************/ + HAL_FLASH_Unlock(); + + // check for PG bit set if so clear bit + FLASH_WaitForLastOperation(1000); + if(READ_BIT(FLASH->CR, FLASH_CR_PG)) + { + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + } + + /* Fill EraseInit structure*/ + EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES; + EraseInitStruct.Page = FLASH_PAGE_NB - 1; // Page löschen + EraseInitStruct.NbPages = 1; + + /* erase Sektoren daten dürfen nicht im instuction cache liegen */ + if (HAL_FLASHEx_Erase(&EraseInitStruct, &PageError) != HAL_OK) + { + printf("Error while deleting log data area in flash\n"); + return HAL_ERROR; + } + + /****************IM_FLASH_SPEICHERN********************/ + + /* programmiere uint64_t */ + uint32_t startAdress = USER_EEPROM_BASE_ADRESS + FLASH_PAGE_SIZE; + Address = startAdress; + x = 0; + while (Address < (startAdress + sizeof(log_data_t))) + { + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, Address, eepromLogData[x]) == HAL_OK) + { + Address = Address + 8; + x ++; + } + else + { + printf("Error while saving data to flash\n"); + return HAL_ERROR; + } + } + + /* Lock the Flash */ + HAL_FLASH_Lock(); + + return HAL_OK; +} + + + +HAL_StatusTypeDef EEPROM_readConfig(sys_data_t * data) +{ + eeprom_stored_data_t * dataToStore; + + /****************WERTE_AUS_FLASH_LESEN********************/ + + + if(getEEPROMData(USER_EEPROM_BASE_ADRESS, (uint8_t *)eepromData, sizeof(eepromData)) != HAL_OK) return HAL_ERROR; + + dataToStore = (eeprom_stored_data_t *) eepromData; + + // Schnittstellenparameter + data->s.baudrate = dataToStore->changedData.baudrate; + data->s.parityMode = dataToStore->changedData.parityMode; + data->s.stopBits = dataToStore->changedData.stopBits; + data->s.slaveAddress = dataToStore->changedData.slaveAddress; + + // // Cell Parameter + data->s.ovpAlarm = dataToStore ->changedData.ovpAlarm; + data->s.lvpAlarm = dataToStore ->changedData.lvpAlarm; + data->s.ovpStart = dataToStore ->changedData.ovpStart; + data->s.ovpStop = dataToStore ->changedData.ovpStop; + data->s.lvpStart = dataToStore ->changedData.lvpStart; + data->s.lvpStop = dataToStore ->changedData.lvpStop; + data->s.vShutdownStart = dataToStore->changedData.vShutdownStart; + data->s.vShutdownStop = dataToStore->changedData.vShutdownStop; + data->s.otShutdownStart = dataToStore->changedData.otShutdownStart; + data->s.otShutdownStop = dataToStore->changedData.otShutdownStop; + data->s.utpChargeStart = dataToStore->changedData.utpChargeStart; + data->s.utpChargeStop = dataToStore->changedData.utpChargeStop; + data->s.utpDischargeStart = dataToStore->changedData.utpDischargeStart; + data->s.utpDischargeStop = dataToStore->changedData.utpDischargeStop; + data->s.lvpTime = dataToStore->changedData.lvpTime; + data->s.defaultBalVoltage = dataToStore->changedData.defaultBalVoltage; + + + // tempco + data->s.refTemp = dataToStore ->changedData.refTemp; + data->s.ovpAlarmTempco = dataToStore ->changedData.ovpAlarmTempco; + data->s.lvpAlarmTempco = dataToStore ->changedData.lvpAlarmTempco; + data->s.ovpStartTempco = dataToStore ->changedData.ovpStartTempco; + data->s.ovpStopTempco = dataToStore->changedData.ovpStopTempco; + data->s.lvpStartTempco = dataToStore->changedData.lvpStartTempco; + data->s.lvpStopTempco = dataToStore->changedData.lvpStopTempco; + data->s.vShutdownStartTempco = dataToStore->changedData.vShutdownStartTempco; + data->s.vShutdownStopTempco = dataToStore->changedData.vShutdownStopTempco; + data->s.balancerVoltageTempco = dataToStore->changedData.balancerVoltageTempco; + savedLockKey = dataToStore->changedData.lockKey; + if (savedLockKey != 0) sysData.s.writeLocked = 1 ; + // Geräteinformation + data->s.deviceSn = dataToStore->deviceInfo.SN; + + + // prüfe Eeprom Status Infos + if(dataToStore->eepromState.structureSize != sizeof(eeprom_stored_data_t)) return HAL_ERROR; + if(dataToStore->eepromState.revisionInfo != 0) return HAL_ERROR; + if(dataToStore->eepromState.firstStartId != FIRST_START_ID) return HAL_ERROR; + + return HAL_OK; +} + + + +HAL_StatusTypeDef EEPROM_readLogData() +{ + log_data_t * logData; + + /****************WERTE_AUS_FLASH_LESEN********************/ + + + if(getEEPROMData(USER_EEPROM_BASE_ADRESS + FLASH_PAGE_SIZE, (uint8_t *)eepromLogData, sizeof(eepromLogData)) != HAL_OK) return HAL_ERROR; + + logData = (log_data_t *) eepromLogData; + sysData.s.cycleCounter = logData->cycleCounter; + sysData.s.maxVoltage = logData->maxVoltage; + sysData.s.minVoltage = logData->minVoltage; + sysData.s.maxTemperature = logData->maxVoltage; + sysData.s.minTemperature = logData->minTemperature; + sysData.s.criticalOverVoltageTime = logData->criticalOvervoltageTime; + sysData.s.criticalUnderVoltageTime = logData->criticalUndervoltageTime; + sysData.s.criticalOverTempTime = logData->criticalOverTempTime; + sysData.s.criticalUnderTempTime = logData->criticalUnderTempTime; + + return HAL_OK; +} Index: ecs_cellMon/firmware/src/led.c =================================================================== --- ecs_cellMon/firmware/src/led.c (revision 3) +++ ecs_cellMon/firmware/src/led.c (revision 3) @@ -0,0 +1,192 @@ +/** + ****************************************************************************** + * @file led.c + * @author ECS, Falko Jahn + * @version V1.0.0 + * @date 29-Jan-2021 + * @brief LED Modul + * Beschreibung in Header + ****************************************************************************** + */ + +// --- INCLUDES ---------------------------------------------------------------- +#include "led.h" +#include "main.h" + +//--- GGF. EXTERNE VARIABLEN --------------------------------------------------- + +//--- LOKALE DEFINES - bitte hier dokumentieren -------------------------------- +#define LED_OFF 0 +#define LED_ON (!LED_OFF) +//--- LOKALE TYPE DEFS - bitte hier dokumentieren------------------------------- +typedef struct +{ + uint32_t onTime; + uint32_t offTime; + uint32_t counter; + uint32_t currentState; +} LED_TypeDef; + +//--- DEFINATIONEN GLOBALER VARIABLEN - Bitte in Header dokumentieren ---------- + +//--- LOKALE VARIABLEN - bitte hier dokumentieren ------------------------------ +LED_TypeDef ledError; +LED_TypeDef ledFunction; + +//--- LOKALE FUNKTIONS PROTOTYPEN ---------------------------------------------- + + + +//--- LOKALE FUNKTIONEN - bitte hier dokumentieren ----------------------------- + +//--- GLOBALE FUNKTIONEN - bitte in Header dokumentieren------------------------ +void LED_Init(void) +{ + +} + +void LED_ErrorOn() +{ + HAL_GPIO_WritePin(LED_ERROR_GPIO_Port, LED_ERROR_Pin,GPIO_PIN_SET); + HAL_GPIO_WritePin(BUZZER_GPIO_Port, BUZZER_Pin,GPIO_PIN_SET); + ledError.currentState = LED_ON; + ledError.counter = 0; +} + +void LED_ErrorOff() +{ + HAL_GPIO_WritePin(LED_ERROR_GPIO_Port, LED_ERROR_Pin,GPIO_PIN_RESET); + HAL_GPIO_WritePin(BUZZER_GPIO_Port, BUZZER_Pin,GPIO_PIN_RESET); + ledError.currentState = LED_OFF; + ledError.counter = 0; +} + +void LED_ErrorToggle() +{ + HAL_GPIO_TogglePin(LED_ERROR_GPIO_Port, LED_ERROR_Pin); + HAL_GPIO_TogglePin(BUZZER_GPIO_Port, BUZZER_Pin); + + ledError.currentState = !ledError.currentState; + ledError.counter = 0; +} + + +void LED_ErrorStartBlink(int ontime, int offtime) +{ + ledError.onTime = ontime; + ledError.offTime = offtime; + HAL_GPIO_TogglePin(LED_ERROR_GPIO_Port, LED_ERROR_Pin); + HAL_GPIO_TogglePin(BUZZER_GPIO_Port, BUZZER_Pin); + ledError.currentState = !ledError.currentState; + + if (ledError.currentState == LED_ON) ledError.counter = ontime; + if (ledError.currentState == LED_OFF) ledError.counter = offtime; + +} + +void LED_ErrorExec() +{ + if (ledError.counter > 0) + { + ledError.counter--; + if (ledError.counter == 0) + { + if (ledError.currentState == LED_ON) + { + HAL_GPIO_WritePin(LED_ERROR_GPIO_Port, LED_ERROR_Pin,GPIO_PIN_RESET); + HAL_GPIO_WritePin(BUZZER_GPIO_Port, BUZZER_Pin,GPIO_PIN_RESET); + ledError.currentState = LED_OFF; + ledError.counter = ledError.offTime; + } + else + { + HAL_GPIO_WritePin(LED_ERROR_GPIO_Port, LED_ERROR_Pin,GPIO_PIN_SET); + HAL_GPIO_WritePin(BUZZER_GPIO_Port, BUZZER_Pin,GPIO_PIN_SET); + ledError.currentState = LED_ON; + ledError.counter = ledError.onTime; + } + } + } +} + +// ----- LED FUNCTION ------ + +void LED_FunctionOn() +{ + HAL_GPIO_WritePin(LED_FUNC_GPIO_Port, LED_FUNC_Pin,GPIO_PIN_SET); + ledFunction.currentState = LED_ON; + ledFunction.counter = 0; +} + +void LED_FunctionOff() +{ + HAL_GPIO_WritePin(LED_FUNC_GPIO_Port, LED_FUNC_Pin,GPIO_PIN_RESET); + ledFunction.currentState = LED_OFF; + ledFunction.counter = 0; +} + +void LED_FunctionToggle() +{ + HAL_GPIO_TogglePin(LED_FUNC_GPIO_Port, LED_FUNC_Pin); + ledFunction.currentState = !ledFunction.currentState; + ledFunction.counter = 0; +} + +void LED_FunctionStartBlink(int ontime, int offtime) +{ + ledFunction.onTime = ontime; + ledFunction.offTime = offtime; + HAL_GPIO_TogglePin(LED_FUNC_GPIO_Port, LED_FUNC_Pin); + ledFunction.currentState = !ledFunction.currentState; + + if (ledFunction.currentState == LED_ON) ledFunction.counter = ontime; + if (ledFunction.currentState == LED_OFF) ledFunction.counter = offtime; + +} + +void LED_FunctionSetTimes(int ontime, int offtime) +{ + ledFunction.onTime = ontime; + ledFunction.offTime = offtime; +} + +void LED_FunctionExec() +{ + if (ledFunction.counter > 0) + { + ledFunction.counter--; + if (ledFunction.counter == 0) + { + if (ledFunction.currentState == LED_ON) + { + HAL_GPIO_WritePin(LED_FUNC_GPIO_Port, LED_FUNC_Pin,GPIO_PIN_RESET); + ledFunction.currentState = LED_OFF; + ledFunction.counter = ledFunction.offTime; + } + else + { + HAL_GPIO_WritePin(LED_FUNC_GPIO_Port, LED_FUNC_Pin,GPIO_PIN_SET); + ledFunction.currentState = LED_ON; + ledFunction.counter = ledFunction.onTime; + } + } + } +} + + + +void LED_Test() +{ + LED_ErrorOn(); + HAL_Delay(1000); + LED_ErrorOff(); + HAL_Delay(1000); + +} + +void LED_Exec() +{ + LED_ErrorExec(); + LED_FunctionExec(); +} + Index: ecs_cellMon/firmware/src/meas.c =================================================================== --- ecs_cellMon/firmware/src/meas.c (revision 3) +++ ecs_cellMon/firmware/src/meas.c (revision 3) @@ -0,0 +1,209 @@ +/** + ****************************************************************************** + * @file meas.c + * @author ECS, Falko Jahn + * @version V1.0.0 + * @date 30-Jan-2021 + * @brief Measurement Modul + * Beschreibung in Header + ****************************************************************************** + */ + +// --- INCLUDES ---------------------------------------------------------------- +#include "meas.h" +#include "main.h" +#include "adc.h" +#include "stdio.h" +#include "sysdata.h" +//--- GGF. EXTERNE VARIABLEN --------------------------------------------------- + +//--- LOKALE DEFINES - bitte hier dokumentieren -------------------------------- +#define ADC_CONVERTED_DATA_BUFFER_SIZE 4 +#define VREF 2500 //in mV +#define CELL_VOLTAGE_DIVIDER 2 +#define ADC_RESOLUTION 65536 //16 bit AD Wandler durch Oversampling + +#define CELL_VOLTAGE_FILTER 8 // Filterlängen in 2er-Potenzen --> Compiler optimiert +#define CELL_TEMPERATURE_FILTER 8 +#define BALANCER_CURRENT_FILTER 8 +//--- LOKALE TYPE DEFS - bitte hier dokumentieren------------------------------- + +//--- DEFINATIONEN GLOBALER VARIABLEN - Bitte in Header dokumentieren ---------- + +//--- LOKALE VARIABLEN - bitte hier dokumentieren ------------------------------ +__IO uint16_t aADCxConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE]; /* ADC group regular conversion data (array of data) */ +__IO uint32_t newADCDataFlag; +uint32_t currentOffset; +uint32_t totalMeas; + + +//--- LOKALE FUNKTIONS PROTOTYPEN ---------------------------------------------- +uint32_t calcCellVoltageFiltered(void); +uint32_t calcCellVoltageUnfiltered(void); +int32_t calcCellTemperature(void); +uint32_t calcBalancerCurrent(void); +extern uint32_t initRefresh; + +//--- LOKALE FUNKTIONEN - bitte hier dokumentieren ----------------------------- + + +//--- GLOBALE FUNKTIONEN - bitte in Header dokumentieren------------------------ +void MEAS_Init() +{ + if (HAL_ADCEx_Calibration_Start(&hadc1) != HAL_OK) + { + printf("HAL_ADCEx_Calibration_Start: ERROR\n"); + return; + } + printf("HAL_ADCEx_Calibration_Start: OK\n"); + + if (HAL_ADC_Start_DMA(&hadc1, (uint32_t *)aADCxConvertedData, ADC_CONVERTED_DATA_BUFFER_SIZE ) != HAL_OK) + { + /* ADC conversion start error */ + printf("Error HAL_ADC_Start_DMA\n"); + return; + } + printf("HAL_ADC_Start_DMA: OK\n"); + + //---- Offset calibrierung --- + //Warte bis Mittelwert gebildet + while (totalMeas < 100) + { + MEAS_Exec(); + initRefresh = 1; + } + + currentOffset = calcBalancerCurrent(); + + + +} + +void MEAS_Exec() +{ + if (newADCDataFlag) + { + totalMeas++; + sysData.s.cellVoltage = calcCellVoltageFiltered(); + sysData.s.cellVoltageUnfiltered = calcCellVoltageUnfiltered(); + sysData.s.cellTemperature = calcCellTemperature(); + sysData.s.balancerCurrent = calcBalancerCurrent() - currentOffset; + newADCDataFlag=0; + } + +} + +/** + * @brief Conversion complete callback in non blocking mode + * @param hadc: ADC handle + * @note This example shows a simple way to report end of conversion + * and get conversion result. You can add your own implementation. + * @retval None + */ +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) +{ + newADCDataFlag = 1; +} + + +uint32_t calcCellVoltageFiltered() +{ + static unsigned long avgsum = 0; + + //ADC Wert gefiltert + uint32_t adcValue; + + //Wert umgerechnet in Spannung [mV] + uint32_t u; + + //Filter + avgsum -= avgsum / CELL_VOLTAGE_FILTER; + avgsum += aADCxConvertedData[1];; + adcValue = avgsum / CELL_VOLTAGE_FILTER; + + //Umrechnung in Spannung + u = (adcValue * VREF * CELL_VOLTAGE_DIVIDER) / ADC_RESOLUTION; + + return u; +} + +uint32_t calcCellVoltageUnfiltered() +{ + static unsigned long avgsum = 0; + + //ADC Wert gefiltert + uint32_t adcValue; + + //Wert umgerechnet in Spannung [mV] + uint32_t u; + adcValue = aADCxConvertedData[1];; + + + //Umrechnung in Spannung + u = (adcValue * VREF * CELL_VOLTAGE_DIVIDER) / ADC_RESOLUTION; + + return u; +} + + + +int32_t calcCellTemperature() +{ + static unsigned long avgsum = 0; + + //ADC Wert gefiltert + uint32_t adcValue; + + //Wert umgerechnet in Spannung [mV] + uint32_t u; + + //Wert umgerechnet in [°C ] + int32_t temp; + + //Filter + avgsum -= avgsum / CELL_TEMPERATURE_FILTER; + avgsum += aADCxConvertedData[2]; + adcValue = avgsum / CELL_TEMPERATURE_FILTER; + + //Umrechnung in Spannung + u = (adcValue * VREF ) / ADC_RESOLUTION; + + + //Umrechnung in Grade C + temp = u; + temp = temp - 600; + temp = temp * 100; + temp = temp / 100; //Von Milligrad in Grad * 10 + return temp; +} + +uint32_t calcBalancerCurrent() +{ + static unsigned long avgsum = 0; + + //ADC Wert gefiltert + uint32_t adcValue; + + //Wert umgerechnet in Spannung [mV] + uint32_t u; + + //Wert umgerechnet in mA + int32_t i; + + //Filter + avgsum -= avgsum / BALANCER_CURRENT_FILTER; + avgsum += aADCxConvertedData[0]; + adcValue = avgsum / BALANCER_CURRENT_FILTER; + + //Umrechnung in Spannung + u = (adcValue * VREF ) / ADC_RESOLUTION; + + //Umrechnung in Strom + //u = u / 100; //Verstärkunsfaktor INA180A3 + //i = u / 0.001; Shunt Widerstand + //Die beiden letzten Zeilen wurden zusammengefasst in + i = u * 10; + + return i; + +} Index: ecs_cellMon/firmware/src/modbus.c =================================================================== --- ecs_cellMon/firmware/src/modbus.c (revision 3) +++ ecs_cellMon/firmware/src/modbus.c (revision 3) @@ -0,0 +1,981 @@ +/* + * modbus.c + * + * Created: 03.09.2012 08:39:20 + * Author: Falko + */ + + + +#if MODBUS_SUPPORT == TRUE + + #include "modbus.h" + #include "stm32g0xx_hal.h" + #include "main.h" + #include "stm32g0xx_hal_tim.h" + #include "stm32_hal_legacy.h" + #include "sysdata.h" + #include + // --------------------------------------------------------- + // -------------------- MODUL DEFINES ---------------------- + // --------------------------------------------------------- + + + + + #define MODBUS_BROADCAST_ADDRESS 0x00 + #define FC_READ_COILS 0x01 + #define FC_READ_HOLDING_REGISTERS 0x03 + #define FC_WRITE_SINGLE_REGISTER 0x06 + #define FC_WRITE_MULTIPLE_REGISTER 0x10 + + /* Protocol exceptions */ + #define ILLEGAL_FUNCTION 0x01 + #define ILLEGAL_DATA_ADDRESS 0x02 + #define ILLEGAL_DATA_VALUE 0x03 + #define SLAVE_DEVICE_FAILURE 0x04 + #define SERVER_FAILURE 0x04 + #define ACKNOWLEDGE 0x05 + #define SLAVE_DEVICE_BUSY 0x06 + #define SERVER_BUSY 0x06 + #define NEGATIVE_ACKNOWLEDGE 0x07 + #define MEMORY_PARITY_ERROR 0x08 + #define GATEWAY_PROBLEM_PATH 0x0A + #define GATEWAY_PROBLEM_TARGET 0x0B + + /* Local Error codes */ + #define INVALID_CRC -1 + + // Position der Daten im Rx String + #define OFFSET_SLAVE_ADRESS 0x00 + #define OFFSET_FUNCTION_CODE 0x01 + #define OFFSET_START_ADRESS_HI 0x02 + #define OFFSET_START_ADRESS_LO 0x03 + #define OFFSET_NO_OF_REGISTERS_HI 0x04 + #define OFFSET_NO_OF_REGISTERS_LO 0x05 + + #define MIN_NUMBER_OF_REGISTERS_FC3 0x01 + #define MAX_NUMBER_OF_REGISTERS_FC3 0x7D + #define MIN_NUMBER_OF_REGISTERS_FC16 0x01 + #define MAX_NUMBER_OF_REGISTERS_FC16 0x7B + + #ifdef DEBUG + #define RESPONSE_TIMEOUT 300 // * 1ms + #else + #define RESPONSE_TIMEOUT 1000 // * 1ms + #endif + + // --- Externe Variablen -------------------------------------------- + extern modbus_t modbusData; + + + + // --- Private Funktions Prototypen -------------------------------------------- + + void mbUartInit (modbus_t * mb_data,UART_HandleTypeDef * usart, uint32_t baudrate, uint32_t parityMode, uint32_t stopBits , uint32_t nrOfBitsPerChar); + uint16_t mbCrc16 (uint8_t *buf, uint32_t len); + void mbSend (modbus_t * mb_data ); + uint32_t mbSlaveReadHoldingRegisters (modbus_t * mb_data, uint8_t *msg, uint32_t tx_position, uint8_t deviceID); + uint32_t mbSlaveWriteMultipleRegisters (modbus_t * mb_data, uint8_t *msg, uint32_t tx_position, uint32_t deviceID); + uint32_t mbSlaveWriteSingleRegister (modbus_t * mb_data, uint8_t *msg,uint32_t tx_position, uint32_t deviceID); + uint32_t mbSlaveResponseException (modbus_t * mb_data, uint32_t function_code, uint32_t exception_code,uint32_t tx_position) ; +static HAL_StatusTypeDef RS485_ModbusEx_Init (UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime, uint32_t charReceiveTimeout); +static void UART_TxISR_8BIT (UART_HandleTypeDef *huart); + + // --- GEMEINSAME MODBUS FUNKTIONEN -------------------------------------------- + // Diese Funktionen werden sowohl von Modbus Master als auch Modbus Slave verwendet + + /* + * + * @brief Diese Funktion Initialisert die Modbus Datenstrukturen und die Hardware + * + * Das Modbus Modul benötigt einen UART und einen Timer pro Modbus Anschluss + * Die Funktion erfordert eine vorhandene Callback funktion namens HAL_UART_MspInit + * In dieser muss: + * - Der UART CLK eingeschaltet werden + * - Die Pins initialisert werden (Alternate Port Funktion) + * - Der NVIC Interrupt eingeschaltet werden + * @param mb_data : Datenstruktur zur Aufnahme aller Daten + * @param baudrate : Bautrate + * @param parityMode : Parity, möglich ist UART_PARITY_ODD, UART_PARITY_EVEN, UART_PARITY_NONE. Default ist lt. Modbus Standart EVEN + * @param usart : Timer Modul, z.B. USART1 + * @retval None + */ + void mbInit(modbus_t * mb_data, uint32_t baudrate, uint32_t parityMode, UART_HandleTypeDef * usart, accessMode_t * accessModeTable, uint16_t * currentAccessState ) + { + uint32_t numberOfBitsPerChar; + uint32_t stopBits; + + // Berechne Stop Bits + if ((parityMode== MODBUS_UART_PARITY_EVEN) || (parityMode == MODBUS_UART_PARITY_ODD)) + { + stopBits = 1; + } + else + { + stopBits = 2; + } + + // Berechne Anzahl der Bits per Char + numberOfBitsPerChar = NUMBER_OF_STARTBITS + NUMBER_OF_DATABITS + stopBits; + if ((parityMode == MODBUS_UART_PARITY_EVEN) || (parityMode == MODBUS_UART_PARITY_ODD)) + { + numberOfBitsPerChar +=1; + } + + mbUartInit(mb_data,usart, baudrate, parityMode, stopBits, numberOfBitsPerChar); + + // Datenstrukturen zurücksetzen + mb_data->last_query_function_code = 0; + mb_data->last_query_tcp_id.w = 0; + mb_data->last_query_number_of_register.w = 0; + mb_data->current_query = MB_QUERY_NOTHING; + mb_data->last_query_slave_adress = 0; + mb_data->last_query_start_adress.w = 0; + mb_data->last_query_timeout = false; + + mb_data->accessModeTable = accessModeTable; + mb_data->currentAccessState = currentAccessState; + } + + /* + * + * @brief Diese Funktion Initialisert die Modbus UART Hardware + * + * @param mb_data : Datenstruktur zur Aufnahme aller Daten + * @param usart : UART Modul, z.B. USART1 + * @param baudrate : UART BAUD + * @param parityMmode : Parity, möglich ist: + UART_PARITY_ODD, UART_PARITY_EVEN, UART_PARITY_NONE. + Default ist lt. Modbus Standart EVEN + * @param stopBits : Anzahl der Stop Bits, lt Modbus Standart + * 2 Stop Bits bei Parity None, ansonsten 2 Stop Bits + * @retval None + */ + void mbUartInit(modbus_t * mb_data,UART_HandleTypeDef * usart, uint32_t baudrate, uint32_t parityMode, uint32_t stopBits , uint32_t nrOfBitsPerChar) + { + //--- Uart Init ------------------------------------------------------------ + mb_data->uart = usart; + + // Init aus Cube + //mb_data->uart->Instance = USART3; + //mb_data->uart->Init.BaudRate = 19200; + //mb_data->uart->Init.WordLength = UART_WORDLENGTH_9B; + //mb_data->uart->Init.StopBits = UART_STOPBITS_1; + //mb_data->uart->Init.Parity = UART_PARITY_EVEN; + //mb_data->uart->Init.Mode = UART_MODE_TX_RX; + //mb_data->uart->Init.HwFlowCtl = UART_HWCONTROL_NONE; + //mb_data->uart->Init.OverSampling = UART_OVERSAMPLING_16; + //mb_data->uart->Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + //mb_data->uart->Init.ClockPrescaler = UART_PRESCALER_DIV1; + //mb_data->uart->AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + + // Init Änderungen + + // Baudrate + mb_data->uart->Init.BaudRate = baudrate; + // Parity Mode // Word length + if(parityMode == MODBUS_UART_PARITY_EVEN) + { + mb_data->uart->Init.Parity = UART_PARITY_EVEN; + mb_data->uart->Init.WordLength = UART_WORDLENGTH_9B; + } + else if(parityMode == MODBUS_UART_PARITY_ODD) + { + mb_data->uart->Init.Parity = UART_PARITY_ODD; + mb_data->uart->Init.WordLength = UART_WORDLENGTH_9B; + } + else + { + mb_data->uart->Init.Parity = UART_PARITY_NONE; + mb_data->uart->Init.WordLength = UART_WORDLENGTH_8B; + } + // Stopbits + if (stopBits == 1) + { + mb_data->uart->Init.StopBits = UART_STOPBITS_1; + } + else + { + mb_data->uart->Init.StopBits = UART_STOPBITS_2; + } + // Init + if (RS485_ModbusEx_Init(mb_data->uart, UART_DE_POLARITY_HIGH, 0, 0,TIMEOUT_FRAME_COMPLETE*nrOfBitsPerChar) != HAL_OK) + { + Error_Handler(); + } + //if (HAL_UARTEx_DisableFifoMode(mb_data->uart) != HAL_OK) + //{ + // Error_Handler(); + //} + + if(HAL_UART_Receive_IT(mb_data->uart, mb_data->rx_buffer, RXBUFFERSIZE) != HAL_OK) + { + printf("uart error \n\r"); + while(1) + { + } + } + } + + /* + * + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart: UART handle. + * @retval None + */ + void mbUartEndRxTransfer(UART_HandleTypeDef *huart) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + //CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + //CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + } + + void mbUartRx(modbus_t* mb_data) + { + uint32_t pos; + uint8_t data; + + pos = mb_data->rx_head; + + if (pos >= RXBUFFERSIZE) + { + return; + } + //data = mb_data->uart->Instance->RDR + data = mb_data->uart->Instance->RDR & (uint8_t)0x00FF; //NOTE: mb_data->uart.Instance->DR geändert + mb_data->rx_buffer[pos] = data; + + mb_data->rx_head++; + + //mbTimerStart(mb_data); + } + + HAL_StatusTypeDef mbUartTx(UART_HandleTypeDef *huart) + { + uint16_t* tmp; + + if(huart->Init.WordLength == UART_WORDLENGTH_9B) + { + tmp = (uint16_t*) huart->pTxBuffPtr; + huart->Instance->TDR = (uint16_t)(*tmp & (uint16_t)0x01FF); //NOTE: huart->Instance->DR geändert + + if(huart->Init.Parity == UART_PARITY_NONE) + { + huart->pTxBuffPtr += 2; + } + else + { + huart->pTxBuffPtr += 1; + } + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); //NOTE:huart->Instance->DR geändert + } + + if(--huart->TxXferCount == 0) + { + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + } + return HAL_OK; + } + + // huart->State gibt es nicht mehr. Ersetzt durch huart->gState. + /** + * @brief Wraps up transmission in non blocking mode. + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ + static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) + { + /* Disable the UART Transmit Complete Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); + #else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); + #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + +static HAL_StatusTypeDef RS485_ModbusEx_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime, uint32_t charReceiveTimeout) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + +// EDIT ECS START + /*Set receive timeout time*/ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, charReceiveTimeout); +// EDIT ECS END + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +static int test; +void MODBUS_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr2its = READ_REG(huart->Instance->CR2); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + + /* If some errors occur */ + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + } /* End if some error occurs */ + + + /* UART in mode Receiver (receive Timeout occured)--------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) + && (((cr1its & USART_CR1_RTOIE) != 0U) + || ((cr3its & USART_CR2_RTOEN) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, USART_ICR_RTOCF); + huart->RxState = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + modbusData.mb_rx_frame_complete = 1; + modbusData.setRxLed = true; + + } + + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && (modbusData.rx_head < RXBUFFERSIZE)) //-> empfängt dann ein byte aber das ist nicht wild + { + modbusData.rx_buffer[modbusData.rx_head] = huart->Instance->RDR; + //printf("xx%d: nr:%d %d\n",test ++,modbusData.rx_head, modbusData.rx_buffer[modbusData.rx_head]); + modbusData.rx_head++; + modbusData.setRxLed = true; + } + else + { + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + UART_TxISR_8BIT(modbusData.uart); + modbusData.setTxLed = true; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + modbusData.current_query = MB_QUERY_NOTHING; + UART_EndTransmit_IT(huart); + huart->RxState = HAL_UART_STATE_BUSY_RX; +// /*Reset TX complete interrupt flag*/ +// __HAL_UART_CLEAR_FLAG(huart, USART_ISR_TC); +// /* Disable the UART Transmit Complete Interrupt */ +// CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); +// /*TX complete callback function*/ +// HAL_UART_TxCpltCallback(huart); +// /* Tx process is ended, restore huart->gState to Ready */ +// huart->gState = HAL_UART_STATE_READY; + } + + /* Call UART Error Call back function if need be --------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + huart->RxState = HAL_UART_STATE_BUSY_RX; + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + else if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + modbusData.current_query = MB_QUERY_NOTHING; + UART_EndTransmit_IT(huart); + huart->RxState = HAL_UART_STATE_BUSY_RX; + modbusData.setTxLed = true; + } + } +} + + + + + + + +/** + * @brief TX interrrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } + else + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } +} + + + + + + + + + + + + + /** + * @brief Output Compare callback in non blocking mode + * @param htim : TIM OC handle + * @retval None + */ + void mbTimerIsr(modbus_t * mb_data) + { + /* Capture compare 1 event */ + mb_data->mb_rx_frame_complete=true; + } + + + void mbSend(modbus_t * mb_data ) + { + mb_data->current_query = MB_QUERY_SEND_DATA; + HAL_UART_Transmit_IT(mb_data->uart, mb_data->tx_buffer, mb_data->tx_head); + } + + void mbClearTxBuffer(modbus_t * mb_data) + { + mb_data->tx_head = 0; + } + + + + // Compute the MODBUS RTU CRC + uint16_t mbCrc16 ( uint8_t *buf, uint32_t len) + { + uint16_t crc = 0xFFFF; + + for (uint32_t pos = 0; pos < len; pos++) + { + crc ^= (uint16_t)buf[pos]; // XOR byte into least sig. byte of crc + + for (int i = 8; i != 0; i--) + { // Loop over each bit + if ((crc & 0x0001) != 0) + { // If the LSB is set + crc >>= 1; // Shift right and XOR 0xA001 + crc ^= 0xA001; + } + else // Else LSB is not set + { + crc >>= 1; // Just shift right + } + } + } + + // Note, this number has low and high bytes swapped, so use it accordingly (or swap bytes) + return crc; + } + + /* If CRC is correct returns msg_length else returns INVALID_CRC */ + int mbCheckCrc16( uint8_t *msg, const int msg_length) + { + int ret; + uint16_t crc_calc; + uint16_t crc_received; + + crc_calc = mbCrc16(msg, msg_length - 2); + crc_received = (msg[msg_length - 1] << 8) | msg[msg_length - 2]; + + // Check CRC of msg + if (crc_calc == crc_received) { + ret = msg_length; + } else { + ret = INVALID_CRC; + } + return ret; + } + + uint32_t mbAppendCrc16(uint8_t * buffer, uint32_t tx_position) + { + uint16_t crc = mbCrc16( buffer , tx_position); + + uint8_t l_crc = (uint8_t) (crc & 0x00FF) ; + uint8_t h_crc = (uint8_t) (crc >> 8); + buffer[tx_position] = l_crc; + tx_position++; + buffer[tx_position] = h_crc; + tx_position++; + return tx_position; + } + + /************************************************************************************************************ + Function: mb_get_frame_complete + Purpose: Rückabe ob Frame komplett empfangen wurde + *************************************************************************************************************/ + bool mbGetFrameComplete(modbus_t * mb_data) + { + return mb_data->mb_rx_frame_complete; + } + + void mbClearRxFrame(modbus_t * mb_data) + { + // Wieder bei 0 im buffer anfangen + mb_data->rx_head = 0; + + // keine Daten mehr vorhanden + mb_data->mb_rx_frame_complete=false; + } + + + // --------------------- SLAVE FUNCTIONS --------------------------------------- + +#define SEND_TO_SLAVES_BUFFER_COUNT 1000 +//static TASK_MODBUS_MASTER_Message_t xMessage[255]; +//static TASK_MODBUS_MASTER_Message_t *pxMessage; +static bword_t values[SEND_TO_SLAVES_BUFFER_COUNT]; +static uint32_t y; +static uint32_t z; + + uint32_t mbSlaveCheckModbusRtuQuery(modbus_t * mb_data) + { + uint32_t message_lengh; + uint8_t *modbus_rx_message; + modbus_rx_message = mb_data->rx_buffer; + message_lengh= mb_data->rx_head; + uint32_t slave_adress; + slave_adress = modbus_rx_message[0]; + + if (message_lengh < 5) //Mindestens 5 Zeichen (Slave Adress + Function Code + 2x CRC + { + mbClearRxFrame(mb_data); + printf("->Message to short"); + return 0; + } + + // Prüfe CRC + if (mbCheckCrc16(modbus_rx_message,message_lengh) == INVALID_CRC) + { + printf("->Message with wrong crc"); + mbClearRxFrame(mb_data); + return 0; + } + + if (slave_adress == MODBUS_BROADCAST_ADDRESS) + { + //printf("->Message with broadcast address"); + return RESPOND_TO_QUERY; + } + /* auf richtige Slave Adresse checken ansonsten nicht antworten*/ + else if (slave_adress == sysData.s.slaveAddress) + { + //printf("->Message with correct slave addresse"); + return RESPOND_TO_QUERY; + } + + //printf("->Message with wrong slave address"); + mbClearRxFrame(mb_data); + return 0; + } + + void mbSlaveProcessRtuQuery(modbus_t * mb_data) + { + uint32_t tx_position=0; //die _Nächste_ Position in der Zeichen eingefügt werden müssen + uint8_t *modbus_rx_message; + modbus_rx_message = &mb_data->rx_buffer[0]; + + //Vorbereiten auf neues senden + mbClearTxBuffer(mb_data); + + //mb_data->tx_buffer[0] = sys_data.s.vmGreenview.s.lb_slave_adress; + mb_data->tx_buffer[0] = *modbus_rx_message; + tx_position++; + tx_position = mbSlaveProcessPdu(mb_data , modbus_rx_message,tx_position, *modbus_rx_message); + + tx_position = mbAppendCrc16(mb_data->tx_buffer ,tx_position); + mb_data->tx_head=tx_position; + mbSend(mb_data); + mbClearRxFrame(mb_data); + } + + uint32_t mbSlaveProcessPdu ( modbus_t * mb_data, uint8_t * msg, uint32_t tx_position, uint8_t deviceID) + { + uint32_t function_code; + uint32_t ret; + + function_code = msg[OFFSET_FUNCTION_CODE]; + + switch (function_code) + { + case FC_READ_HOLDING_REGISTERS: + ret= mbSlaveReadHoldingRegisters(mb_data, msg,tx_position, deviceID); + break; + + case FC_WRITE_SINGLE_REGISTER: + ret = mbSlaveWriteSingleRegister(mb_data, msg,tx_position, deviceID); + break; + + case FC_WRITE_MULTIPLE_REGISTER: + ret=mbSlaveWriteMultipleRegisters(mb_data, msg,tx_position, deviceID); + break; + + default: + ret=mbSlaveResponseException(mb_data,function_code,ILLEGAL_FUNCTION,tx_position); + break; + } + + return ret; + } + + + uint32_t mbSlaveReadHoldingRegisters(modbus_t * mb_data, uint8_t *msg, uint32_t tx_position, uint8_t deviceID) + { + uint32_t start_adress; + uint32_t adress; + uint32_t number_of_registers; + + /*stimmt die device ID mit der eigenen überein*/ + if((deviceID != sysData.s.slaveAddress) && (deviceID != 0)) + { + return mbSlaveResponseException(mb_data,FC_WRITE_SINGLE_REGISTER,GATEWAY_PROBLEM_TARGET,tx_position); + } + + start_adress = (msg[OFFSET_START_ADRESS_HI] << 8) + msg[OFFSET_START_ADRESS_LO]; + number_of_registers = ( msg[OFFSET_NO_OF_REGISTERS_HI] << 8) + msg[OFFSET_NO_OF_REGISTERS_LO]; + + if ((number_of_registers < MIN_NUMBER_OF_REGISTERS_FC3) || (number_of_registers > MAX_NUMBER_OF_REGISTERS_FC3) ) + { + return mbSlaveResponseException(mb_data,FC_READ_HOLDING_REGISTERS,ILLEGAL_DATA_VALUE,tx_position); + } + + if (start_adress+number_of_registers-1 > MAX_ADRESS) + { + return mbSlaveResponseException(mb_data, FC_READ_HOLDING_REGISTERS,ILLEGAL_DATA_ADDRESS,tx_position); + } + + mb_data->tx_buffer[tx_position] = FC_READ_HOLDING_REGISTERS; // FUNCTION CODE + tx_position++; + mb_data->tx_buffer[tx_position] = number_of_registers * 2; // Bytes + tx_position++; + + for(adress=start_adress;adress < (start_adress + number_of_registers);adress++) + { + /*Daten aus dem Speicher senden*/ + mb_data->tx_buffer[tx_position] = sysData.mb[adress].b[1]; + tx_position++; + mb_data->tx_buffer[tx_position] = sysData.mb[adress].b[0]; + tx_position++; + } + + return tx_position; + } + + + uint32_t mbSlaveWriteMultipleRegisters(modbus_t * mb_data, uint8_t *msg, uint32_t tx_position, uint32_t deviceID) + { + + uint32_t start_adress; + uint32_t number_of_registers; + uint32_t adress; + uint32_t offset; + + /*stimmt die device ID mit der eigenen überein*/ + if((deviceID != sysData.s.slaveAddress) && (deviceID != 0)) + { + return mbSlaveResponseException(mb_data,FC_WRITE_SINGLE_REGISTER,GATEWAY_PROBLEM_TARGET,tx_position); + } + + start_adress = (msg[OFFSET_START_ADRESS_HI] << 8) + msg[OFFSET_START_ADRESS_LO]; + number_of_registers = ( msg[OFFSET_NO_OF_REGISTERS_HI] << 8) + msg[OFFSET_NO_OF_REGISTERS_LO]; + offset=7; + + if ((number_of_registers < MIN_NUMBER_OF_REGISTERS_FC16) || (number_of_registers > MAX_NUMBER_OF_REGISTERS_FC16) ) + { + return mbSlaveResponseException(mb_data, FC_WRITE_MULTIPLE_REGISTER,ILLEGAL_DATA_VALUE,tx_position); + } + + if (start_adress+number_of_registers-1 > MAX_ADRESS) + { + return mbSlaveResponseException(mb_data, FC_WRITE_MULTIPLE_REGISTER,ILLEGAL_DATA_ADDRESS,tx_position); + } + + /*Daten in Gerätespeicher schreiben*/ + for(adress=start_adress;adress < (start_adress + number_of_registers);adress++) + { + + + //Schreibzugriff prüfen + if (mb_data->accessModeTable[adress] == ACCESS_MODE_READ_ONLY) + { + // Schreibzugriff nicht erlaubt + offset+=2; + continue; + + } + + + //Schreibzugriff prüfen + if ((mb_data->accessModeTable[adress] == ACCESS_MODE_WRITE_PROTECTABLE ) && (*mb_data->currentAccessState == 0)) + { + // Schreibzugriff nicht erlaubt + offset+=2; + continue; + + } + + sysData.mb[adress].b[1] = msg[offset]; + sysData.mb[adress].b[0] = msg[offset+1]; + offset+=2; + } + + mb_data->tx_buffer[tx_position] = FC_WRITE_MULTIPLE_REGISTER; // FUNCTION CODE - 1 byte + tx_position++; + mb_data->tx_buffer[tx_position] = start_adress >> 8; + tx_position++; + mb_data->tx_buffer[tx_position] = (uint8_t ) ( start_adress & 0x00FF); // start adresse 2 byte + tx_position++; + mb_data->tx_buffer[tx_position] = number_of_registers >> 8; + tx_position++; + mb_data->tx_buffer[tx_position] = (uint8_t ) ( number_of_registers & 0x00FF); // Anzahl Register 2 byte + tx_position++; + return tx_position; + } + + + uint32_t mbSlaveWriteSingleRegister(modbus_t * mb_data,uint8_t *msg,uint32_t tx_position, uint32_t deviceID) + { + + uint32_t adress; + + /*stimmt die device ID mit der eigenen überein*/ + if((deviceID != sysData.s.slaveAddress) && (deviceID != 0)) + { + return mbSlaveResponseException(mb_data,FC_WRITE_SINGLE_REGISTER,GATEWAY_PROBLEM_TARGET,tx_position); + } + + adress = (msg[2] << 8) + msg[3]; + + if (adress > MAX_ADRESS) + { + return mbSlaveResponseException(mb_data,FC_WRITE_SINGLE_REGISTER,ILLEGAL_DATA_ADDRESS,tx_position); + } + + //Schreibzugriff prüfen + if (mb_data->accessModeTable[adress] == ACCESS_MODE_READ_ONLY) + { + // Schreibzugriff nicht erlaubt + printf("Error, read only Register!\n"); + return mbSlaveResponseException(mb_data,FC_WRITE_SINGLE_REGISTER,ILLEGAL_DATA_ADDRESS,tx_position); + } + + + //Schreibzugriff prüfen + if ((mb_data->accessModeTable[adress] == ACCESS_MODE_WRITE_PROTECTABLE ) && (*mb_data->currentAccessState == 0)) + { + // Schreibzugriff nicht erlaubt + printf("Protected Register, write not allowed!\n"); + return mbSlaveResponseException(mb_data,FC_WRITE_SINGLE_REGISTER,ILLEGAL_DATA_ADDRESS,tx_position); + } + + + + /*schreibe Daten in eigenen Speicher*/ + sysData.mb[adress].b[1] = msg[4]; + sysData.mb[adress].b[0] = msg[5]; + + mb_data->tx_buffer[tx_position]= FC_WRITE_SINGLE_REGISTER; // FUNCTION CODE + tx_position++; + mb_data->tx_buffer[tx_position]= adress >> 8; + tx_position++; + mb_data->tx_buffer[tx_position]= (uint8_t ) ( adress & 0x00FF); + + tx_position++; + mb_data->tx_buffer[tx_position]= msg[4]; + tx_position++; + mb_data->tx_buffer[tx_position]= msg[5]; + tx_position++; + + return tx_position; + } + + + uint32_t mbSlaveResponseException(modbus_t * mb_data, uint32_t function_code, uint32_t exception_code,uint32_t tx_position ) + { + function_code += 0x80; + mb_data->tx_buffer[tx_position] = function_code; // FUNCTION CODE + tx_position++; + mb_data->tx_buffer[tx_position] = exception_code; // + tx_position++; + return tx_position; + } + + + //---------------------------- UNKNOWN ----------------------------------------- + //- - + //------------------------------------------------------------------------------ + +#endif + Index: ecs_cellMon/firmware/src/output.c =================================================================== --- ecs_cellMon/firmware/src/output.c (revision 3) +++ ecs_cellMon/firmware/src/output.c (revision 3) @@ -0,0 +1,57 @@ +/** + ****************************************************************************** + * @file output.c + * @author ECS, Falko Jahn + * @version V1.0.0 + * @date 29-Jan-2021 + * @brief Output Modul + * Beschreibung in Header + ****************************************************************************** + */ + +// --- INCLUDES ---------------------------------------------------------------- +#include "output.h" +#include "main.h" +//--- GGF. EXTERNE VARIABLEN --------------------------------------------------- + +//--- LOKALE DEFINES - bitte hier dokumentieren -------------------------------- + +//--- LOKALE TYPE DEFS - bitte hier dokumentieren------------------------------- + +//--- DEFINATIONEN GLOBALER VARIABLEN - Bitte in Header dokumentieren ---------- + +//--- LOKALE VARIABLEN - bitte hier dokumentieren ------------------------------ + + +//--- LOKALE FUNKTIONS PROTOTYPEN ---------------------------------------------- + + + +//--- LOKALE FUNKTIONEN - bitte hier dokumentieren ----------------------------- + +//--- GLOBALE FUNKTIONEN - bitte in Header dokumentieren------------------------ +void OUTPUT_Init(void) +{ + +} + +void OUTPUT_OVP_Enable() +{ + HAL_GPIO_WritePin(OVP_GPIO_Port,OVP_Pin,GPIO_PIN_RESET); +} + +void OUTPUT_LVP_Enable() +{ + HAL_GPIO_WritePin(LVP_GPIO_Port,LVP_Pin,GPIO_PIN_RESET); +} + +void OUTPUT_OVP_Disable() +{ + HAL_GPIO_WritePin(OVP_GPIO_Port,OVP_Pin,GPIO_PIN_SET); +} + +void OUTPUT_LVP_Disable() +{ + HAL_GPIO_WritePin(LVP_GPIO_Port,LVP_Pin,GPIO_PIN_SET); +} + Index: ecs_cellMon/firmware/src/sysdata.c =================================================================== --- ecs_cellMon/firmware/src/sysdata.c (revision 3) +++ ecs_cellMon/firmware/src/sysdata.c (revision 3) @@ -0,0 +1,108 @@ +/** + ****************************************************************************** + * @file sysdata.c + * @author ECS, Falko Jahn + * @version V1.0.0 + * @date 30-Jan-2021 + * @brief SYSTEM DATEN Modul + * Beschreibung in Header + ****************************************************************************** + */ + +// --- INCLUDES ---------------------------------------------------------------- +#include "sysdata.h" +#include "modbus.h" + +//--- GGF. EXTERNE VARIABLEN --------------------------------------------------- + +//--- LOKALE DEFINES - bitte hier dokumentieren -------------------------------- + + +//--- LOKALE TYPE DEFS - bitte hier dokumentieren------------------------------- + +//--- DEFINATIONEN GLOBALER VARIABLEN - Bitte in Header dokumentieren ---------- +sys_data_t sysData; + + +//--- LOKALE VARIABLEN - bitte hier dokumentieren ------------------------------ + + +//--- LOKALE FUNKTIONS PROTOTYPEN ---------------------------------------------- + + +//--- LOKALE FUNKTIONEN - bitte hier dokumentieren ----------------------------- + + +//--- GLOBALE FUNKTIONEN - bitte in Header dokumentieren------------------------ + +accessMode_t accessModeTable[MAX_ADRESS+1] = { + ACCESS_MODE_READ_ONLY, //0 DEVICE_TYPE_ID + ACCESS_MODE_READ_ONLY, //1 RESERVIERT + ACCESS_MODE_WRITE_PROTECTABLE, //2 SN1 + ACCESS_MODE_WRITE_PROTECTABLE, //3 SN2 + ACCESS_MODE_READ_ONLY, //4 FW + ACCESS_MODE_READ_ONLY, //5 FW + ACCESS_MODE_READ_ONLY, //6 FW + ACCESS_MODE_READ_ONLY, //7 RESERVIERT + ACCESS_MODE_WRITE_PROTECTABLE, //8 BAUDRATE + ACCESS_MODE_WRITE_PROTECTABLE, //9 BAUDRATE + ACCESS_MODE_WRITE_PROTECTABLE, //10 PARITY MODE + ACCESS_MODE_WRITE_PROTECTABLE, //11 STOPP_BITS + ACCESS_MODE_READ_WRITE, //12 SLAVE_ADRESS + ACCESS_MODE_READ_WRITE, //13 CMD + ACCESS_MODE_READ_ONLY, //14 RESERVED + ACCESS_MODE_READ_ONLY, //15 RESERVED + ACCESS_MODE_READ_ONLY, //16 RESERVED + ACCESS_MODE_READ_ONLY, //17 RESERVED + ACCESS_MODE_READ_ONLY, //18 RESERVED + ACCESS_MODE_READ_ONLY, //19 RESERVED + ACCESS_MODE_WRITE_PROTECTABLE, //20 OVP ALARM + ACCESS_MODE_WRITE_PROTECTABLE, //21 LVP ALARM + ACCESS_MODE_WRITE_PROTECTABLE, //22 OVP START + ACCESS_MODE_WRITE_PROTECTABLE, //23 OVP STOP + ACCESS_MODE_WRITE_PROTECTABLE, //24 LVP START + ACCESS_MODE_WRITE_PROTECTABLE, //25 LVP STOP + ACCESS_MODE_WRITE_PROTECTABLE, //26 V SHUTDOWN START + ACCESS_MODE_WRITE_PROTECTABLE, //27 V SHUTDOWN STOP + ACCESS_MODE_WRITE_PROTECTABLE, //28 OT SHUTDOWN START + ACCESS_MODE_WRITE_PROTECTABLE, //29 OT SHUTDOWN STOP + ACCESS_MODE_WRITE_PROTECTABLE, //30 UTP CHARGE VSHUTDOWN START + ACCESS_MODE_WRITE_PROTECTABLE, //31 UTP CHARGE SHUTDOWN STOP + ACCESS_MODE_WRITE_PROTECTABLE, //32 UTP LOAD VSHUTDOWN START + ACCESS_MODE_WRITE_PROTECTABLE, //33 UTP LOAD SHUTDOWN STOP + ACCESS_MODE_WRITE_PROTECTABLE, //34 LVP TIME + ACCESS_MODE_WRITE_PROTECTABLE, //35 DEFAULT BAL VOLTAGE + ACCESS_MODE_WRITE_PROTECTABLE, //36 REF TEMP + ACCESS_MODE_WRITE_PROTECTABLE, //37 OVP ALARM TEMPCO + ACCESS_MODE_WRITE_PROTECTABLE, //38 LVP ALARM TEMPCO + ACCESS_MODE_WRITE_PROTECTABLE, //39 OVP START TEMPCO + ACCESS_MODE_WRITE_PROTECTABLE, //40 OVP STOPP TEMPCO + ACCESS_MODE_WRITE_PROTECTABLE, //41 LVP START TEMPCO + ACCESS_MODE_WRITE_PROTECTABLE, //42 LVP START TEMPCO + ACCESS_MODE_WRITE_PROTECTABLE, //43 V SHUTDOWN START TEMPCO + ACCESS_MODE_WRITE_PROTECTABLE, //44 V SHUTDOWN STOP TEMPCO + ACCESS_MODE_WRITE_PROTECTABLE, //45 BALANCER VOLTAGE TEMPCO + ACCESS_MODE_READ_WRITE, //46 Balancer voltage remote + ACCESS_MODE_READ_ONLY, //47 WRITE LOCKED + ACCESS_MODE_READ_ONLY, //48 KEY ACCEPTED + ACCESS_MODE_READ_WRITE, //49 LOCK KEY + ACCESS_MODE_WRITE_PROTECTABLE, //50 NEW LOCK KEY + + //Alle anderen sind 0 , also automatisch auf read only +}; + + + + +void SYSDATA_Init() +{ + sysData.s.deviceTypeId = 103; //100: LiPro 1-x, 101: LiPro1-x active , 102 ist LiPro 1-x V2 + sysData.s.fwMajor = 1; + sysData.s.fwMinor = 0; + sysData.s.fwRevision = 2; + sysData.s.minVoltage = MIN_VOLTAGE_DEFAULT; + sysData.s.maxVoltage = MAX_VOLTAGE_DEFAULT; + sysData.s.minTemperature = MIN_TEMPERATURE_DEFAULT; + sysData.s.maxTemperature = MAX_TEMPERATURE_DEFAULT; + +} Index: ecs_cellMon/firmware/src/template.c =================================================================== --- ecs_cellMon/firmware/src/template.c (revision 3) +++ ecs_cellMon/firmware/src/template.c (revision 3) @@ -0,0 +1,39 @@ +/** + ****************************************************************************** + * @file template.c + * @author ECS, + * @version V1.0.0 + * @date 09-Sep-2015 + * @brief BEISPIEL Modul + * Beschreibung in Header + ****************************************************************************** + */ + +// --- INCLUDES ---------------------------------------------------------------- +#include "template.h" + +//--- GGF. EXTERNE VARIABLEN --------------------------------------------------- + +//--- LOKALE DEFINES - bitte hier dokumentieren -------------------------------- + +//--- LOKALE TYPE DEFS - bitte hier dokumentieren------------------------------- + +//--- DEFINATIONEN GLOBALER VARIABLEN - Bitte in Header dokumentieren ---------- + +//--- LOKALE VARIABLEN - bitte hier dokumentieren ------------------------------ + + +//--- LOKALE FUNKTIONS PROTOTYPEN ---------------------------------------------- +void TEMPLATE_MachWas(void); + + +//--- LOKALE FUNKTIONEN - bitte hier dokumentieren ----------------------------- +void TEMPLATE_MachWas() +{ +} + +//--- GLOBALE FUNKTIONEN - bitte in Header dokumentieren------------------------ +void TEMPLATE_Init(void) +{ + +} Index: ecs_cellMon/firmware/start.s =================================================================== --- ecs_cellMon/firmware/start.s (revision 3) +++ ecs_cellMon/firmware/start.s (revision 3) @@ -0,0 +1,60 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* The Embedded Experts * +********************************************************************** +* * +* (c) 2014 - 2020 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +* * +* All rights reserved. * +* * +* Redistribution and use in source and binary forms, with or * +* without modification, are permitted provided that the following * +* condition is met: * +* * +* - Redistributions of source code must retain the above copyright * +* notice, this condition and the following disclaimer. * +* * +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * +* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * +* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * +* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * +* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * +* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * +* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * +* DAMAGE. * +* * +*********************************************************************/ + +/********************************************************************* +* +* _start +* +* Function description +* Defines entry point for an STM32G0xx assembly code only +* application. +* +* Additional information +* Please note, as this is an assembly code only project, the C/C++ +* runtime library has not been initialised. So do not attempt to call +* any C/C++ library functions because they probably won't work. +*/ + + .syntax unified + .global _start + .text + + .thumb_func +_start: + ldr r0, =#0x12345678 +loop: + adds r0, r0, #1 + b loop Index: ecs_cellMon/firmware/startup/startup_stm32g071xx.s =================================================================== --- ecs_cellMon/firmware/startup/startup_stm32g071xx.s (revision 3) +++ ecs_cellMon/firmware/startup/startup_stm32g071xx.s (revision 3) @@ -0,0 +1,298 @@ +/** + ****************************************************************************** + * @file startup_stm32g071xx.s + * @author MCD Application Team + * @brief STM32G071xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. All rights reserved. + * + * This software component is licensed by ST under Apache License, Version 2.0, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/Apache-2.0 + * + ****************************************************************************** + */ + +.syntax unified +.cpu cortex-m0plus +.fpu softvfp +.thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application s entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word UCPD1_2_IRQHandler /* UCPD1, UCPD2 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */ + .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC and LPTIM1 */ + .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_4_LPUART1_IRQHandler /* USART3, USART4 and LPUART1 */ + .word CEC_IRQHandler /* CEC */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_TAMP_IRQHandler + .thumb_set RTC_TAMP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak UCPD1_2_IRQHandler + .thumb_set UCPD1_2_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler + .thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_LPTIM1_IRQHandler + .thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler + + .weak TIM7_LPTIM2_IRQHandler + .thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_4_LPUART1_IRQHandler + .thumb_set USART3_4_LPUART1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + Index: ecs_cellMon/jlink/bootloader.jflash =================================================================== --- ecs_cellMon/jlink/bootloader.jflash (revision 3) +++ ecs_cellMon/jlink/bootloader.jflash (revision 3) @@ -0,0 +1,85 @@ + AppVersion = 64206 + FileVersion = 2 +[GENERAL] + ConnectMode = 0 + CurrentFile = "D:\projekte\ecs_lipro\branches\lipro1-6_v2\Bootloader\SES\Output\Release\Exe\bootloader.hex" + DataFileSAddr = 0x08003000 + GUIMode = 0 + HostName = "" + TargetIF = 1 + USBPort = 0 + USBSerialNo = 0x00000000 +[JTAG] + IRLen = 0 + MultipleTargets = 0 + NumDevices = 0 + Speed0 = 4000 + Speed1 = 4000 + TAP_Number = 0 + UseAdaptive0 = 0 + UseAdaptive1 = 0 + UseMaxSpeed0 = 0 + UseMaxSpeed1 = 0 +[CPU] + NumInitSteps = 1 + InitStep0_Action = "Reset" + InitStep0_Value0 = 0x00000000 + InitStep0_Value1 = 0x00000000 + InitStep0_Comment = "Reset and halt target" + NumExitSteps = 0 + UseScriptFile = 0 + ScriptFile = "" + UseRAM = 1 + RAMAddr = 0x20000000 + RAMSize = 0x00008000 + CheckCoreID = 1 + CoreID = 0x0BC11477 + CoreIDMask = 0x0F000FFF + UseAutoSpeed = 0x00000001 + ClockSpeed = 0x00000000 + EndianMode = 0 + ChipName = "ST STM32G071CB" +[FLASH] + NumBanks = 2 +[FLASH0] + aRangeSel[1] = 0-63 + BankName = "Internal program flash" + BankSelMode = 1 + BaseAddr = 0x08000000 +[FLASH1] + aRangeSel[1] = 0-1 + BankName = "Option bytes" + BankSelMode = 1 + BaseAddr = 0x1FFF7800 +[PRODUCTION] + AutoPerformsErase = 1 + AutoPerformsProgram = 1 + AutoPerformsSecure = 0 + AutoPerformsStartApp = 0 + AutoPerformsUnsecure = 0 + AutoPerformsVerify = 1 + EnableFixedVTref = 0 + EnableTargetPower = 0 + EraseType = 1 + FixedVTref = 0x00000CE4 + MonitorVTref = 0 + MonitorVTrefMax = 0x0000157C + MonitorVTrefMin = 0x000003E8 + OverrideTimeouts = 0 + ProgramSN = 0 + SerialFile = "" + SNAddr = 0x00000000 + SNInc = 0x00000001 + SNLen = 0x00000004 + SNListFile = "" + SNValue = 0x00000001 + StartAppType = 0 + TargetPowerDelay = 0x00000014 + TimeoutErase = 0x00003A98 + TimeoutProgram = 0x00002710 + TimeoutVerify = 0x00002710 + VerifyType = 1 +[PERFORMANCE] + DisableSkipBlankDataOnProgram = 0x00000000 + PerfromBlankCheckPriorEraseChip = 0x00000001 + PerfromBlankCheckPriorEraseSelectedSectors = 0x00000001 Index: ecs_cellMon/jlink/main.jflash =================================================================== --- ecs_cellMon/jlink/main.jflash (revision 3) +++ ecs_cellMon/jlink/main.jflash (revision 3) @@ -0,0 +1,85 @@ + AppVersion = 64206 + FileVersion = 2 +[GENERAL] + ConnectMode = 0 + CurrentFile = "D:\projekte\ecs_lipro\branches\lipro1-6_v2\firmware\Output\Release\Exe\lipro1_6_v2_main.bin" + DataFileSAddr = 0x08003000 + GUIMode = 0 + HostName = "" + TargetIF = 1 + USBPort = 0 + USBSerialNo = 0x00000000 +[JTAG] + IRLen = 0 + MultipleTargets = 0 + NumDevices = 0 + Speed0 = 4000 + Speed1 = 4000 + TAP_Number = 0 + UseAdaptive0 = 0 + UseAdaptive1 = 0 + UseMaxSpeed0 = 0 + UseMaxSpeed1 = 0 +[CPU] + NumInitSteps = 1 + InitStep0_Action = "Reset" + InitStep0_Value0 = 0x00000000 + InitStep0_Value1 = 0x00000000 + InitStep0_Comment = "Reset and halt target" + NumExitSteps = 0 + UseScriptFile = 0 + ScriptFile = "" + UseRAM = 1 + RAMAddr = 0x20000000 + RAMSize = 0x00008000 + CheckCoreID = 1 + CoreID = 0x0BC11477 + CoreIDMask = 0x0F000FFF + UseAutoSpeed = 0x00000001 + ClockSpeed = 0x00000000 + EndianMode = 0 + ChipName = "ST STM32G071CB" +[FLASH] + NumBanks = 2 +[FLASH0] + aRangeSel[1] = 0-63 + BankName = "Internal program flash" + BankSelMode = 1 + BaseAddr = 0x08000000 +[FLASH1] + aRangeSel[1] = 0-1 + BankName = "Option bytes" + BankSelMode = 1 + BaseAddr = 0x1FFF7800 +[PRODUCTION] + AutoPerformsErase = 1 + AutoPerformsProgram = 1 + AutoPerformsSecure = 0 + AutoPerformsStartApp = 0 + AutoPerformsUnsecure = 0 + AutoPerformsVerify = 1 + EnableFixedVTref = 0 + EnableTargetPower = 0 + EraseType = 1 + FixedVTref = 0x00000CE4 + MonitorVTref = 0 + MonitorVTrefMax = 0x0000157C + MonitorVTrefMin = 0x000003E8 + OverrideTimeouts = 0 + ProgramSN = 0 + SerialFile = "" + SNAddr = 0x00000000 + SNInc = 0x00000001 + SNLen = 0x00000004 + SNListFile = "" + SNValue = 0x00000001 + StartAppType = 0 + TargetPowerDelay = 0x00000014 + TimeoutErase = 0x00003A98 + TimeoutProgram = 0x00002710 + TimeoutVerify = 0x00002710 + VerifyType = 1 +[PERFORMANCE] + DisableSkipBlankDataOnProgram = 0x00000000 + PerfromBlankCheckPriorEraseChip = 0x00000001 + PerfromBlankCheckPriorEraseSelectedSectors = 0x00000001 Index: ecs_cellMon/tools/FileEncrypt/.cproject =================================================================== --- ecs_cellMon/tools/FileEncrypt/.cproject (revision 3) +++ ecs_cellMon/tools/FileEncrypt/.cproject (revision 3) @@ -0,0 +1,109 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: ecs_cellMon/tools/FileEncrypt/.project =================================================================== --- ecs_cellMon/tools/FileEncrypt/.project (revision 3) +++ ecs_cellMon/tools/FileEncrypt/.project (revision 3) @@ -0,0 +1,26 @@ + + + FileEncrypt + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + Index: ecs_cellMon/tools/FileEncrypt/.settings/language.settings.xml =================================================================== --- ecs_cellMon/tools/FileEncrypt/.settings/language.settings.xml (revision 3) +++ ecs_cellMon/tools/FileEncrypt/.settings/language.settings.xml (revision 3) @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + Index: ecs_cellMon/tools/FileEncrypt/.settings/org.eclipse.cdt.managedbuilder.core.prefs =================================================================== --- ecs_cellMon/tools/FileEncrypt/.settings/org.eclipse.cdt.managedbuilder.core.prefs (revision 3) +++ ecs_cellMon/tools/FileEncrypt/.settings/org.eclipse.cdt.managedbuilder.core.prefs (revision 3) @@ -0,0 +1,11 @@ +eclipse.preferences.version=1 +environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.1883486453/CPATH/delimiter=; +environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.1883486453/CPATH/operation=remove +environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.1883486453/C_INCLUDE_PATH/delimiter=; +environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.1883486453/C_INCLUDE_PATH/operation=remove +environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.1883486453/append=true +environment/buildEnvironmentInclude/cdt.managedbuild.config.gnu.mingw.exe.debug.1883486453/appendContributed=true +environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.1883486453/LIBRARY_PATH/delimiter=; +environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.1883486453/LIBRARY_PATH/operation=remove +environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.1883486453/append=true +environment/buildEnvironmentLibrary/cdt.managedbuild.config.gnu.mingw.exe.debug.1883486453/appendContributed=true Index: ecs_cellMon/tools/FileEncrypt/Debug/FileEncrypt.bat =================================================================== --- ecs_cellMon/tools/FileEncrypt/Debug/FileEncrypt.bat (revision 3) +++ ecs_cellMon/tools/FileEncrypt/Debug/FileEncrypt.bat (revision 3) @@ -0,0 +1,2 @@ +%2 -open%1 -saveas%~dpn1.bin -hide -exit +%~dp0FileEncrypt.exe %~dpn1.bin Index: ecs_cellMon/tools/FileEncrypt/src/Makefile =================================================================== --- ecs_cellMon/tools/FileEncrypt/src/Makefile (revision 3) +++ ecs_cellMon/tools/FileEncrypt/src/Makefile (revision 3) @@ -0,0 +1,40 @@ +#CC = avr-gcc +#CFLAGS = -Wall -mmcu=atmega16 -Os -Wl,-Map,test.map +#OBJCOPY = avr-objcopy +CC = gcc +CFLAGS = -Wall -Os -Wl,-Map,test.map +OBJCOPY = objcopy + +# include path to AVR library +INCLUDE_PATH = /usr/lib/avr/include +# splint static check +SPLINT = splint test.c aes.c -I$(INCLUDE_PATH) +charindex -unrecog + +.SILENT: +.PHONY: lint clean + + +rom.hex : test.out + # copy object-code to new image and format in hex + $(OBJCOPY) -j .text -O ihex test.out rom.hex + +test.o : test.c + # compiling test.c + $(CC) $(CFLAGS) -c test.c -o test.o + +aes.o : aes.h aes.c + # compiling aes.c + $(CC) $(CFLAGS) -c aes.c -o aes.o + +test.out : aes.o test.o + # linking object code to binary + $(CC) $(CFLAGS) aes.o test.o -o test.out + +small: test.out + $(OBJCOPY) -j .text -O ihex test.out rom.hex + +clean: + rm -f *.OBJ *.LST *.o *.gch *.out *.hex *.map + +lint: + $(call SPLINT) Index: ecs_cellMon/tools/FileEncrypt/src/README.md =================================================================== --- ecs_cellMon/tools/FileEncrypt/src/README.md (revision 3) +++ ecs_cellMon/tools/FileEncrypt/src/README.md (revision 3) @@ -0,0 +1,65 @@ +### Tiny AES128 in C + +This is a small and portable implementation of the AES128 ECB and CBC encryption algorithms written in C. + +The API is very simple and looks like this (I am using C99 ``-style annotated types): + +```C +void AES128_ECB_encrypt(uint8_t* input, const uint8_t* key, uint8_t* output); +void AES128_ECB_decrypt(uint8_t* input, const uint8_t* key, uint8_t* output); +void AES128_CBC_encrypt_buffer(uint8_t* output, uint8_t* input, uint32_t length, const uint8_t* key, const uint8_t* iv); +void AES128_CBC_decrypt_buffer(uint8_t* output, uint8_t* input, uint32_t length, const uint8_t* key, const uint8_t* iv); +``` + +You can choose to use one or both of the modes-of-operation, by defining the symbols CBC and ECB. See the header file for clarification. + +There is no built-in error checking or protection from out-of-bounds memory access errors as a result of malicious input. The two functions AES128_ECB_xxcrypt() do most of the work, and they expect inputs of 128 bit length. + +The module uses around 200 bytes of RAM and 2.5K ROM when compiled for ARM (~2K for Thumb but YMMV). + +It is one of the smallest implementation in C I've seen yet, but do contact me if you know of something smaller (or have improvements to the code here). + +I've successfully used the code on 64bit x86, 32bit ARM and 8 bit AVR platforms. + + +GCC size output when ECB mode is compiled for ARM: + + + + $ arm-none-eabi-gcc -Os -c aes.c -DCBC=0 + $ size aes.o + text data bss dec hex filename + 2323 0 184 2507 9cb aes.o + + + + +.. and when compiling for the THUMB instruction set, we end up around 2K in code size. + + $ arm-none-eabi-gcc -mthumb -Os -c aes.c -DCBC=0 + $ size aes.o + text data bss dec hex filename + 1775 0 184 1959 7a7 aes.o + + + +I am using Mentor Graphics free ARM toolchain: + + + $ arm-none-eabi-gcc --version + arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.8.4 20140526 (release) [ARM/embedded-4_8-branch revision 211358] + Copyright (C) 2013 Free Software Foundation, Inc. + This is free software; see the source for copying conditions. There is NO + warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + + + + +This implementation is verified against the data in: + +[National Institute of Standards and Technology Special Publication 800-38A 2001 ED](http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf) Appendix F: Example Vectors for Modes of Operation of the AES. + + +All material in this repository is in the public domain. + +I am a bit slow to react to pull requests and issues, but I have an ambition to go through all issues sometime in the future and release a stable version. Index: ecs_cellMon/tools/FileEncrypt/src/aes.c =================================================================== --- ecs_cellMon/tools/FileEncrypt/src/aes.c (revision 3) +++ ecs_cellMon/tools/FileEncrypt/src/aes.c (revision 3) @@ -0,0 +1,592 @@ +/* + +This is an implementation of the AES128 algorithm, specifically ECB and CBC mode. + +The implementation is verified against the test vectors in: + National Institute of Standards and Technology Special Publication 800-38A 2001 ED + +ECB-AES128 +---------- + + plain-text: + 6bc1bee22e409f96e93d7e117393172a + ae2d8a571e03ac9c9eb76fac45af8e51 + 30c81c46a35ce411e5fbc1191a0a52ef + f69f2445df4f9b17ad2b417be66c3710 + + key: + 2b7e151628aed2a6abf7158809cf4f3c + + resulting cipher + 3ad77bb40d7a3660a89ecaf32466ef97 + f5d3d58503b9699de785895a96fdbaaf + 43b1cd7f598ece23881b00e3ed030688 + 7b0c785e27e8ad3f8223207104725dd4 + + +NOTE: String length must be evenly divisible by 16byte (str_len % 16 == 0) + You should pad the end of the string with zeros if this is not the case. + +*/ + + +/*****************************************************************************/ +/* Includes: */ +/*****************************************************************************/ +#include +#include // CBC mode, for memset +#include "aes.h" +#include + + +/*****************************************************************************/ +/* Defines: */ +/*****************************************************************************/ +// The number of columns comprising a state in AES. This is a constant in AES. Value=4 +#define Nb 4 +// The number of 32 bit words in a key. +#define Nk 4 +// Key length in bytes [128 bit] +#define KEYLEN 16 +// The number of rounds in AES Cipher. +#define Nr 10 + +// jcallan@github points out that declaring Multiply as a function +// reduces code size considerably with the Keil ARM compiler. +// See this link for more information: https://github.com/kokke/tiny-AES128-C/pull/3 +#ifndef MULTIPLY_AS_A_FUNCTION + #define MULTIPLY_AS_A_FUNCTION 0 +#endif + + +/*****************************************************************************/ +/* Private variables: */ +/*****************************************************************************/ +// state - array holding the intermediate results during decryption. +typedef uint8_t state_t[4][4]; +static state_t* state; + +// The array that stores the round keys. +static uint8_t RoundKey[176]; + +// The Key input to the AES Program +static const uint8_t* Key; + +#if defined(CBC) && CBC + // Initial Vector used only for CBC mode + static uint8_t* Iv; +#endif + +// The lookup-tables are marked const so they can be placed in read-only storage instead of RAM +// The numbers below can be computed dynamically trading ROM for RAM - +// This can be useful in (embedded) bootloader applications, where ROM is often limited. +static const uint8_t sbox[256] = { + //0 1 2 3 4 5 6 7 8 9 A B C D E F + 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, + 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, + 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, + 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, + 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, + 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, + 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, + 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, + 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, + 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, + 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, + 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, + 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, + 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, + 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, + 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 }; + +static const uint8_t rsbox[256] = +{ 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, + 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, + 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, + 0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, + 0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, + 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, + 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, + 0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, + 0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, + 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, + 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, + 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, + 0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, + 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, + 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, + 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d }; + + +// The round constant word array, Rcon[i], contains the values given by +// x to th e power (i-1) being powers of x (x is denoted as {02}) in the field GF(2^8) +// Note that i starts at 1, not 0). +static const uint8_t Rcon[255] = { + 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, + 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, + 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, + 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, + 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, + 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, + 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, + 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, + 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, + 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, + 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, 0xc6, 0x97, 0x35, + 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, 0x61, 0xc2, 0x9f, + 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb, 0x8d, 0x01, 0x02, 0x04, + 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36, 0x6c, 0xd8, 0xab, 0x4d, 0x9a, 0x2f, 0x5e, 0xbc, 0x63, + 0xc6, 0x97, 0x35, 0x6a, 0xd4, 0xb3, 0x7d, 0xfa, 0xef, 0xc5, 0x91, 0x39, 0x72, 0xe4, 0xd3, 0xbd, + 0x61, 0xc2, 0x9f, 0x25, 0x4a, 0x94, 0x33, 0x66, 0xcc, 0x83, 0x1d, 0x3a, 0x74, 0xe8, 0xcb }; + + +/*****************************************************************************/ +/* Private functions: */ +/*****************************************************************************/ +static uint8_t getSBoxValue(uint8_t num) +{ + return sbox[num]; +} + +static uint8_t getSBoxInvert(uint8_t num) +{ + return rsbox[num]; +} + +// This function produces Nb(Nr+1) round keys. The round keys are used in each round to decrypt the states. +static void KeyExpansion(void) +{ + uint32_t i, j, k; + uint8_t tempa[4]; // Used for the column/row operations + + // The first round key is the key itself. + for(i = 0; i < Nk; ++i) + { + RoundKey[(i * 4) + 0] = Key[(i * 4) + 0]; + RoundKey[(i * 4) + 1] = Key[(i * 4) + 1]; + RoundKey[(i * 4) + 2] = Key[(i * 4) + 2]; + RoundKey[(i * 4) + 3] = Key[(i * 4) + 3]; + } + + // All other round keys are found from the previous round keys. + for(; (i < (Nb * (Nr + 1))); ++i) + { + for(j = 0; j < 4; ++j) + { + tempa[j]=RoundKey[(i-1) * 4 + j]; + } + if (i % Nk == 0) + { + // This function rotates the 4 bytes in a word to the left once. + // [a0,a1,a2,a3] becomes [a1,a2,a3,a0] + + // Function RotWord() + { + k = tempa[0]; + tempa[0] = tempa[1]; + tempa[1] = tempa[2]; + tempa[2] = tempa[3]; + tempa[3] = k; + } + + // SubWord() is a function that takes a four-byte input word and + // applies the S-box to each of the four bytes to produce an output word. + + // Function Subword() + { + tempa[0] = getSBoxValue(tempa[0]); + tempa[1] = getSBoxValue(tempa[1]); + tempa[2] = getSBoxValue(tempa[2]); + tempa[3] = getSBoxValue(tempa[3]); + } + + tempa[0] = tempa[0] ^ Rcon[i/Nk]; + } + else if (Nk > 6 && i % Nk == 4) + { + // Function Subword() + { + tempa[0] = getSBoxValue(tempa[0]); + tempa[1] = getSBoxValue(tempa[1]); + tempa[2] = getSBoxValue(tempa[2]); + tempa[3] = getSBoxValue(tempa[3]); + } + } + RoundKey[i * 4 + 0] = RoundKey[(i - Nk) * 4 + 0] ^ tempa[0]; + RoundKey[i * 4 + 1] = RoundKey[(i - Nk) * 4 + 1] ^ tempa[1]; + RoundKey[i * 4 + 2] = RoundKey[(i - Nk) * 4 + 2] ^ tempa[2]; + RoundKey[i * 4 + 3] = RoundKey[(i - Nk) * 4 + 3] ^ tempa[3]; + } +} + +// This function adds the round key to state. +// The round key is added to the state by an XOR function. +static void AddRoundKey(uint8_t round) +{ + uint8_t i,j; + for(i=0;i<4;++i) + { + for(j = 0; j < 4; ++j) + { + (*state)[i][j] ^= RoundKey[round * Nb * 4 + i * Nb + j]; + } + } +} + +// The SubBytes Function Substitutes the values in the +// state matrix with values in an S-box. +static void SubBytes(void) +{ + uint8_t i, j; + for(i = 0; i < 4; ++i) + { + for(j = 0; j < 4; ++j) + { + (*state)[j][i] = getSBoxValue((*state)[j][i]); + } + } +} + +// The ShiftRows() function shifts the rows in the state to the left. +// Each row is shifted with different offset. +// Offset = Row number. So the first row is not shifted. +static void ShiftRows(void) +{ + uint8_t temp; + + // Rotate first row 1 columns to left + temp = (*state)[0][1]; + (*state)[0][1] = (*state)[1][1]; + (*state)[1][1] = (*state)[2][1]; + (*state)[2][1] = (*state)[3][1]; + (*state)[3][1] = temp; + + // Rotate second row 2 columns to left + temp = (*state)[0][2]; + (*state)[0][2] = (*state)[2][2]; + (*state)[2][2] = temp; + + temp = (*state)[1][2]; + (*state)[1][2] = (*state)[3][2]; + (*state)[3][2] = temp; + + // Rotate third row 3 columns to left + temp = (*state)[0][3]; + (*state)[0][3] = (*state)[3][3]; + (*state)[3][3] = (*state)[2][3]; + (*state)[2][3] = (*state)[1][3]; + (*state)[1][3] = temp; +} + +static uint8_t xtime(uint8_t x) +{ + return ((x<<1) ^ (((x>>7) & 1) * 0x1b)); +} + +// MixColumns function mixes the columns of the state matrix +static void MixColumns(void) +{ + uint8_t i; + uint8_t Tmp,Tm,t; + for(i = 0; i < 4; ++i) + { + t = (*state)[i][0]; + Tmp = (*state)[i][0] ^ (*state)[i][1] ^ (*state)[i][2] ^ (*state)[i][3] ; + Tm = (*state)[i][0] ^ (*state)[i][1] ; Tm = xtime(Tm); (*state)[i][0] ^= Tm ^ Tmp ; + Tm = (*state)[i][1] ^ (*state)[i][2] ; Tm = xtime(Tm); (*state)[i][1] ^= Tm ^ Tmp ; + Tm = (*state)[i][2] ^ (*state)[i][3] ; Tm = xtime(Tm); (*state)[i][2] ^= Tm ^ Tmp ; + Tm = (*state)[i][3] ^ t ; Tm = xtime(Tm); (*state)[i][3] ^= Tm ^ Tmp ; + } +} + +// Multiply is used to multiply numbers in the field GF(2^8) +#if MULTIPLY_AS_A_FUNCTION +static uint8_t Multiply(uint8_t x, uint8_t y) +{ + return (((y & 1) * x) ^ + ((y>>1 & 1) * xtime(x)) ^ + ((y>>2 & 1) * xtime(xtime(x))) ^ + ((y>>3 & 1) * xtime(xtime(xtime(x)))) ^ + ((y>>4 & 1) * xtime(xtime(xtime(xtime(x)))))); + } +#else +#define Multiply(x, y) \ + ( ((y & 1) * x) ^ \ + ((y>>1 & 1) * xtime(x)) ^ \ + ((y>>2 & 1) * xtime(xtime(x))) ^ \ + ((y>>3 & 1) * xtime(xtime(xtime(x)))) ^ \ + ((y>>4 & 1) * xtime(xtime(xtime(xtime(x)))))) \ + +#endif + +// MixColumns function mixes the columns of the state matrix. +// The method used to multiply may be difficult to understand for the inexperienced. +// Please use the references to gain more information. +static void InvMixColumns(void) +{ + int i; + uint8_t a,b,c,d; + for(i=0;i<4;++i) + { + a = (*state)[i][0]; + b = (*state)[i][1]; + c = (*state)[i][2]; + d = (*state)[i][3]; + + (*state)[i][0] = Multiply(a, 0x0e) ^ Multiply(b, 0x0b) ^ Multiply(c, 0x0d) ^ Multiply(d, 0x09); + (*state)[i][1] = Multiply(a, 0x09) ^ Multiply(b, 0x0e) ^ Multiply(c, 0x0b) ^ Multiply(d, 0x0d); + (*state)[i][2] = Multiply(a, 0x0d) ^ Multiply(b, 0x09) ^ Multiply(c, 0x0e) ^ Multiply(d, 0x0b); + (*state)[i][3] = Multiply(a, 0x0b) ^ Multiply(b, 0x0d) ^ Multiply(c, 0x09) ^ Multiply(d, 0x0e); + } +} + + +// The SubBytes Function Substitutes the values in the +// state matrix with values in an S-box. +static void InvSubBytes(void) +{ + uint8_t i,j; + for(i=0;i<4;++i) + { + for(j=0;j<4;++j) + { + (*state)[j][i] = getSBoxInvert((*state)[j][i]); + } + } +} + +static void InvShiftRows(void) +{ + uint8_t temp; + + // Rotate first row 1 columns to right + temp=(*state)[3][1]; + (*state)[3][1]=(*state)[2][1]; + (*state)[2][1]=(*state)[1][1]; + (*state)[1][1]=(*state)[0][1]; + (*state)[0][1]=temp; + + // Rotate second row 2 columns to right + temp=(*state)[0][2]; + (*state)[0][2]=(*state)[2][2]; + (*state)[2][2]=temp; + + temp=(*state)[1][2]; + (*state)[1][2]=(*state)[3][2]; + (*state)[3][2]=temp; + + // Rotate third row 3 columns to right + temp=(*state)[0][3]; + (*state)[0][3]=(*state)[1][3]; + (*state)[1][3]=(*state)[2][3]; + (*state)[2][3]=(*state)[3][3]; + (*state)[3][3]=temp; +} + + +// Cipher is the main function that encrypts the PlainText. +static void Cipher(void) +{ + uint8_t round = 0; + + // Add the First round key to the state before starting the rounds. + AddRoundKey(0); + + // There will be Nr rounds. + // The first Nr-1 rounds are identical. + // These Nr-1 rounds are executed in the loop below. + for(round = 1; round < Nr; ++round) + { + SubBytes(); + ShiftRows(); + MixColumns(); + AddRoundKey(round); + } + + // The last round is given below. + // The MixColumns function is not here in the last round. + SubBytes(); + ShiftRows(); + AddRoundKey(Nr); +} + +static void InvCipher(void) +{ + uint8_t round=0; + + // Add the First round key to the state before starting the rounds. + AddRoundKey(Nr); + + // There will be Nr rounds. + // The first Nr-1 rounds are identical. + // These Nr-1 rounds are executed in the loop below. + for(round=Nr-1;round>0;round--) + { + InvShiftRows(); + InvSubBytes(); + AddRoundKey(round); + InvMixColumns(); + } + + // The last round is given below. + // The MixColumns function is not here in the last round. + InvShiftRows(); + InvSubBytes(); + AddRoundKey(0); +} + +static void BlockCopy(uint8_t* output, uint8_t* input) +{ + uint8_t i; + for (i=0;i + + +// #define the macros below to 1/0 to enable/disable the mode of operation. +// +// CBC enables AES128 encryption in CBC-mode of operation and handles 0-padding. +// ECB enables the basic ECB 16-byte block algorithm. Both can be enabled simultaneously. + +// The #ifndef-guard allows it to be configured before #include'ing or at compile time. +#ifndef CBC + #define CBC 1 +#endif + +#ifndef ECB + #define ECB 1 +#endif + + + +#if defined(ECB) && ECB + +void AES128_ECB_encrypt(uint8_t* input, const uint8_t* key, uint8_t *output); +void AES128_ECB_decrypt(uint8_t* input, const uint8_t* key, uint8_t *output); + +#endif // #if defined(ECB) && ECB + + +#if defined(CBC) && CBC + +void AES128_CBC_encrypt_buffer(uint8_t* output, uint8_t* input, uint32_t length, const uint8_t* key, const uint8_t* iv); +void AES128_CBC_decrypt_buffer(uint8_t* output, uint8_t* input, uint32_t length, const uint8_t* key, const uint8_t* iv); + +#endif // #if defined(CBC) && CBC + + + +#endif //_AES_H_ +void phex(uint8_t* str, int num); Index: ecs_cellMon/tools/FileEncrypt/src/crc.c =================================================================== --- ecs_cellMon/tools/FileEncrypt/src/crc.c (revision 3) +++ ecs_cellMon/tools/FileEncrypt/src/crc.c (revision 3) @@ -0,0 +1,459 @@ +#include "crc.h" + + + + /*******************************************************************\ + * * + * Library : lib_crc * + * File : lib_crc.c * + * Author : Lammert Bies 1999-2008 * + * E-mail : info@lammertbies.nl * + * Language : ANSI C * + * * + * * + * Description * + * =========== * + * * + * The file lib_crc.c contains the private and public func- * + * tions used for the calculation of CRC-16, CRC-CCITT and * + * CRC-32 cyclic redundancy values. * + * * + * * + * Dependencies * + * ============ * + * * + * lib_crc.h CRC definitions and prototypes * + * * + * * + * Modification history * + * ==================== * + * * + * Date Version Comment * + * * + * 2008-04-20 1.16 Added CRC-CCITT calculation for Kermit * + * * + * 2007-04-01 1.15 Added CRC16 calculation for Modbus * + * * + * 2007-03-28 1.14 Added CRC16 routine for Sick devices * + * * + * 2005-12-17 1.13 Added CRC-CCITT with initial 0x1D0F * + * * + * 2005-05-14 1.12 Added CRC-CCITT with start value 0 * + * * + * 2005-02-05 1.11 Fixed bug in CRC-DNP routine * + * * + * 2005-02-04 1.10 Added CRC-DNP routines * + * * + * 1999-02-21 1.01 Added FALSE and TRUE mnemonics * + * * + * 1999-01-22 1.00 Initial source * + * * + \*******************************************************************/ + + + + /*******************************************************************\ + * * + * #define P_xxxx * + * * + * The CRC's are computed using polynomials. The coefficients * + * for the algorithms are defined by the following constants. * + * * + \*******************************************************************/ + +#define P_16 0xA001 +#define P_32 0xEDB88320L +#define P_CCITT 0x1021 +#define P_DNP 0xA6BC +#define P_KERMIT 0x8408 +#define P_SICK 0x8005 + + + + /*******************************************************************\ + * * + * static int crc_tab...init * + * static unsigned ... crc_tab...[] * + * * + * The algorithms use tables with precalculated values. This * + * speeds up the calculation dramaticaly. The first time the * + * CRC function is called, the table for that specific calcu- * + * lation is set up. The ...init variables are used to deter- * + * mine if the initialization has taken place. The calculated * + * values are stored in the crc_tab... arrays. * + * * + * The variables are declared static. This makes them invisi- * + * ble for other modules of the program. * + * * + \*******************************************************************/ + +static int crc_tab16_init = FALSE; +static int crc_tab32_init = FALSE; +static int crc_tabccitt_init = FALSE; +static int crc_tabdnp_init = FALSE; +static int crc_tabkermit_init = FALSE; + +static unsigned short crc_tab16[256]; +static unsigned long crc_tab32[256]; +static unsigned short crc_tabccitt[256]; +static unsigned short crc_tabdnp[256]; +static unsigned short crc_tabkermit[256]; + + + + /*******************************************************************\ + * * + * static void init_crc...tab(); * + * * + * Three local functions are used to initialize the tables * + * with values for the algorithm. * + * * + \*******************************************************************/ + +static void init_crc16_tab( void ); +static void init_crc32_tab( void ); +static void init_crcccitt_tab( void ); +static void init_crcdnp_tab( void ); +static void init_crckermit_tab( void ); + + + + /*******************************************************************\ + * * + * unsigned short update_crc_ccitt( unsigned long crc, char c ); * + * * + * The function update_crc_ccitt calculates a new CRC-CCITT * + * value based on the previous value of the CRC and the next * + * byte of the data to be checked. * + * * + \*******************************************************************/ + +unsigned short update_crc_ccitt( unsigned short crc, char c ) { + + unsigned short tmp, short_c; + + short_c = 0x00ff & (unsigned short) c; + + if ( ! crc_tabccitt_init ) init_crcccitt_tab(); + + tmp = (crc >> 8) ^ short_c; + crc = (crc << 8) ^ crc_tabccitt[tmp]; + + return crc; + +} /* update_crc_ccitt */ + + + + /*******************************************************************\ + * * + * unsigned short update_crc_sick( * + * unsigned long crc, char c, char prev_byte ); * + * * + * The function update_crc_sick calculates a new CRC-SICK * + * value based on the previous value of the CRC and the next * + * byte of the data to be checked. * + * * + \*******************************************************************/ + +unsigned short update_crc_sick( unsigned short crc, char c, char prev_byte ) { + + unsigned short short_c, short_p; + + short_c = 0x00ff & (unsigned short) c; + short_p = ( 0x00ff & (unsigned short) prev_byte ) << 8; + + if ( crc & 0x8000 ) crc = ( crc << 1 ) ^ P_SICK; + else crc = crc << 1; + + crc &= 0xffff; + crc ^= ( short_c | short_p ); + + return crc; + +} /* update_crc_sick */ + + + + /*******************************************************************\ + * * + * unsigned short update_crc_16( unsigned short crc, char c ); * + * * + * The function update_crc_16 calculates a new CRC-16 value * + * based on the previous value of the CRC and the next byte * + * of the data to be checked. * + * * + \*******************************************************************/ + +unsigned short update_crc_16( unsigned short crc, char c ) { + + unsigned short tmp, short_c; + + short_c = 0x00ff & (unsigned short) c; + + if ( ! crc_tab16_init ) init_crc16_tab(); + + tmp = crc ^ short_c; + crc = (crc >> 8) ^ crc_tab16[ tmp & 0xff ]; + + return crc; + +} /* update_crc_16 */ + + + + /*******************************************************************\ + * * + * unsigned short update_crc_kermit( unsigned short crc, char c ); * + * * + * The function update_crc_kermit calculates a new CRC value * + * based on the previous value of the CRC and the next byte * + * of the data to be checked. * + * * + \*******************************************************************/ + +unsigned short update_crc_kermit( unsigned short crc, char c ) { + + unsigned short tmp, short_c; + + short_c = 0x00ff & (unsigned short) c; + + if ( ! crc_tabkermit_init ) init_crckermit_tab(); + + tmp = crc ^ short_c; + crc = (crc >> 8) ^ crc_tabkermit[ tmp & 0xff ]; + + return crc; + +} /* update_crc_kermit */ + + + + /*******************************************************************\ + * * + * unsigned short update_crc_dnp( unsigned short crc, char c ); * + * * + * The function update_crc_dnp calculates a new CRC-DNP value * + * based on the previous value of the CRC and the next byte * + * of the data to be checked. * + * * + \*******************************************************************/ + +unsigned short update_crc_dnp( unsigned short crc, char c ) { + + unsigned short tmp, short_c; + + short_c = 0x00ff & (unsigned short) c; + + if ( ! crc_tabdnp_init ) init_crcdnp_tab(); + + tmp = crc ^ short_c; + crc = (crc >> 8) ^ crc_tabdnp[ tmp & 0xff ]; + + return crc; + +} /* update_crc_dnp */ + + + + /*******************************************************************\ + * * + * unsigned long update_crc_32( unsigned long crc, char c ); * + * * + * The function update_crc_32 calculates a new CRC-32 value * + * based on the previous value of the CRC and the next byte * + * of the data to be checked. * + * * + \*******************************************************************/ + +unsigned long update_crc_32( unsigned long crc, char c ) { + + unsigned long tmp, long_c; + + long_c = 0x000000ffL & (unsigned long) c; + + if ( ! crc_tab32_init ) init_crc32_tab(); + + tmp = crc ^ long_c; + crc = (crc >> 8) ^ crc_tab32[ tmp & 0xff ]; + + return crc; + +} /* update_crc_32 */ + + + + /*******************************************************************\ + * * + * static void init_crc16_tab( void ); * + * * + * The function init_crc16_tab() is used to fill the array * + * for calculation of the CRC-16 with values. * + * * + \*******************************************************************/ + +static void init_crc16_tab( void ) { + + int i, j; + unsigned short crc, c; + + for (i=0; i<256; i++) { + + crc = 0; + c = (unsigned short) i; + + for (j=0; j<8; j++) { + + if ( (crc ^ c) & 0x0001 ) crc = ( crc >> 1 ) ^ P_16; + else crc = crc >> 1; + + c = c >> 1; + } + + crc_tab16[i] = crc; + } + + crc_tab16_init = TRUE; + +} /* init_crc16_tab */ + + + + /*******************************************************************\ + * * + * static void init_crckermit_tab( void ); * + * * + * The function init_crckermit_tab() is used to fill the array * + * for calculation of the CRC Kermit with values. * + * * + \*******************************************************************/ + +static void init_crckermit_tab( void ) { + + int i, j; + unsigned short crc, c; + + for (i=0; i<256; i++) { + + crc = 0; + c = (unsigned short) i; + + for (j=0; j<8; j++) { + + if ( (crc ^ c) & 0x0001 ) crc = ( crc >> 1 ) ^ P_KERMIT; + else crc = crc >> 1; + + c = c >> 1; + } + + crc_tabkermit[i] = crc; + } + + crc_tabkermit_init = TRUE; + +} /* init_crckermit_tab */ + + + + /*******************************************************************\ + * * + * static void init_crcdnp_tab( void ); * + * * + * The function init_crcdnp_tab() is used to fill the array * + * for calculation of the CRC-DNP with values. * + * * + \*******************************************************************/ + +static void init_crcdnp_tab( void ) { + + int i, j; + unsigned short crc, c; + + for (i=0; i<256; i++) { + + crc = 0; + c = (unsigned short) i; + + for (j=0; j<8; j++) { + + if ( (crc ^ c) & 0x0001 ) crc = ( crc >> 1 ) ^ P_DNP; + else crc = crc >> 1; + + c = c >> 1; + } + + crc_tabdnp[i] = crc; + } + + crc_tabdnp_init = TRUE; + +} /* init_crcdnp_tab */ + + + + /*******************************************************************\ + * * + * static void init_crc32_tab( void ); * + * * + * The function init_crc32_tab() is used to fill the array * + * for calculation of the CRC-32 with values. * + * * + \*******************************************************************/ + +static void init_crc32_tab( void ) { + + int i, j; + unsigned long crc; + + for (i=0; i<256; i++) { + + crc = (unsigned long) i; + + for (j=0; j<8; j++) { + + if ( crc & 0x00000001L ) crc = ( crc >> 1 ) ^ P_32; + else crc = crc >> 1; + } + + crc_tab32[i] = crc; + } + + crc_tab32_init = TRUE; + +} /* init_crc32_tab */ + + + + /*******************************************************************\ + * * + * static void init_crcccitt_tab( void ); * + * * + * The function init_crcccitt_tab() is used to fill the array * + * for calculation of the CRC-CCITT with values. * + * * + \*******************************************************************/ + +static void init_crcccitt_tab( void ) { + + int i, j; + unsigned short crc, c; + + for (i=0; i<256; i++) { + + crc = 0; + c = ((unsigned short) i) << 8; + + for (j=0; j<8; j++) { + + if ( (crc ^ c) & 0x8000 ) crc = ( crc << 1 ) ^ P_CCITT; + else crc = crc << 1; + + c = c << 1; + } + + crc_tabccitt[i] = crc; + } + + crc_tabccitt_init = TRUE; + +} /* init_crcccitt_tab */ Index: ecs_cellMon/tools/FileEncrypt/src/crc.h =================================================================== --- ecs_cellMon/tools/FileEncrypt/src/crc.h (revision 3) +++ ecs_cellMon/tools/FileEncrypt/src/crc.h (revision 3) @@ -0,0 +1,66 @@ + /*******************************************************************\ + * * + * Library : lib_crc * + * File : lib_crc.h * + * Author : Lammert Bies 1999-2008 * + * E-mail : info@lammertbies.nl * + * Language : ANSI C * + * * + * * + * Description * + * =========== * + * * + * The file lib_crc.h contains public definitions and proto- * + * types for the CRC functions present in lib_crc.c. * + * * + * * + * Dependencies * + * ============ * + * * + * none * + * * + * * + * Modification history * + * ==================== * + * * + * Date Version Comment * + * * + * 2008-04-20 1.16 Added CRC-CCITT routine for Kermit * + * * + * 2007-04-01 1.15 Added CRC16 calculation for Modbus * + * * + * 2007-03-28 1.14 Added CRC16 routine for Sick devices * + * * + * 2005-12-17 1.13 Added CRC-CCITT with initial 0x1D0F * + * * + * 2005-02-14 1.12 Added CRC-CCITT with initial 0x0000 * + * * + * 2005-02-05 1.11 Fixed bug in CRC-DNP routine * + * * + * 2005-02-04 1.10 Added CRC-DNP routines * + * * + * 2005-01-07 1.02 Changes in tst_crc.c * + * * + * 1999-02-21 1.01 Added FALSE and TRUE mnemonics * + * * + * 1999-01-22 1.00 Initial source * + * * + \*******************************************************************/ + + + +#define CRC_VERSION "1.16" + + + +#define FALSE 0 +#define TRUE 1 + + + +unsigned short update_crc_16( unsigned short crc, char c ); +unsigned long update_crc_32( unsigned long crc, char c ); +unsigned short update_crc_ccitt( unsigned short crc, char c ); +unsigned short update_crc_dnp( unsigned short crc, char c ); +unsigned short update_crc_kermit( unsigned short crc, char c ); +unsigned short update_crc_sick( unsigned short crc, char c, char prev_byte ); Index: ecs_cellMon/tools/FileEncrypt/src/main.c =================================================================== --- ecs_cellMon/tools/FileEncrypt/src/main.c (revision 3) +++ ecs_cellMon/tools/FileEncrypt/src/main.c (revision 3) @@ -0,0 +1,158 @@ +#include +#include +#include "aes.h" +//#include "crc.h" + +#define MAX_LENGH (2 * 1024 * 1024) // muss durch 16 teilbar. Da AES auf 16Bit Buffer eingestellt, eventuell änderbar + +#define MAX_PATH 255 + +uint8_t input[MAX_LENGH]; +uint8_t output[MAX_LENGH]; + +uint8_t key[16] = { 0x5c, 0x38, 0x36, 0x57, 0x60, 0x3d, 0x0e, 0x38, 0x61, 0x1e, 0x4e, 0x21, 0x62, 0x19, 0x47, 0x62 }; + +int main(int argc, char *argv[]) +{ + + int i=0; + FILE *fp= NULL; + int c=0; + int filePos=0; + uint32_t fileSize=0; + char outputFilename[MAX_PATH] = ""; + //uint16_t crc=0; + + //uint16_t hw_id; + //uint16_t fw_major; + //uint16_t fw_minor; + //uint16_t fw_build; + + printf("Starting file %s.\n", argv[0]); + + memset(input,0xFF,MAX_LENGH); + memset(output,0xFF,MAX_LENGH); + + if (argc < 2) + { + printf("Was soll ich den verschluesseln?\nDu hast vergessen einen Dateinahmen anzugeben!\n"); + printf("Bitte gib es z.B. so ein: FileEncrypt abc.bin\n"); + printf("LG Falko\n"); + return 0; + } + + //printf ("Bitte geben Sie die Hardware ID ein: "); + //scanf ("%hu", &hw_id); + + //printf ("Bitte geben Sie die Firmware Version ein, Major: "); + //scanf ("%hu", &fw_major); + + //printf ("Bitte geben Sie die Firmware Version ein, Minor: "); + //scanf ("%hu", &fw_minor); + + //printf ("Bitte geben Sie die Firmware Version ein, Build: "); + //scanf ("%hu", &fw_build); + + + // oeffnen im Lesemodus + fp = fopen(argv[1], "rb"); + + if(fp == NULL) + { + printf("Cannot open firmware file %s!\n", argv[1]); + fflush(stdout); + return -1; + } + + printf("Loading file %s\n", argv[1]); + fflush(stdout); + do + { + c = fgetc (fp); + if (c == EOF) break; + input[filePos] = c; + //crc= update_crc_16(crc, c ); + filePos++; + if (filePos > (MAX_LENGH-1)) + { + printf("Datei zu groß für aktuellen Buffer\n");fflush(stdout); + return -2; + } + + } while (1); + + + fclose (fp); + + fileSize = filePos; + + + // --- ENDE DATEI EINLESEN ---- + + + fflush(stdout); + + // print the resulting cipher as 4 x 16 byte strings + printf("Encrypting file...\n"); + fflush(stdout); + + for(i = 0; i < (MAX_LENGH / 16); ++i) + { + AES128_ECB_encrypt(input + (i*16), key, output+(i*16)); + } + + //Datei schreiben - verschlüsselt + //oeffnen im schreibmodus, binär + //strcat (outputFilename, "encrypted_"); + strcat(outputFilename, argv[1]); + // Let's find last '/' or '\' in path + char* fn = NULL; + if (!((fn = strrchr(outputFilename, '/')) || (fn = strrchr(outputFilename, '\\')))) + { + printf("Cannot find filename in %s", argv[1]); + return -4; + } + // Moving pointer to the beginning of the real file name + fn++; + char filename[MAX_PATH] = ""; + strcpy(filename, fn); + char dir[MAX_PATH] = ""; + strncat(dir, outputFilename, fn - outputFilename); + char new_filename[255] = ""; + strcpy(new_filename, "encrypted_"); + strcat(new_filename, filename); + strcat(dir, new_filename); + + printf("Writing file %s\n", dir); + fflush(stdout); + + fp = fopen(dir, "wb"); + + if(fp == NULL) + { + printf("File %s cannot be written!\n", dir); + return -3; + } + + filePos=0; + do + { + c = output[filePos]; + fputc (c, fp); + filePos++; + } while (filePos < fileSize); + fclose (fp); + + + printf ("Bootloader file generated!\n"); + printf ("Bin file size:\t\t\t\t %d\n", fileSize); + //printf ("HW Id:\t\t\t\t\t %d\n", hw_id ); + //printf ("FW Version:\t\t\t\t %d.%d.%d\n", fw_major, fw_minor, fw_build ); + printf ("Used Key for AES 128 Bit encryption:\t "); + phex(key,15); + //printf ("Calculated CRC:\t\t\t\t %x\n", crc); + printf("Finished!\n"); + fflush(stdout); + + return 0; +} Index: ecs_cellMon/tools/FileEncrypt/src/test.c =================================================================== --- ecs_cellMon/tools/FileEncrypt/src/test.c (revision 3) +++ ecs_cellMon/tools/FileEncrypt/src/test.c (revision 3) @@ -0,0 +1,180 @@ +#include +#include +#include + +// Enable both ECB and CBC mode. Note this can be done before including aes.h or at compile-time. +// E.g. with GCC by using the -D flag: gcc -c aes.c -DCBC=0 -DECB=1 +#define CBC 1 +#define ECB 1 + +#include "aes.h" + +static void phex(uint8_t* str); +static void test_encrypt_ecb(void); +static void test_decrypt_ecb(void); +static void test_encrypt_ecb_verbose(void); +static void test_encrypt_cbc(void); +static void test_decrypt_cbc(void); + + + +int main(void) +{ + test_encrypt_cbc(); + test_decrypt_cbc(); + test_decrypt_ecb(); + test_encrypt_ecb(); + test_encrypt_ecb_verbose(); + + return 0; +} + + + + +static void test_encrypt_ecb_verbose(void) +{ + // Example of more verbose verification + + uint8_t i, buf[64], buf2[64]; + + // 128bit key + uint8_t key[16] = { (uint8_t) 0x2b, (uint8_t) 0x7e, (uint8_t) 0x15, (uint8_t) 0x16, (uint8_t) 0x28, (uint8_t) 0xae, (uint8_t) 0xd2, (uint8_t) 0xa6, (uint8_t) 0xab, (uint8_t) 0xf7, (uint8_t) 0x15, (uint8_t) 0x88, (uint8_t) 0x09, (uint8_t) 0xcf, (uint8_t) 0x4f, (uint8_t) 0x3c }; + // 512bit text + uint8_t plain_text[64] = { (uint8_t) 0x6b, (uint8_t) 0xc1, (uint8_t) 0xbe, (uint8_t) 0xe2, (uint8_t) 0x2e, (uint8_t) 0x40, (uint8_t) 0x9f, (uint8_t) 0x96, (uint8_t) 0xe9, (uint8_t) 0x3d, (uint8_t) 0x7e, (uint8_t) 0x11, (uint8_t) 0x73, (uint8_t) 0x93, (uint8_t) 0x17, (uint8_t) 0x2a, + (uint8_t) 0xae, (uint8_t) 0x2d, (uint8_t) 0x8a, (uint8_t) 0x57, (uint8_t) 0x1e, (uint8_t) 0x03, (uint8_t) 0xac, (uint8_t) 0x9c, (uint8_t) 0x9e, (uint8_t) 0xb7, (uint8_t) 0x6f, (uint8_t) 0xac, (uint8_t) 0x45, (uint8_t) 0xaf, (uint8_t) 0x8e, (uint8_t) 0x51, + (uint8_t) 0x30, (uint8_t) 0xc8, (uint8_t) 0x1c, (uint8_t) 0x46, (uint8_t) 0xa3, (uint8_t) 0x5c, (uint8_t) 0xe4, (uint8_t) 0x11, (uint8_t) 0xe5, (uint8_t) 0xfb, (uint8_t) 0xc1, (uint8_t) 0x19, (uint8_t) 0x1a, (uint8_t) 0x0a, (uint8_t) 0x52, (uint8_t) 0xef, + (uint8_t) 0xf6, (uint8_t) 0x9f, (uint8_t) 0x24, (uint8_t) 0x45, (uint8_t) 0xdf, (uint8_t) 0x4f, (uint8_t) 0x9b, (uint8_t) 0x17, (uint8_t) 0xad, (uint8_t) 0x2b, (uint8_t) 0x41, (uint8_t) 0x7b, (uint8_t) 0xe6, (uint8_t) 0x6c, (uint8_t) 0x37, (uint8_t) 0x10 }; + + memset(buf, 0, 64); + memset(buf2, 0, 64); + + // print text to encrypt, key and IV + printf("ECB encrypt verbose:\n\n"); + printf("plain text:\n"); + for(i = (uint8_t) 0; i < (uint8_t) 4; ++i) + { + phex(plain_text + i * (uint8_t) 16); + } + printf("\n"); + + printf("key:\n"); + phex(key); + printf("\n"); + + // print the resulting cipher as 4 x 16 byte strings + printf("ciphertext:\n"); + for(i = 0; i < 4; ++i) + { + AES128_ECB_encrypt(plain_text + (i*16), key, buf+(i*16)); + phex(buf + (i*16)); + } + printf("\n"); +} + + +static void test_encrypt_ecb(void) +{ + uint8_t key[] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}; + uint8_t in[] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a}; + uint8_t out[] = {0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60, 0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97}; + uint8_t buffer[16]; + + AES128_ECB_encrypt(in, key, buffer); + + printf("ECB decrypt: "); + + if(0 == strncmp((char*) out, (char*) buffer, 16)) + { + printf("SUCCESS!\n"); + } + else + { + printf("FAILURE!\n"); + } +} + +static void test_decrypt_cbc(void) +{ + // Example "simulating" a smaller buffer... + + uint8_t key[] = { 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c }; + uint8_t iv[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f }; + uint8_t in[] = { 0x76, 0x49, 0xab, 0xac, 0x81, 0x19, 0xb2, 0x46, 0xce, 0xe9, 0x8e, 0x9b, 0x12, 0xe9, 0x19, 0x7d, + 0x50, 0x86, 0xcb, 0x9b, 0x50, 0x72, 0x19, 0xee, 0x95, 0xdb, 0x11, 0x3a, 0x91, 0x76, 0x78, 0xb2, + 0x73, 0xbe, 0xd6, 0xb8, 0xe3, 0xc1, 0x74, 0x3b, 0x71, 0x16, 0xe6, 0x9e, 0x22, 0x22, 0x95, 0x16, + 0x3f, 0xf1, 0xca, 0xa1, 0x68, 0x1f, 0xac, 0x09, 0x12, 0x0e, 0xca, 0x30, 0x75, 0x86, 0xe1, 0xa7 }; + uint8_t out[] = { 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51, + 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11, 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef, + 0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17, 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10 }; + uint8_t buffer[64]; + + AES128_CBC_decrypt_buffer(buffer+0, in+0, 16, key, iv); + AES128_CBC_decrypt_buffer(buffer+16, in+16, 16, 0, 0); + AES128_CBC_decrypt_buffer(buffer+32, in+32, 16, 0, 0); + AES128_CBC_decrypt_buffer(buffer+48, in+48, 16, 0, 0); + + printf("CBC decrypt: "); + + if(0 == strncmp((char*) out, (char*) buffer, 64)) + { + printf("SUCCESS!\n"); + } + else + { + printf("FAILURE!\n"); + } +} + +static void test_encrypt_cbc(void) +{ + uint8_t key[] = { 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c }; + uint8_t iv[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f }; + uint8_t in[] = { 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51, + 0x30, 0xc8, 0x1c, 0x46, 0xa3, 0x5c, 0xe4, 0x11, 0xe5, 0xfb, 0xc1, 0x19, 0x1a, 0x0a, 0x52, 0xef, + 0xf6, 0x9f, 0x24, 0x45, 0xdf, 0x4f, 0x9b, 0x17, 0xad, 0x2b, 0x41, 0x7b, 0xe6, 0x6c, 0x37, 0x10 }; + uint8_t out[] = { 0x76, 0x49, 0xab, 0xac, 0x81, 0x19, 0xb2, 0x46, 0xce, 0xe9, 0x8e, 0x9b, 0x12, 0xe9, 0x19, 0x7d, + 0x50, 0x86, 0xcb, 0x9b, 0x50, 0x72, 0x19, 0xee, 0x95, 0xdb, 0x11, 0x3a, 0x91, 0x76, 0x78, 0xb2, + 0x73, 0xbe, 0xd6, 0xb8, 0xe3, 0xc1, 0x74, 0x3b, 0x71, 0x16, 0xe6, 0x9e, 0x22, 0x22, 0x95, 0x16, + 0x3f, 0xf1, 0xca, 0xa1, 0x68, 0x1f, 0xac, 0x09, 0x12, 0x0e, 0xca, 0x30, 0x75, 0x86, 0xe1, 0xa7 }; + uint8_t buffer[64]; + + AES128_CBC_encrypt_buffer(buffer, in, 64, key, iv); + + printf("CBC encrypt: "); + + if(0 == strncmp((char*) out, (char*) buffer, 64)) + { + printf("SUCCESS!\n"); + } + else + { + printf("FAILURE!\n"); + } +} + + +static void test_decrypt_ecb(void) +{ + uint8_t key[] = {0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c}; + uint8_t in[] = {0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60, 0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97}; + uint8_t out[] = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a}; + uint8_t buffer[16]; + + AES128_ECB_decrypt(in, key, buffer); + + printf("ECB decrypt: "); + + if(0 == strncmp((char*) out, (char*) buffer, 16)) + { + printf("SUCCESS!\n"); + } + else + { + printf("FAILURE!\n"); + } +} + + Index: ecs_cellMon/tools/FileEncrypt/src/unlicense.txt =================================================================== --- ecs_cellMon/tools/FileEncrypt/src/unlicense.txt (revision 3) +++ ecs_cellMon/tools/FileEncrypt/src/unlicense.txt (revision 3) @@ -0,0 +1,24 @@ +This is free and unencumbered software released into the public domain. + +Anyone is free to copy, modify, publish, use, compile, sell, or +distribute this software, either in source code form or as a compiled +binary, for any purpose, commercial or non-commercial, and by any +means. + +In jurisdictions that recognize copyright laws, the author or authors +of this software dedicate any and all copyright interest in the +software to the public domain. We make this dedication for the benefit +of the public at large and to the detriment of our heirs and +successors. We intend this dedication to be an overt act of +relinquishment in perpetuity of all present and future rights to this +software under copyright law. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +For more information, please refer to