source: ecs_cellMon/firmware/startup/startup_stm32g071xx.s@ 3

Last change on this file since 3 was 3, checked in by f.jahn, 3 years ago

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File size: 9.9 KB
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1/**
2 ******************************************************************************
3 * @file startup_stm32g071xx.s
4 * @author MCD Application Team
5 * @brief STM32G071xx devices vector table GCC toolchain.
6 * This module performs:
7 * - Set the initial SP
8 * - Set the initial PC == Reset_Handler,
9 * - Set the vector table entries with the exceptions ISR address
10 * - Branches to main in the C library (which eventually
11 * calls main()).
12 * After Reset the Cortex-M0+ processor is in Thread mode,
13 * priority is Privileged, and the Stack is set to Main.
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2018 STMicroelectronics. All rights reserved.
18 *
19 * This software component is licensed by ST under Apache License, Version 2.0,
20 * the "License"; You may not use this file except in compliance with the
21 * License. You may obtain a copy of the License at:
22 * opensource.org/licenses/Apache-2.0
23 *
24 ******************************************************************************
25 */
26
27.syntax unified
28.cpu cortex-m0plus
29.fpu softvfp
30.thumb
31
32.global g_pfnVectors
33.global Default_Handler
34
35/* start address for the initialization values of the .data section.
36defined in linker script */
37.word _sidata
38/* start address for the .data section. defined in linker script */
39.word _sdata
40/* end address for the .data section. defined in linker script */
41.word _edata
42/* start address for the .bss section. defined in linker script */
43.word _sbss
44/* end address for the .bss section. defined in linker script */
45.word _ebss
46
47/**
48 * @brief This is the code that gets called when the processor first
49 * starts execution following a reset event. Only the absolutely
50 * necessary set is performed, after which the application
51 * supplied main() routine is called.
52 * @param None
53 * @retval None
54*/
55
56 .section .text.Reset_Handler
57 .weak Reset_Handler
58 .type Reset_Handler, %function
59Reset_Handler:
60 ldr r0, =_estack
61 mov sp, r0 /* set stack pointer */
62
63/* Call the clock system initialization function.*/
64 bl SystemInit
65
66/* Copy the data segment initializers from flash to SRAM */
67 ldr r0, =_sdata
68 ldr r1, =_edata
69 ldr r2, =_sidata
70 movs r3, #0
71 b LoopCopyDataInit
72
73CopyDataInit:
74 ldr r4, [r2, r3]
75 str r4, [r0, r3]
76 adds r3, r3, #4
77
78LoopCopyDataInit:
79 adds r4, r0, r3
80 cmp r4, r1
81 bcc CopyDataInit
82
83/* Zero fill the bss segment. */
84 ldr r2, =_sbss
85 ldr r4, =_ebss
86 movs r3, #0
87 b LoopFillZerobss
88
89FillZerobss:
90 str r3, [r2]
91 adds r2, r2, #4
92
93LoopFillZerobss:
94 cmp r2, r4
95 bcc FillZerobss
96
97/* Call static constructors */
98 bl __libc_init_array
99/* Call the application s entry point.*/
100 bl main
101
102LoopForever:
103 b LoopForever
104
105.size Reset_Handler, .-Reset_Handler
106
107/**
108 * @brief This is the code that gets called when the processor receives an
109 * unexpected interrupt. This simply enters an infinite loop, preserving
110 * the system state for examination by a debugger.
111 *
112 * @param None
113 * @retval None
114*/
115 .section .text.Default_Handler,"ax",%progbits
116Default_Handler:
117Infinite_Loop:
118 b Infinite_Loop
119 .size Default_Handler, .-Default_Handler
120
121/******************************************************************************
122*
123* The minimal vector table for a Cortex M0. Note that the proper constructs
124* must be placed on this to ensure that it ends up at physical address
125* 0x0000.0000.
126*
127******************************************************************************/
128 .section .isr_vector,"a",%progbits
129 .type g_pfnVectors, %object
130 .size g_pfnVectors, .-g_pfnVectors
131
132g_pfnVectors:
133 .word _estack
134 .word Reset_Handler
135 .word NMI_Handler
136 .word HardFault_Handler
137 .word 0
138 .word 0
139 .word 0
140 .word 0
141 .word 0
142 .word 0
143 .word 0
144 .word SVC_Handler
145 .word 0
146 .word 0
147 .word PendSV_Handler
148 .word SysTick_Handler
149 .word WWDG_IRQHandler /* Window WatchDog */
150 .word PVD_IRQHandler /* PVD through EXTI Line detect */
151 .word RTC_TAMP_IRQHandler /* RTC through the EXTI line */
152 .word FLASH_IRQHandler /* FLASH */
153 .word RCC_IRQHandler /* RCC */
154 .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
155 .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
156 .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
157 .word UCPD1_2_IRQHandler /* UCPD1, UCPD2 */
158 .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
159 .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
160 .word DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler /* DMA1 Channel 4 to Channel 7, DMAMUX1 overrun */
161 .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
162 .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
163 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
164 .word TIM2_IRQHandler /* TIM2 */
165 .word TIM3_IRQHandler /* TIM3 */
166 .word TIM6_DAC_LPTIM1_IRQHandler /* TIM6, DAC and LPTIM1 */
167 .word TIM7_LPTIM2_IRQHandler /* TIM7 and LPTIM2 */
168 .word TIM14_IRQHandler /* TIM14 */
169 .word TIM15_IRQHandler /* TIM15 */
170 .word TIM16_IRQHandler /* TIM16 */
171 .word TIM17_IRQHandler /* TIM17 */
172 .word I2C1_IRQHandler /* I2C1 */
173 .word I2C2_IRQHandler /* I2C2 */
174 .word SPI1_IRQHandler /* SPI1 */
175 .word SPI2_IRQHandler /* SPI2 */
176 .word USART1_IRQHandler /* USART1 */
177 .word USART2_IRQHandler /* USART2 */
178 .word USART3_4_LPUART1_IRQHandler /* USART3, USART4 and LPUART1 */
179 .word CEC_IRQHandler /* CEC */
180
181/*******************************************************************************
182*
183* Provide weak aliases for each Exception handler to the Default_Handler.
184* As they are weak aliases, any function with the same name will override
185* this definition.
186*
187*******************************************************************************/
188
189 .weak NMI_Handler
190 .thumb_set NMI_Handler,Default_Handler
191
192 .weak HardFault_Handler
193 .thumb_set HardFault_Handler,Default_Handler
194
195 .weak SVC_Handler
196 .thumb_set SVC_Handler,Default_Handler
197
198 .weak PendSV_Handler
199 .thumb_set PendSV_Handler,Default_Handler
200
201 .weak SysTick_Handler
202 .thumb_set SysTick_Handler,Default_Handler
203
204 .weak WWDG_IRQHandler
205 .thumb_set WWDG_IRQHandler,Default_Handler
206
207 .weak PVD_IRQHandler
208 .thumb_set PVD_IRQHandler,Default_Handler
209
210 .weak RTC_TAMP_IRQHandler
211 .thumb_set RTC_TAMP_IRQHandler,Default_Handler
212
213 .weak FLASH_IRQHandler
214 .thumb_set FLASH_IRQHandler,Default_Handler
215
216 .weak RCC_IRQHandler
217 .thumb_set RCC_IRQHandler,Default_Handler
218
219 .weak EXTI0_1_IRQHandler
220 .thumb_set EXTI0_1_IRQHandler,Default_Handler
221
222 .weak EXTI2_3_IRQHandler
223 .thumb_set EXTI2_3_IRQHandler,Default_Handler
224
225 .weak EXTI4_15_IRQHandler
226 .thumb_set EXTI4_15_IRQHandler,Default_Handler
227
228 .weak UCPD1_2_IRQHandler
229 .thumb_set UCPD1_2_IRQHandler,Default_Handler
230
231 .weak DMA1_Channel1_IRQHandler
232 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
233
234 .weak DMA1_Channel2_3_IRQHandler
235 .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
236
237 .weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
238 .thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler
239
240 .weak ADC1_COMP_IRQHandler
241 .thumb_set ADC1_COMP_IRQHandler,Default_Handler
242
243 .weak TIM1_BRK_UP_TRG_COM_IRQHandler
244 .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
245
246 .weak TIM1_CC_IRQHandler
247 .thumb_set TIM1_CC_IRQHandler,Default_Handler
248
249 .weak TIM2_IRQHandler
250 .thumb_set TIM2_IRQHandler,Default_Handler
251
252 .weak TIM3_IRQHandler
253 .thumb_set TIM3_IRQHandler,Default_Handler
254
255 .weak TIM6_DAC_LPTIM1_IRQHandler
256 .thumb_set TIM6_DAC_LPTIM1_IRQHandler,Default_Handler
257
258 .weak TIM7_LPTIM2_IRQHandler
259 .thumb_set TIM7_LPTIM2_IRQHandler,Default_Handler
260
261 .weak TIM14_IRQHandler
262 .thumb_set TIM14_IRQHandler,Default_Handler
263
264 .weak TIM15_IRQHandler
265 .thumb_set TIM15_IRQHandler,Default_Handler
266
267 .weak TIM16_IRQHandler
268 .thumb_set TIM16_IRQHandler,Default_Handler
269
270 .weak TIM17_IRQHandler
271 .thumb_set TIM17_IRQHandler,Default_Handler
272
273 .weak I2C1_IRQHandler
274 .thumb_set I2C1_IRQHandler,Default_Handler
275
276 .weak I2C2_IRQHandler
277 .thumb_set I2C2_IRQHandler,Default_Handler
278
279 .weak SPI1_IRQHandler
280 .thumb_set SPI1_IRQHandler,Default_Handler
281
282 .weak SPI2_IRQHandler
283 .thumb_set SPI2_IRQHandler,Default_Handler
284
285 .weak USART1_IRQHandler
286 .thumb_set USART1_IRQHandler,Default_Handler
287
288 .weak USART2_IRQHandler
289 .thumb_set USART2_IRQHandler,Default_Handler
290
291 .weak USART3_4_LPUART1_IRQHandler
292 .thumb_set USART3_4_LPUART1_IRQHandler,Default_Handler
293
294 .weak CEC_IRQHandler
295 .thumb_set CEC_IRQHandler,Default_Handler
296
297/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
298
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