1 | /********************************************************************* |
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2 | * SEGGER Microcontroller GmbH * |
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3 | * The Embedded Experts * |
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4 | ********************************************************************** |
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5 | * * |
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6 | * (c) 2014 - 2020 SEGGER Microcontroller GmbH * |
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7 | * * |
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8 | * www.segger.com Support: support@segger.com * |
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9 | * * |
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10 | ********************************************************************** |
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11 | * * |
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12 | * All rights reserved. * |
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13 | * * |
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14 | * Redistribution and use in source and binary forms, with or * |
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15 | * without modification, are permitted provided that the following * |
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16 | * condition is met: * |
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17 | * * |
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18 | * - Redistributions of source code must retain the above copyright * |
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19 | * notice, this condition and the following disclaimer. * |
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20 | * * |
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21 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * |
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22 | * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * |
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23 | * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * |
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24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * |
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25 | * DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * |
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26 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * |
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27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * |
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28 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * |
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29 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * |
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30 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * |
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31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * |
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32 | * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * |
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33 | * DAMAGE. * |
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34 | * * |
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35 | ********************************************************************** |
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36 | |
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37 | -------------------------- END-OF-HEADER ----------------------------- |
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38 | |
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39 | File : STM32G0xx_Startup.s |
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40 | Purpose : Startup and exception handlers for STM32G0xx devices. |
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41 | |
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42 | Additional information: |
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43 | Preprocessor Definitions |
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44 | __NO_SYSTEM_INIT |
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45 | If defined, |
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46 | SystemInit is not called. |
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47 | If not defined, |
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48 | SystemInit is called. |
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49 | SystemInit is usually supplied by the CMSIS files. |
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50 | This file declares a weak implementation as fallback. |
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51 | |
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52 | __MEMORY_INIT |
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53 | If defined, |
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54 | MemoryInit is called after SystemInit. |
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55 | void MemoryInit(void) can be implemented to enable external |
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56 | memory controllers. |
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57 | |
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58 | */ |
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59 | |
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60 | .syntax unified |
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61 | |
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62 | /********************************************************************* |
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63 | * |
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64 | * Global functions |
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65 | * |
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66 | ********************************************************************** |
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67 | */ |
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68 | /********************************************************************* |
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69 | * |
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70 | * Reset_Handler |
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71 | * |
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72 | * Function description |
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73 | * Exception handler for reset. |
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74 | * Generic bringup of a Cortex-M system. |
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75 | * |
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76 | * Additional information |
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77 | * The stack pointer is expected to be initialized by hardware, |
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78 | * i.e. read from vectortable[0]. |
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79 | * For manual initialization add |
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80 | * ldr R0, =__stack_end__ |
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81 | * mov SP, R0 |
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82 | */ |
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83 | .global reset_handler |
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84 | .global Reset_Handler |
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85 | .equ reset_handler, Reset_Handler |
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86 | .section .init.Reset_Handler, "ax" |
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87 | .balign 2 |
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88 | .thumb_func |
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89 | Reset_Handler: |
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90 | #ifndef __NO_SYSTEM_INIT |
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91 | // |
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92 | // Call SystemInit |
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93 | // |
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94 | bl SystemInit |
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95 | #endif |
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96 | #ifdef __MEMORY_INIT |
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97 | // |
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98 | // Call MemoryInit |
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99 | // |
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100 | bl MemoryInit |
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101 | #endif |
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102 | #ifdef __VECTORS_IN_RAM |
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103 | // |
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104 | // Copy vector table (from Flash) to RAM |
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105 | // |
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106 | ldr R0, =__vectors_start__ |
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107 | ldr R1, =__vectors_end__ |
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108 | ldr R2, =__vectors_ram_start__ |
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109 | 1: |
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110 | cmp R0, R1 |
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111 | beq 2f |
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112 | ldr R3, [R0] |
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113 | str R3, [R2] |
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114 | adds R0, R0, #4 |
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115 | adds R2, R2, #4 |
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116 | b 1b |
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117 | 2: |
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118 | #endif |
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119 | // |
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120 | // Call runtime initialization, which calls main(). |
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121 | // |
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122 | bl _start |
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123 | |
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124 | // |
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125 | // Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP, |
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126 | // when there is no strong definition of SystemInit. |
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127 | // |
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128 | .weak SystemInit |
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129 | // |
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130 | // Place SystmeCoreClockUpdate in .init_array |
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131 | // to be called after runtime initialization |
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132 | // |
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133 | #ifndef __NO_SYSTEM_INIT |
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134 | .section .init_array, "aw" |
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135 | .balign 4 |
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136 | .word SystemCoreClockUpdate |
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137 | #endif |
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138 | |
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139 | /********************************************************************* |
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140 | * |
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141 | * HardFault_Handler |
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142 | * |
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143 | * Function description |
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144 | * Simple exception handler for HardFault. |
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145 | * In case of a HardFault caused by BKPT instruction without |
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146 | * debugger attached, return execution, otherwise stay in loop. |
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147 | * |
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148 | * Additional information |
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149 | * The stack pointer is expected to be initialized by hardware, |
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150 | * i.e. read from vectortable[0]. |
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151 | * For manual initialization add |
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152 | * ldr R0, =__stack_end__ |
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153 | * mov SP, R0 |
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154 | */ |
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155 | .weak HardFault_Handler |
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156 | .section .init.HardFault_Handler, "ax" |
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157 | .balign 2 |
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158 | .thumb_func |
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159 | HardFault_Handler: |
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160 | // |
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161 | // Check if HardFault is caused by BKPT instruction |
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162 | // |
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163 | ldr R1, =0xE000ED2C // Load NVIC_HFSR |
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164 | ldr R2, [R1] |
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165 | cmp R2, #0 // Check NVIC_HFSR[31] |
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166 | |
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167 | hfLoop: |
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168 | bmi hfLoop // Not set? Stay in HardFault Handler. |
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169 | // |
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170 | // Continue execution after BKPT instruction |
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171 | // |
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172 | #if defined(__thumb__) && !defined(__thumb2__) |
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173 | movs R0, #4 |
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174 | mov R1, LR |
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175 | tst R0, R1 // Check EXC_RETURN in Link register bit 2. |
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176 | bne Uses_PSP |
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177 | mrs R0, MSP // Stacking was using MSP. |
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178 | b Pass_StackPtr |
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179 | Uses_PSP: |
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180 | mrs R0, PSP // Stacking was using PSP. |
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181 | Pass_StackPtr: |
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182 | #else |
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183 | tst LR, #4 // Check EXC_RETURN[2] in link register to get the return stack |
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184 | ite eq |
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185 | mrseq R0, MSP // Frame stored on MSP |
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186 | mrsne R0, PSP // Frame stored on PSP |
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187 | #endif |
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188 | // |
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189 | // Reset HardFault Status |
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190 | // |
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191 | #if defined(__thumb__) && !defined(__thumb2__) |
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192 | movs R3, #1 |
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193 | lsls R3, R3, #31 |
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194 | orrs R2, R3 |
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195 | str R2, [R1] |
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196 | #else |
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197 | orr R2, R2, #0x80000000 |
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198 | str R2, [R1] |
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199 | #endif |
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200 | // |
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201 | // Adjust return address |
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202 | // |
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203 | ldr R1, [R0, #24] // Get stored PC from stack |
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204 | adds R1, #2 // Adjust PC by 2 to skip current BKPT |
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205 | str R1, [R0, #24] // Write back adjusted PC to stack |
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206 | // |
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207 | bx LR // Return |
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208 | |
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209 | /*************************** End of file ****************************/ |
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