source: ecs_cellMon/firmware/Drivers/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h

Last change on this file was 3, checked in by f.jahn, 20 months ago

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1/**
2  ******************************************************************************
3  * @file    stm32g0xx_hal.h
4  * @author  MCD Application Team
5  * @brief   This file contains all the functions prototypes for the HAL
6  *          module driver.
7  ******************************************************************************
8  * @attention
9  *
10  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
11  * All rights reserved.</center></h2>
12  *
13  * This software component is licensed by ST under BSD 3-Clause license,
14  * the "License"; You may not use this file except in compliance with the
15  * License. You may obtain a copy of the License at:
16  *                        opensource.org/licenses/BSD-3-Clause
17  *
18  ******************************************************************************
19  */
20
21/* Define to prevent recursive inclusion -------------------------------------*/
22#ifndef STM32G0xx_HAL_H
23#define STM32G0xx_HAL_H
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29/* Includes ------------------------------------------------------------------*/
30#include "stm32g0xx_hal_conf.h"
31
32/** @addtogroup STM32G0xx_HAL_Driver
33  * @{
34  */
35
36/** @defgroup HAL HAL
37  * @{
38  */
39
40/* Exported types ------------------------------------------------------------*/
41/** @defgroup HAL_TICK_FREQ Tick Frequency
42  * @{
43  */
44typedef enum
45{
46  HAL_TICK_FREQ_10HZ         = 100U,
47  HAL_TICK_FREQ_100HZ        = 10U,
48  HAL_TICK_FREQ_1KHZ         = 1U,
49  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
50} HAL_TickFreqTypeDef;
51/**
52  * @}
53  */
54
55/* Exported constants --------------------------------------------------------*/
56/** @defgroup HAL_Exported_Constants HAL Exported Constants
57  * @{
58  */
59
60/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
61  * @{
62  */
63
64/** @defgroup SYSCFG_BootMode Boot Mode
65  * @{
66  */
67#define SYSCFG_BOOT_MAINFLASH          0x00000000U                      /*!< Main Flash memory mapped at 0x0000 0000   */
68#define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_CFGR1_MEM_MODE_0          /*!< System Flash memory mapped at 0x0000 0000 */
69#define SYSCFG_BOOT_SRAM               (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0)  /*!< Embedded SRAM mapped at 0x0000 0000 */
70
71/**
72  * @}
73  */
74
75/** @defgroup SYSCFG_Break Break
76  * @{
77  */
78#define SYSCFG_BREAK_SP                SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM Parity error signal with Break Input of TIM1/15/16/17 */
79#if defined(SYSCFG_CFGR2_PVDL)
80#define SYSCFG_BREAK_PVD               SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */
81#endif /* SYSCFG_CFGR2_PVDL */
82#define SYSCFG_BREAK_LOCKUP            SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM0+ with Break Input of TIM1/15/16/17 */
83#define SYSCFG_BREAK_ECC               SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC of CortexM0+ with Break Input of TIM1/15/16/17 */
84/**
85  * @}
86  */
87
88#if defined(SYSCFG_CDEN_SUPPORT)
89/** @defgroup SYSCFG_ClampingDiode Clamping Diode
90  * @{
91  */
92#define SYSCFG_CDEN_PA1                SYSCFG_CFGR2_PA1_CDEN    /*!< Enables Clamping Diode on PA1 */
93#define SYSCFG_CDEN_PA3                SYSCFG_CFGR2_PA3_CDEN    /*!< Enables Clamping Diode on PA3 */
94#define SYSCFG_CDEN_PA5                SYSCFG_CFGR2_PA5_CDEN    /*!< Enables Clamping Diode on PA5 */
95#define SYSCFG_CDEN_PA6                SYSCFG_CFGR2_PA6_CDEN    /*!< Enables Clamping Diode on PA6 */
96#define SYSCFG_CDEN_PA13               SYSCFG_CFGR2_PA13_CDEN   /*!< Enables Clamping Diode on PA13 */
97#define SYSCFG_CDEN_PB0                SYSCFG_CFGR2_PB0_CDEN    /*!< Enables Clamping Diode on PB0 */
98#define SYSCFG_CDEN_PB1                SYSCFG_CFGR2_PB1_CDEN    /*!< Enables Clamping Diode on PB1 */
99#define SYSCFG_CDEN_PB2                SYSCFG_CFGR2_PB2_CDEN    /*!< Enables Clamping Diode on PB2 */
100
101/**
102  * @}
103  */
104#endif /* SYSCFG_CDEN_SUPPORT */
105
106/** @defgroup HAL_Pin_remapping Pin remapping
107  * @{
108  */
109/* Only available on cut2.0 */
110#define SYSCFG_REMAP_PA11                   SYSCFG_CFGR1_PA11_RMP       /*!< PA11 pad behaves digitally as PA9 GPIO pin */
111#define SYSCFG_REMAP_PA12                   SYSCFG_CFGR1_PA12_RMP       /*!< PA12 pad behaves digitally as PA10 GPIO pin */
112/**
113  * @}
114  */
115
116/** @defgroup HAL_IR_ENV_SEL IR Modulation Envelope signal selection
117  * @{
118  */
119#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16     (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1)    /*!< 00: Timer16 is selected as IR Modulation envelope source */
120#define HAL_SYSCFG_IRDA_ENV_SEL_USART1    (SYSCFG_CFGR1_IR_MOD_0)                            /*!< 01: USART1 is selected as IR Modulation envelope source */
121#if defined(USART4)
122#define HAL_SYSCFG_IRDA_ENV_SEL_USART4    (SYSCFG_CFGR1_IR_MOD_1)                            /*!< 10: USART4 is selected as IR Modulation envelope source */
123#else
124#define HAL_SYSCFG_IRDA_ENV_SEL_USART2    (SYSCFG_CFGR1_IR_MOD_1)                            /*!< 10: USART2 is selected as IR Modulation envelope source */
125#endif /* USART4 */
126
127/**
128  * @}
129  */
130
131/** @defgroup HAL_IR_POL_SEL IR output polarity selection
132  * @{
133  */
134#define HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED     0x00000000U                                /*!< 00: IR output polarity not inverted */
135#define HAL_SYSCFG_IRDA_POLARITY_INVERTED         SYSCFG_CFGR1_IR_POL                        /*!< 01: IR output polarity inverted */
136
137/**
138  * @}
139  */
140
141#if defined(VREFBUF)
142/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
143  * @{
144  */
145#define SYSCFG_VREFBUF_VOLTAGE_SCALE0  0x00000000U            /*!< Voltage reference scale 0: VREF_OUT1 around 2.048 V.
146                                                                   This requires VDDA equal to or higher than 2.4 V.   */
147#define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS        /*!< Voltage reference scale 1: VREF_OUT1 around 2.5 V.
148                                                                   This requires VDDA equal to or higher than 2.8 V.   */
149
150/**
151  * @}
152  */
153
154/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
155  * @{
156  */
157#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  0x00000000U        /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
158#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ    /*!< VREF_plus pin is high impedance */
159
160/**
161  * @}
162  */
163#endif /* VREFBUF */
164
165/** @defgroup SYSCFG_FastModePlus_GPIO Fast mode Plus on GPIO
166  * @{
167  */
168
169/** @brief  Fast mode Plus driving capability on a specific GPIO
170  */
171#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast mode Plus on PB6 */
172#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast mode Plus on PB7 */
173#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast mode Plus on PB8 */
174#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast mode Plus on PB9 */
175#define SYSCFG_FASTMODEPLUS_PA9        SYSCFG_CFGR1_I2C_PA9_FMP  /*!< Enable Fast mode Plus on PA9 */
176#define SYSCFG_FASTMODEPLUS_PA10       SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast mode Plus on PA10 */
177
178/**
179 * @}
180 */
181
182/** @defgroup SYSCFG_FastModePlus_I2Cx Fast mode Plus driving capability activation for I2Cx
183  * @{
184  */
185
186/** @brief  Fast mode Plus driving capability on a specific GPIO
187  */
188#define SYSCFG_FASTMODEPLUS_I2C1       SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast mode Plus on I2C1 */
189#define SYSCFG_FASTMODEPLUS_I2C2       SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast mode Plus on I2C2 */
190#if  defined (I2C3)
191#define SYSCFG_FASTMODEPLUS_I2C3       SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast mode Plus on I2C3 */ 
192#endif /* I2C3 */
193
194/**
195 * @}
196 */
197#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
198/** @defgroup SYSCFG_UCPDx_STROBE SYSCFG Dead Battery feature configuration
199  * @{
200  */
201#define SYSCFG_UCPD1_STROBE          SYSCFG_CFGR1_UCPD1_STROBE /*!< UCPD1 Dead battery sw configuration */
202#define SYSCFG_UCPD2_STROBE          SYSCFG_CFGR1_UCPD2_STROBE /*!< UCPD2 Dead battery sw configuration */
203/**
204  * @}
205  */
206#endif /* SYSCFG_CFGR1_UCPD1_STROBE) || SYSCFG_CFGR1_UCPD2_STROBE */
207
208/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
209  * @brief ISR Wrapper
210  * @{
211  */
212#define HAL_SYSCFG_ITLINE0                           0x00000000U /*!< Internal define for macro handling */
213#define HAL_SYSCFG_ITLINE1                           0x00000001U /*!< Internal define for macro handling */
214#define HAL_SYSCFG_ITLINE2                           0x00000002U /*!< Internal define for macro handling */
215#define HAL_SYSCFG_ITLINE3                           0x00000003U /*!< Internal define for macro handling */
216#define HAL_SYSCFG_ITLINE4                           0x00000004U /*!< Internal define for macro handling */
217#define HAL_SYSCFG_ITLINE5                           0x00000005U /*!< Internal define for macro handling */
218#define HAL_SYSCFG_ITLINE6                           0x00000006U /*!< Internal define for macro handling */
219#define HAL_SYSCFG_ITLINE7                           0x00000007U /*!< Internal define for macro handling */
220#define HAL_SYSCFG_ITLINE8                           0x00000008U /*!< Internal define for macro handling */
221#define HAL_SYSCFG_ITLINE9                           0x00000009U /*!< Internal define for macro handling */
222#define HAL_SYSCFG_ITLINE10                          0x0000000AU /*!< Internal define for macro handling */
223#define HAL_SYSCFG_ITLINE11                          0x0000000BU /*!< Internal define for macro handling */
224#define HAL_SYSCFG_ITLINE12                          0x0000000CU /*!< Internal define for macro handling */
225#define HAL_SYSCFG_ITLINE13                          0x0000000DU /*!< Internal define for macro handling */
226#define HAL_SYSCFG_ITLINE14                          0x0000000EU /*!< Internal define for macro handling */
227#define HAL_SYSCFG_ITLINE15                          0x0000000FU /*!< Internal define for macro handling */
228#define HAL_SYSCFG_ITLINE16                          0x00000010U /*!< Internal define for macro handling */
229#define HAL_SYSCFG_ITLINE17                          0x00000011U /*!< Internal define for macro handling */
230#define HAL_SYSCFG_ITLINE18                          0x00000012U /*!< Internal define for macro handling */
231#define HAL_SYSCFG_ITLINE19                          0x00000013U /*!< Internal define for macro handling */
232#define HAL_SYSCFG_ITLINE20                          0x00000014U /*!< Internal define for macro handling */
233#define HAL_SYSCFG_ITLINE21                          0x00000015U /*!< Internal define for macro handling */
234#define HAL_SYSCFG_ITLINE22                          0x00000016U /*!< Internal define for macro handling */
235#define HAL_SYSCFG_ITLINE23                          0x00000017U /*!< Internal define for macro handling */
236#define HAL_SYSCFG_ITLINE24                          0x00000018U /*!< Internal define for macro handling */
237#define HAL_SYSCFG_ITLINE25                          0x00000019U /*!< Internal define for macro handling */
238#define HAL_SYSCFG_ITLINE26                          0x0000001AU /*!< Internal define for macro handling */
239#define HAL_SYSCFG_ITLINE27                          0x0000001BU /*!< Internal define for macro handling */
240#define HAL_SYSCFG_ITLINE28                          0x0000001CU /*!< Internal define for macro handling */
241#define HAL_SYSCFG_ITLINE29                          0x0000001DU /*!< Internal define for macro handling */
242#define HAL_SYSCFG_ITLINE30                          0x0000001EU /*!< Internal define for macro handling */
243#define HAL_SYSCFG_ITLINE31                          0x0000001FU /*!< Internal define for macro handling */
244
245#define HAL_ITLINE_WWDG           ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)          /*!< WWDG has expired .... */
246#if defined (PWR_PVD_SUPPORT)
247#define HAL_ITLINE_PVDOUT         ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)        /*!< Power voltage detection Interrupt .... */
248#endif /* PWR_PVD_SUPPORT */
249#if defined (PWR_PVM_SUPPORT)
250#define HAL_ITLINE_PVMOUT         ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVMOUT)        /*!< Power voltage monitor Interrupt .... */
251#endif /* PWR_PVM_SUPPORT */
252#define HAL_ITLINE_RTC            ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC)           /*!< RTC -> exti[19] Interrupt */
253#define HAL_ITLINE_TAMPER         ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_TAMPER)        /*!< TAMPER -> exti[21] interrupt .... */
254#define HAL_ITLINE_FLASH_ECC      ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ECC)     /*!< Flash ECC Interrupt */
255#define HAL_ITLINE_FLASH_ITF      ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)     /*!< Flash ITF Interrupt */
256#define HAL_ITLINE_CLK_CTRL       ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)      /*!< CLK Control Interrupt */
257#if defined (CRS)
258#define HAL_ITLINE_CRS            ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)           /*!< CRS Interrupt */
259#endif /*CRS  */
260#define HAL_ITLINE_EXTI0          ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)         /*!< External Interrupt 0 */
261#define HAL_ITLINE_EXTI1          ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)         /*!< External Interrupt 1 */
262#define HAL_ITLINE_EXTI2          ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)         /*!< External Interrupt 2 */
263#define HAL_ITLINE_EXTI3          ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)         /*!< External Interrupt 3 */
264#define HAL_ITLINE_EXTI4          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)         /*!< EXTI4 Interrupt */
265#define HAL_ITLINE_EXTI5          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)         /*!< EXTI5 Interrupt */
266#define HAL_ITLINE_EXTI6          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)         /*!< EXTI6 Interrupt */
267#define HAL_ITLINE_EXTI7          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)         /*!< EXTI7 Interrupt */
268#define HAL_ITLINE_EXTI8          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)         /*!< EXTI8 Interrupt */
269#define HAL_ITLINE_EXTI9          ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)         /*!< EXTI9 Interrupt */
270#define HAL_ITLINE_EXTI10         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)        /*!< EXTI10 Interrupt */
271#define HAL_ITLINE_EXTI11         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)        /*!< EXTI11 Interrupt */
272#define HAL_ITLINE_EXTI12         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)        /*!< EXTI12 Interrupt */
273#define HAL_ITLINE_EXTI13         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)        /*!< EXTI13 Interrupt */
274#define HAL_ITLINE_EXTI14         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)        /*!< EXTI14 Interrupt */
275#define HAL_ITLINE_EXTI15         ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)        /*!< EXTI15 Interrupt */
276#if defined (UCPD1)
277#define HAL_ITLINE_UCPD1          ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD1)         /*!< UCPD1 Interrupt */
278#endif /* UCPD1 */
279#if defined (UCPD2)
280#define HAL_ITLINE_UCPD2          ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_UCPD2)         /*!< UCPD2 Interrupt */
281#endif /* UCPD2 */
282#if defined (STM32G0C1xx) || defined (STM32G0B1xx) || defined (STM32G0B0xx)
283#define HAL_ITLINE_USB            ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_USB)           /*!< USB Interrupt */
284#endif /* STM32G0C1xx) || STM32G0B1xx) || STM32G0B0xx */
285#define HAL_ITLINE_DMA1_CH1       ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)      /*!< DMA1 Channel 1 Interrupt */
286#define HAL_ITLINE_DMA1_CH2       ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)    /*!< DMA1 Channel 2 Interrupt */
287#define HAL_ITLINE_DMA1_CH3       ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)    /*!< DMA1 Channel 3 Interrupt */
288#define HAL_ITLINE_DMAMUX1        ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMAMUX1)     /*!< DMAMUX1 Interrupt */
289#define HAL_ITLINE_DMA1_CH4       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)    /*!< DMA1 Channel 4 Interrupt */
290#define HAL_ITLINE_DMA1_CH5       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)    /*!< DMA1 Channel 5 Interrupt */
291#if defined(DMA1_Channel7)
292#define HAL_ITLINE_DMA1_CH6       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)    /*!< DMA1 Channel 6 Interrupt */
293#define HAL_ITLINE_DMA1_CH7       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)    /*!< DMA1 Channel 7 Interrupt */
294#endif /* DMA1_Channel7 */
295#if defined (DMA2)
296#define HAL_ITLINE_DMA2_CH1       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH1)    /*!< DMA2 Channel 1 Interrupt */
297#define HAL_ITLINE_DMA2_CH2       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH2)    /*!< DMA2 Channel 2 Interrupt */
298#define HAL_ITLINE_DMA2_CH3       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)    /*!< DMA2 Channel 3 Interrupt */
299#define HAL_ITLINE_DMA2_CH4       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)    /*!< DMA2 Channel 4 Interrupt */
300#define HAL_ITLINE_DMA2_CH5       ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)    /*!< DMA2 Channel 5 Interrupt */
301#endif /* DMA2 */
302#define HAL_ITLINE_ADC            ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)         /*!< ADC Interrupt */
303#if defined (COMP1)
304#define HAL_ITLINE_COMP1          ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)       /*!< COMP1 Interrupt -> exti[17] */
305#endif /* COMP1 */
306#if defined (COMP2)
307#define HAL_ITLINE_COMP2          ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)       /*!< COMP2 Interrupt -> exti[18] */
308#endif /* COMP2 */
309#if defined (COMP3)
310#define HAL_ITLINE_COMP3          ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP3)       /*!< COMP3 Interrupt -> exti[1x] */
311#endif /* COMP3 */
312#define HAL_ITLINE_TIM1_BRK       ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)    /*!< TIM1 BRK Interrupt */
313#define HAL_ITLINE_TIM1_UPD       ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)    /*!< TIM1 UPD Interrupt */
314#define HAL_ITLINE_TIM1_TRG       ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)    /*!< TIM1 TRG Interrupt */
315#define HAL_ITLINE_TIM1_CCU       ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)    /*!< TIM1 CCU Interrupt */
316#define HAL_ITLINE_TIM1_CC        ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)     /*!< TIM1 CC Interrupt */
317#if defined (TIM2)
318#define HAL_ITLINE_TIM2           ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)    /*!< TIM2 Interrupt */
319#endif /* TIM2 */
320#define HAL_ITLINE_TIM3           ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)    /*!< TIM3 Interrupt */
321#if defined (TIM4)
322#define HAL_ITLINE_TIM4           ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM4_GLB)    /*!< TIM4 Interrupt */
323#endif /* TIM4 */
324#if defined(TIM6)
325#define HAL_ITLINE_TIM6           ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)    /*!< TIM6 Interrupt */
326#endif /* TIM6 */
327#if defined(DAC1)
328#define HAL_ITLINE_DAC            ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)         /*!< DAC Interrupt */
329#endif /* DAC1 */
330#if defined(LPTIM1)
331#define HAL_ITLINE_LPTIM1         ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_LPTIM1_GLB)  /*!< LPTIM1 Interrupt -> exti[29] */
332#endif /* LPTIM1 */
333#if defined(TIM7)
334#define HAL_ITLINE_TIM7           ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)    /*!< TIM7 Interrupt */
335#endif /* TIM7 */
336#if defined(LPTIM2)
337#define HAL_ITLINE_LPTIM2         ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_LPTIM2_GLB)  /*!< LPTIM2 Interrupt -> exti[30] */
338#endif /* LPTIM2 */
339#define HAL_ITLINE_TIM14          ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)   /*!< TIM14 Interrupt */
340#if defined(TIM15)
341#define HAL_ITLINE_TIM15          ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)   /*!< TIM15 Interrupt */
342#endif /* TIM15 */
343#define HAL_ITLINE_TIM16          ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)   /*!< TIM16 Interrupt */
344#if defined (FDCAN1) || defined (FDCAN2)
345#define HAL_ITLINE_FDCAN1_IT0     ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN1_IT0)  /*!< FDCAN1_IT0 Interrupt */
346#define HAL_ITLINE_FDCAN2_IT0     ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_FDCAN2_IT0)  /*!< FDCAN2_IT0 Interrupt */
347#endif /* FDCAN1 || FDCAN2 */
348#define HAL_ITLINE_TIM17          ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)   /*!< TIM17 Interrupt */
349#if defined (FDCAN1) || defined (FDCAN2)
350#define HAL_ITLINE_FDCAN1_IT1     ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN1_IT1)  /*!< FDCAN1_IT1 Interrupt */
351#define HAL_ITLINE_FDCAN2_IT1     ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_FDCAN2_IT1)  /*!< FDCAN2_IT1 Interrupt */
352#endif /* FDCAN1 || FDCAN2 */
353#define HAL_ITLINE_I2C1           ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)    /*!< I2C1 Interrupt -> exti[23] */
354#define HAL_ITLINE_I2C2           ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)    /*!< I2C2 Interrupt -> exti[24] */
355#if defined (I2C3)
356#define HAL_ITLINE_I2C3           ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C3_GLB)    /*!< I2C3 Interrupt -> exti[22] */
357#endif /* I2C3 */
358#define HAL_ITLINE_SPI1           ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)        /*!< SPI1 Interrupt  */
359#define HAL_ITLINE_SPI2           ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)        /*!< SPI2 Interrupt */
360#if defined (SPI3)
361#define HAL_ITLINE_SPI3           ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI3)        /*!< SPI3 Interrupt */
362#endif /* SPI3 */
363#define HAL_ITLINE_USART1         ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)  /*!< USART1 GLB Interrupt -> exti[25] */
364#define HAL_ITLINE_USART2         ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)  /*!< USART2 GLB Interrupt -> exti[26] */
365#if defined (LPUART2)
366#define HAL_ITLINE_LPUART2        ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_LPUART2_GLB)  /*!< LPUART2 GLB Interrupt -> exti[26] */
367#endif /* LPUART2 */
368#if defined(USART3)
369#define HAL_ITLINE_USART3         ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)  /*!< USART3 Interrupt .... */
370#endif /* USART3 */
371#if defined(USART4)
372#define HAL_ITLINE_USART4         ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)  /*!< USART4 Interrupt .... */
373#endif /* USART4 */
374#if defined (LPUART1)
375#define HAL_ITLINE_LPUART1        ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_LPUART1_GLB) /*!< LPUART1 Interrupt -> exti[28]*/
376#endif /* LPUART1 */
377#if defined (USART5)
378#define HAL_ITLINE_USART5         ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)  /*!< USART5 Interrupt .... */
379#endif /* USART5 */
380#if defined (USART6)
381#define HAL_ITLINE_USART6         ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)  /*!< USART6 Interrupt .... */
382#endif /* USART6 */
383#if defined (CEC)
384#define HAL_ITLINE_CEC            ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)         /*!< CEC Interrupt -> exti[27] */
385#endif /* CEC */
386#if defined (RNG)
387#define HAL_ITLINE_RNG            ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_RNG)         /*!< RNG Interrupt */
388#endif /* RNG */
389#if defined (AES)
390#define HAL_ITLINE_AES            ((HAL_SYSCFG_ITLINE31 << 0x18U) | SYSCFG_ITLINE31_SR_AES)         /*!< AES Interrupt */
391#endif /* AES */
392/**
393  * @}
394  */
395
396/**
397  * @}
398  */
399
400/**
401  * @}
402  */
403
404/* Exported macros -----------------------------------------------------------*/
405/** @defgroup HAL_Exported_Macros HAL Exported Macros
406  * @{
407  */
408
409/** @defgroup DBG_Exported_Macros DBG Exported Macros
410  * @{
411  */
412
413/** @brief  Freeze and Unfreeze Peripherals in Debug mode
414  */
415#if defined(DBG_APB_FZ1_DBG_TIM2_STOP)
416#define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
417#define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM2_STOP)
418#endif /* DBG_APB_FZ1_DBG_TIM2_STOP */
419
420#if defined(DBG_APB_FZ1_DBG_TIM3_STOP)
421#define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
422#define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM3_STOP)
423#endif /* DBG_APB_FZ1_DBG_TIM3_STOP */
424
425#if defined(DBG_APB_FZ1_DBG_TIM4_STOP)
426#define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
427#define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM4_STOP)
428#endif /* DBG_APB_FZ1_DBG_TIM4_STOP */
429
430#if defined(DBG_APB_FZ1_DBG_TIM6_STOP)
431#define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
432#define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM6_STOP)
433#endif /* DBG_APB_FZ1_DBG_TIM6_STOP */
434
435#if defined(DBG_APB_FZ1_DBG_TIM7_STOP)
436#define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
437#define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_TIM7_STOP)
438#endif /* DBG_APB_FZ1_DBG_TIM7_STOP */
439
440#if defined(DBG_APB_FZ1_DBG_RTC_STOP)
441#define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
442#define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_RTC_STOP)
443#endif /* DBG_APB_FZ1_DBG_RTC_STOP */
444
445#if defined(DBG_APB_FZ1_DBG_WWDG_STOP)
446#define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
447#define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_WWDG_STOP)
448#endif /* DBG_APB_FZ1_DBG_WWDG_STOP */
449
450#if defined(DBG_APB_FZ1_DBG_IWDG_STOP)
451#define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
452#define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP)
453#endif /* DBG_APB_FZ1_DBG_IWDG_STOP */
454
455#if defined(DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
456#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
457#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP)
458#endif /* DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP */
459
460#if defined(DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
461#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
462#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP)
463#endif /* DBG_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_STOP */
464
465#if defined(DBG_APB_FZ1_DBG_LPTIM1_STOP)
466#define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
467#define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM1_STOP)
468#endif /* DBG_APB_FZ1_DBG_LPTIM1_STOP */
469
470#if defined(DBG_APB_FZ1_DBG_LPTIM2_STOP)
471#define __HAL_DBGMCU_FREEZE_LPTIM2()         SET_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
472#define __HAL_DBGMCU_UNFREEZE_LPTIM2()       CLEAR_BIT(DBG->APBFZ1, DBG_APB_FZ1_DBG_LPTIM2_STOP)
473#endif /* DBG_APB_FZ1_DBG_LPTIM2_STOP */
474
475#if defined(DBG_APB_FZ2_DBG_TIM1_STOP)
476#define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
477#define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM1_STOP)
478#endif /* DBG_APB_FZ2_DBG_TIM1_STOP */
479
480#if defined(DBG_APB_FZ2_DBG_TIM14_STOP)
481#define __HAL_DBGMCU_FREEZE_TIM14()          SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
482#define __HAL_DBGMCU_UNFREEZE_TIM14()        CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM14_STOP)
483#endif /* DBG_APB_FZ2_DBG_TIM14_STOP */
484
485#if defined(DBG_APB_FZ2_DBG_TIM15_STOP)
486#define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
487#define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM15_STOP)
488#endif /* DBG_APB_FZ2_DBG_TIM15_STOP */
489
490#if defined(DBG_APB_FZ2_DBG_TIM16_STOP)
491#define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
492#define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM16_STOP)
493#endif /* DBG_APB_FZ2_DBG_TIM16_STOP */
494
495#if defined(DBG_APB_FZ2_DBG_TIM17_STOP)
496#define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
497#define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBG->APBFZ2, DBG_APB_FZ2_DBG_TIM17_STOP)
498#endif /* DBG_APB_FZ2_DBG_TIM17_STOP */
499   
500/**
501  * @}
502  */
503
504/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
505  * @{
506  */
507
508/**
509  * @brief ISR wrapper check
510  * @note Allow to determine interrupt source per line.
511  */
512#define __HAL_GET_PENDING_IT(__SOURCE__)     (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
513   
514/** @brief  Main Flash memory mapped at 0x00000000
515  */
516#define __HAL_SYSCFG_REMAPMEMORY_FLASH()     CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
517
518/** @brief  System Flash memory mapped at 0x00000000
519  */
520#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0)
521
522/** @brief  Embedded SRAM mapped at 0x00000000
523  */
524#define __HAL_SYSCFG_REMAPMEMORY_SRAM() \
525  MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, (SYSCFG_CFGR1_MEM_MODE_1|SYSCFG_CFGR1_MEM_MODE_0))
526
527/**
528  * @brief  Return the boot mode as configured by user.
529  * @retval The boot mode as configured by user. The returned value can be one
530  *         of the following values @ref SYSCFG_BootMode
531  */
532#define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)
533
534/** @brief  SYSCFG Break ECC lock.
535  *         Enable and lock the connection of Flash ECC error connection to TIM1 Break input.
536  * @note   The selected configuration is locked and can be unlocked only by system reset.
537  */
538#define __HAL_SYSCFG_BREAK_ECC_LOCK()           SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
539
540
541/** @brief  SYSCFG Break Cortex-M0+ Lockup lock.
542  *         Enables and locks the connection of Cortex-M0+ LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
543  * @note   The selected configuration is locked and can be unlocked only by system reset.
544  */
545#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
546
547#if defined(SYSCFG_CFGR2_PVDL)
548/** @brief  SYSCFG Break PVD lock.
549  *         Enables and locks the PVD connection with Timer1/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register
550  * @note   The selected configuration is locked and can be unlocked only by system reset
551  */
552#define __HAL_SYSCFG_BREAK_PVD_LOCK()           SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
553#endif /* SYSCFG_CFGR2_PVDL */
554
555/** @brief  SYSCFG Break SRAM PARITY lock
556  *         Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/15/16/17
557  * @note   The selected configuration is locked and can only be unlocked by system reset
558  */
559#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK()    SET_BIT(SYSCFG->CFGR2,SYSCFG_CFGR2_SPL)
560
561/** @brief  Parity check on RAM disable macro
562  * @note   Disabling the parity check on RAM locks the configuration bit.
563  *         To re-enable the parity check on RAM perform a system reset.
564  */
565#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE()  (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SPF)
566
567/** @brief  Set the PEF bit to clear the SRAM Parity Error Flag.
568  */
569#define __HAL_SYSCFG_CLEAR_FLAG()               SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
570
571/** @brief  Fast-mode Plus driving capability enable/disable macros
572  * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
573  */
574#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
575                                                                SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
576                                                               }while(0U)
577
578#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
579                                                                CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
580                                                               }while(0U)
581
582#if defined(SYSCFG_CDEN_SUPPORT)
583/** @brief  Clamping Diode on specific pins enable/disable macros
584  * @param __PIN__ This parameter can be a combination of values @ref SYSCFG_ClampingDiode
585  */
586#define __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__)  do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
587                                                                SET_BIT(SYSCFG->CFGR2, (__PIN__));\
588                                                               }while(0U)
589
590#define __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
591                                                                CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\
592                                                               }while(0U)
593#endif /* SYSCFG_CDEN_SUPPORT */
594
595/** @brief  ISR wrapper check
596  * @note Allow to determine interrupt source per line.
597  */
598#define __HAL_SYSCFG_GET_PENDING_IT(__SOURCE__)  \
599  (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFFU))
600
601/** @brief  selection of the modulation envelope signal macro, using bits [7:6] of SYSCFG_CFGR1 register
602  * @param __SOURCE__ This parameter can be a value of @ref HAL_IR_ENV_SEL
603  */
604#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__)  do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__)));\
605                                                         CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD);\
606                                                         SET_BIT(SYSCFG->CFGR1, (__SOURCE__));\
607                                                        }while(0U)
608
609#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION()  ((SYSCFG->CFGR1) & 0x000000C0U)
610
611/** @brief  IROut Polarity Selection, using bit[5] of SYSCFG_CFGR1 register
612  * @param __SEL__ This parameter can be a value of @ref HAL_IR_POL_SEL
613  */
614#define __HAL_SYSCFG_IRDA_OUT_POLARITY_SELECTION(__SEL__)  do { assert_param(IS_HAL_SYSCFG_IRDA_POL_SEL((__SEL__)));\
615                                                                CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL);\
616                                                                SET_BIT(SYSCFG->CFGR1,(__SEL__));\
617                                                              }while(0U)
618
619/**
620  * @brief  Return the IROut Polarity mode as configured by user.
621  * @retval The IROut polarity as configured by user. The returned value can be one
622  *         of @ref HAL_IR_POL_SEL
623  */
624#define __HAL_SYSCFG_GET_POLARITY()           READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL)
625
626/** @brief  Break input to TIM1/15/16/17 capability enable/disable macros
627  * @param __BREAK__ This parameter can be a value of @ref SYSCFG_Break
628  */
629#define __HAL_SYSCFG_BREAK_ENABLE(__BREAK__)     do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
630                                                     SET_BIT(SYSCFG->CFGR2, (__BREAK__));\
631                                                    }while(0U)
632
633#define __HAL_SYSCFG_BREAK_DISABLE(__BREAK__)    do {assert_param(IS_SYSCFG_BREAK_CONFIG((__BREAK__)));\
634                                                     CLEAR_BIT(SYSCFG->CFGR2, (__BREAK__));\
635                                                    }while(0U)
636
637
638/**
639  * @}
640  */
641
642/**
643  * @}
644  */
645
646/* Private macros ------------------------------------------------------------*/
647/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
648  * @{
649  */
650#if defined (PWR_PVD_SUPPORT)
651#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP)        || \
652                                            ((__CONFIG__) == SYSCFG_BREAK_PVD)       || \
653                                            ((__CONFIG__) == SYSCFG_BREAK_ECC)       || \
654                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
655#else
656#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_SP)        || \
657                                            ((__CONFIG__) == SYSCFG_BREAK_ECC)       || \
658                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
659#endif /* PWR_PVD_SUPPORT */
660
661#if defined(SYSCFG_CDEN_SUPPORT)
662#define IS_SYSCFG_CLAMPINGDIODE(__PIN__) ((((__PIN__) & SYSCFG_CDEN_PA1)  == SYSCFG_CDEN_PA1)  || \
663                                          (((__PIN__) & SYSCFG_CDEN_PA3)  == SYSCFG_CDEN_PA3)  || \
664                                          (((__PIN__) & SYSCFG_CDEN_PA5)  == SYSCFG_CDEN_PA5)  || \
665                                          (((__PIN__) & SYSCFG_CDEN_PA6)  == SYSCFG_CDEN_PA6)  || \
666                                          (((__PIN__) & SYSCFG_CDEN_PA13) == SYSCFG_CDEN_PA13) || \
667                                          (((__PIN__) & SYSCFG_CDEN_PB0)  == SYSCFG_CDEN_PB0)  || \
668                                          (((__PIN__) & SYSCFG_CDEN_PB1)  == SYSCFG_CDEN_PB1)  || \
669                                          (((__PIN__) & SYSCFG_CDEN_PB2)  == SYSCFG_CDEN_PB2))
670#endif /* SYSCFG_CDEN_SUPPORT */
671
672#if defined (USART4)
673#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL)   (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16)   || \
674                                           ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1)  || \
675                                           ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
676#else
677#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL)   (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16)   || \
678                                           ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1)  || \
679                                           ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2))
680#endif /* USART4 */
681#define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL)   (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED)   || \
682                                           ((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED))
683
684#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
685#define IS_SYSCFG_DBATT_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_UCPD1_STROBE) || \
686                                            ((__CONFIG__) == SYSCFG_UCPD2_STROBE) || \
687                                            ((__CONFIG__) == (SYSCFG_UCPD1_STROBE | SYSCFG_UCPD2_STROBE)))
688#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
689#if defined(VREFBUF)
690#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
691                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
692
693#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
694                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
695
696#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
697#endif /* VREFBUF */
698
699#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9)  == SYSCFG_FASTMODEPLUS_PA9)  || \
700                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
701                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \
702                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \
703                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \
704                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))
705
706#define IS_HAL_REMAP_PIN(RMP)               (((RMP) == SYSCFG_REMAP_PA11) || \
707                                             ((RMP) == SYSCFG_REMAP_PA12) || \
708                                             ((RMP) == (SYSCFG_REMAP_PA11 | SYSCFG_REMAP_PA12)))
709/**
710  * @}
711  */
712
713/** @defgroup HAL_Private_Macros HAL Private Macros
714  * @{
715  */
716#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
717                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
718                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
719/**
720  * @}
721  */
722/* Exported functions --------------------------------------------------------*/
723
724/** @defgroup HAL_Exported_Functions HAL Exported Functions
725  * @{
726  */
727
728/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions
729  * @{
730  */
731
732/* Initialization and Configuration functions  ******************************/
733HAL_StatusTypeDef HAL_Init(void);
734HAL_StatusTypeDef HAL_DeInit(void);
735void HAL_MspInit(void);
736void HAL_MspDeInit(void);
737HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
738
739/**
740  * @}
741  */
742
743/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
744  * @{
745  */
746
747/* Peripheral Control functions  ************************************************/
748void HAL_IncTick(void);
749void HAL_Delay(uint32_t Delay);
750uint32_t HAL_GetTick(void);
751uint32_t HAL_GetTickPrio(void);
752HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
753HAL_TickFreqTypeDef HAL_GetTickFreq(void);
754void HAL_SuspendTick(void);
755void HAL_ResumeTick(void);
756uint32_t HAL_GetHalVersion(void);
757uint32_t HAL_GetREVID(void);
758uint32_t HAL_GetDEVID(void);
759uint32_t HAL_GetUIDw0(void);
760uint32_t HAL_GetUIDw1(void);
761uint32_t HAL_GetUIDw2(void);
762
763/**
764  * @}
765  */
766
767/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Control functions
768  * @{
769  */
770
771/* DBGMCU Peripheral Control functions  *****************************************/
772void HAL_DBGMCU_EnableDBGStopMode(void);
773void HAL_DBGMCU_DisableDBGStopMode(void);
774void HAL_DBGMCU_EnableDBGStandbyMode(void);
775void HAL_DBGMCU_DisableDBGStandbyMode(void);
776
777/**
778  * @}
779  */
780
781/* Exported variables ---------------------------------------------------------*/
782/** @addtogroup HAL_Exported_Variables
783  * @{
784  */
785extern __IO uint32_t uwTick;
786extern uint32_t uwTickPrio;
787extern HAL_TickFreqTypeDef uwTickFreq;
788/**
789  * @}
790  */
791
792/** @defgroup HAL_Exported_Functions_Group4 SYSCFG configuration functions
793  * @{
794  */
795
796/* SYSCFG Control functions  ****************************************************/
797
798#if defined(VREFBUF)
799void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
800void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
801void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
802HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
803void HAL_SYSCFG_DisableVREFBUF(void);
804#endif /* VREFBUF */
805
806void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
807void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
808void HAL_SYSCFG_EnableRemap(uint32_t PinRemap);
809void HAL_SYSCFG_DisableRemap(uint32_t PinRemap);
810#if defined(SYSCFG_CDEN_SUPPORT)
811void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig);
812void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig);
813#endif /* SYSCFG_CDEN_SUPPORT */
814#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
815void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery);
816#endif /* SYSCFG_CFGR1_UCPD1_STROBE || SYSCFG_CFGR1_UCPD2_STROBE */
817/**
818  * @}
819  */
820
821/**
822  * @}
823  */
824
825/**
826  * @}
827  */
828
829/**
830  * @}
831  */
832
833#ifdef __cplusplus
834}
835#endif
836
837#endif /* STM32G0xx_HAL_H */
838
839/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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