source: ecs_cellMon/Bootloader/SES/STM32G0xx/Source/STM32G0xx_Startup.s @ 3

Last change on this file since 3 was 3, checked in by f.jahn, 20 months ago

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37-------------------------- END-OF-HEADER -----------------------------
38
39File      : STM32G0xx_Startup.s
40Purpose   : Startup and exception handlers for STM32G0xx devices.
41
42Additional information:
43  Preprocessor Definitions
44    __NO_SYSTEM_INIT
45      If defined, 
46        SystemInit is not called.
47      If not defined,
48        SystemInit is called.
49        SystemInit is usually supplied by the CMSIS files.
50        This file declares a weak implementation as fallback.
51
52    __MEMORY_INIT
53      If defined,
54        MemoryInit is called after SystemInit.
55        void MemoryInit(void) can be implemented to enable external
56        memory controllers.
57
58*/
59
60        .syntax unified 
61
62/*********************************************************************
63*
64*       Global functions
65*
66**********************************************************************
67*/
68/*********************************************************************
69*
70*       Reset_Handler
71*
72*  Function description
73*    Exception handler for reset.
74*    Generic bringup of a Cortex-M system.
75*
76*  Additional information
77*    The stack pointer is expected to be initialized by hardware,
78*    i.e. read from vectortable[0].
79*    For manual initialization add
80*      ldr R0, =__stack_end__
81*      mov SP, R0
82*/
83        .global reset_handler
84        .global Reset_Handler
85        .equ reset_handler, Reset_Handler
86        .section .init.Reset_Handler, "ax"
87        .balign 2
88        .thumb_func
89Reset_Handler:
90#ifndef __NO_SYSTEM_INIT
91        //
92        // Call SystemInit
93        //
94        bl      SystemInit
95#endif
96#ifdef __MEMORY_INIT
97        //
98        // Call MemoryInit
99        //
100        bl      MemoryInit
101#endif
102#ifdef __VECTORS_IN_RAM
103        //
104        // Copy vector table (from Flash) to RAM
105        //
106        ldr     R0, =__vectors_start__
107        ldr     R1, =__vectors_end__
108        ldr     R2, =__vectors_ram_start__
1091:
110        cmp     R0, R1
111        beq     2f
112        ldr     R3, [R0]
113        str     R3, [R2]
114        adds    R0, R0, #4
115        adds    R2, R2, #4
116        b       1b
1172:
118#endif
119        //
120        // Jump to runtime initialization, which calls main().
121        //
122        b       _start
123       
124        //
125        // Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP,
126        // when there is no strong definition of SystemInit.
127        //
128        .weak SystemInit
129        //
130        // Place SystmeCoreClockUpdate in .init_array
131        // to be called after runtime initialization
132        //
133#ifndef __NO_SYSTEM_INIT
134        .section .init_array, "aw"
135        .balign 4
136        .word   SystemCoreClockUpdate
137#endif
138
139/*********************************************************************
140*
141*       HardFault_Handler
142*
143*  Function description
144*    Simple exception handler for HardFault.
145*    In case of a HardFault caused by BKPT instruction without
146*    debugger attached, return execution, otherwise stay in loop.
147*
148*  Additional information
149*    The stack pointer is expected to be initialized by hardware,
150*    i.e. read from vectortable[0].
151*    For manual initialization add
152*      ldr R0, =__stack_end__
153*      mov SP, R0
154*/
155        .weak HardFault_Handler
156        .section .init.HardFault_Handler, "ax"
157        .balign 2
158        .thumb_func
159HardFault_Handler:
160        //
161        // Check if HardFault is caused by BKPT instruction
162        //
163        ldr     R1, =0xE000ED2C        // Load NVIC_HFSR
164        ldr     R2, [R1]
165        cmp     R2, #0                  // Check NVIC_HFSR[31]
166
167hfLoop:
168        bmi     hfLoop                  // Not set? Stay in HardFault Handler.
169        //
170        // Continue execution after BKPT instruction
171        //
172#if defined(__thumb__) && !defined(__thumb2__)
173        movs    R0, #4
174        mov     R1, LR
175        tst     R0, R1                  // Check EXC_RETURN in Link register bit 2.
176        bne     Uses_PSP
177        mrs     R0, MSP                 // Stacking was using MSP.
178        b       Pass_StackPtr
179Uses_PSP:
180        mrs     R0, PSP                 // Stacking was using PSP.
181Pass_StackPtr:
182#else
183        tst     LR, #4                  // Check EXC_RETURN[2] in link register to get the return stack
184        ite     eq
185        mrseq   R0, MSP                 // Frame stored on MSP
186        mrsne   R0, PSP                 // Frame stored on PSP
187#endif
188        //
189        // Reset HardFault Status
190        //
191#if defined(__thumb__) && !defined(__thumb2__)
192        movs    R3, #1
193        lsls    R3, R3, #31
194        orrs    R2, R3
195        str     R2, [R1]
196#else
197        orr R2, R2, #0x80000000
198        str R2, [R1]
199#endif
200        //
201        // Adjust return address
202        //
203        ldr     R1, [R0, #24]           // Get stored PC from stack
204        adds    R1, #2                  // Adjust PC by 2 to skip current BKPT
205        str     R1, [R0, #24]           // Write back adjusted PC to stack
206        //
207        bx      LR                      // Return
208
209/*************************** End of file ****************************/
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