source: ecs_cellMon/Bootloader/SES/STM32G0xx/CMSIS/Device/Source/system_stm32g0xx.c

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1/**
2  ******************************************************************************
3  * @file    system_stm32g0xx.c
4  * @author  MCD Application Team
5  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
6  *
7  *   This file provides two functions and one global variable to be called from
8  *   user application:
9  *      - SystemInit(): This function is called at startup just after reset and
10  *                      before branch to main program. This call is made inside
11  *                      the "startup_stm32g0xx.s" file.
12  *
13  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14  *                                  by the user application to setup the SysTick
15  *                                  timer or configure other parameters.
16  *
17  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18  *                                 be called whenever the core clock is changed
19  *                                 during program execution.
20  *
21  *   After each device reset the HSI (8 MHz then 16 MHz) is used as system clock source.
22  *   Then SystemInit() function is called, in "startup_stm32g0xx.s" file, to
23  *   configure the system clock before to branch to main program.
24  *
25  *   This file configures the system clock as follows:
26  *=============================================================================
27  *-----------------------------------------------------------------------------
28  *        System Clock source                    | HSI
29  *-----------------------------------------------------------------------------
30  *        SYSCLK(Hz)                             | 16000000
31  *-----------------------------------------------------------------------------
32  *        HCLK(Hz)                               | 16000000
33  *-----------------------------------------------------------------------------
34  *        AHB Prescaler                          | 1
35  *-----------------------------------------------------------------------------
36  *        APB Prescaler                          | 1
37  *-----------------------------------------------------------------------------
38  *        HSI Division factor                    | 1
39  *-----------------------------------------------------------------------------
40  *        PLL_M                                  | 1
41  *-----------------------------------------------------------------------------
42  *        PLL_N                                  | 8
43  *-----------------------------------------------------------------------------
44  *        PLL_P                                  | 7
45  *-----------------------------------------------------------------------------
46  *        PLL_Q                                  | 2
47  *-----------------------------------------------------------------------------
48  *        PLL_R                                  | 2
49  *-----------------------------------------------------------------------------
50  *        Require 48MHz for RNG                  | Disabled
51  *-----------------------------------------------------------------------------
52  *=============================================================================
53  ******************************************************************************
54  * @attention
55  *
56  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
57  * All rights reserved.</center></h2>
58  *
59  * This software component is licensed by ST under BSD 3-Clause license,
60  * the "License"; You may not use this file except in compliance with the
61  * License. You may obtain a copy of the License at:
62  *                        opensource.org/licenses/BSD-3-Clause
63  *
64  ******************************************************************************
65  */
66
67/** @addtogroup CMSIS
68  * @{
69  */
70
71/** @addtogroup stm32g0xx_system
72  * @{
73  */
74
75/** @addtogroup STM32G0xx_System_Private_Includes
76  * @{
77  */
78
79#include "stm32g0xx.h"
80
81#if !defined  (HSE_VALUE)
82#define HSE_VALUE    (8000000UL)    /*!< Value of the External oscillator in Hz */
83#endif /* HSE_VALUE */
84
85#if !defined  (HSI_VALUE)
86  #define HSI_VALUE  (16000000UL)   /*!< Value of the Internal oscillator in Hz*/
87#endif /* HSI_VALUE */
88
89#if !defined  (LSI_VALUE)
90 #define LSI_VALUE   (32000UL)     /*!< Value of LSI in Hz*/
91#endif /* LSI_VALUE */
92
93#if !defined  (LSE_VALUE)
94  #define LSE_VALUE  (32768UL)      /*!< Value of LSE in Hz*/
95#endif /* LSE_VALUE */
96
97/**
98  * @}
99  */
100
101/** @addtogroup STM32G0xx_System_Private_TypesDefinitions
102  * @{
103  */
104
105/**
106  * @}
107  */
108
109/** @addtogroup STM32G0xx_System_Private_Defines
110  * @{
111  */
112
113/************************* Miscellaneous Configuration ************************/
114/*!< Uncomment the following line if you need to relocate your vector Table in
115     Internal SRAM. */
116/* #define VECT_TAB_SRAM */
117#define VECT_TAB_OFFSET  0x0U /*!< Vector Table base offset field.
118                                   This value must be a multiple of 0x100. */
119/******************************************************************************/
120/**
121  * @}
122  */
123
124/** @addtogroup STM32G0xx_System_Private_Macros
125  * @{
126  */
127
128/**
129  * @}
130  */
131
132/** @addtogroup STM32G0xx_System_Private_Variables
133  * @{
134  */
135  /* The SystemCoreClock variable is updated in three ways:
136      1) by calling CMSIS function SystemCoreClockUpdate()
137      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
138      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
139         Note: If you use this function to configure the system clock; then there
140               is no need to call the 2 first functions listed above, since SystemCoreClock
141               variable is updated automatically.
142  */
143  uint32_t SystemCoreClock = 16000000UL;
144
145  const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
146  const uint32_t APBPrescTable[8UL] =  {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
147
148/**
149  * @}
150  */
151
152/** @addtogroup STM32G0xx_System_Private_FunctionPrototypes
153  * @{
154  */
155
156/**
157  * @}
158  */
159
160/** @addtogroup STM32G0xx_System_Private_Functions
161  * @{
162  */
163
164/**
165  * @brief  Setup the microcontroller system.
166  * @param  None
167  * @retval None
168  */
169void SystemInit(void)
170{
171  /* Configure the Vector Table location add offset address ------------------*/
172#ifdef VECT_TAB_SRAM
173  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
174#else
175  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
176#endif
177}
178
179/**
180  * @brief  Update SystemCoreClock variable according to Clock Register Values.
181  *         The SystemCoreClock variable contains the core clock (HCLK), it can
182  *         be used by the user application to setup the SysTick timer or configure
183  *         other parameters.
184  *
185  * @note   Each time the core clock (HCLK) changes, this function must be called
186  *         to update SystemCoreClock variable value. Otherwise, any configuration
187  *         based on this variable will be incorrect.
188  *
189  * @note   - The system frequency computed by this function is not the real
190  *           frequency in the chip. It is calculated based on the predefined
191  *           constant and the selected clock source:
192  *
193  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) / HSI division factor
194  *
195  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
196  *
197  *           - If SYSCLK source is LSI, SystemCoreClock will contain the LSI_VALUE
198  *
199  *           - If SYSCLK source is LSE, SystemCoreClock will contain the LSE_VALUE
200  *
201  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
202  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
203  *
204  *         (**) HSI_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
205  *              16 MHz) but the real value may vary depending on the variations
206  *              in voltage and temperature.
207  *
208  *         (***) HSE_VALUE is a constant defined in stm32g0xx_hal_conf.h file (default value
209  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
210  *              frequency of the crystal used. Otherwise, this function may
211  *              have wrong result.
212  *
213  *         - The result of this function could be not correct when using fractional
214  *           value for HSE crystal.
215  *
216  * @param  None
217  * @retval None
218  */
219void SystemCoreClockUpdate(void)
220{
221  uint32_t tmp;
222  uint32_t pllvco;
223  uint32_t pllr;
224  uint32_t pllsource;
225  uint32_t pllm;
226  uint32_t hsidiv;
227
228  /* Get SYSCLK source -------------------------------------------------------*/
229  switch (RCC->CFGR & RCC_CFGR_SWS)
230  {
231    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
232      SystemCoreClock = HSE_VALUE;
233      break;
234
235    case RCC_CFGR_SWS_LSI:  /* LSI used as system clock */
236      SystemCoreClock = LSI_VALUE;
237      break;
238
239    case RCC_CFGR_SWS_LSE:  /* LSE used as system clock */
240      SystemCoreClock = LSE_VALUE;
241      break;
242
243    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
244      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
245         SYSCLK = PLL_VCO / PLLR
246         */
247      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
248      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
249
250      if(pllsource == 0x03UL) /* HSE used as PLL clock source */
251      {
252        pllvco = (HSE_VALUE / pllm);
253      }
254      else /* HSI used as PLL clock source */
255      {
256          pllvco = (HSI_VALUE / pllm);
257      }
258      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
259      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
260
261      SystemCoreClock = pllvco/pllr;
262      break;
263     
264    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
265    default:                /* HSI used as system clock */
266      hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
267      SystemCoreClock = (HSI_VALUE/hsidiv);
268      break;
269  }
270  /* Compute HCLK clock frequency --------------------------------------------*/
271  /* Get HCLK prescaler */
272  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
273  /* HCLK clock frequency */
274  SystemCoreClock >>= tmp;
275}
276
277
278/**
279  * @}
280  */
281
282/**
283  * @}
284  */
285
286/**
287  * @}
288  */
289
290/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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