Index: /ctrl/firmware/Main/CubeMX/Core/Inc/main.h =================================================================== --- /ctrl/firmware/Main/CubeMX/Core/Inc/main.h (revision 44) +++ /ctrl/firmware/Main/CubeMX/Core/Inc/main.h (revision 45) @@ -58,4 +58,10 @@ /* Private defines -----------------------------------------------------------*/ +#define SPI4_NSS_DISPLAY_Pin GPIO_PIN_11 +#define SPI4_NSS_DISPLAY_GPIO_Port GPIOE +#define SPI4_SCK_DISPLAY_Pin GPIO_PIN_12 +#define SPI4_SCK_DISPLAY_GPIO_Port GPIOE +#define SPI4_MOSI_DISPLAY_Pin GPIO_PIN_14 +#define SPI4_MOSI_DISPLAY_GPIO_Port GPIOE /* USER CODE BEGIN Private defines */ Index: /ctrl/firmware/Main/CubeMX/Core/Inc/stm32h7xx_hal_conf.h =================================================================== --- /ctrl/firmware/Main/CubeMX/Core/Inc/stm32h7xx_hal_conf.h (revision 44) +++ /ctrl/firmware/Main/CubeMX/Core/Inc/stm32h7xx_hal_conf.h (revision 45) @@ -73,5 +73,5 @@ /* #define HAL_MMC_MODULE_ENABLED */ /* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED /* #define HAL_SWPMI_MODULE_ENABLED */ /* #define HAL_TIM_MODULE_ENABLED */ Index: /ctrl/firmware/Main/CubeMX/Core/Inc/stm32h7xx_it.h =================================================================== --- /ctrl/firmware/Main/CubeMX/Core/Inc/stm32h7xx_it.h (revision 44) +++ /ctrl/firmware/Main/CubeMX/Core/Inc/stm32h7xx_it.h (revision 45) @@ -56,4 +56,6 @@ void PendSV_Handler(void); void SysTick_Handler(void); +void DMA1_Stream0_IRQHandler(void); +void SPI4_IRQHandler(void); /* USER CODE BEGIN EFP */ Index: /ctrl/firmware/Main/CubeMX/Core/Src/main.c =================================================================== --- /ctrl/firmware/Main/CubeMX/Core/Src/main.c (revision 44) +++ /ctrl/firmware/Main/CubeMX/Core/Src/main.c (revision 45) @@ -44,4 +44,7 @@ RTC_HandleTypeDef hrtc; +SPI_HandleTypeDef hspi4; +DMA_HandleTypeDef hdma_spi4_tx; + /* USER CODE BEGIN PV */ @@ -52,5 +55,7 @@ static void MPU_Config(void); static void MX_GPIO_Init(void); +static void MX_DMA_Init(void); static void MX_RTC_Init(void); +static void MX_SPI4_Init(void); /* USER CODE BEGIN PFP */ @@ -102,5 +107,7 @@ /* Initialize all configured peripherals */ MX_GPIO_Init(); + MX_DMA_Init(); MX_RTC_Init(); + MX_SPI4_Init(); /* USER CODE BEGIN 2 */ @@ -150,11 +157,11 @@ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 25; - RCC_OscInitStruct.PLL.PLLN = 200; + RCC_OscInitStruct.PLL.PLLM = 5; + RCC_OscInitStruct.PLL.PLLN = 40; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 2; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_0; - RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOMEDIUM; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) @@ -219,4 +226,68 @@ /** + * @brief SPI4 Initialization Function + * @param None + * @retval None + */ +static void MX_SPI4_Init(void) +{ + + /* USER CODE BEGIN SPI4_Init 0 */ + + /* USER CODE END SPI4_Init 0 */ + + /* USER CODE BEGIN SPI4_Init 1 */ + + /* USER CODE END SPI4_Init 1 */ + /* SPI4 parameter configuration*/ + hspi4.Instance = SPI4; + hspi4.Init.Mode = SPI_MODE_MASTER; + hspi4.Init.Direction = SPI_DIRECTION_1LINE; + hspi4.Init.DataSize = SPI_DATASIZE_9BIT; + hspi4.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi4.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi4.Init.NSS = SPI_NSS_HARD_OUTPUT; + hspi4.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi4.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi4.Init.TIMode = SPI_TIMODE_DISABLE; + hspi4.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi4.Init.CRCPolynomial = 0x0; + hspi4.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + hspi4.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; + hspi4.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; + hspi4.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; + hspi4.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; + hspi4.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; + hspi4.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; + hspi4.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; + hspi4.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; + hspi4.Init.IOSwap = SPI_IO_SWAP_DISABLE; + if (HAL_SPI_Init(&hspi4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI4_Init 2 */ + + /* USER CODE END SPI4_Init 2 */ + +} + +/** + * Enable DMA controller clock + */ +static void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA1_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA1_Stream0_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn); + +} + +/** * @brief GPIO Initialization Function * @param None @@ -231,4 +302,5 @@ __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); /* USER CODE BEGIN MX_GPIO_Init_2 */ Index: /ctrl/firmware/Main/CubeMX/Core/Src/stm32h7xx_hal_msp.c =================================================================== --- /ctrl/firmware/Main/CubeMX/Core/Src/stm32h7xx_hal_msp.c (revision 44) +++ /ctrl/firmware/Main/CubeMX/Core/Src/stm32h7xx_hal_msp.c (revision 45) @@ -24,4 +24,5 @@ /* USER CODE END Includes */ +extern DMA_HandleTypeDef hdma_spi4_tx; /* Private typedef -----------------------------------------------------------*/ @@ -133,4 +134,118 @@ } +/** +* @brief SPI MSP Initialization +* This function configures the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(hspi->Instance==SPI4) + { + /* USER CODE BEGIN SPI4_MspInit 0 */ + + /* USER CODE END SPI4_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI4; + PeriphClkInitStruct.PLL2.PLL2M = 3; + PeriphClkInitStruct.PLL2.PLL2N = 40; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 11; + PeriphClkInitStruct.PLL2.PLL2R = 2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; + PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; + PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0; + PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_SPI4_CLK_ENABLE(); + + __HAL_RCC_GPIOE_CLK_ENABLE(); + /**SPI4 GPIO Configuration + PE11 ------> SPI4_NSS + PE12 ------> SPI4_SCK + PE14 ------> SPI4_MOSI + */ + GPIO_InitStruct.Pin = SPI4_NSS_DISPLAY_Pin|SPI4_SCK_DISPLAY_Pin|SPI4_MOSI_DISPLAY_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI4; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /* SPI4 DMA Init */ + /* SPI4_TX Init */ + hdma_spi4_tx.Instance = DMA1_Stream0; + hdma_spi4_tx.Init.Request = DMA_REQUEST_SPI4_TX; + hdma_spi4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_spi4_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_spi4_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_spi4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_spi4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_spi4_tx.Init.Mode = DMA_NORMAL; + hdma_spi4_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_spi4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_spi4_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(hspi,hdmatx,hdma_spi4_tx); + + /* SPI4 interrupt Init */ + HAL_NVIC_SetPriority(SPI4_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(SPI4_IRQn); + /* USER CODE BEGIN SPI4_MspInit 1 */ + + /* USER CODE END SPI4_MspInit 1 */ + + } + +} + +/** +* @brief SPI MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hspi: SPI handle pointer +* @retval None +*/ +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) +{ + if(hspi->Instance==SPI4) + { + /* USER CODE BEGIN SPI4_MspDeInit 0 */ + + /* USER CODE END SPI4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI4_CLK_DISABLE(); + + /**SPI4 GPIO Configuration + PE11 ------> SPI4_NSS + PE12 ------> SPI4_SCK + PE14 ------> SPI4_MOSI + */ + HAL_GPIO_DeInit(GPIOE, SPI4_NSS_DISPLAY_Pin|SPI4_SCK_DISPLAY_Pin|SPI4_MOSI_DISPLAY_Pin); + + /* SPI4 DMA DeInit */ + HAL_DMA_DeInit(hspi->hdmatx); + + /* SPI4 interrupt DeInit */ + HAL_NVIC_DisableIRQ(SPI4_IRQn); + /* USER CODE BEGIN SPI4_MspDeInit 1 */ + + /* USER CODE END SPI4_MspDeInit 1 */ + } + +} + /* USER CODE BEGIN 1 */ Index: /ctrl/firmware/Main/CubeMX/Core/Src/stm32h7xx_it.c =================================================================== --- /ctrl/firmware/Main/CubeMX/Core/Src/stm32h7xx_it.c (revision 44) +++ /ctrl/firmware/Main/CubeMX/Core/Src/stm32h7xx_it.c (revision 45) @@ -56,5 +56,6 @@ /* External variables --------------------------------------------------------*/ - +extern DMA_HandleTypeDef hdma_spi4_tx; +extern SPI_HandleTypeDef hspi4; /* USER CODE BEGIN EV */ @@ -199,4 +200,32 @@ /******************************************************************************/ +/** + * @brief This function handles DMA1 stream0 global interrupt. + */ +void DMA1_Stream0_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */ + + /* USER CODE END DMA1_Stream0_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_spi4_tx); + /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */ + + /* USER CODE END DMA1_Stream0_IRQn 1 */ +} + +/** + * @brief This function handles SPI4 global interrupt. + */ +void SPI4_IRQHandler(void) +{ + /* USER CODE BEGIN SPI4_IRQn 0 */ + + /* USER CODE END SPI4_IRQn 0 */ + HAL_SPI_IRQHandler(&hspi4); + /* USER CODE BEGIN SPI4_IRQn 1 */ + + /* USER CODE END SPI4_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ Index: /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h =================================================================== --- /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h (revision 45) +++ /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h (revision 45) @@ -0,0 +1,1130 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_spi.h + * @author MCD Application Team + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7xx_HAL_SPI_H +#define STM32H7xx_HAL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal_def.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_Mode */ + + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + This parameter can be a value of @ref SPI_Direction */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_Data_Size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of + @ref SPI_Slave_Select_Management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_Transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_Mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be an odd number between + Min_Data = 0 and Max_Data = 65535 */ + + uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. + This parameter can be a value of @ref SPI_CRC_length */ + + uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . + This parameter can be a value of @ref SPI_NSSP_Mode + This mode is activated by the SSOM bit in the SPIx_CR2 register + and it takes effect only if the SPI interface is configured + as Motorola SPI master (FRF=0). */ + + uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal + (present on SS pin) is considered as active one. + This parameter can be a value of @ref SPI_NSS_Polarity */ + + uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref SPI_Fifo_Threshold */ + + uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for + the CRC calculation. This parameter can be a value of + @ref SPI_CRC_Calculation_Initialization_Pattern */ + + uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for + the CRC calculation. This parameter can be a value of + @ref SPI_CRC_Calculation_Initialization_Pattern */ + + uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle + periods, inserted additionally between active edge of SS + and first data transaction start in master mode. + This parameter can be a value of @ref SPI_Master_SS_Idleness */ + + uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) + inserted between two consecutive data frames in master mode. + This parameter can be a value of + @ref SPI_Master_InterData_Idleness */ + + uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode + and automatic management in order to avoid overrun condition. + This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/ + + uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state + This parameter can be a value of @ref SPI_Master_Keep_IO_State */ + + uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions + This parameter can be a value of @ref SPI_IO_Swap */ +} SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; + +#if defined(USE_SPI_RELOAD_TRANSFER) +/** + * @brief SPI Reload Structure definition + */ +typedef struct +{ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx Transfer size to reload */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx Transfer size to reload */ + + uint32_t Requested; /*!< SPI reload request */ + +} SPI_ReloadTypeDef; +#endif /* USE_SPI_RELOAD_TRANSFER */ + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + +#if defined(USE_SPI_RELOAD_TRANSFER) + + SPI_ReloadTypeDef Reload; /*!< SPI reload parameters */ + +#endif /* USE_SPI_RELOAD_TRANSFER */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Suspend callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} SPI_HandleTypeDef; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ + HAL_SPI_SUSPEND_CB_ID = 0x08UL, /*!< SPI Suspend callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x09UL, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_FIFO_Type SPI FIFO Type + * @{ + */ +#define SPI_LOWEND_FIFO_SIZE 8UL +#define SPI_HIGHEND_FIFO_SIZE 16UL +/** + * @} + */ + +/** @defgroup SPI_Error_Code SPI Error Codes + * @{ + */ +#define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */ +#define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */ +#define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */ +#define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */ +#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ +#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */ +#define HAL_SPI_ERROR_RELOAD (0x00000800UL) /*!< Reload error */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Mode SPI Mode + * @{ + */ +#define SPI_MODE_SLAVE (0x00000000UL) +#define SPI_MODE_MASTER SPI_CFG2_MASTER +/** + * @} + */ + +/** @defgroup SPI_Direction SPI Direction Mode + * @{ + */ +#define SPI_DIRECTION_2LINES (0x00000000UL) +#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0 +#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1 +#define SPI_DIRECTION_1LINE SPI_CFG2_COMM +/** + * @} + */ + +/** @defgroup SPI_Data_Size SPI Data Size + * @{ + */ +#define SPI_DATASIZE_4BIT (0x00000003UL) +#define SPI_DATASIZE_5BIT (0x00000004UL) +#define SPI_DATASIZE_6BIT (0x00000005UL) +#define SPI_DATASIZE_7BIT (0x00000006UL) +#define SPI_DATASIZE_8BIT (0x00000007UL) +#define SPI_DATASIZE_9BIT (0x00000008UL) +#define SPI_DATASIZE_10BIT (0x00000009UL) +#define SPI_DATASIZE_11BIT (0x0000000AUL) +#define SPI_DATASIZE_12BIT (0x0000000BUL) +#define SPI_DATASIZE_13BIT (0x0000000CUL) +#define SPI_DATASIZE_14BIT (0x0000000DUL) +#define SPI_DATASIZE_15BIT (0x0000000EUL) +#define SPI_DATASIZE_16BIT (0x0000000FUL) +#define SPI_DATASIZE_17BIT (0x00000010UL) +#define SPI_DATASIZE_18BIT (0x00000011UL) +#define SPI_DATASIZE_19BIT (0x00000012UL) +#define SPI_DATASIZE_20BIT (0x00000013UL) +#define SPI_DATASIZE_21BIT (0x00000014UL) +#define SPI_DATASIZE_22BIT (0x00000015UL) +#define SPI_DATASIZE_23BIT (0x00000016UL) +#define SPI_DATASIZE_24BIT (0x00000017UL) +#define SPI_DATASIZE_25BIT (0x00000018UL) +#define SPI_DATASIZE_26BIT (0x00000019UL) +#define SPI_DATASIZE_27BIT (0x0000001AUL) +#define SPI_DATASIZE_28BIT (0x0000001BUL) +#define SPI_DATASIZE_29BIT (0x0000001CUL) +#define SPI_DATASIZE_30BIT (0x0000001DUL) +#define SPI_DATASIZE_31BIT (0x0000001EUL) +#define SPI_DATASIZE_32BIT (0x0000001FUL) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW (0x00000000UL) +#define SPI_POLARITY_HIGH SPI_CFG2_CPOL +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0x00000000UL) +#define SPI_PHASE_2EDGE SPI_CFG2_CPHA +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_Management SPI Slave Select Management + * @{ + */ +#define SPI_NSS_SOFT SPI_CFG2_SSM +#define SPI_NSS_HARD_INPUT (0x00000000UL) +#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE +/** + * @} + */ + +/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode + * @{ + */ +#define SPI_NSS_PULSE_DISABLE (0x00000000UL) +#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 (0x00000000UL) +#define SPI_BAUDRATEPRESCALER_4 (0x10000000UL) +#define SPI_BAUDRATEPRESCALER_8 (0x20000000UL) +#define SPI_BAUDRATEPRESCALER_16 (0x30000000UL) +#define SPI_BAUDRATEPRESCALER_32 (0x40000000UL) +#define SPI_BAUDRATEPRESCALER_64 (0x50000000UL) +#define SPI_BAUDRATEPRESCALER_128 (0x60000000UL) +#define SPI_BAUDRATEPRESCALER_256 (0x70000000UL) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB (0x00000000UL) +#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST +/** + * @} + */ + +/** @defgroup SPI_TI_Mode SPI TI Mode + * @{ + */ +#define SPI_TIMODE_DISABLE (0x00000000UL) +#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0 +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE (0x00000000UL) +#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN +/** + * @} + */ + +/** @defgroup SPI_CRC_length SPI CRC Length + * @{ + */ +#define SPI_CRC_LENGTH_DATASIZE (0x00000000UL) +#define SPI_CRC_LENGTH_4BIT (0x00030000UL) +#define SPI_CRC_LENGTH_5BIT (0x00040000UL) +#define SPI_CRC_LENGTH_6BIT (0x00050000UL) +#define SPI_CRC_LENGTH_7BIT (0x00060000UL) +#define SPI_CRC_LENGTH_8BIT (0x00070000UL) +#define SPI_CRC_LENGTH_9BIT (0x00080000UL) +#define SPI_CRC_LENGTH_10BIT (0x00090000UL) +#define SPI_CRC_LENGTH_11BIT (0x000A0000UL) +#define SPI_CRC_LENGTH_12BIT (0x000B0000UL) +#define SPI_CRC_LENGTH_13BIT (0x000C0000UL) +#define SPI_CRC_LENGTH_14BIT (0x000D0000UL) +#define SPI_CRC_LENGTH_15BIT (0x000E0000UL) +#define SPI_CRC_LENGTH_16BIT (0x000F0000UL) +#define SPI_CRC_LENGTH_17BIT (0x00100000UL) +#define SPI_CRC_LENGTH_18BIT (0x00110000UL) +#define SPI_CRC_LENGTH_19BIT (0x00120000UL) +#define SPI_CRC_LENGTH_20BIT (0x00130000UL) +#define SPI_CRC_LENGTH_21BIT (0x00140000UL) +#define SPI_CRC_LENGTH_22BIT (0x00150000UL) +#define SPI_CRC_LENGTH_23BIT (0x00160000UL) +#define SPI_CRC_LENGTH_24BIT (0x00170000UL) +#define SPI_CRC_LENGTH_25BIT (0x00180000UL) +#define SPI_CRC_LENGTH_26BIT (0x00190000UL) +#define SPI_CRC_LENGTH_27BIT (0x001A0000UL) +#define SPI_CRC_LENGTH_28BIT (0x001B0000UL) +#define SPI_CRC_LENGTH_29BIT (0x001C0000UL) +#define SPI_CRC_LENGTH_30BIT (0x001D0000UL) +#define SPI_CRC_LENGTH_31BIT (0x001E0000UL) +#define SPI_CRC_LENGTH_32BIT (0x001F0000UL) +/** + * @} + */ + +/** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold + * @{ + */ +#define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL) +#define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL) +#define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL) +#define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL) +#define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL) +#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL) +#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL) +#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL) +#define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL) +#define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL) +#define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL) +#define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL) +#define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL) +#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL) +#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL) +#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL) +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern + * @{ + */ +#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL) +#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL) +/** + * @} + */ + +/** @defgroup SPI_NSS_Polarity SPI NSS Polarity + * @{ + */ +#define SPI_NSS_POLARITY_LOW (0x00000000UL) +#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP +/** + * @} + */ + +/** @defgroup SPI_Master_Keep_IO_State Keep IO State + * @{ + */ +#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL) +#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR +/** + * @} + */ + +/** @defgroup SPI_IO_Swap Control SPI IO Swap + * @{ + */ +#define SPI_IO_SWAP_DISABLE (0x00000000UL) +#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP +/** + * @} + */ + +/** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness + * @{ + */ +#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL) +#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL) +#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL) +#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL) +#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL) +#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL) +#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL) +#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL) +#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL) +#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL) +#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL) +#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL) +#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL) +#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL) +#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL) +#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL) +/** + * @} + */ + +/** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness + * @{ + */ +#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL) +#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL) +#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL) +#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL) +#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL) +#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL) +#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL) +#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL) +#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL) +#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL) +#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL) +/** + * @} + */ + +/** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend + * @{ + */ +#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL) +#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX +/** + * @} + */ + +/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior + * @{ + */ +#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) +#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0 +#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1 +/** + * @} + */ + +/** @defgroup SPI_Underrun_Detection SPI Underrun Detection + * @{ + */ +#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL) +#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0 +#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1 +/** + * @} + */ + +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition + * @{ + */ +#define SPI_IT_RXP SPI_IER_RXPIE +#define SPI_IT_TXP SPI_IER_TXPIE +#define SPI_IT_DXP SPI_IER_DXPIE +#define SPI_IT_EOT SPI_IER_EOTIE +#define SPI_IT_TXTF SPI_IER_TXTFIE +#define SPI_IT_UDR SPI_IER_UDRIE +#define SPI_IT_OVR SPI_IER_OVRIE +#define SPI_IT_CRCERR SPI_IER_CRCEIE +#define SPI_IT_FRE SPI_IER_TIFREIE +#define SPI_IT_MODF SPI_IER_MODFIE +#define SPI_IT_TSERF SPI_IER_TSERFIE +#define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR) +/** + * @} + */ + +/** @defgroup SPI_Flags_definition SPI Flags Definition + * @{ + */ +#define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */ +#define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */ +#define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */ +#define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */ +#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */ +#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */ +#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */ +#define SPI_FLAG_TSERF SPI_SR_TSERF /* SPI status flag : Additional number of data reloaded flag */ +#define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */ +#define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */ +#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */ +#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */ +/** + * @} + */ + +/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level + * @{ + */ +#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ +#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) +#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) +#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @retval None + */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SPI_IT_RXP : Rx-Packet available interrupt + * @arg SPI_IT_TXP : Tx-Packet space available interrupt + * @arg SPI_IT_DXP : Duplex Packet interrupt + * @arg SPI_IT_EOT : End of transfer interrupt + * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt + * @arg SPI_IT_UDR : Underrun interrupt + * @arg SPI_IT_OVR : Overrun interrupt + * @arg SPI_IT_CRCERR : CRC error interrupt + * @arg SPI_IT_FRE : TI mode frame format error interrupt + * @arg SPI_IT_MODF : Mode fault interrupt + * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt + * @arg SPI_IT_ERR : Error interrupt + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SPI_IT_RXP : Rx-Packet available interrupt + * @arg SPI_IT_TXP : Tx-Packet space available interrupt + * @arg SPI_IT_DXP : Duplex Packet interrupt + * @arg SPI_IT_EOT : End of transfer interrupt + * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt + * @arg SPI_IT_UDR : Underrun interrupt + * @arg SPI_IT_OVR : Overrun interrupt + * @arg SPI_IT_CRCERR : CRC error interrupt + * @arg SPI_IT_FRE : TI mode frame format error interrupt + * @arg SPI_IT_MODF : Mode fault interrupt + * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt + * @arg SPI_IT_ERR : Error interrupt + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_RXP : Rx-Packet available interrupt + * @arg SPI_IT_TXP : Tx-Packet space available interrupt + * @arg SPI_IT_DXP : Duplex Packet interrupt + * @arg SPI_IT_EOT : End of transfer interrupt + * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt + * @arg SPI_IT_UDR : Underrun interrupt + * @arg SPI_IT_OVR : Overrun interrupt + * @arg SPI_IT_CRCERR : CRC error interrupt + * @arg SPI_IT_FRE : TI mode frame format error interrupt + * @arg SPI_IT_MODF : Mode fault interrupt + * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt + * @arg SPI_IT_ERR : Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXP : Rx-Packet available flag + * @arg SPI_FLAG_TXP : Tx-Packet space available flag + * @arg SPI_FLAG_DXP : Duplex Packet flag + * @arg SPI_FLAG_EOT : End of transfer flag + * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag + * @arg SPI_FLAG_UDR : Underrun flag + * @arg SPI_FLAG_OVR : Overrun flag + * @arg SPI_FLAG_CRCERR : CRC error flag + * @arg SPI_FLAG_FRE : TI mode frame format error flag + * @arg SPI_FLAG_MODF : Mode fault flag + * @arg SPI_FLAG_TSERF : Additional number of data reloaded flag + * @arg SPI_FLAG_SUSP : Transfer suspend complete flag + * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag + * @arg SPI_FLAG_FRLVL : Fifo reception level flag + * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC)); + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC) + +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC) + +/** @brief Clear the SPI UDR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC) + +/** @brief Clear the SPI EOT pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC) + +/** @brief Clear the SPI UDR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC) + +/** @brief Clear the SPI SUSP pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC) + +/** @brief Clear the SPI TSERF pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC) + +/** @brief Enable the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) + +/** @brief Disable the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) +/** + * @} + */ + + +/* Include SPI HAL Extension module */ +#include "stm32h7xx_hal_spi_ex.h" + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); + +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); + +#if defined(USE_SPI_RELOAD_TRANSFER) +HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, + uint8_t *pRxData, uint16_t Size); +#endif /* USE_SPI_RELOAD_TRANSFER */ + +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); + +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode in 1Line configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) + +/** @brief Set the SPI receive-only mode in 1Line configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) + +/** @brief Set the SPI transmit-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0) + +/** @brief Set the SPI receive-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1) + +/** @brief Set the SPI Transmit-Receive mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL) + +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ + ((MODE) == SPI_MODE_MASTER)) + +#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) + +#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) + +#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) + +#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) + +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \ + ((DATASIZE) == SPI_DATASIZE_31BIT) || \ + ((DATASIZE) == SPI_DATASIZE_30BIT) || \ + ((DATASIZE) == SPI_DATASIZE_29BIT) || \ + ((DATASIZE) == SPI_DATASIZE_28BIT) || \ + ((DATASIZE) == SPI_DATASIZE_27BIT) || \ + ((DATASIZE) == SPI_DATASIZE_26BIT) || \ + ((DATASIZE) == SPI_DATASIZE_25BIT) || \ + ((DATASIZE) == SPI_DATASIZE_24BIT) || \ + ((DATASIZE) == SPI_DATASIZE_23BIT) || \ + ((DATASIZE) == SPI_DATASIZE_22BIT) || \ + ((DATASIZE) == SPI_DATASIZE_21BIT) || \ + ((DATASIZE) == SPI_DATASIZE_20BIT) || \ + ((DATASIZE) == SPI_DATASIZE_22BIT) || \ + ((DATASIZE) == SPI_DATASIZE_19BIT) || \ + ((DATASIZE) == SPI_DATASIZE_18BIT) || \ + ((DATASIZE) == SPI_DATASIZE_17BIT) || \ + ((DATASIZE) == SPI_DATASIZE_16BIT) || \ + ((DATASIZE) == SPI_DATASIZE_15BIT) || \ + ((DATASIZE) == SPI_DATASIZE_14BIT) || \ + ((DATASIZE) == SPI_DATASIZE_13BIT) || \ + ((DATASIZE) == SPI_DATASIZE_12BIT) || \ + ((DATASIZE) == SPI_DATASIZE_11BIT) || \ + ((DATASIZE) == SPI_DATASIZE_10BIT) || \ + ((DATASIZE) == SPI_DATASIZE_9BIT) || \ + ((DATASIZE) == SPI_DATASIZE_8BIT) || \ + ((DATASIZE) == SPI_DATASIZE_7BIT) || \ + ((DATASIZE) == SPI_DATASIZE_6BIT) || \ + ((DATASIZE) == SPI_DATASIZE_5BIT) || \ + ((DATASIZE) == SPI_DATASIZE_4BIT)) + +#define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA)) + +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ + ((CPOL) == SPI_POLARITY_HIGH)) + +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ + ((CPHA) == SPI_PHASE_2EDGE)) + +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ + ((NSS) == SPI_NSS_HARD_INPUT) || \ + ((NSS) == SPI_NSS_HARD_OUTPUT)) + +#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ + ((NSSP) == SPI_NSS_PULSE_DISABLE)) + +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) + +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ + ((BIT) == SPI_FIRSTBIT_LSB)) + +#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ + ((MODE) == SPI_TIMODE_ENABLE)) + +#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ + ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) + +#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \ + ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)) + +#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \ + ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_4BIT)) + + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) + +#define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL) + + +#define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \ + ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \ + ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS)) + +#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ + ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \ + ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED)) + +#define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ + ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7xx_HAL_SPI_H */ + +/** + * @} + */ Index: /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c =================================================================== --- /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c (revision 45) +++ /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c (revision 45) @@ -0,0 +1,2062 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Stream + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and DMA requests . + + (#) For a given Stream, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular, Normal or peripheral flow control mode, Stream Priority level, + Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + [..] + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + Half-Word data size for the peripheral to access its data register and set Word data size + for the Memory to gain in access time. Each two half words will be packed and written in + a single access to a Word in the Memory). + + -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + and Destination. In this case the Peripheral Data Size will be applied to both Source + and Destination. + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. + (+) __HAL_DMA_GET_FS: Return the current DMA Stream FIFO filled level. + (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Stream interrupts. + (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Stream interrupts. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/** @addtogroup DMA_Private_Types + * @{ + */ +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register */ + __IO uint32_t Reserved0; + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ +} DMA_Base_Registers; + +typedef struct +{ + __IO uint32_t ISR; /*!< BDMA interrupt status register */ + __IO uint32_t IFCR; /*!< BDMA interrupt flag clear register */ +} BDMA_Base_Registers; +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Constants + * @{ + */ +#define HAL_TIMEOUT_DMA_ABORT (5U) /* 5 ms */ + +#define BDMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */ +#define BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR) /*!< Memory to peripheral direction */ +#define BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM) /*!< Memory to memory direction */ + +/* DMA to BDMA conversion */ +#define DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__) (((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \ + ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \ + BDMA_PERIPH_TO_MEMORY) + +#define DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U) +#define DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U) + +#define DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U) +#define DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U) + +#define DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U) + +#define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U) + +#if defined(UART9) +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__REQUEST__) <= DMA_REQUEST_USART10_TX ))) +#else +#define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \ + (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \ + (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX ))) + +#endif +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Stream source + and destination incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Stream priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + The HAL_DMA_DeInit function allows to deinitialize the DMA stream. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and create the associated handle. + * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t registerValue; + uint32_t tickstart = HAL_GetTick(); + DMA_Base_Registers *regs_dma; + BDMA_Base_Registers *regs_bdma; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + assert_param(IS_DMA_REQUEST(hdma->Init.Request)); + assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + { + assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Get the CR register value */ + registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + registerValue &= ((uint32_t)~(DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + registerValue |= hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get memory burst and peripheral burst */ + registerValue |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + } + + /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be + lock when transferring data to/from USART/UART */ +#if (STM32H7_DEV_ID == 0x450UL) + if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) + { +#endif /* STM32H7_DEV_ID == 0x450UL */ + if(IS_DMA_UART_USART_REQUEST(hdma->Init.Request) != 0U) + { + registerValue |= DMA_SxCR_TRBUFF; + } +#if (STM32H7_DEV_ID == 0x450UL) + } +#endif /* STM32H7_DEV_ID == 0x450UL */ + + /* Write to DMA Stream CR register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR = registerValue; + + /* Get the FCR register value */ + registerValue = ((DMA_Stream_TypeDef *)hdma->Instance)->FCR; + + /* Clear Direct mode and FIFO threshold bits */ + registerValue &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Prepare the DMA Stream FIFO configuration */ + registerValue |= hdma->Init.FIFOMode; + + /* the FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get the FIFO threshold */ + registerValue |= hdma->Init.FIFOThreshold; + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 */ + if(hdma->Init.MemBurst != DMA_MBURST_SINGLE) + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_ERROR; + } + } + } + + /* Write to DMA Stream FCR */ + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = registerValue; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* Check the request parameter */ + assert_param(IS_BDMA_REQUEST(hdma->Init.Request)); + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Get the CR register value */ + registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR; + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, MEM2MEM, DBM and CT bits */ + registerValue &= ((uint32_t)~(BDMA_CCR_PL | BDMA_CCR_MSIZE | BDMA_CCR_PSIZE | \ + BDMA_CCR_MINC | BDMA_CCR_PINC | BDMA_CCR_CIRC | \ + BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_DBM | \ + BDMA_CCR_CT)); + + /* Prepare the DMA Channel configuration */ + registerValue |= DMA_TO_BDMA_DIRECTION(hdma->Init.Direction) | + DMA_TO_BDMA_PERIPHERAL_INC(hdma->Init.PeriphInc) | + DMA_TO_BDMA_MEMORY_INC(hdma->Init.MemInc) | + DMA_TO_BDMA_PDATA_SIZE(hdma->Init.PeriphDataAlignment) | + DMA_TO_BDMA_MDATA_SIZE(hdma->Init.MemDataAlignment) | + DMA_TO_BDMA_MODE(hdma->Init.Mode) | + DMA_TO_BDMA_PRIORITY(hdma->Init.Priority); + + /* Write to DMA Channel CR register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = registerValue; + + /* calculation of the channel index */ + hdma->StreamIndex = (((uint32_t)((uint32_t*)hdma->Instance) - (uint32_t)BDMA_Channel0) / ((uint32_t)BDMA_Channel1 - (uint32_t)BDMA_Channel0)) << 2U; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + } + else + { + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Initialize parameters for DMAMUX request generator : + if the DMA request is DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR7 + */ + if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register */ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + else + { + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } + } + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + DMA_Base_Registers *regs_dma; + BDMA_Base_Registers *regs_bdma; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Reset DMA Streamx control register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR = 0U; + + /* Reset DMA Streamx number of data to transfer register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = 0U; + + /* Reset DMA Streamx peripheral address register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = 0U; + + /* Reset DMA Streamx memory 0 address register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = 0U; + + /* Reset DMA Streamx memory 1 address register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = 0U; + + /* Reset DMA Streamx FIFO control register */ + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR = (uint32_t)0x00000021U; + + /* Get DMA steam Base Address */ + regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + /* Reset DMA Channel control register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR = 0U; + + /* Reset DMA Channel Number of Data to Transfer register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = 0U; + + /* Reset DMA Channel peripheral address register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = 0U; + + /* Reset DMA Channel memory 0 address register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = 0U; + + /* Reset DMA Channel memory 1 address register */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = 0U; + + /* Get DMA steam Base Address */ + regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + } + else + { + /* Return error status */ + return HAL_ERROR; + } + +#if defined (BDMA1) /* No DMAMUX available for BDMA1 available on STM32H7Ax/Bx devices only */ + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ +#endif /* BDMA1 */ + { + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + + if(hdma->DMAmuxChannel != 0U) + { + /* Resett he DMAMUX channel that corresponds to the DMA stream */ + hdma->DMAmuxChannel->CCR = 0U; + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + } + + if((hdma->Init.Request >= DMA_REQUEST_GENERATOR0) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR7)) + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + + /* Reset the DMAMUX request generator register */ + hdma->DMAmuxRequestGen->RGCR = 0U; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + + hdma->DMAmuxRequestGen = 0U; + hdma->DMAmuxRequestGenStatus = 0U; + hdma->DMAmuxRequestGenStatusMask = 0U; + } + + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Register and Unregister DMA callbacks + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Enable Common interrupts*/ + MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME)); + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Enable Half Transfer IT if corresponding Callback is set */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT; + } + } + else /* BDMA channel */ + { + /* Enable Common interrupts */ + MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE)); + + if(hdma->XferHalfCpltCallback != NULL) + { + /*Enable Half Transfer IT if corresponding Callback is set */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE; + } + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Check if DMAMUX Synchronization is enabled */ + if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + } + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + } + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Set the error code to busy */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Aborts the DMA Transfer. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * + * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + * effectively disabled is added. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs_dma; + BDMA_Base_Registers *regs_bdma; + const __IO uint32_t *enableRegister; + + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Disable DMA All Interrupts */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT); + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + + enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR)); + } + else /* BDMA channel */ + { + /* Disable DMA All Interrupts */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); + + enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR)); + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* disable the DMAMUX sync overrun IT */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + } + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while(((*enableRegister) & DMA_SxCR_EN) != 0U) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Clear all interrupt flags at correct offset within the register */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA channel */ + { + regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT */ + /* disable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + BDMA_Base_Registers *regs_bdma; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + return HAL_ERROR; + } + else + { + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + } + else /* BDMA channel */ + { + /* Disable DMA All Interrupts */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* disable the DMAMUX sync overrun IT */ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + + /* Clear all flags */ + regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU)); + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT */ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CompleteLevel: Specifies the DMA level complete. + * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. + * This model could be used for debug purpose. + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). + * @param Timeout: Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t cpltlevel_mask; + uint32_t tickstart = HAL_GetTick(); + + /* IT status register */ + __IO uint32_t *isr_reg; + /* IT clear flag register */ + __IO uint32_t *ifcr_reg; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* No transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Polling mode not supported in circular mode and double buffering mode */ + if ((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + cpltlevel_mask = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); + } + else + { + /* Half Transfer Complete flag */ + cpltlevel_mask = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + isr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); + ifcr_reg = &(((DMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + } + else /* BDMA channel */ + { + /* Polling mode not supported in circular mode */ + if ((((BDMA_Channel_TypeDef *)hdma->Instance)->CCR & BDMA_CCR_CIRC) != 0U) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + cpltlevel_mask = BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU); + } + else + { + /* Half Transfer Complete flag */ + cpltlevel_mask = BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU); + } + + isr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->ISR); + ifcr_reg = &(((BDMA_Base_Registers *)hdma->StreamBaseAddress)->IFCR); + } + + while(((*isr_reg) & cpltlevel_mask) == 0U) + { + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + if(((*isr_reg) & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + (*ifcr_reg) = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + if(((*isr_reg) & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + (*ifcr_reg) = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); + } + + if(((*isr_reg) & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + (*ifcr_reg) = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + else /* BDMA channel */ + { + if(((*isr_reg) & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + (*isr_reg) = ((BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU)); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Check for the Timeout (Not applicable in circular mode)*/ + if(Timeout != HAL_MAX_DELAY) + { + if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* if timeout then abort the current transfer */ + /* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code */ + (void) HAL_DMA_Abort(hdma); + /* + Note that the Abort function will + - Clear the transfer error flags + - Unlock + - Set the State + */ + + return HAL_ERROR; + } + } + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Check for DMAMUX Request generator (if used) overrun status */ + if(hdma->DMAmuxRequestGen != 0U) + { + /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ + if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; + } + } + + /* Check for DMAMUX Synchronization overrun */ + if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; + } + } + } + + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the half transfer and transfer complete flags */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + (*ifcr_reg) = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA channel */ + { + (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU)); + } + + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/ + { + /* Clear the half transfer and transfer complete flags */ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + (*ifcr_reg) = (DMA_FLAG_HTIF0_4) << (hdma->StreamIndex & 0x1FU); + } + else /* BDMA channel */ + { + (*ifcr_reg) = (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU)); + } + } + + return status; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t tmpisr_dma, tmpisr_bdma; + uint32_t ccr_reg; + __IO uint32_t count = 0U; + uint32_t timeout = SystemCoreClock / 9600U; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + + tmpisr_dma = regs_dma->ISR; + tmpisr_bdma = regs_bdma->ISR; + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Transfer Error Interrupt management ***************************************/ + if ((tmpisr_dma & (DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != 0U) + { + /* Disable the transfer error interrupt */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TE); + + /* Clear the transfer error flag */ + regs_dma->IFCR = DMA_FLAG_TEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + } + } + /* FIFO Error Interrupt management ******************************************/ + if ((tmpisr_dma & (DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != 0U) + { + /* Clear the FIFO error flag */ + regs_dma->IFCR = DMA_FLAG_FEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + } + } + /* Direct Mode Error Interrupt management ***********************************/ + if ((tmpisr_dma & (DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != 0U) + { + /* Clear the direct mode error flag */ + regs_dma->IFCR = DMA_FLAG_DMEIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + } + } + /* Half Transfer Complete Interrupt management ******************************/ + if ((tmpisr_dma & (DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) + { + /* Clear the half transfer complete flag */ + regs_dma->IFCR = DMA_FLAG_HTIF0_4 << (hdma->StreamIndex & 0x1FU); + + /* Multi_Buffering mode enabled */ + if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + } + else + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); + } + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + } + /* Transfer Complete Interrupt management ***********************************/ + if ((tmpisr_dma & (DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU))) != 0U) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) + { + /* Clear the transfer complete flag */ + regs_dma->IFCR = DMA_FLAG_TCIF0_4 << (hdma->StreamIndex & 0x1FU); + + if(HAL_DMA_STATE_ABORT == hdma->State) + { + /* Disable all the transfer interrupts */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + ((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_HT); + } + + /* Clear all interrupt flags at correct offset within the register */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + return; + } + + if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CT) == 0U) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for memory1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for memory0 */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + else + { + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_CIRC) == 0U) + { + /* Disable the transfer complete interrupt */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != 0U) + { + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U); + + if((((DMA_Stream_TypeDef *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U) + { + /* Change the DMA state to error if DMA disable fails */ + hdma->State = HAL_DMA_STATE_ERROR; + } + else + { + /* Change the DMA state to Ready if DMA disable success */ + hdma->State = HAL_DMA_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + ccr_reg = (((BDMA_Channel_TypeDef *)hdma->Instance)->CCR); + + /* Half Transfer Complete Interrupt management ******************************/ + if (((tmpisr_bdma & (BDMA_FLAG_HT0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_HTIE) != 0U)) + { + /* Clear the half transfer complete flag */ + regs_bdma->IFCR = (BDMA_ISR_HTIF0 << (hdma->StreamIndex & 0x1FU)); + + /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ + if((ccr_reg & BDMA_CCR_DBM) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((ccr_reg & BDMA_CCR_CT) == 0U) + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer Callback for Memory 1 */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer Callback for Memory 0 */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + else + { + if((ccr_reg & BDMA_CCR_CIRC) == 0U) + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if (((tmpisr_bdma & (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TCIE) != 0U)) + { + /* Clear the transfer complete flag */ + regs_bdma->IFCR = (BDMA_ISR_TCIF0) << (hdma->StreamIndex & 0x1FU); + + /* Disable the transfer complete interrupt if the DMA mode is Double Buffering */ + if((ccr_reg & BDMA_CCR_DBM) != 0U) + { + /* Current memory buffer used is Memory 0 */ + if((ccr_reg & BDMA_CCR_CT) == 0U) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for Memory 1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for Memory 0 */ + hdma->XferCpltCallback(hdma); + } + } + } + else + { + if((ccr_reg & BDMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Transfer Error Interrupt management **************************************/ + else if (((tmpisr_bdma & (BDMA_FLAG_TE0 << (hdma->StreamIndex & 0x1FU))) != 0U) && ((ccr_reg & BDMA_CCR_TEIE) != 0U)) + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Clear all flags */ + regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } + else + { + /* Nothing To Do */ + } + } + else + { + /* Nothing To Do */ + } +} + +/** + * @brief Register callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifier + * a DMA_HandleTypeDef structure as parameter. + * @param pCallback: pointer to private callback function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID: User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress: The source memory Buffer address + * @param DstAddress: The destination memory Buffer address + * @param DataLength: The length of data to be transferred from source to destination + * @retval None + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress; + BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress; + + if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */ + { + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + + if(hdma->DMAmuxRequestGen != 0U) + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + } + } + + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + /* Clear all interrupt flags at correct offset within the register */ + regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU); + + /* Clear DBM bit */ + ((DMA_Stream_TypeDef *)hdma->Instance)->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + ((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress; + + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + ((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress; + } + } + else if(IS_BDMA_CHANNEL_INSTANCE(hdma->Instance) != 0U) /* BDMA instance(s) */ + { + /* Clear all flags */ + regs_bdma->IFCR = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU); + + /* Configure DMA Channel data length */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Channel destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress; + + /* Configure DMA Channel source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Channel source address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + ((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress; + } + } + else + { + /* Nothing To Do */ + } +} + +/** + * @brief Returns the DMA Stream base address depending on stream number + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */ + { + uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number & 0x7U]; + + if (stream_number > 3U) + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)) + 4U); + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0x3FFU)); + } + } + else /* BDMA instance(s) */ + { + /* return pointer to ISR and IFCR */ + hdma->StreamBaseAddress = ((uint32_t)((uint32_t*)hdma->Instance) & (uint32_t)(~0xFFU)); + } + + return hdma->StreamBaseAddress; +} + +/** + * @brief Check compatibility between FIFO threshold level and size of the memory burst + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Memory Data size equal to Byte */ + if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + { + switch (hdma->Init.FIFOThreshold) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + + case DMA_FIFO_THRESHOLD_FULL: + break; + + default: + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + switch (hdma->Init.FIFOThreshold) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + + default: + break; + } + } + + /* Memory Data size equal to Word */ + else + { + switch (hdma->Init.FIFOThreshold) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_HALFFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + + case DMA_FIFO_THRESHOLD_FULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + + default: + break; + } + } + + return status; +} + +/** + * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t stream_number; + uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->Instance); + + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* BDMA Channels are connected to DMAMUX2 channels */ + stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 8U) / 20U; + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_Channel0) + (stream_number * 4U))); + hdma->DMAmuxChannelStatus = DMAMUX2_ChannelStatus; + hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); + } + else + { + /* DMA1/DMA2 Streams are connected to DMAMUX1 channels */ + stream_number = (((uint32_t)((uint32_t*)hdma->Instance) & 0xFFU) - 16U) / 24U; + + if((stream_baseaddress <= ((uint32_t)DMA2_Stream7) ) && \ + (stream_baseaddress >= ((uint32_t)DMA2_Stream0))) + { + stream_number += 8U; + } + hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_Channel0) + (stream_number * 4U))); + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + hdma->DMAmuxChannelStatusMask = 1UL << (stream_number & 0x1FU); + } +} + +/** + * @brief Updates the DMA handle with the DMAMUX request generator params + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + + if((request >= DMA_REQUEST_GENERATOR0) && (request <= DMA_REQUEST_GENERATOR7)) + { + if(IS_BDMA_CHANNEL_DMAMUX_INSTANCE(hdma->Instance) != 0U) + { + /* BDMA Channels are connected to DMAMUX2 request generator blocks */ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX2_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX2_RequestGenStatus; + } + else + { + /* DMA1 and DMA2 Streams use DMAMUX1 request generator blocks */ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + } + + hdma->DMAmuxRequestGenStatusMask = 1UL << (request - 1U); + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + Index: /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c =================================================================== --- /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c (revision 45) +++ /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c (revision 45) @@ -0,0 +1,555 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +#if defined(DUAL_CORE) +#define EXTI_CPU1 (0x01000000U) +#define EXTI_CPU2 (0x02000000U) +#endif /*DUAL_CORE*/ +#define GPIO_NUMBER (16U) +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the GPIOs + to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00U; + uint32_t iocurrent; + uint32_t temp; + EXTI_Core_TypeDef *EXTI_CurrentCPU; + +#if defined(DUAL_CORE) && defined(CORE_CM4) + EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ +#else + EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ +#endif + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00U) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1UL << position); + + if (iocurrent != 0x00U) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + temp |= (GPIO_Init->Speed << (position * 2U)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + temp |= ((GPIO_Init->Pull) << (position * 2U)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2U]; + temp &= ~(0x0FUL << (4U * (position & 0x03U))); + temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + SYSCFG->EXTICR[position >> 2U] = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->RTSR1 = temp; + + temp = EXTI->FTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->FTSR1 = temp; + + temp = EXTI_CurrentCPU->EMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + { + temp |= iocurrent; + } + EXTI_CurrentCPU->EMR1 = temp; + + /* Clear EXTI line configuration */ + temp = EXTI_CurrentCPU->IMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + { + temp |= iocurrent; + } + EXTI_CurrentCPU->IMR1 = temp; + } + } + + position++; + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00U; + uint32_t iocurrent; + uint32_t tmp; + EXTI_Core_TypeDef *EXTI_CurrentCPU; + +#if defined(DUAL_CORE) && defined(CORE_CM4) + EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */ +#else + EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */ +#endif + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00U) + { + /* Get current io position */ + iocurrent = GPIO_Pin & (1UL << position) ; + + if (iocurrent != 0x00U) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + tmp = SYSCFG->EXTICR[position >> 2U]; + tmp &= (0x0FUL << (4U * (position & 0x03U))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + { + /* Clear EXTI line configuration for Current CPU */ + EXTI_CurrentCPU->IMR1 &= ~(iocurrent); + EXTI_CurrentCPU->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->FTSR1 &= ~(iocurrent); + EXTI->RTSR1 &= ~(iocurrent); + + tmp = 0x0FUL << (4U * (position & 0x03U)); + SYSCFG->EXTICR[position >> 2U] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + } + + position++; + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0x00U) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @param PinState: specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; + } +} + +/** + * @brief Toggles the specified GPIO pins. + * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin: Specifies the pins to be toggled. + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32H7 family + * @param GPIO_Pin: specifies the port bit to be locked. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence*/ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ +#if defined(DUAL_CORE) && defined(CORE_CM4) + if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U) + { + __HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +#else + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +#endif +} + +/** + * @brief EXTI line detection callback. + * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + Index: /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c =================================================================== --- /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c (revision 45) +++ /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c (revision 45) @@ -0,0 +1,4016 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_spi.c + * @author MCD Application Team + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process or DMA process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream/Channel + (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SPI_MspInit() API. + [..] + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1UL + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : SPI Tx Completed callback + (+) RxCpltCallback : SPI Rx Completed callback + (+) TxRxCpltCallback : SPI TxRx Completed callback + (+) TxHalfCpltCallback : SPI Tx Half Completed callback + (+) RxHalfCpltCallback : SPI Rx Half Completed callback + (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (+) ErrorCallback : SPI Error callback + (+) AbortCpltCallback : SPI Abort callback + (+) SuspendCallback : SPI Suspend callback + (+) MspInitCallback : SPI Msp Init callback + (+) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : SPI Tx Completed callback + (+) RxCpltCallback : SPI Rx Completed callback + (+) TxRxCpltCallback : SPI TxRx Completed callback + (+) TxHalfCpltCallback : SPI Tx Half Completed callback + (+) RxHalfCpltCallback : SPI Rx Half Completed callback + (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (+) ErrorCallback : SPI Error callback + (+) AbortCpltCallback : SPI Abort callback + (+) SuspendCallback : SPI Suspend callback + (+) MspInitCallback : SPI Msp Init callback + (+) MspDeInitCallback : SPI Msp DeInit callback + + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined, + the callback registering feature is not available and weak callbacks are used. + + SuspendCallback restriction: + SuspendCallback is called only when MasterReceiverAutoSusp is enabled and + EOT interrupt is activated. SuspendCallback is used in relation with functions + HAL_SPI_Transmit_IT, HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive_IT. + + [..] + Circular mode restriction: + (+) The DMA circular mode cannot be used when the SPI is configured in these modes: + (++) Master 2Lines RxOnly + (++) Master 1Line Rx + (+) The CRC feature is not managed when the DMA circular mode is enabled + (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always + HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED. + Those functions are maintained for backward compatibility reasons. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 100UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, + FlagStatus FlagStatus, uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi); +static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi); +static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi); +static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi); +static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi); +static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi); + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + (++) CRC Length, used only with Data8 and Data16 + (++) FIFO reception threshold + (++) FIFO transmission threshold + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + uint32_t crc_length; + uint32_t packet_length; +#if (USE_SPI_CRC != 0UL) + uint32_t crc_poly_msb_mask; +#endif /* USE_SPI_CRC */ + + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + } +#if (USE_SPI_CRC != 0UL) + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern)); + assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ + + /* Verify that the SPI instance supports Data Size higher than 16bits */ + if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT)) + { + return HAL_ERROR; + } + + /* Verify that the SPI instance supports requested data packing */ + packet_length = SPI_GetPacketSize(hspi); + if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) || + ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE))) + { + return HAL_ERROR; + } + +#if (USE_SPI_CRC != 0UL) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Verify that the SPI instance supports CRC Length higher than 16bits */ + if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT)) + { + return HAL_ERROR; + } + + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + crc_length = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos; + } + else + { + crc_length = hspi->Init.CRCLength; + } + + /* Verify the correctness of polynom size */ + assert_param(IS_SPI_CRC_POLYNOMIAL_SIZE(hspi->Init.CRCPolynomial, crc_length)); + + /* Verify that the CRC Length is higher than DataSize */ + if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos)) + { + return HAL_ERROR; + } + } + else + { + crc_length = hspi->Init.DataSize << SPI_CFG1_CRCSIZE_Pos; + } +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_SPI_CRC == 0) + /* Keep the default value of CRCSIZE in case of CRC is not used */ + crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; +#endif /* USE_SPI_CRC */ + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + Communication speed, First bit, CRC calculation state, CRC Length */ + + /* SPIx NSS Software Management Configuration */ + if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \ + (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \ + ((hspi->Init.Mode == SPI_MODE_SLAVE) && \ + (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH)))) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI); + } + + /* SPIx Master Rx Auto Suspend Configuration */ + if (((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) && (hspi->Init.DataSize >= SPI_DATASIZE_8BIT)) + { + MODIFY_REG(hspi->Instance->CR1, SPI_CR1_MASRX, hspi->Init.MasterReceiverAutoSusp); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_MASRX); + } + + /* SPIx CFG1 Configuration */ + WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length | + hspi->Init.FifoThreshold | hspi->Init.DataSize)); + + /* SPIx CFG2 Configuration */ + WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | + hspi->Init.NSSPolarity | hspi->Init.NSS | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | + hspi->Init.FirstBit | hspi->Init.Mode | + hspi->Init.MasterInterDataIdleness | hspi->Init.Direction | + hspi->Init.MasterSSIdleness | hspi->Init.IOSwap)); + +#if (USE_SPI_CRC != 0UL) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Initialize TXCRC Pattern Initial Value */ + if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI); + } + + /* Initialize RXCRC Pattern Initial Value */ + if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI); + } + + /* Enable 33/17 bits CRC computation */ + if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) || + ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT))) + { + /* Set SPI_CR1_CRC33_17 bit */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + /* Write CRC polynomial in SPI Register */ + WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); + } + else + { + /* Clear SPI_CR1_CRC33_17 bit */ + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + + /* Write CRC polynomial and set MSB bit at 1 in SPI Register */ + /* Set MSB is mandatory for a correct CRC computation */ + crc_poly_msb_mask = (0x1UL << ((crc_length >> SPI_CFG1_CRCSIZE_Pos) + 0x1U)); + WRITE_REG(hspi->Instance->CRCPOLY, (hspi->Init.CRCPolynomial) | crc_poly_msb_mask); + } + } +#endif /* USE_SPI_CRC */ + + /* Insure that Underrun configuration is managed only by Salve */ + if (hspi->Init.Mode == SPI_MODE_SLAVE) + { + /* Set Default Underrun configuration */ +#if (USE_SPI_CRC != 0UL) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_DISABLE) +#endif /* USE_SPI_CRC */ + { + MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0); + } + MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG_1); + } + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + /* Insure that AFCNTR is managed only by Master */ + if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) + { + /* Alternate function GPIOs control */ + MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState)); + } + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initialize the SPI peripheral. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Initialize the SPI MSP. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ +} + +/** + * @brief De-Initialize the SPI MSP. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file + */ +} + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @note The HAL_SPI_RegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET + * to register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @note The HAL_SPI_UnRegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET + * to un-register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (##) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (##) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData : pointer to data buffer + * @param Size : amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); +#endif /* __GNUC__ */ + + uint32_t tickstart; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = (uint16_t) 0UL; + hspi->RxXferCount = (uint16_t) 0UL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + else + { + SPI_2LINES_TX(hspi); + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Transmit data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + /* Transmit data in 32 Bit mode */ + while (hspi->TxXferCount > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) + { + if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount -= (uint16_t)2UL; + } + else + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 8 Bit mode */ + else + { + while (hspi->TxXferCount > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) + { + if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount -= (uint16_t)4UL; + } + else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= (uint16_t)2UL; + } + else + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + + /* Wait for Tx (and CRC) data to be sent */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData : pointer to data buffer + * @param Size : amount of data to be received + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t temp_sr_reg; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); +#endif /* __GNUC__ */ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else + { + SPI_2LINES_RX(hspi); + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Receive data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0UL) + { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + /* Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0UL) + { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + /* Receive data in 8 Bit mode */ + else + { + /* Transfer loop */ + while (hspi->RxXferCount > 0UL) + { + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((hspi->RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + +#if (USE_SPI_CRC != 0UL) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait for crc data to be received */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + } +#endif /* USE_SPI_CRC */ + + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent and received + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); +#endif /* __GNUC__ */ + + uint32_t tickstart; + uint32_t fifo_length; + uint32_t temp_sr_reg; + uint16_t initial_TxXferCount; + uint16_t initial_RxXferCount; + uint16_t init_max_data_in_fifo; + init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + initial_TxXferCount = Size; + initial_RxXferCount = Size; + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + + /* Initialize FIFO length */ + if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) + { + fifo_length = SPI_HIGHEND_FIFO_SIZE; + } + else + { + fifo_length = SPI_LOWEND_FIFO_SIZE; + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + __HAL_SPI_ENABLE(hspi); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Transmit and Receive data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + /* Adapt fifo length to 32bits data width */ + fifo_length = (fifo_length / 4UL); + + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) + { + /* Check TXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount --; + initial_TxXferCount = hspi->TxXferCount; + } + + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + if (initial_RxXferCount > 0UL) + { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + } + /* Transmit and Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Adapt fifo length to 16bits data width */ + fifo_length = (fifo_length / 2UL); + + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) + { + /* Check the TXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; + } + + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + if (initial_RxXferCount > 0UL) + { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= (uint16_t)2UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) + { + /* Check the TXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; + } + + /* Evaluate state of SR register */ + temp_sr_reg = hspi->Instance->SR; + + if (initial_RxXferCount > 0UL) + { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXWNE flag if RXP cannot be reached */ + else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount -= (uint16_t)4UL; + initial_RxXferCount = hspi->RxXferCount; + } + /* Check RXPLVL flags when RXWNE cannot be reached */ + else if ((initial_RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + } + + /* Wait for Tx/Rx (and CRC) data to be sent/received */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = (uint16_t) 0UL; + hspi->RxXferCount = (uint16_t) 0UL; + hspi->RxISR = NULL; + +#if defined(USE_SPI_RELOAD_TRANSFER) + hspi->Reload.Requested = 0UL; + hspi->Reload.pTxBuffPtr = NULL; + hspi->Reload.TxXferSize = NULL; +#endif /* USE_SPI_RELOAD_TRANSFER */ + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + hspi->TxISR = SPI_TxISR_32BIT; + } + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + else + { + SPI_2LINES_TX(hspi); + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + /* Enable EOT, TXP, FRE, MODF, UDR and TSERF interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + hspi->TxISR = NULL; + +#if defined(USE_SPI_RELOAD_TRANSFER) + hspi->Reload.Requested = 0UL; + hspi->Reload.pRxBuffPtr = NULL; + hspi->Reload.RxXferSize = NULL; +#endif /* USE_SPI_RELOAD_TRANSFER */ + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + hspi->RxISR = SPI_RxISR_32BIT; + } + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else + { + SPI_2LINES_RX(hspi); + } + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + /* Enable EOT, RXP, OVR, FRE, MODF and TSERF interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_TxXferCount; +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); +#endif /* __GNUC__ */ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + tmp_TxXferCount = hspi->TxXferCount; + +#if defined(USE_SPI_RELOAD_TRANSFER) + hspi->Reload.Requested = 0UL; + hspi->Reload.pRxBuffPtr = NULL; + hspi->Reload.RxXferSize = NULL; + hspi->Reload.pTxBuffPtr = NULL; + hspi->Reload.TxXferSize = NULL; +#endif /* USE_SPI_RELOAD_TRANSFER */ + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + hspi->TxISR = SPI_TxISR_32BIT; + hspi->RxISR = SPI_RxISR_32BIT; + } + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_RxISR_16BIT; + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + /* Fill in the TxFIFO */ + while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL)) + { + /* Transmit data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + /* Transmit data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + /* Transmit data in 8 Bit mode */ + else + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + /* Enable EOT, DXP, UDR, OVR, FRE, MODF and TSERF interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | + SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Start Master transfer */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + return HAL_OK; +} + +#if defined(USE_SPI_RELOAD_TRANSFER) +/** + * @brief Transmit an additional amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + /* check if there is already a request to reload */ + if ((hspi->Reload.Requested == 1UL) || (pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + if (hspi->State == HAL_SPI_STATE_BUSY_TX) + { + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Insert the new number of data to be sent just after the current one */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL); + + /* Set the transaction information */ + hspi->Reload.Requested = 1UL; + hspi->Reload.pTxBuffPtr = (const uint8_t *)pData; + hspi->Reload.TxXferSize = Size; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +#endif /* USE_SPI_RELOAD_TRANSFER */ + +#if defined(USE_SPI_RELOAD_TRANSFER) +/** + * @brief Receive an additional amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + /* check if there is already a request to reload */ + if ((hspi->Reload.Requested == 1UL) || (pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Insert the new number of data that will be received just after the current one */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL); + + /* Set the transaction information */ + hspi->Reload.Requested = 1UL; + hspi->Reload.pRxBuffPtr = (uint8_t *)pData; + hspi->Reload.RxXferSize = Size; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +#endif /* USE_SPI_RELOAD_TRANSFER */ + +#if defined(USE_SPI_RELOAD_TRANSFER) +/** + * @brief Transmit and receive an additional amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, + uint8_t *pRxData, uint16_t Size) +{ + /* check if there is already a request to reload */ + if ((hspi->Reload.Requested == 1UL) || (pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + if (hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Insert the new number of data that will be sent and received just after the current one */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL); + + /* Set the transaction information */ + hspi->Reload.Requested = 1UL; + hspi->Reload.pTxBuffPtr = (const uint8_t *)pTxData; + hspi->Reload.TxXferSize = Size; + hspi->Reload.pRxBuffPtr = (uint8_t *)pRxData; + hspi->Reload.RxXferSize = Size; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +#endif /* USE_SPI_RELOAD_TRANSFER */ + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = NULL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = (uint16_t)0UL; + hspi->RxXferCount = (uint16_t)0UL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + else + { + SPI_2LINES_TX(hspi); + } + + /* Packing mode management is enabled by the DMA settings */ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ + (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)))) + { + /* Restriction the DMA data received is not allowed in this mode */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Adjust XferCount according to DMA alignment / Data size */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL; + } + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Clear TXDMAEN bit*/ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Set the number of data at current transfer */ + if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR) + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); + } + else + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + __HAL_UNLOCK(hspi); + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else + { + SPI_2LINES_RX(hspi); + } + + /* Packing mode management is enabled by the DMA settings */ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ + (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)))) + { + /* Restriction the DMA data received is not allowed in this mode */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Clear RXDMAEN bit */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Adjust XferCount according to DMA alignment / Data size */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL; + } + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Set the number of data at current transfer */ + if (hspi->hdmarx->Init.Mode == DMA_CIRCULAR) + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); + } + else + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + + /* Reset the Tx/Rx DMA bits */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Packing mode management is enabled by the DMA settings */ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && \ + ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD) || \ + (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && \ + (((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ + (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ + ((hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \ + (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))) + { + /* Restriction the DMA data received is not allowed in this mode */ + /* Unlock the process */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Adjust XferCount according to DMA alignment / Data size */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL; + } + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL; + } + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount)) + { + /* Abort Rx DMA Channel already started */ + (void)HAL_DMA_Abort(hspi->hdmarx); + + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR) + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); + } + else + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * @note This procedure performs following operations : + * + Disable SPI Interrupts (depending of transfer direction) + * + Disable the DMA transfer in the peripheral register (if enabled) + * + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * + Set handle State to READY. + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + + __IO uint32_t count; + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set hspi->state to aborting to avoid any interaction */ + hspi->State = HAL_SPI_STATE_ABORT; + + /* Initialized local variable */ + errorcode = HAL_OK; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + + /* If master communication on going, make sure current frame is done before closing the connection */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) + { + if (hspi->hdmatx != NULL) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + if (hspi->hdmarx != NULL) + { + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + } + } + + /* Proceed with abort procedure */ + SPI_AbortTransfer(hspi); + + /* Check error during Abort procedure */ + if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * @note This procedure performs following operations : + * + Disable SPI Interrupts (depending of transfer direction) + * + Disable the DMA transfer in the peripheral register (if enabled) + * + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * + Set handle State to READY + * + At abort completion, call user abort complete callback. + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + __IO uint32_t count; + uint32_t dma_tx_abort_done = 1UL; + uint32_t dma_rx_abort_done = 1UL; + + /* Set hspi->state to aborting to avoid any interaction */ + hspi->State = HAL_SPI_STATE_ABORT; + + /* Initialized local variable */ + errorcode = HAL_OK; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + + /* If master communication on going, make sure current frame is done before closing the connection */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); + } + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized + before any call to DMA Abort functions */ + + if (hspi->hdmatx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Tx request if enabled */ + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + + dma_tx_abort_done = 0UL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER) + { + dma_tx_abort_done = 1UL; + hspi->hdmatx->XferAbortCallback = NULL; + } + } + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + + if (hspi->hdmarx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */ + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + + dma_rx_abort_done = 0UL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER) + { + dma_rx_abort_done = 1UL; + hspi->hdmarx->XferAbortCallback = NULL; + } + } + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* If no running DMA transfer, finish cleanup and call callbacks */ + if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL)) + { + /* Proceed with abort procedure */ + SPI_AbortTransfer(hspi); + + /* Check error during Abort procedure */ + if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. + * This API is not supported, it is maintained for backward compatibility. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL_ERROR + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Set error code to not supported */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); + + return HAL_ERROR; +} + +/** + * @brief Resume the DMA Transfer. + * This API is not supported, it is maintained for backward compatibility. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL_ERROR + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Set error code to not supported */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); + + return HAL_ERROR; +} + +/** + * @brief Stop the DMA Transfer. + * This API is not supported, it is maintained for backward compatibility. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL_ERROR + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + /* Set error code to not supported */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); + + return HAL_ERROR; +} + +/** + * @brief Handle SPI interrupt request. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + uint32_t itsource = hspi->Instance->IER; + uint32_t itflag = hspi->Instance->SR; + uint32_t trigger = itsource & itflag; + uint32_t cfg1 = hspi->Instance->CFG1; + uint32_t handled = 0UL; + + HAL_SPI_StateTypeDef State = hspi->State; +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); +#endif /* __GNUC__ */ + + /* SPI in SUSPEND mode ----------------------------------------------------*/ + if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT)) + { + /* Clear the Suspend flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + + /* Suspend on going, Call the Suspend callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->SuspendCallback(hspi); +#else + HAL_SPI_SuspendCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + + /* SPI in mode Transmitter and Receiver ------------------------------------*/ + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \ + HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP)) + { + hspi->TxISR(hspi); + hspi->RxISR(hspi); + handled = 1UL; + } + + /* SPI in mode Receiver ----------------------------------------------------*/ + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \ + HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) + { + hspi->RxISR(hspi); + handled = 1UL; + } + + /* SPI in mode Transmitter -------------------------------------------------*/ + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \ + HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) + { + hspi->TxISR(hspi); + handled = 1UL; + } + +#if defined(USE_SPI_RELOAD_TRANSFER) + /* SPI Reload -------------------------------------------------*/ + if (HAL_IS_BIT_SET(trigger, SPI_FLAG_TSERF)) + { + __HAL_SPI_CLEAR_TSERFFLAG(hspi); + } +#endif /* USE_SPI_RELOAD_TRANSFER */ + + if (handled != 0UL) + { + return; + } + + /* SPI End Of Transfer: DMA or IT based transfer */ + if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT)) + { + /* Clear EOT/TXTF/SUSP flag */ + __HAL_SPI_CLEAR_EOTFLAG(hspi); + __HAL_SPI_CLEAR_TXTFFLAG(hspi); + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + + /* For the IT based receive extra polling maybe required for last packet */ + if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) + { + /* Pooling remaining data */ + while (hspi->RxXferCount != 0UL) + { + /* Receive data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + } + /* Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + } + /* Receive data in 8 Bit mode */ + else + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + } + + hspi->RxXferCount--; + } + } + + /* Call SPI Standard close procedure */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + /* Call appropriate user callback */ + if (State == HAL_SPI_STATE_BUSY_TX_RX) + { + hspi->TxRxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_RX) + { + hspi->RxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_TX) + { + hspi->TxCpltCallback(hspi); + } +#else + /* Call appropriate user callback */ + if (State == HAL_SPI_STATE_BUSY_TX_RX) + { + HAL_SPI_TxRxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_RX) + { + HAL_SPI_RxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_TX) + { + HAL_SPI_TxCpltCallback(hspi); + } +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + else + { + /* End of the appropriate call */ + } + + return; + } + + /* SPI in Error Treatment --------------------------------------------------*/ + if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL) + { + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if ((trigger & SPI_FLAG_OVR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if ((trigger & SPI_FLAG_MODF) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if ((trigger & SPI_FLAG_FRE) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + /* SPI Underrun error interrupt occurred ------------------------------------*/ + if ((trigger & SPI_FLAG_UDR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR); + __HAL_SPI_CLEAR_UDRFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF | + SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR)); + + /* Disable the SPI DMA requests if enabled */ + if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) + { + /* Disable the SPI DMA requests */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + } + else + { + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Half Transfer callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief SPI error callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SPI Suspend callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_SuspendCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI handle state. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI handle state */ + return hspi->State; +} + +/** + * @brief Return the SPI error code. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI error code in bitmap format + */ +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI ErrorCode */ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hspi->State != HAL_SPI_STATE_ABORT) + { + if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Enable EOT interrupt */ + __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); + } + } +} + +/** + * @brief DMA SPI receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hspi->State != HAL_SPI_STATE_ABORT) + { + if (hspi->hdmarx->Init.Mode == DMA_CIRCULAR) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Enable EOT interrupt */ + __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); + } + } +} + +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hspi->State != HAL_SPI_STATE_ABORT) + { + if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Enable EOT interrupt */ + __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); + } + } +} + +/** + * @brief DMA SPI half transmit process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxHalfCpltCallback(hspi); +#else + HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->RxHalfCpltCallback(hspi); +#else + HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxRxHalfCpltCallback(hspi); +#else + HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication error callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* if DMA error is FIFO error ignore it */ + if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + /* Call SPI standard close procedure */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + hspi->RxXferCount = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hspi->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* Call the Abort procedure */ + SPI_AbortTransfer(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* Call the Abort procedure */ + SPI_AbortTransfer(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + *((uint8_t *)hspi->pRxBuffPtr) = (*(__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->RxXferCount == 0UL) + { +#if defined(USE_SPI_RELOAD_TRANSFER) + /* Check if there is any request to reload */ + if (hspi->Reload.Requested == 1UL) + { + hspi->RxXferSize = hspi->Reload.RxXferSize; + hspi->RxXferCount = hspi->Reload.RxXferSize; + hspi->pRxBuffPtr = hspi->Reload.pRxBuffPtr; + hspi->Reload.Requested = 0UL; + } + else + { + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); + } +#else + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); +#endif /* USE_SPI_RELOAD_TRANSFER */ + } +} + + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); + + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = (*(__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->RxXferCount == 0UL) + { +#if defined(USE_SPI_RELOAD_TRANSFER) + /* Check if there is any request to reload */ + if (hspi->Reload.Requested == 1UL) + { + hspi->RxXferSize = hspi->Reload.RxXferSize; + hspi->RxXferCount = hspi->Reload.RxXferSize; + hspi->pRxBuffPtr = hspi->Reload.pRxBuffPtr; + hspi->Reload.Requested = 0UL; + } + else + { + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); + } +#else + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); +#endif /* USE_SPI_RELOAD_TRANSFER */ + } +} + + +/** + * @brief Manage the 32-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 32 Bit mode */ + *((uint32_t *)hspi->pRxBuffPtr) = (*(__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->RxXferCount == 0UL) + { +#if defined(USE_SPI_RELOAD_TRANSFER) + /* Check if there is any request to reload */ + if (hspi->Reload.Requested == 1UL) + { + hspi->RxXferSize = hspi->Reload.RxXferSize; + hspi->RxXferCount = hspi->Reload.RxXferSize; + hspi->pRxBuffPtr = hspi->Reload.pRxBuffPtr; + hspi->Reload.Requested = 0UL; + } + else + { + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); + } +#else + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); +#endif /* USE_SPI_RELOAD_TRANSFER */ + } +} + + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 8 Bit mode */ + *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->TxXferCount == 0UL) + { +#if defined(USE_SPI_RELOAD_TRANSFER) + /* Check if there is any request to reload */ + if (hspi->Reload.Requested == 1UL) + { + hspi->TxXferSize = hspi->Reload.TxXferSize; + hspi->TxXferCount = hspi->Reload.TxXferSize; + hspi->pTxBuffPtr = hspi->Reload.pTxBuffPtr; + + /* In full duplex mode the reload request is reset in RX side */ + if (hspi->State == HAL_SPI_STATE_BUSY_TX) + { + hspi->Reload.Requested = 0UL; + } + } + else + { + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); + } +#else + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); +#endif /* USE_SPI_RELOAD_TRANSFER */ + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); + + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->TxXferCount == 0UL) + { +#if defined(USE_SPI_RELOAD_TRANSFER) + /* Check if there is any request to reload */ + if (hspi->Reload.Requested == 1UL) + { + hspi->TxXferSize = hspi->Reload.TxXferSize; + hspi->TxXferCount = hspi->Reload.TxXferSize; + hspi->pTxBuffPtr = hspi->Reload.pTxBuffPtr; + + /* In full duplex mode the reload request is reset in RX side */ + if (hspi->State == HAL_SPI_STATE_BUSY_TX) + { + hspi->Reload.Requested = 0UL; + } + } + else + { + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); + } +#else + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); +#endif /* USE_SPI_RELOAD_TRANSFER */ + } +} + +/** + * @brief Handle the data 32-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 32 Bit mode */ + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->TxXferCount == 0UL) + { +#if defined(USE_SPI_RELOAD_TRANSFER) + /* Check if there is any request to reload */ + if (hspi->Reload.Requested == 1UL) + { + hspi->TxXferSize = hspi->Reload.TxXferSize; + hspi->TxXferCount = hspi->Reload.TxXferSize; + hspi->pTxBuffPtr = hspi->Reload.pTxBuffPtr; + + /* In full duplex mode the reload request is reset in RX side */ + if (hspi->State == HAL_SPI_STATE_BUSY_TX) + { + hspi->Reload.Requested = 0UL; + } + } + else + { + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); + } +#else + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); +#endif /* USE_SPI_RELOAD_TRANSFER */ + } +} + +/** + * @brief Abort Transfer and clear flags. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi) +{ + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable ITs */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \ + SPI_IT_FRE | SPI_IT_MODF)); + + /* Clear the Status flags in the SR register */ + __HAL_SPI_CLEAR_EOTFLAG(hspi); + __HAL_SPI_CLEAR_TXTFFLAG(hspi); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_UDRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + +#if (USE_SPI_CRC != 0U) + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +#endif /* USE_SPI_CRC */ + + hspi->TxXferCount = (uint16_t)0UL; + hspi->RxXferCount = (uint16_t)0UL; +} + + +/** + * @brief Close Transfer and clear flags. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL_ERROR: if any error detected + * HAL_OK: if nothing detected + */ +static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi) +{ + uint32_t itflag = hspi->Instance->SR; + + __HAL_SPI_CLEAR_EOTFLAG(hspi); + __HAL_SPI_CLEAR_TXTFFLAG(hspi); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable ITs */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \ + SPI_IT_FRE | SPI_IT_MODF)); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Report UnderRun error for non RX Only communication */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + if ((itflag & SPI_FLAG_UDR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR); + __HAL_SPI_CLEAR_UDRFLAG(hspi); + } + } + + /* Report OverRun error for non TX Only communication */ + if (hspi->State != HAL_SPI_STATE_BUSY_TX) + { + if ((itflag & SPI_FLAG_OVR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +#if (USE_SPI_CRC != 0UL) + /* Check if CRC error occurred */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + if ((itflag & SPI_FLAG_CRCERR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } +#endif /* USE_SPI_CRC */ + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if ((itflag & SPI_FLAG_MODF) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if ((itflag & SPI_FLAG_FRE) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + hspi->TxXferCount = (uint16_t)0UL; + hspi->RxXferCount = (uint16_t)0UL; +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param Status: flag state to check + * @param Timeout: Timeout duration + * @param Tickstart: Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait until flag is set */ + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if ((((HAL_GetTick() - Tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Compute configured packet size from fifo perspective. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval Packet size occupied in the fifo + */ +static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi) +{ + uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; + uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL; + + /* Convert data size to Byte */ + data_size = (data_size + 7UL) / 8UL; + + return data_size * fifo_threashold; +} + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ Index: /ctrl/firmware/Main/CubeMX/charger.ioc =================================================================== --- /ctrl/firmware/Main/CubeMX/charger.ioc (revision 44) +++ /ctrl/firmware/Main/CubeMX/charger.ioc (revision 45) @@ -7,4 +7,24 @@ CORTEX_M7.IPParameters=default_mode_Activation,CPU_ICache,CPU_DCache CORTEX_M7.default_mode_Activation=1 +Dma.Request0=SPI4_TX +Dma.RequestsNb=1 +Dma.SPI4_TX.0.Direction=DMA_MEMORY_TO_PERIPH +Dma.SPI4_TX.0.EventEnable=DISABLE +Dma.SPI4_TX.0.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.SPI4_TX.0.Instance=DMA1_Stream0 +Dma.SPI4_TX.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD +Dma.SPI4_TX.0.MemInc=DMA_MINC_ENABLE +Dma.SPI4_TX.0.Mode=DMA_NORMAL +Dma.SPI4_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD +Dma.SPI4_TX.0.PeriphInc=DMA_PINC_DISABLE +Dma.SPI4_TX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.SPI4_TX.0.Priority=DMA_PRIORITY_LOW +Dma.SPI4_TX.0.RequestNumber=1 +Dma.SPI4_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.SPI4_TX.0.SignalID=NONE +Dma.SPI4_TX.0.SyncEnable=DISABLE +Dma.SPI4_TX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.SPI4_TX.0.SyncRequestNumber=1 +Dma.SPI4_TX.0.SyncSignalID=NONE File.Version=6 GPIO.groupedBy= @@ -15,10 +35,12 @@ Mcu.Family=STM32H7 Mcu.IP0=CORTEX_M7 -Mcu.IP1=MEMORYMAP -Mcu.IP2=NVIC -Mcu.IP3=RCC -Mcu.IP4=RTC -Mcu.IP5=SYS -Mcu.IPNb=6 +Mcu.IP1=DMA +Mcu.IP2=MEMORYMAP +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=RTC +Mcu.IP6=SPI4 +Mcu.IP7=SYS +Mcu.IPNb=8 Mcu.Name=STM32H723ZETx Mcu.Package=LQFP144 @@ -27,8 +49,11 @@ Mcu.Pin2=PH0-OSC_IN Mcu.Pin3=PH1-OSC_OUT -Mcu.Pin4=VP_RTC_VS_RTC_Activate -Mcu.Pin5=VP_SYS_VS_Systick -Mcu.Pin6=VP_MEMORYMAP_VS_MEMORYMAP -Mcu.PinsNb=7 +Mcu.Pin4=PE11 +Mcu.Pin5=PE12 +Mcu.Pin6=PE14 +Mcu.Pin7=VP_RTC_VS_RTC_Activate +Mcu.Pin8=VP_SYS_VS_Systick +Mcu.Pin9=VP_MEMORYMAP_VS_MEMORYMAP +Mcu.PinsNb=10 Mcu.ThirdPartyNb=0 Mcu.UserConstants= @@ -37,4 +62,5 @@ MxDb.Version=DB.6.0.130 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DMA1_Stream0_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.ForceEnableDMAVector=true @@ -44,4 +70,5 @@ NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SPI4_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false @@ -51,4 +78,19 @@ PC15-OSC32_OUT.Mode=LSE-External-Oscillator PC15-OSC32_OUT.Signal=RCC_OSC32_OUT +PE11.GPIOParameters=GPIO_Label +PE11.GPIO_Label=SPI4_NSS_DISPLAY +PE11.Locked=true +PE11.Mode=NSS_Signal_Hard_Output +PE11.Signal=SPI4_NSS +PE12.GPIOParameters=GPIO_Label +PE12.GPIO_Label=SPI4_SCK_DISPLAY +PE12.Locked=true +PE12.Mode=Simplex_Bidirectional_Master +PE12.Signal=SPI4_SCK +PE14.GPIOParameters=GPIO_Label +PE14.GPIO_Label=SPI4_MOSI_DISPLAY +PE14.Locked=true +PE14.Mode=Simplex_Bidirectional_Master +PE14.Signal=SPI4_MOSI PH0-OSC_IN.Mode=HSE-External-Oscillator PH0-OSC_IN.Signal=RCC_OSC_IN @@ -86,6 +128,6 @@ ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true -RCC.ADCFreq_Value=100000000 +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_RTC_Init-RTC-false-HAL-true,5-MX_SPI4_Init-SPI4-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.ADCFreq_Value=166666666.66666666 RCC.AHB12Freq_Value=100000000 RCC.AHB4Freq_Value=100000000 @@ -102,18 +144,19 @@ RCC.DFSDMACLkFreq_Value=100000000 RCC.DFSDMFreq_Value=100000000 -RCC.DIVM1=25 -RCC.DIVM2=25 +RCC.DIVM1=5 +RCC.DIVM2=3 RCC.DIVM3=25 -RCC.DIVN1=200 -RCC.DIVN2=200 +RCC.DIVN1=40 +RCC.DIVN2=40 RCC.DIVN3=200 RCC.DIVP1Freq_Value=100000000 -RCC.DIVP2Freq_Value=100000000 +RCC.DIVP2Freq_Value=166666666.66666666 RCC.DIVP3Freq_Value=100000000 RCC.DIVQ1Freq_Value=100000000 -RCC.DIVQ2Freq_Value=100000000 +RCC.DIVQ2=11 +RCC.DIVQ2Freq_Value=30303030.3030303 RCC.DIVQ3Freq_Value=100000000 RCC.DIVR1Freq_Value=100000000 -RCC.DIVR2Freq_Value=100000000 +RCC.DIVR2Freq_Value=166666666.66666666 RCC.DIVR3Freq_Value=100000000 RCC.FDCANFreq_Value=100000000 @@ -124,5 +167,5 @@ RCC.I2C123Freq_Value=100000000 RCC.I2C4Freq_Value=100000000 -RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value +RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Spi45ClockSelection,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value RCC.LPTIM1Freq_Value=100000000 RCC.LPTIM2Freq_Value=100000000 @@ -132,4 +175,6 @@ RCC.MCO1PinFreq_Value=64000000 RCC.MCO2PinFreq_Value=100000000 +RCC.PLL2FRACN=0 +RCC.PLLFRACN=0 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE RCC.QSPIFreq_Value=100000000 @@ -143,9 +188,10 @@ RCC.SPDIFRXFreq_Value=100000000 RCC.SPI123Freq_Value=100000000 -RCC.SPI45Freq_Value=100000000 +RCC.SPI45Freq_Value=30303030.3030303 RCC.SPI6Freq_Value=100000000 RCC.SWPMI1Freq_Value=100000000 RCC.SYSCLKFreq_VALUE=100000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.Spi45ClockSelection=RCC_SPI45CLKSOURCE_PLL2 RCC.Tim1OutputFreq_Value=100000000 RCC.Tim2OutputFreq_Value=100000000 @@ -155,9 +201,17 @@ RCC.USBFreq_Value=100000000 RCC.VCO1OutputFreq_Value=200000000 -RCC.VCO2OutputFreq_Value=200000000 +RCC.VCO2OutputFreq_Value=333333333.3333333 RCC.VCO3OutputFreq_Value=200000000 -RCC.VCOInput1Freq_Value=1000000 -RCC.VCOInput2Freq_Value=1000000 +RCC.VCOInput1Freq_Value=5000000 +RCC.VCOInput2Freq_Value=8333333.333333333 RCC.VCOInput3Freq_Value=1000000 +SPI4.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2 +SPI4.CalculateBaudRate=15.151515 MBits/s +SPI4.DataSize=SPI_DATASIZE_9BIT +SPI4.Direction=SPI_DIRECTION_1LINE +SPI4.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,DataSize,BaudRatePrescaler +SPI4.Mode=SPI_MODE_MASTER +SPI4.VirtualNSS=VM_NSSHARD +SPI4.VirtualType=VM_MASTER VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP Index: /ctrl/firmware/Main/SES/Output/Release/Exe/charger.hex =================================================================== --- /ctrl/firmware/Main/SES/Output/Release/Exe/charger.hex (revision 44) +++ /ctrl/firmware/Main/SES/Output/Release/Exe/charger.hex (revision 45) @@ -1,48 +1,48 @@ :020000040800F2 -:1000000000800030970B0008AD070008AD0700081E -:10001000AD070008AD070008AD07000800000000AC -:10002000000000000000000000000000AF07000812 -:10003000AF07000800000000AF070008070B00082A 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+:0C22EC00002A80F83410ACD09047A9E71D +:1022F800806B0021A0F86A10A0F86210012180F814 +:042308008110704789 +:10230C00FFF74BFB4EF68850CEF20000016851F4FB +:08231C0070010160FEF774FC82 +:102324000000000000000000010203040607080981 +:102334005923000800000030290100006B23000825 +:102344002C0100305423000804000000170C00087E +:042354000090D00322 +:10235800206861680834002200E042540139FCD545 +:022368007047BC +:10236A0020686168A2680C3401E08B5C8354013AEE +:04237A00FBD57047D8 +:040000050800230DBF :00000001FF Index: /ctrl/firmware/Main/SES/Output/Release/Exe/charger.htm =================================================================== --- /ctrl/firmware/Main/SES/Output/Release/Exe/charger.htm (revision 44) +++ /ctrl/firmware/Main/SES/Output/Release/Exe/charger.htm (revision 45) @@ -51,4 +51,5 @@
  • Module stm32h723xx_Vectors.o
  • Module SEGGER_crtinit.o (SEGGER_crtinit_v7em_fpv5_d16_hard_t_le_eabi_balanced.a)
    • +
  • Module strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a)
  • All modules
    • @@ -121,15 +122,22 @@
  • Section .vectors from stm32h723xx_Vectors.o, size=716, align=1024
  • Section .text.HAL_RCC_GetSysClockFreq from charger_lto.o, size=268, align=4
    • +
  • Section .text.HAL_RCCEx_PeriphCLKConfig from charger_lto.o, size=2100, align=4
  • Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4
    • -
  • Section .text.SystemClock_Config() from charger_lto.o, size=794, align=2
    • -
  • Section .text.SystemInit from charger_lto.o, size=166, align=2
    • +
  • Section .text.libc.__aeabi_memclr from strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a), size=104, align=4
    • +
  • Section .text.HAL_SPI_Init from charger_lto.o, size=1158, align=4
    • +
  • Section .text.main from charger_lto.o, size=1566, align=2
  • Section .text.NMI_Handler from charger_lto.o, size=2, align=2
  • Section .text.SVC_Handler from charger_lto.o, size=2, align=2
    • -
  • Section .text.HAL_Init from charger_lto.o, size=114, align=2
    • -
  • Section .text.HAL_RTC_Init from charger_lto.o, size=382, align=2
    • +
  • Section .text.SPI4_IRQHandler from charger_lto.o, size=630, align=2
    • +
  • Section .text.SystemInit from charger_lto.o, size=166, align=2
    • +
  • Section .text.HAL_InitTick from charger_lto.o, size=90, align=2
  • Section .text.HAL_RTC_WaitForSynchro from charger_lto.o, size=54, align=2
    • -
  • Section .text.main from charger_lto.o, size=304, align=2
  • Section .text.SysTick_Handler from charger_lto.o, size=16, align=2
    • -
  • Section .text.HAL_InitTick from charger_lto.o, size=128, align=2
    • +
  • Section .text.DMA1_Stream0_IRQHandler from charger_lto.o, size=1012, align=2
    • +
  • Section .text.HAL_NVIC_SetPriority from charger_lto.o, size=76, align=2
    • +
  • Section .text.RCCEx_PLL2_Config from charger_lto.o, size=272, align=2
    • +
  • Section .text.RCCEx_PLL3_Config from charger_lto.o, size=272, align=2
    • +
  • Section .text.HAL_DMA_Abort_IT from charger_lto.o, size=428, align=2
    • +
  • Section .text.SPI_DMAAbortOnError from charger_lto.o, size=20, align=2
  • Section .init.Reset_Handler from Cortex_M_Startup.o, size=24, align=2
  • Section .rodata.D1CorePrescTable from charger_lto.o, size=16, align=1
    • @@ -138,4 +146,6 @@
  • Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v7em_fpv5_d16_hard_t_le_eabi_balanced.a), size=18, align=2
  • Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v7em_fpv5_d16_hard_t_le_eabi_balanced.a), size=20, align=2
    • +
  • Section .bss.hspi4 from charger_lto.o, size=136, align=4
    • +
  • Section .bss.hdma_spi4_tx from charger_lto.o, size=120, align=4
  • Section .bss.hrtc from charger_lto.o, size=36, align=4
  • Section .bss.uwTick from charger_lto.o, size=4, align=4
    • @@ -409,7 +419,15 @@ + HAL_RCCEx_PeriphCLKConfig + Code + 0x080003D8 + 2 100 + 4 + charger_lto.o + + _start Code - 0x080003D8 + 0x08000C0C 20 4 @@ -417,8 +435,48 @@ - SystemClock_Config() - Code - 0x080003EC - 794 + __aeabi_memclr + Code + 0x08000C20 + 104 + 4 + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + HAL_SPI_Init + Code + 0x08000C88 + 1 158 + 4 + charger_lto.o + + + main + Code + 0x0800110E + 1 566 + 2 + charger_lto.o + + + NMI_Handler + Code + 0x0800172C + 2 + 2 + charger_lto.o + + + SVC_Handler + Code + 0x0800172E + 2 + 2 + charger_lto.o + + + SPI4_IRQHandler + Code + 0x08001730 + 630 2 charger_lto.o @@ -427,5 +485,5 @@ SystemInit Code - 0x08000706 + 0x080019A6 166 2 @@ -433,32 +491,8 @@ - NMI_Handler - Code - 0x080007AC - 2 - 2 - charger_lto.o - - - SVC_Handler - Code - 0x080007AE - 2 - 2 - charger_lto.o - - - HAL_Init - Code - 0x080007B0 - 114 - 2 - charger_lto.o - - - HAL_RTC_Init - Code - 0x08000822 - 382 + HAL_InitTick + Code + 0x08001A4C + 90 2 charger_lto.o @@ -467,5 +501,5 @@ HAL_RTC_WaitForSynchro Code - 0x080009A0 + 0x08001AA6 54 2 @@ -473,15 +507,7 @@ - main - Code - 0x080009D6 - 304 - 2 - charger_lto.o - - SysTick_Handler Code - 0x08000B06 + 0x08001ADC 16 2 @@ -489,8 +515,48 @@ - HAL_InitTick - Code - 0x08000B16 - 128 + DMA1_Stream0_IRQHandler + Code + 0x08001AEC + 1 012 + 2 + charger_lto.o + + + HAL_NVIC_SetPriority + Code + 0x08001EE0 + 76 + 2 + charger_lto.o + + + RCCEx_PLL2_Config + Code + 0x08001F2C + 272 + 2 + charger_lto.o + + + RCCEx_PLL3_Config + Code + 0x0800203C + 272 + 2 + charger_lto.o + + + HAL_DMA_Abort_IT + Code + 0x0800214C + 428 + 2 + charger_lto.o + + + SPI_DMAAbortOnError + Code + 0x080022F8 + 20 2 charger_lto.o @@ -499,5 +565,5 @@ Reset_Handler Code - 0x08000B96 + 0x0800230C 24 2 @@ -507,5 +573,5 @@ D1CorePrescTable Cnst - 0x08000BAE + 0x08002324 16 1 @@ -515,5 +581,5 @@ [.rodata.block.tdata.copy] Cnst - 0x08000BAE + 0x08002324 1 @@ -523,5 +589,5 @@ __SEGGER_init_table__ Cnst - 0x08000BC0 + 0x08002334 32 4 @@ -531,5 +597,5 @@ __SEGGER_init_data__ Cnst - 0x08000BE0 + 0x08002354 4 4 @@ -539,5 +605,5 @@ __SEGGER_init_zero Code - 0x08000BE4 + 0x08002358 18 2 @@ -547,5 +613,5 @@ __SEGGER_init_copy Code - 0x08000BF6 + 0x0800236A 20 2 @@ -564,7 +630,23 @@ + hspi4 + Zero + 0x30000000 + 136 + 4 + charger_lto.o + + + hdma_spi4_tx + Zero + 0x30000088 + 120 + 4 + charger_lto.o + + hrtc Zero - 0x30000000 + 0x30000100 36 4 @@ -574,5 +656,5 @@ uwTick Zero - 0x30000024 + 0x30000124 4 4 @@ -582,5 +664,5 @@ uwTickPrio Zero - 0x30000028 + 0x30000128 1 4 @@ -590,5 +672,5 @@ SystemCoreClock Init - 0x3000002C + 0x3000012C 4 4 @@ -598,5 +680,5 @@ [.bss.block.heap] None - 0x30000030 + 0x30000130 8 @@ -633,5 +715,5 @@ [.bss.block.heap] None - 0x30000030 + 0x30000130 8 @@ -651,8 +733,8 @@ charger_lto.o - 2 230 + 8 132 16 4 - 41 + 297 @@ -679,8 +761,8 @@ Subtotal (4 objects) - 2 990 + 8 892 16 4 - 41 + 297 @@ -692,6 +774,13 @@ - Subtotal (1 archives) - 38 + strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a + 104 + + + + + + Subtotal (2 archives) + 142 @@ -707,8 +796,8 @@ Total: - 3 028 + 9 034 52 4 - 8 233 + 8 489 @@ -730,6 +819,13 @@ - Subtotal (1 members from 1 archives) - 38 + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + 104 + + + + + + Subtotal (2 members from 2 archives) + 142 @@ -738,8 +834,8 @@ Objects (4 files) - 2 990 + 8 892 16 4 - 41 + 297 @@ -752,8 +848,8 @@ Total: - 3 028 + 9 034 52 4 - 8 233 + 8 489 @@ -790,12 +886,12 @@ Objects (4 files) - 2 990 + 8 892 16 4 - 41 - - - Archives (1 files) - 38 + 297 + + + Archives (2 files) + 142 @@ -804,8 +900,8 @@ Total: - 3 028 + 9 034 52 4 - 8 233 + 8 489 @@ -821,13 +917,6 @@ - SystemClock_Config() - 794 - - - - - - HAL_RTC_Init - 382 + HAL_RCCEx_PeriphCLKConfig + 2 100 @@ -836,5 +925,47 @@ main - 304 + 1 566 + + + + + + HAL_SPI_Init + 1 158 + + + + + + DMA1_Stream0_IRQHandler + 1 012 + + + + + + SPI4_IRQHandler + 630 + + + + + + HAL_DMA_Abort_IT + 428 + + + + + + RCCEx_PLL2_Config + 272 + + + + + + RCCEx_PLL3_Config + 272 @@ -857,12 +988,12 @@ HAL_InitTick - 128 - - - - - - HAL_Init - 114 + 90 + + + + + + HAL_NVIC_SetPriority + 76 @@ -877,4 +1008,11 @@ + SPI_DMAAbortOnError + 20 + + + + + SysTick_Handler 16 @@ -912,4 +1050,18 @@ + hspi4 + + + + 136 + + + hdma_spi4_tx + + + + 120 + + hrtc @@ -934,8 +1086,8 @@ Total: - 2 230 + 8 132 16 4 - 41 + 297 @@ -1043,4 +1195,28 @@ +

    Module strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a)

    + + + + + + + + + + + + + + + + + + + + + + +
    Symbol or [section] nameCodeRO DataRW DataZI Data
    __aeabi_memclr104
    Total:104

    All modules

    @@ -1054,8 +1230,8 @@ - + - +
    Grand total:3 0289 034 16 441297
    @@ -1091,5 +1267,14 @@ - 080003d8-080003eb + 080003d8-08000c0b + HAL_RCCEx_PeriphCLKConfig + 2 100 + 4 + Code + RX + charger_lto.o + + + 08000c0c-08000c1f _start 20 @@ -1100,14 +1285,59 @@ - 080003ec-08000705 - SystemClock_Config() - 794 - 2 + 08000c20-08000c87 + __aeabi_memclr + 104 + 4 Code RX - charger_lto.o - - - 08000706-080007ab + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + 08000c88-0800110d + HAL_SPI_Init + 1 158 + 4 + Code + RX + charger_lto.o + + + 0800110e-0800172b + main + 1 566 + 2 + Code + RX + charger_lto.o + + + 0800172c-0800172d + NMI_Handler + 2 + 2 + Code + RX + charger_lto.o + + + 0800172e-0800172f + SVC_Handler + 2 + 2 + Code + RX + charger_lto.o + + + 08001730-080019a5 + SPI4_IRQHandler + 630 + 2 + Code + RX + charger_lto.o + + + 080019a6-08001a4b SystemInit 166 @@ -1118,7 +1348,7 @@ - 080007ac-080007ad - NMI_Handler - 2 + 08001a4c-08001aa5 + HAL_InitTick + 90 2 Code @@ -1127,32 +1357,5 @@ - 080007ae-080007af - SVC_Handler - 2 - 2 - Code - RX - charger_lto.o - - - 080007b0-08000821 - HAL_Init - 114 - 2 - Code - RX - charger_lto.o - - - 08000822-0800099f - HAL_RTC_Init - 382 - 2 - Code - RX - charger_lto.o - - - 080009a0-080009d5 + 08001aa6-08001adb HAL_RTC_WaitForSynchro 54 @@ -1163,14 +1366,5 @@ - 080009d6-08000b05 - main - 304 - 2 - Code - RX - charger_lto.o - - - 08000b06-08000b15 + 08001adc-08001aeb SysTick_Handler 16 @@ -1181,7 +1375,7 @@ - 08000b16-08000b95 - HAL_InitTick - 128 + 08001aec-08001edf + DMA1_Stream0_IRQHandler + 1 012 2 Code @@ -1190,5 +1384,50 @@ - 08000b96-08000bad + 08001ee0-08001f2b + HAL_NVIC_SetPriority + 76 + 2 + Code + RX + charger_lto.o + + + 08001f2c-0800203b + RCCEx_PLL2_Config + 272 + 2 + Code + RX + charger_lto.o + + + 0800203c-0800214b + RCCEx_PLL3_Config + 272 + 2 + Code + RX + charger_lto.o + + + 0800214c-080022f7 + HAL_DMA_Abort_IT + 428 + 2 + Code + RX + charger_lto.o + + + 080022f8-0800230b + SPI_DMAAbortOnError + 20 + 2 + Code + RX + charger_lto.o + + + 0800230c-08002323 Reset_Handler 24 @@ -1199,5 +1438,5 @@ - 08000bae-08000bbd + 08002324-08002333 D1CorePrescTable 16 @@ -1208,14 +1447,5 @@ - 08000bbe-08000bbf - ( UNUSED .=.+2 ) - 2 - - - ---- - - - - - - - 08000bc0-08000bdf + 08002334-08002353 __SEGGER_init_table__ 32 @@ -1226,5 +1456,5 @@ - 08000be0-08000be3 + 08002354-08002357 __SEGGER_init_data__ 4 @@ -1235,5 +1465,5 @@ - 08000be4-08000bf5 + 08002358-08002369 __SEGGER_init_zero 18 @@ -1244,5 +1474,5 @@ - 08000bf6-08000c09 + 0800236a-0800237d __SEGGER_init_copy 20 @@ -1253,7 +1483,7 @@ - 08000c0a-2fffffff - ( UNUSED .=.+671085558 ) - 671 085 558 + 0800237e-2fffffff + ( UNUSED .=.+671079554 ) + 671 079 554 - ---- @@ -1262,5 +1492,23 @@ - 30000000-30000023 + 30000000-30000087 + hspi4 + 136 + 4 + Zero + ZI + charger_lto.o + + + 30000088-300000ff + hdma_spi4_tx + 120 + 4 + Zero + ZI + charger_lto.o + + + 30000100-30000123 hrtc 36 @@ -1271,5 +1519,5 @@ - 30000024-30000027 + 30000124-30000127 uwTick 4 @@ -1280,5 +1528,5 @@ - 30000028-30000028 + 30000128-30000128 uwTickPrio 1 @@ -1289,5 +1537,5 @@ - 30000029-3000002b + 30000129-3000012b ( ALIGN .=.+3 ) 3 @@ -1298,5 +1546,5 @@ - 3000002c-3000002f + 3000012c-3000012f SystemCoreClock 4 @@ -1307,7 +1555,7 @@ - 30000030-30005fff - ( UNUSED .=.+24528 ) - 24 528 + 30000130-30005fff + ( UNUSED .=.+24272 ) + 24 272 - ---- @@ -1334,15 +1582,10 @@ - 08000bbe-08000bbf - 2 - Unused memory between sections '.rodata.D1CorePrescTable' and '.segger.init.table' - - - 08000c0a-2fffffff - 671 085 558 - Unused memory between sections '.segger.init.__SEGGER_init_copy' and '.bss.hrtc' - - - 30000029-3000002b + 0800237e-2fffffff + 671 079 554 + Unused memory between sections '.segger.init.__SEGGER_init_copy' and '.bss.hspi4' + + + 30000129-3000012b 3 Filler between sections '.bss.uwTickPrio' and '.data.SystemCoreClock' as align=4 @@ -1354,6 +1597,6 @@ - 30000030-30005fff - 24 528 + 30000130-30005fff + 24 272 Unused memory between sections '.data.SystemCoreClock' and '.bss.block.stack' @@ -1368,22 +1611,32 @@ - 30000000-30000023 + 30000000-30000087 + 136 + hspi4 + + + 30000088-300000ff + 120 + hdma_spi4_tx + + + 30000100-30000123 36 hrtc - 30000024-30000027 + 30000124-30000127 4 uwTick - 30000028-30000028 + 30000128-30000128 1 uwTickPrio - 30000000-30000028 - 41 - Total (3 sections) + 30000000-30000128 + 297 + Total (5 sections)

    Initialize by copy with packing=none

    @@ -1395,10 +1648,10 @@ - 3000002c-3000002f + 3000012c-3000012f 4 SystemCoreClock - 3000002c-3000002f + 3000012c-3000012f 4 Total (1 sections) @@ -1421,9 +1674,9 @@ Destination image - 45 bytes + 301 bytes Saving - 9 bytes + 265 bytes @@ -1522,5 +1775,5 @@ ADC3_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1531,5 +1784,5 @@ ADC_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1540,5 +1793,5 @@ BDMA_Channel0_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1549,5 +1802,5 @@ BDMA_Channel1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1558,5 +1811,5 @@ BDMA_Channel2_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1567,5 +1820,5 @@ BDMA_Channel3_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1576,5 +1829,5 @@ BDMA_Channel4_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1585,5 +1838,5 @@ BDMA_Channel5_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1594,5 +1847,5 @@ BDMA_Channel6_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1603,5 +1856,5 @@ BDMA_Channel7_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1612,5 +1865,5 @@ BusFault_Handler - 0x080007AD + 0x0800172D 2 2 @@ -1621,5 +1874,5 @@ CEC_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1630,5 +1883,5 @@ COMP1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1639,5 +1892,5 @@ CORDIC_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1648,5 +1901,5 @@ CRS_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1657,5 +1910,5 @@ DCMI_PSSI_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1666,5 +1919,5 @@ DFSDM1_FLT0_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1675,5 +1928,5 @@ DFSDM1_FLT1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1684,5 +1937,5 @@ DFSDM1_FLT2_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1693,5 +1946,5 @@ DFSDM1_FLT3_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1702,14 +1955,14 @@ DMA1_Stream0_IRQHandler - 0x080007AD - - 2 - Code - Wk - stm32h723xx_Vectors.o + 0x08001AED + 1 012 + 2 + Code + Gb + charger_lto.o DMA1_Stream1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1720,5 +1973,5 @@ DMA1_Stream2_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1729,5 +1982,5 @@ DMA1_Stream3_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1738,5 +1991,5 @@ DMA1_Stream4_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1747,5 +2000,5 @@ DMA1_Stream5_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1756,5 +2009,5 @@ DMA1_Stream6_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1765,5 +2018,5 @@ DMA1_Stream7_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1774,5 +2027,5 @@ DMA2D_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1783,5 +2036,5 @@ DMA2_Stream0_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1792,5 +2045,5 @@ DMA2_Stream1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1801,5 +2054,5 @@ DMA2_Stream2_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1810,5 +2063,5 @@ DMA2_Stream3_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1819,5 +2072,5 @@ DMA2_Stream4_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1828,5 +2081,5 @@ DMA2_Stream5_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1837,5 +2090,5 @@ DMA2_Stream6_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1846,5 +2099,5 @@ DMA2_Stream7_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1855,5 +2108,5 @@ DMAMUX1_OVR_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1864,5 +2117,5 @@ DMAMUX2_OVR_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1873,5 +2126,5 @@ DTS_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1882,5 +2135,5 @@ DebugMon_Handler - 0x080007AF + 0x0800172F 2 2 @@ -1891,5 +2144,5 @@ ECC_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1900,5 +2153,5 @@ ETH_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1909,5 +2162,5 @@ ETH_WKUP_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1918,5 +2171,5 @@ EXTI0_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1927,5 +2180,5 @@ EXTI15_10_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1936,5 +2189,5 @@ EXTI1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1945,5 +2198,5 @@ EXTI2_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1954,5 +2207,5 @@ EXTI3_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1963,5 +2216,5 @@ EXTI4_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1972,5 +2225,5 @@ EXTI9_5_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1981,5 +2234,5 @@ FDCAN1_IT0_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1990,5 +2243,5 @@ FDCAN1_IT1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -1999,5 +2252,5 @@ FDCAN2_IT0_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2008,5 +2261,5 @@ FDCAN2_IT1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2017,5 +2270,5 @@ FDCAN3_IT0_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2026,5 +2279,5 @@ FDCAN3_IT1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2035,5 +2288,5 @@ FDCAN_CAL_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2044,5 +2297,5 @@ FLASH_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2053,5 +2306,5 @@ FMAC_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2062,5 +2315,5 @@ FMC_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2071,15 +2324,15 @@ FPU_IRQHandler - 0x080007AD - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - HAL_Init - 0x080007B1 - 114 + 0x0800172D + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + HAL_DMA_Abort_IT + 0x0800214D + 428 2 Code @@ -2089,7 +2342,25 @@ HAL_InitTick - 0x08000B17 - 128 - 2 + 0x08001A4D + 90 + 2 + Code + Lc + charger_lto.o + + + HAL_NVIC_SetPriority + 0x08001EE1 + 76 + 2 + Code + Lc + charger_lto.o + + + HAL_RCCEx_PeriphCLKConfig + 0x080003D9 + 2 100 + 4 Code Lc @@ -2106,7 +2377,7 @@ - HAL_RTC_Init - 0x08000823 - 382 + HAL_RTC_WaitForSynchro + 0x08001AA7 + 54 2 Code @@ -2115,8 +2386,8 @@ - HAL_RTC_WaitForSynchro - 0x080009A1 - 54 - 2 + HAL_SPI_Init + 0x08000C89 + 1 158 + 4 Code Lc @@ -2125,5 +2396,5 @@ HSEM1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2134,5 +2405,5 @@ HardFault_Handler - 0x080007AD + 0x0800172D 2 2 @@ -2143,5 +2414,5 @@ I2C1_ER_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2152,5 +2423,5 @@ I2C1_EV_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2161,5 +2432,5 @@ I2C2_ER_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2170,5 +2441,5 @@ I2C2_EV_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2179,5 +2450,5 @@ I2C3_ER_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2188,5 +2459,5 @@ I2C3_EV_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2197,5 +2468,5 @@ I2C4_ER_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2206,5 +2477,5 @@ I2C4_EV_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2215,5 +2486,5 @@ I2C5_ER_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2224,5 +2495,5 @@ I2C5_EV_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2233,5 +2504,5 @@ LPTIM1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2242,5 +2513,5 @@ LPTIM2_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2251,5 +2522,5 @@ LPTIM3_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2260,5 +2531,5 @@ LPTIM4_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2269,5 +2540,5 @@ LPTIM5_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2278,5 +2549,5 @@ LPUART1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2287,5 +2558,5 @@ LTDC_ER_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2296,5 +2567,5 @@ LTDC_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2305,5 +2576,5 @@ MDIOS_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2314,5 +2585,5 @@ MDIOS_WKUP_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2323,5 +2594,5 @@ MDMA_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2332,5 +2603,5 @@ MemManage_Handler - 0x080007AD + 0x0800172D 2 2 @@ -2341,5 +2612,5 @@ NMI_Handler - 0x080007AD + 0x0800172D 2 2 @@ -2350,5 +2621,5 @@ OCTOSPI1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2359,5 +2630,5 @@ OCTOSPI2_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2368,5 +2639,5 @@ OTG_HS_EP1_IN_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2377,5 +2648,5 @@ OTG_HS_EP1_OUT_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2386,5 +2657,5 @@ OTG_HS_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2395,5 +2666,5 @@ OTG_HS_WKUP_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2404,5 +2675,5 @@ PVD_AVD_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2413,14 +2684,32 @@ PendSV_Handler - 0x080007AF - 2 - 2 - Code - Gb + 0x0800172F + 2 + 2 + Code + Gb + charger_lto.o + + + RCCEx_PLL2_Config + 0x08001F2D + 272 + 2 + Code + Lc + charger_lto.o + + + RCCEx_PLL3_Config + 0x0800203D + 272 + 2 + Code + Lc charger_lto.o RCC_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2431,5 +2720,5 @@ RNG_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2440,5 +2729,5 @@ RTC_Alarm_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2449,5 +2738,5 @@ RTC_WKUP_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2458,5 +2747,5 @@ Reset_Handler - 0x08000B97 + 0x0800230D 24 2 @@ -2467,5 +2756,5 @@ SAI1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2476,5 +2765,5 @@ SAI4_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2485,5 +2774,5 @@ SDMMC1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2494,5 +2783,5 @@ SDMMC2_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2503,5 +2792,5 @@ SPDIF_RX_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2512,5 +2801,5 @@ SPI1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2521,5 +2810,5 @@ SPI2_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2530,5 +2819,5 @@ SPI3_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2539,14 +2828,14 @@ SPI4_IRQHandler - 0x080007AD - - 2 - Code - Wk - stm32h723xx_Vectors.o + 0x08001731 + 630 + 2 + Code + Gb + charger_lto.o SPI5_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2557,14 +2846,23 @@ SPI6_IRQHandler - 0x080007AD - - 2 - Code - Wk - stm32h723xx_Vectors.o + 0x0800172D + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + SPI_DMAAbortOnError + 0x080022F9 + 20 + 2 + Code + Lc + charger_lto.o SVC_Handler - 0x080007AF + 0x0800172F 2 2 @@ -2575,5 +2873,5 @@ SWPMI1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2584,5 +2882,5 @@ SysTick_Handler - 0x08000B07 + 0x08001ADD 16 2 @@ -2592,15 +2890,6 @@ - SystemClock_Config() - 0x080003ED - 794 - 2 - Code - Lc - charger_lto.o - - SystemInit - 0x08000707 + 0x080019A7 166 2 @@ -2611,5 +2900,5 @@ TAMP_STAMP_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2620,5 +2909,5 @@ TIM15_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2629,5 +2918,5 @@ TIM16_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2638,5 +2927,5 @@ TIM17_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2647,5 +2936,5 @@ TIM1_BRK_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2656,5 +2945,5 @@ TIM1_CC_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2665,5 +2954,5 @@ TIM1_TRG_COM_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2674,5 +2963,5 @@ TIM1_UP_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2683,5 +2972,5 @@ TIM23_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2692,5 +2981,5 @@ TIM24_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2701,5 +2990,5 @@ TIM2_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2710,5 +2999,5 @@ TIM3_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2719,5 +3008,5 @@ TIM4_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2728,5 +3017,5 @@ TIM5_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2737,5 +3026,5 @@ TIM6_DAC_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2746,5 +3035,5 @@ TIM7_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2755,5 +3044,5 @@ TIM8_BRK_TIM12_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2764,5 +3053,5 @@ TIM8_CC_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2773,5 +3062,5 @@ TIM8_TRG_COM_TIM14_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2782,5 +3071,5 @@ TIM8_UP_TIM13_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2791,5 +3080,5 @@ UART4_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2800,5 +3089,5 @@ UART5_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2809,5 +3098,5 @@ UART7_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2818,5 +3107,5 @@ UART8_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2827,5 +3116,5 @@ UART9_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2836,5 +3125,5 @@ USART10_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2845,5 +3134,5 @@ USART1_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2854,5 +3143,5 @@ USART2_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2863,5 +3152,5 @@ USART3_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2872,5 +3161,5 @@ USART6_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2881,5 +3170,5 @@ UsageFault_Handler - 0x080007AD + 0x0800172D 2 2 @@ -2890,5 +3179,5 @@ WAKEUP_PIN_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2899,5 +3188,5 @@ WWDG_IRQHandler - 0x080007AD + 0x0800172D 2 @@ -2908,5 +3197,5 @@ __SEGGER_init_copy - 0x08000BF7 + 0x0800236B 20 2 @@ -2917,5 +3206,5 @@ __SEGGER_init_done - 0x080003E3 + 0x08000C17 4 @@ -2926,5 +3215,5 @@ __SEGGER_init_zero - 0x08000BE5 + 0x08002359 18 2 @@ -2934,6 +3223,60 @@ + __aeabi_memclr + 0x08000C21 + 104 + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + __aeabi_memclr4 + 0x08000C21 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + __aeabi_memclr8 + 0x08000C21 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + __aeabi_memset + 0x08000C23 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + __aeabi_memset4 + 0x08000C23 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + __aeabi_memset8 + 0x08000C23 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + __startup_complete - 0x080003E3 + 0x08000C17 4 @@ -2944,5 +3287,5 @@ _start - 0x080003D9 + 0x08000C0D 14 4 @@ -2953,5 +3296,5 @@ exit - 0x080003E7 + 0x08000C1B 2 4 @@ -2962,14 +3305,23 @@ main - 0x080009D7 - 304 - 2 - Code - Gb - charger_lto.o + 0x0800110F + 1 566 + 2 + Code + Gb + charger_lto.o + + + memset + 0x08000C29 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) reset_handler - 0x08000B97 + 0x0800230D 24 2 @@ -3001,4 +3353,13 @@ 0x080003D9 + HAL_RCCEx_PeriphCLKConfig + 2 100 + 4 + Code + Lc + charger_lto.o + + + 0x08000C0D _start 14 @@ -3009,5 +3370,5 @@ - 0x080003E3 + 0x08000C17 __startup_complete @@ -3018,5 +3379,5 @@ - 0x080003E3 + 0x08000C17 __SEGGER_init_done @@ -3027,5 +3388,5 @@ - 0x080003E7 + 0x08000C1B exit 2 @@ -3036,8 +3397,71 @@ - 0x080003ED - SystemClock_Config() - 794 - 2 + 0x08000C21 + __aeabi_memclr8 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + 0x08000C21 + __aeabi_memclr4 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + 0x08000C21 + __aeabi_memclr + 104 + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + 0x08000C23 + __aeabi_memset8 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + 0x08000C23 + __aeabi_memset4 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + 0x08000C23 + __aeabi_memset + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + 0x08000C29 + memset + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + 0x08000C89 + HAL_SPI_Init + 1 158 + 4 Code Lc @@ -3045,5 +3469,1310 @@ - 0x08000707 + 0x0800110F + main + 1 566 + 2 + Code + Gb + charger_lto.o + + + 0x0800172D + WWDG_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + WAKEUP_PIN_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + UsageFault_Handler + 2 + 2 + Code + Gb + charger_lto.o + + + 0x0800172D + USART6_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + USART3_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + USART2_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + USART1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + USART10_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + UART9_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + UART8_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + UART7_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + UART5_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + UART4_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM8_UP_TIM13_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM8_TRG_COM_TIM14_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM8_CC_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM8_BRK_TIM12_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM7_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM6_DAC_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM5_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM4_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM3_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM2_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM24_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM23_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM1_UP_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM1_TRG_COM_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM1_CC_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM1_BRK_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM17_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM16_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TIM15_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + TAMP_STAMP_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + SWPMI1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + SPI6_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + SPI5_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + SPI3_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + SPI2_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + SPI1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + SPDIF_RX_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + SDMMC2_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + SDMMC1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + SAI4_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + SAI1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + RTC_WKUP_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + RTC_Alarm_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + RNG_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + RCC_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + PVD_AVD_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + OTG_HS_WKUP_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + OTG_HS_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + OTG_HS_EP1_OUT_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + OTG_HS_EP1_IN_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + OCTOSPI2_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + OCTOSPI1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + NMI_Handler + 2 + 2 + Code + Gb + charger_lto.o + + + 0x0800172D + MemManage_Handler + 2 + 2 + Code + Gb + charger_lto.o + + + 0x0800172D + MDMA_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + MDIOS_WKUP_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + MDIOS_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + LTDC_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + LTDC_ER_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + LPUART1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + LPTIM5_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + LPTIM4_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + LPTIM3_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + LPTIM2_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + LPTIM1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + I2C5_EV_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + I2C5_ER_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + I2C4_EV_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + I2C4_ER_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + I2C3_EV_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + I2C3_ER_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + I2C2_EV_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + I2C2_ER_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + I2C1_EV_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + I2C1_ER_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + HardFault_Handler + 2 + 2 + Code + Gb + charger_lto.o + + + 0x0800172D + HSEM1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + FPU_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + FMC_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + FMAC_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + FLASH_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + FDCAN_CAL_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + FDCAN3_IT1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + FDCAN3_IT0_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + FDCAN2_IT1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + FDCAN2_IT0_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + FDCAN1_IT1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + FDCAN1_IT0_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + EXTI9_5_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + EXTI4_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + EXTI3_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + EXTI2_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + EXTI1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + EXTI15_10_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + EXTI0_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + ETH_WKUP_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + ETH_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + ECC_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DTS_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMAMUX2_OVR_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMAMUX1_OVR_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA2_Stream7_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA2_Stream6_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA2_Stream5_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA2_Stream4_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA2_Stream3_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA2_Stream2_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA2_Stream1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA2_Stream0_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA2D_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA1_Stream7_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA1_Stream6_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA1_Stream5_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA1_Stream4_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA1_Stream3_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA1_Stream2_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DMA1_Stream1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DFSDM1_FLT3_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DFSDM1_FLT2_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DFSDM1_FLT1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DFSDM1_FLT0_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + DCMI_PSSI_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + CRS_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + CORDIC_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + COMP1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + CEC_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + BusFault_Handler + 2 + 2 + Code + Gb + charger_lto.o + + + 0x0800172D + BDMA_Channel7_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + BDMA_Channel6_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + BDMA_Channel5_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + BDMA_Channel4_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + BDMA_Channel3_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + BDMA_Channel2_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + BDMA_Channel1_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + BDMA_Channel0_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + ADC_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172D + ADC3_IRQHandler + + 2 + Code + Wk + stm32h723xx_Vectors.o + + + 0x0800172F + SVC_Handler + 2 + 2 + Code + Gb + charger_lto.o + + + 0x0800172F + PendSV_Handler + 2 + 2 + Code + Gb + charger_lto.o + + + 0x0800172F + DebugMon_Handler + 2 + 2 + Code + Gb + charger_lto.o + + + 0x08001731 + SPI4_IRQHandler + 630 + 2 + Code + Gb + charger_lto.o + + + 0x080019A7 SystemInit 166 @@ -3054,1312 +4783,7 @@ - 0x080007AD - WWDG_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - WAKEUP_PIN_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - UsageFault_Handler - 2 - 2 - Code - Gb - charger_lto.o - - - 0x080007AD - USART6_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - USART3_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - USART2_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - USART1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - USART10_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - UART9_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - UART8_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - UART7_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - UART5_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - UART4_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM8_UP_TIM13_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM8_TRG_COM_TIM14_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM8_CC_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM8_BRK_TIM12_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM7_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM6_DAC_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM5_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM4_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM3_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM2_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM24_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM23_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM1_UP_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM1_TRG_COM_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM1_CC_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM1_BRK_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM17_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM16_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TIM15_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - TAMP_STAMP_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - SWPMI1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - SPI6_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - SPI5_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - SPI4_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - SPI3_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - SPI2_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - SPI1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - SPDIF_RX_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - SDMMC2_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - SDMMC1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - SAI4_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - SAI1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - RTC_WKUP_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - RTC_Alarm_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - RNG_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - RCC_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - PVD_AVD_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - OTG_HS_WKUP_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - OTG_HS_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - OTG_HS_EP1_OUT_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - OTG_HS_EP1_IN_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - OCTOSPI2_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - OCTOSPI1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - NMI_Handler - 2 - 2 - Code - Gb - charger_lto.o - - - 0x080007AD - MemManage_Handler - 2 - 2 - Code - Gb - charger_lto.o - - - 0x080007AD - MDMA_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - MDIOS_WKUP_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - MDIOS_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - LTDC_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - LTDC_ER_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - LPUART1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - LPTIM5_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - LPTIM4_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - LPTIM3_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - LPTIM2_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - LPTIM1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - I2C5_EV_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - I2C5_ER_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - I2C4_EV_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - I2C4_ER_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - I2C3_EV_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - I2C3_ER_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - I2C2_EV_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - I2C2_ER_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - I2C1_EV_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - I2C1_ER_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - HardFault_Handler - 2 - 2 - Code - Gb - charger_lto.o - - - 0x080007AD - HSEM1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - FPU_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - FMC_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - FMAC_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - FLASH_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - FDCAN_CAL_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - FDCAN3_IT1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - FDCAN3_IT0_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - FDCAN2_IT1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - FDCAN2_IT0_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - FDCAN1_IT1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - FDCAN1_IT0_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - EXTI9_5_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - EXTI4_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - EXTI3_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - EXTI2_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - EXTI1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - EXTI15_10_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - EXTI0_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - ETH_WKUP_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - ETH_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - ECC_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DTS_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMAMUX2_OVR_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMAMUX1_OVR_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA2_Stream7_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA2_Stream6_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA2_Stream5_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA2_Stream4_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA2_Stream3_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA2_Stream2_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA2_Stream1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA2_Stream0_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA2D_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA1_Stream7_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA1_Stream6_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA1_Stream5_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA1_Stream4_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA1_Stream3_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA1_Stream2_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA1_Stream1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DMA1_Stream0_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DFSDM1_FLT3_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DFSDM1_FLT2_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DFSDM1_FLT1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DFSDM1_FLT0_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - DCMI_PSSI_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - CRS_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - CORDIC_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - COMP1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - CEC_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - BusFault_Handler - 2 - 2 - Code - Gb - charger_lto.o - - - 0x080007AD - BDMA_Channel7_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - BDMA_Channel6_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - BDMA_Channel5_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - BDMA_Channel4_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - BDMA_Channel3_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - BDMA_Channel2_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - BDMA_Channel1_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - BDMA_Channel0_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - ADC_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AD - ADC3_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - - 0x080007AF - SVC_Handler - 2 - 2 - Code - Gb - charger_lto.o - - - 0x080007AF - PendSV_Handler - 2 - 2 - Code - Gb - charger_lto.o - - - 0x080007AF - DebugMon_Handler - 2 - 2 - Code - Gb - charger_lto.o - - - 0x080007B1 - HAL_Init - 114 + 0x08001A4D + HAL_InitTick + 90 2 Code @@ -4368,14 +4792,5 @@ - 0x08000823 - HAL_RTC_Init - 382 - 2 - Code - Lc - charger_lto.o - - - 0x080009A1 + 0x08001AA7 HAL_RTC_WaitForSynchro 54 @@ -4386,14 +4801,5 @@ - 0x080009D7 - main - 304 - 2 - Code - Gb - charger_lto.o - - - 0x08000B07 + 0x08001ADD SysTick_Handler 16 @@ -4404,7 +4810,16 @@ - 0x08000B17 - HAL_InitTick - 128 + 0x08001AED + DMA1_Stream0_IRQHandler + 1 012 + 2 + Code + Gb + charger_lto.o + + + 0x08001EE1 + HAL_NVIC_SetPriority + 76 2 Code @@ -4413,5 +4828,41 @@ - 0x08000B97 + 0x08001F2D + RCCEx_PLL2_Config + 272 + 2 + Code + Lc + charger_lto.o + + + 0x0800203D + RCCEx_PLL3_Config + 272 + 2 + Code + Lc + charger_lto.o + + + 0x0800214D + HAL_DMA_Abort_IT + 428 + 2 + Code + Lc + charger_lto.o + + + 0x080022F9 + SPI_DMAAbortOnError + 20 + 2 + Code + Lc + charger_lto.o + + + 0x0800230D reset_handler 24 @@ -4422,5 +4873,5 @@ - 0x08000B97 + 0x0800230D Reset_Handler 24 @@ -4431,5 +4882,5 @@ - 0x08000BE5 + 0x08002359 __SEGGER_init_zero 18 @@ -4440,5 +4891,5 @@ - 0x08000BF7 + 0x0800236B __SEGGER_init_copy 20 @@ -4460,7 +4911,7 @@ - SystemClock_Config() - 794 - 2 + HAL_RCCEx_PeriphCLKConfig + 2 100 + 4 Code Lc @@ -4468,7 +4919,15 @@ - HAL_RTC_Init - 382 - 2 + main + 1 566 + 2 + Code + Gb + charger_lto.o + + + HAL_SPI_Init + 1 158 + 4 Code Lc @@ -4476,9 +4935,41 @@ - main - 304 - 2 - Code - Gb + DMA1_Stream0_IRQHandler + 1 012 + 2 + Code + Gb + charger_lto.o + + + SPI4_IRQHandler + 630 + 2 + Code + Gb + charger_lto.o + + + HAL_DMA_Abort_IT + 428 + 2 + Code + Lc + charger_lto.o + + + RCCEx_PLL2_Config + 272 + 2 + Code + Lc + charger_lto.o + + + RCCEx_PLL3_Config + 272 + 2 + Code + Lc charger_lto.o @@ -4500,6 +4991,14 @@ + __aeabi_memclr + 104 + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + HAL_InitTick - 128 + 90 2 Code @@ -4508,6 +5007,6 @@ - HAL_Init - 114 + HAL_NVIC_SetPriority + 76 2 Code @@ -4538,4 +5037,12 @@ Gb Cortex_M_Startup.o + + + SPI_DMAAbortOnError + 20 + 2 + Code + Lc + charger_lto.o @@ -4796,12 +5303,4 @@ - DMA1_Stream0_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - DMA1_Stream1_IRQHandler @@ -5452,12 +5951,4 @@ - SPI4_IRQHandler - - 2 - Code - Wk - stm32h723xx_Vectors.o - - SPI5_IRQHandler @@ -5748,4 +6239,44 @@ + __aeabi_memclr4 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + __aeabi_memclr8 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + __aeabi_memset + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + __aeabi_memset4 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + + __aeabi_memset8 + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) + + __startup_complete @@ -5754,4 +6285,12 @@ Gb SEGGER_THUMB_Startup.o + + + memset + + 4 + Code + Wk + strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a) @@ -5769,5 +6308,5 @@ SystemCoreClock - 0x3000002C + 0x3000012C 4 4 @@ -5777,6 +6316,15 @@ + hdma_spi4_tx + 0x30000088 + 120 + 4 + Zero + Lc + charger_lto.o + + hrtc - 0x30000000 + 0x30000100 36 4 @@ -5786,6 +6334,15 @@ + hspi4 + 0x30000000 + 136 + 4 + Zero + Lc + charger_lto.o + + uwTick - 0x30000024 + 0x30000124 4 4 @@ -5796,5 +6353,5 @@ uwTickPrio - 0x30000028 + 0x30000128 1 4 @@ -5817,4 +6374,22 @@ 0x30000000 + hspi4 + 136 + 4 + Zero + Lc + charger_lto.o + + + 0x30000088 + hdma_spi4_tx + 120 + 4 + Zero + Lc + charger_lto.o + + + 0x30000100 hrtc 36 @@ -5825,5 +6400,5 @@ - 0x30000024 + 0x30000124 uwTick 4 @@ -5834,5 +6409,5 @@ - 0x30000028 + 0x30000128 uwTickPrio 1 @@ -5843,5 +6418,5 @@ - 0x3000002C + 0x3000012C SystemCoreClock 4 @@ -5861,4 +6436,20 @@ Bd Object File + + + hspi4 + 136 + 4 + Zero + Lc + charger_lto.o + + + hdma_spi4_tx + 120 + 4 + Zero + Lc + charger_lto.o @@ -5908,5 +6499,5 @@ D1CorePrescTable - 0x08000BAE + 0x08002324 16 @@ -5917,5 +6508,5 @@ __SEGGER_init_data__ - 0x08000BE0 + 0x08002354 [4] 4 @@ -5926,5 +6517,5 @@ __SEGGER_init_table__ - 0x08000BC0 + 0x08002334 [32] 4 @@ -5946,5 +6537,5 @@ - 0x08000BAE + 0x08002324 D1CorePrescTable 16 @@ -5955,5 +6546,5 @@ - 0x08000BC0 + 0x08002334 __SEGGER_init_table__ [32] @@ -5964,5 +6555,5 @@ - 0x08000BE0 + 0x08002354 __SEGGER_init_data__ [4] @@ -6175,5 +6766,5 @@ __FLASH1_segment_used_end__ - 0x08000C0A + 0x0800237E @@ -6184,5 +6775,5 @@ __FLASH1_segment_used_size__ - 0x00000C0A + 0x0000237E @@ -6229,5 +6820,5 @@ __FLASH_segment_used_end__ - 0x08000C0A + 0x0800237E @@ -6238,5 +6829,5 @@ __FLASH_segment_used_size__ - 0x00000C0A + 0x0000237E @@ -6663,22 +7254,4 @@ - 0x00000C0A - __FLASH_segment_used_size__ - - - ---- - Gb - [ Linker created ] - - - 0x00000C0A - __FLASH1_segment_used_size__ - - - ---- - Gb - [ Linker created ] - - 0x00001000 __Backup_RAM_segment_size__ @@ -6692,4 +7265,22 @@ 0x00002000 __STACKSIZE__ + + + ---- + Gb + [ Linker created ] + + + 0x0000237E + __FLASH_segment_used_size__ + + + ---- + Gb + [ Linker created ] + + + 0x0000237E + __FLASH1_segment_used_size__ @@ -6852,5 +7443,5 @@ - 0x08000C0A + 0x0800237E __FLASH_segment_used_end__ @@ -6861,5 +7452,5 @@ - 0x08000C0A + 0x0800237E __FLASH1_segment_used_end__ @@ -7232,12 +7823,15 @@

    Functions without stack size information

    - HAL_Init - SystemClock_Config() - HAL_RTC_Init HAL_RCC_GetSysClockFreq HAL_InitTick + HAL_RCCEx_PeriphCLKConfig HAL_RTC_WaitForSynchro + HAL_SPI_Init + SPI_DMAAbortOnError + HAL_DMA_Abort_IT + HAL_NVIC_SetPriority + RCCEx_PLL2_Config + RCCEx_PLL3_Config main - SystemInit NMI_Handler HardFault_Handler @@ -7249,4 +7843,7 @@ PendSV_Handler SysTick_Handler + DMA1_Stream0_IRQHandler + SPI4_IRQHandler + SystemInit Reset_Handler reset_handler @@ -7266,5 +7863,4 @@ EXTI3_IRQHandler EXTI4_IRQHandler - DMA1_Stream0_IRQHandler DMA1_Stream1_IRQHandler DMA1_Stream2_IRQHandler @@ -7333,5 +7929,4 @@ UART7_IRQHandler UART8_IRQHandler - SPI4_IRQHandler SPI5_IRQHandler SPI6_IRQHandler @@ -7394,4 +7989,11 @@ __SEGGER_init_zero __SEGGER_init_copy + __aeabi_memclr + __aeabi_memclr8 + __aeabi_memclr4 + __aeabi_memset8 + __aeabi_memset4 + __aeabi_memset + memset

    UNUSED INPUTS

    Unused object files

    @@ -7400,13 +8002,13 @@

    Section .vectors from stm32h723xx_Vectors.o, size=716, align=1024

    -
    _vectors:
+
    _vectors:
   0x08000000:  30008000     DC.W       0x30008000               ; R_ARM_ABS32
-  0x08000004:  08000B97     DC.W       Reset_Handler
-  0x08000008:  080007AD     DC.W       NMI_Handler
-  0x0800000C:  080007AD     DC.W       NMI_Handler
-  0x08000010:  080007AD     DC.W       NMI_Handler
-  0x08000014:  080007AD     DC.W       NMI_Handler
-  0x08000018:  080007AD     DC.W       NMI_Handler
+  0x08000004:  0800230D     DC.W       Reset_Handler
+  0x08000008:  0800172D     DC.W       NMI_Handler
+  0x0800000C:  0800172D     DC.W       NMI_Handler
+  0x08000010:  0800172D     DC.W       NMI_Handler
+  0x08000014:  0800172D     DC.W       NMI_Handler
+  0x08000018:  0800172D     DC.W       NMI_Handler
   0x0800001C:  00           DC.B       0x00                     ; '\0'
   0x0800001D:  00           DC.B       0x00                     ; '\0'
@@ -7425,79 +8027,79 @@
   0x0800002A:  00           DC.B       0x00                     ; '\0'
   0x0800002B:  00           DC.B       0x00                     ; '\0'
-  0x0800002C:  080007AF     DC.W       SVC_Handler
-  0x08000030:  080007AF     DC.W       SVC_Handler
+  0x0800002C:  0800172F     DC.W       SVC_Handler
+  0x08000030:  0800172F     DC.W       SVC_Handler
   0x08000034:  00           DC.B       0x00                     ; '\0'
   0x08000035:  00           DC.B       0x00                     ; '\0'
   0x08000036:  00           DC.B       0x00                     ; '\0'
   0x08000037:  00           DC.B       0x00                     ; '\0'
-  0x08000038:  080007AF     DC.W       SVC_Handler
-  0x0800003C:  08000B07     DC.W       SysTick_Handler
-  0x08000040:  080007AD     DC.W       NMI_Handler
-  0x08000044:  080007AD     DC.W       NMI_Handler
-  0x08000048:  080007AD     DC.W       NMI_Handler
-  0x0800004C:  080007AD     DC.W       NMI_Handler
-  0x08000050:  080007AD     DC.W       NMI_Handler
-  0x08000054:  080007AD     DC.W       NMI_Handler
-  0x08000058:  080007AD     DC.W       NMI_Handler
-  0x0800005C:  080007AD     DC.W       NMI_Handler
-  0x08000060:  080007AD     DC.W       NMI_Handler
-  0x08000064:  080007AD     DC.W       NMI_Handler
-  0x08000068:  080007AD     DC.W       NMI_Handler
-  0x0800006C:  080007AD     DC.W       NMI_Handler
-  0x08000070:  080007AD     DC.W       NMI_Handler
-  0x08000074:  080007AD     DC.W       NMI_Handler
-  0x08000078:  080007AD     DC.W       NMI_Handler
-  0x0800007C:  080007AD     DC.W       NMI_Handler
-  0x08000080:  080007AD     DC.W       NMI_Handler
-  0x08000084:  080007AD     DC.W       NMI_Handler
-  0x08000088:  080007AD     DC.W       NMI_Handler
-  0x0800008C:  080007AD     DC.W       NMI_Handler
-  0x08000090:  080007AD     DC.W       NMI_Handler
-  0x08000094:  080007AD     DC.W       NMI_Handler
-  0x08000098:  080007AD     DC.W       NMI_Handler
-  0x0800009C:  080007AD     DC.W       NMI_Handler
-  0x080000A0:  080007AD     DC.W       NMI_Handler
-  0x080000A4:  080007AD     DC.W       NMI_Handler
-  0x080000A8:  080007AD     DC.W       NMI_Handler
-  0x080000AC:  080007AD     DC.W       NMI_Handler
-  0x080000B0:  080007AD     DC.W       NMI_Handler
-  0x080000B4:  080007AD     DC.W       NMI_Handler
-  0x080000B8:  080007AD     DC.W       NMI_Handler
-  0x080000BC:  080007AD     DC.W       NMI_Handler
-  0x080000C0:  080007AD     DC.W       NMI_Handler
-  0x080000C4:  080007AD     DC.W       NMI_Handler
-  0x080000C8:  080007AD     DC.W       NMI_Handler
-  0x080000CC:  080007AD     DC.W       NMI_Handler
-  0x080000D0:  080007AD     DC.W       NMI_Handler
-  0x080000D4:  080007AD     DC.W       NMI_Handler
-  0x080000D8:  080007AD     DC.W       NMI_Handler
-  0x080000DC:  080007AD     DC.W       NMI_Handler
-  0x080000E0:  080007AD     DC.W       NMI_Handler
-  0x080000E4:  080007AD     DC.W       NMI_Handler
+  0x08000038:  0800172F     DC.W       SVC_Handler
+  0x0800003C:  08001ADD     DC.W       SysTick_Handler
+  0x08000040:  0800172D     DC.W       NMI_Handler
+  0x08000044:  0800172D     DC.W       NMI_Handler
+  0x08000048:  0800172D     DC.W       NMI_Handler
+  0x0800004C:  0800172D     DC.W       NMI_Handler
+  0x08000050:  0800172D     DC.W       NMI_Handler
+  0x08000054:  0800172D     DC.W       NMI_Handler
+  0x08000058:  0800172D     DC.W       NMI_Handler
+  0x0800005C:  0800172D     DC.W       NMI_Handler
+  0x08000060:  0800172D     DC.W       NMI_Handler
+  0x08000064:  0800172D     DC.W       NMI_Handler
+  0x08000068:  0800172D     DC.W       NMI_Handler
+  0x0800006C:  08001AED     DC.W       DMA1_Stream0_IRQHandler
+  0x08000070:  0800172D     DC.W       NMI_Handler
+  0x08000074:  0800172D     DC.W       NMI_Handler
+  0x08000078:  0800172D     DC.W       NMI_Handler
+  0x0800007C:  0800172D     DC.W       NMI_Handler
+  0x08000080:  0800172D     DC.W       NMI_Handler
+  0x08000084:  0800172D     DC.W       NMI_Handler
+  0x08000088:  0800172D     DC.W       NMI_Handler
+  0x0800008C:  0800172D     DC.W       NMI_Handler
+  0x08000090:  0800172D     DC.W       NMI_Handler
+  0x08000094:  0800172D     DC.W       NMI_Handler
+  0x08000098:  0800172D     DC.W       NMI_Handler
+  0x0800009C:  0800172D     DC.W       NMI_Handler
+  0x080000A0:  0800172D     DC.W       NMI_Handler
+  0x080000A4:  0800172D     DC.W       NMI_Handler
+  0x080000A8:  0800172D     DC.W       NMI_Handler
+  0x080000AC:  0800172D     DC.W       NMI_Handler
+  0x080000B0:  0800172D     DC.W       NMI_Handler
+  0x080000B4:  0800172D     DC.W       NMI_Handler
+  0x080000B8:  0800172D     DC.W       NMI_Handler
+  0x080000BC:  0800172D     DC.W       NMI_Handler
+  0x080000C0:  0800172D     DC.W       NMI_Handler
+  0x080000C4:  0800172D     DC.W       NMI_Handler
+  0x080000C8:  0800172D     DC.W       NMI_Handler
+  0x080000CC:  0800172D     DC.W       NMI_Handler
+  0x080000D0:  0800172D     DC.W       NMI_Handler
+  0x080000D4:  0800172D     DC.W       NMI_Handler
+  0x080000D8:  0800172D     DC.W       NMI_Handler
+  0x080000DC:  0800172D     DC.W       NMI_Handler
+  0x080000E0:  0800172D     DC.W       NMI_Handler
+  0x080000E4:  0800172D     DC.W       NMI_Handler
   0x080000E8:  00           DC.B       0x00                     ; '\0'
   0x080000E9:  00           DC.B       0x00                     ; '\0'
   0x080000EA:  00           DC.B       0x00                     ; '\0'
   0x080000EB:  00           DC.B       0x00                     ; '\0'
-  0x080000EC:  080007AD     DC.W       NMI_Handler
-  0x080000F0:  080007AD     DC.W       NMI_Handler
-  0x080000F4:  080007AD     DC.W       NMI_Handler
-  0x080000F8:  080007AD     DC.W       NMI_Handler
-  0x080000FC:  080007AD     DC.W       NMI_Handler
-  0x08000100:  080007AD     DC.W       NMI_Handler
-  0x08000104:  080007AD     DC.W       NMI_Handler
-  0x08000108:  080007AD     DC.W       NMI_Handler
-  0x0800010C:  080007AD     DC.W       NMI_Handler
-  0x08000110:  080007AD     DC.W       NMI_Handler
-  0x08000114:  080007AD     DC.W       NMI_Handler
-  0x08000118:  080007AD     DC.W       NMI_Handler
-  0x0800011C:  080007AD     DC.W       NMI_Handler
-  0x08000120:  080007AD     DC.W       NMI_Handler
-  0x08000124:  080007AD     DC.W       NMI_Handler
-  0x08000128:  080007AD     DC.W       NMI_Handler
-  0x0800012C:  080007AD     DC.W       NMI_Handler
-  0x08000130:  080007AD     DC.W       NMI_Handler
-  0x08000134:  080007AD     DC.W       NMI_Handler
-  0x08000138:  080007AD     DC.W       NMI_Handler
-  0x0800013C:  080007AD     DC.W       NMI_Handler
+  0x080000EC:  0800172D     DC.W       NMI_Handler
+  0x080000F0:  0800172D     DC.W       NMI_Handler
+  0x080000F4:  0800172D     DC.W       NMI_Handler
+  0x080000F8:  0800172D     DC.W       NMI_Handler
+  0x080000FC:  0800172D     DC.W       NMI_Handler
+  0x08000100:  0800172D     DC.W       NMI_Handler
+  0x08000104:  0800172D     DC.W       NMI_Handler
+  0x08000108:  0800172D     DC.W       NMI_Handler
+  0x0800010C:  0800172D     DC.W       NMI_Handler
+  0x08000110:  0800172D     DC.W       NMI_Handler
+  0x08000114:  0800172D     DC.W       NMI_Handler
+  0x08000118:  0800172D     DC.W       NMI_Handler
+  0x0800011C:  0800172D     DC.W       NMI_Handler
+  0x08000120:  0800172D     DC.W       NMI_Handler
+  0x08000124:  0800172D     DC.W       NMI_Handler
+  0x08000128:  0800172D     DC.W       NMI_Handler
+  0x0800012C:  0800172D     DC.W       NMI_Handler
+  0x08000130:  0800172D     DC.W       NMI_Handler
+  0x08000134:  0800172D     DC.W       NMI_Handler
+  0x08000138:  0800172D     DC.W       NMI_Handler
+  0x0800013C:  0800172D     DC.W       NMI_Handler
   0x08000140:  00           DC.B       0x00                     ; '\0'
   0x08000141:  00           DC.B       0x00                     ; '\0'
@@ -7516,40 +8118,40 @@
   0x0800014E:  00           DC.B       0x00                     ; '\0'
   0x0800014F:  00           DC.B       0x00                     ; '\0'
-  0x08000150:  080007AD     DC.W       NMI_Handler
-  0x08000154:  080007AD     DC.W       NMI_Handler
-  0x08000158:  080007AD     DC.W       NMI_Handler
-  0x0800015C:  080007AD     DC.W       NMI_Handler
-  0x08000160:  080007AD     DC.W       NMI_Handler
-  0x08000164:  080007AD     DC.W       NMI_Handler
-  0x08000168:  080007AD     DC.W       NMI_Handler
-  0x0800016C:  080007AD     DC.W       NMI_Handler
-  0x08000170:  080007AD     DC.W       NMI_Handler
-  0x08000174:  080007AD     DC.W       NMI_Handler
-  0x08000178:  080007AD     DC.W       NMI_Handler
+  0x08000150:  0800172D     DC.W       NMI_Handler
+  0x08000154:  0800172D     DC.W       NMI_Handler
+  0x08000158:  0800172D     DC.W       NMI_Handler
+  0x0800015C:  0800172D     DC.W       NMI_Handler
+  0x08000160:  0800172D     DC.W       NMI_Handler
+  0x08000164:  0800172D     DC.W       NMI_Handler
+  0x08000168:  0800172D     DC.W       NMI_Handler
+  0x0800016C:  0800172D     DC.W       NMI_Handler
+  0x08000170:  0800172D     DC.W       NMI_Handler
+  0x08000174:  0800172D     DC.W       NMI_Handler
+  0x08000178:  0800172D     DC.W       NMI_Handler
   0x0800017C:  00           DC.B       0x00                     ; '\0'
   0x0800017D:  00           DC.B       0x00                     ; '\0'
   0x0800017E:  00           DC.B       0x00                     ; '\0'
   0x0800017F:  00           DC.B       0x00                     ; '\0'
-  0x08000180:  080007AD     DC.W       NMI_Handler
-  0x08000184:  080007AD     DC.W       NMI_Handler
-  0x08000188:  080007AD     DC.W       NMI_Handler
-  0x0800018C:  080007AD     DC.W       NMI_Handler
-  0x08000190:  080007AD     DC.W       NMI_Handler
-  0x08000194:  080007AD     DC.W       NMI_Handler
-  0x08000198:  080007AD     DC.W       NMI_Handler
-  0x0800019C:  080007AD     DC.W       NMI_Handler
-  0x080001A0:  080007AD     DC.W       NMI_Handler
-  0x080001A4:  080007AD     DC.W       NMI_Handler
-  0x080001A8:  080007AD     DC.W       NMI_Handler
+  0x08000180:  0800172D     DC.W       NMI_Handler
+  0x08000184:  0800172D     DC.W       NMI_Handler
+  0x08000188:  0800172D     DC.W       NMI_Handler
+  0x0800018C:  0800172D     DC.W       NMI_Handler
+  0x08000190:  08001731     DC.W       SPI4_IRQHandler
+  0x08000194:  0800172D     DC.W       NMI_Handler
+  0x08000198:  0800172D     DC.W       NMI_Handler
+  0x0800019C:  0800172D     DC.W       NMI_Handler
+  0x080001A0:  0800172D     DC.W       NMI_Handler
+  0x080001A4:  0800172D     DC.W       NMI_Handler
+  0x080001A8:  0800172D     DC.W       NMI_Handler
   0x080001AC:  00           DC.B       0x00                     ; '\0'
   0x080001AD:  00           DC.B       0x00                     ; '\0'
   0x080001AE:  00           DC.B       0x00                     ; '\0'
   0x080001AF:  00           DC.B       0x00                     ; '\0'
-  0x080001B0:  080007AD     DC.W       NMI_Handler
-  0x080001B4:  080007AD     DC.W       NMI_Handler
-  0x080001B8:  080007AD     DC.W       NMI_Handler
-  0x080001BC:  080007AD     DC.W       NMI_Handler
-  0x080001C0:  080007AD     DC.W       NMI_Handler
-  0x080001C4:  080007AD     DC.W       NMI_Handler
+  0x080001B0:  0800172D     DC.W       NMI_Handler
+  0x080001B4:  0800172D     DC.W       NMI_Handler
+  0x080001B8:  0800172D     DC.W       NMI_Handler
+  0x080001BC:  0800172D     DC.W       NMI_Handler
+  0x080001C0:  0800172D     DC.W       NMI_Handler
+  0x080001C4:  0800172D     DC.W       NMI_Handler
   0x080001C8:  00           DC.B       0x00                     ; '\0'
   0x080001C9:  00           DC.B       0x00                     ; '\0'
@@ -7568,5 +8170,5 @@
   0x080001D6:  00           DC.B       0x00                     ; '\0'
   0x080001D7:  00           DC.B       0x00                     ; '\0'
-  0x080001D8:  080007AD     DC.W       NMI_Handler
+  0x080001D8:  0800172D     DC.W       NMI_Handler
   0x080001DC:  00           DC.B       0x00                     ; '\0'
   0x080001DD:  00           DC.B       0x00                     ; '\0'
@@ -7597,63 +8199,63 @@
   0x080001F6:  00           DC.B       0x00                     ; '\0'
   0x080001F7:  00           DC.B       0x00                     ; '\0'
-  0x080001F8:  080007AD     DC.W       NMI_Handler
-  0x080001FC:  080007AD     DC.W       NMI_Handler
-  0x08000200:  080007AD     DC.W       NMI_Handler
-  0x08000204:  080007AD     DC.W       NMI_Handler
+  0x080001F8:  0800172D     DC.W       NMI_Handler
+  0x080001FC:  0800172D     DC.W       NMI_Handler
+  0x08000200:  0800172D     DC.W       NMI_Handler
+  0x08000204:  0800172D     DC.W       NMI_Handler
   0x08000208:  00           DC.B       0x00                     ; '\0'
   0x08000209:  00           DC.B       0x00                     ; '\0'
   0x0800020A:  00           DC.B       0x00                     ; '\0'
   0x0800020B:  00           DC.B       0x00                     ; '\0'
-  0x0800020C:  080007AD     DC.W       NMI_Handler
-  0x08000210:  080007AD     DC.W       NMI_Handler
-  0x08000214:  080007AD     DC.W       NMI_Handler
-  0x08000218:  080007AD     DC.W       NMI_Handler
-  0x0800021C:  080007AD     DC.W       NMI_Handler
-  0x08000220:  080007AD     DC.W       NMI_Handler
+  0x0800020C:  0800172D     DC.W       NMI_Handler
+  0x08000210:  0800172D     DC.W       NMI_Handler
+  0x08000214:  0800172D     DC.W       NMI_Handler
+  0x08000218:  0800172D     DC.W       NMI_Handler
+  0x0800021C:  0800172D     DC.W       NMI_Handler
+  0x08000220:  0800172D     DC.W       NMI_Handler
   0x08000224:  00           DC.B       0x00                     ; '\0'
   0x08000225:  00           DC.B       0x00                     ; '\0'
   0x08000226:  00           DC.B       0x00                     ; '\0'
   0x08000227:  00           DC.B       0x00                     ; '\0'
-  0x08000228:  080007AD     DC.W       NMI_Handler
+  0x08000228:  0800172D     DC.W       NMI_Handler
   0x0800022C:  00           DC.B       0x00                     ; '\0'
   0x0800022D:  00           DC.B       0x00                     ; '\0'
   0x0800022E:  00           DC.B       0x00                     ; '\0'
   0x0800022F:  00           DC.B       0x00                     ; '\0'
-  0x08000230:  080007AD     DC.W       NMI_Handler
-  0x08000234:  080007AD     DC.W       NMI_Handler
+  0x08000230:  0800172D     DC.W       NMI_Handler
+  0x08000234:  0800172D     DC.W       NMI_Handler
   0x08000238:  00           DC.B       0x00                     ; '\0'
   0x08000239:  00           DC.B       0x00                     ; '\0'
   0x0800023A:  00           DC.B       0x00                     ; '\0'
   0x0800023B:  00           DC.B       0x00                     ; '\0'
-  0x0800023C:  080007AD     DC.W       NMI_Handler
-  0x08000240:  080007AD     DC.W       NMI_Handler
-  0x08000244:  080007AD     DC.W       NMI_Handler
-  0x08000248:  080007AD     DC.W       NMI_Handler
-  0x0800024C:  080007AD     DC.W       NMI_Handler
-  0x08000250:  080007AD     DC.W       NMI_Handler
-  0x08000254:  080007AD     DC.W       NMI_Handler
-  0x08000258:  080007AD     DC.W       NMI_Handler
-  0x0800025C:  080007AD     DC.W       NMI_Handler
-  0x08000260:  080007AD     DC.W       NMI_Handler
-  0x08000264:  080007AD     DC.W       NMI_Handler
-  0x08000268:  080007AD     DC.W       NMI_Handler
-  0x0800026C:  080007AD     DC.W       NMI_Handler
-  0x08000270:  080007AD     DC.W       NMI_Handler
-  0x08000274:  080007AD     DC.W       NMI_Handler
-  0x08000278:  080007AD     DC.W       NMI_Handler
+  0x0800023C:  0800172D     DC.W       NMI_Handler
+  0x08000240:  0800172D     DC.W       NMI_Handler
+  0x08000244:  0800172D     DC.W       NMI_Handler
+  0x08000248:  0800172D     DC.W       NMI_Handler
+  0x0800024C:  0800172D     DC.W       NMI_Handler
+  0x08000250:  0800172D     DC.W       NMI_Handler
+  0x08000254:  0800172D     DC.W       NMI_Handler
+  0x08000258:  0800172D     DC.W       NMI_Handler
+  0x0800025C:  0800172D     DC.W       NMI_Handler
+  0x08000260:  0800172D     DC.W       NMI_Handler
+  0x08000264:  0800172D     DC.W       NMI_Handler
+  0x08000268:  0800172D     DC.W       NMI_Handler
+  0x0800026C:  0800172D     DC.W       NMI_Handler
+  0x08000270:  0800172D     DC.W       NMI_Handler
+  0x08000274:  0800172D     DC.W       NMI_Handler
+  0x08000278:  0800172D     DC.W       NMI_Handler
   0x0800027C:  00           DC.B       0x00                     ; '\0'
   0x0800027D:  00           DC.B       0x00                     ; '\0'
   0x0800027E:  00           DC.B       0x00                     ; '\0'
   0x0800027F:  00           DC.B       0x00                     ; '\0'
-  0x08000280:  080007AD     DC.W       NMI_Handler
-  0x08000284:  080007AD     DC.W       NMI_Handler
-  0x08000288:  080007AD     DC.W       NMI_Handler
-  0x0800028C:  080007AD     DC.W       NMI_Handler
+  0x08000280:  0800172D     DC.W       NMI_Handler
+  0x08000284:  0800172D     DC.W       NMI_Handler
+  0x08000288:  0800172D     DC.W       NMI_Handler
+  0x0800028C:  0800172D     DC.W       NMI_Handler
   0x08000290:  00           DC.B       0x00                     ; '\0'
   0x08000291:  00           DC.B       0x00                     ; '\0'
   0x08000292:  00           DC.B       0x00                     ; '\0'
   0x08000293:  00           DC.B       0x00                     ; '\0'
-  0x08000294:  080007AD     DC.W       NMI_Handler
-  0x08000298:  080007AD     DC.W       NMI_Handler
+  0x08000294:  0800172D     DC.W       NMI_Handler
+  0x08000298:  0800172D     DC.W       NMI_Handler
   0x0800029C:  00           DC.B       0x00                     ; '\0'
   0x0800029D:  00           DC.B       0x00                     ; '\0'
@@ -7664,20 +8266,21 @@
   0x080002A2:  00           DC.B       0x00                     ; '\0'
   0x080002A3:  00           DC.B       0x00                     ; '\0'
-  0x080002A4:  080007AD     DC.W       NMI_Handler
-  0x080002A8:  080007AD     DC.W       NMI_Handler
-  0x080002AC:  080007AD     DC.W       NMI_Handler
-  0x080002B0:  080007AD     DC.W       NMI_Handler
-  0x080002B4:  080007AD     DC.W       NMI_Handler
-  0x080002B8:  080007AD     DC.W       NMI_Handler
-  0x080002BC:  080007AD     DC.W       NMI_Handler
-  0x080002C0:  080007AD     DC.W       NMI_Handler
-  0x080002C4:  080007AD     DC.W       NMI_Handler
-  0x080002C8:  080007AD     DC.W       NMI_Handler
+  0x080002A4:  0800172D     DC.W       NMI_Handler
+  0x080002A8:  0800172D     DC.W       NMI_Handler
+  0x080002AC:  0800172D     DC.W       NMI_Handler
+  0x080002B0:  0800172D     DC.W       NMI_Handler
+  0x080002B4:  0800172D     DC.W       NMI_Handler
+  0x080002B8:  0800172D     DC.W       NMI_Handler
+  0x080002BC:  0800172D     DC.W       NMI_Handler
+  0x080002C0:  0800172D     DC.W       NMI_Handler
+  0x080002C4:  0800172D     DC.W       NMI_Handler
+  0x080002C8:  0800172D     DC.W       NMI_Handler

    Section .text.HAL_RCC_GetSysClockFreq from charger_lto.o, size=268, align=4

    -
    HAL_RCC_GetSysClockFreq:
-_vectors_end:
+
    HAL_RCC_GetSysClockFreq:
+_vectors_end:
   0x080002CC:  F244 4100    MOVW       R1, #0x4400
   0x080002D0:  F6C5 0102    MOVT       R1, #0x5802
@@ -7774,1221 +8377,3850 @@
   0x080003D4:  39000000     DC.W       0x39000000
    +

    Section .text.HAL_RCCEx_PeriphCLKConfig from charger_lto.o, size=2100, align=4

    +
    +
    HAL_RCCEx_PeriphCLKConfig:
+  0x080003D8:  E92D 43F8    PUSH.W     {R3-R9, LR}
+  0x080003DC:  4604         MOV        R4, R0
+  0x080003DE:  78C0         LDRB       R0, [R0, #3]
+  0x080003E0:  F244 4610    MOVW       R6, #0x4410
+  0x080003E4:  0700         LSLS       R0, R0, #28
+  0x080003E6:  F6C5 0602    MOVT       R6, #0x5802
+  0x080003EA:  D521         BPL        .L3                      ; 0x08000430
+  0x080003EC:  6E60         LDR        R0, [R4, #100]
+  0x080003EE:  EA4F 5130    ROR        R1, R0, #20
+  0x080003F2:  2903         CMP        R1, #3
+  0x080003F4:  D831         BHI        .L6                      ; 0x0800045A
+  0x080003F6:  E8DF F001    TBB        [PC, R1]
+  0x080003FA:  02           DC.B       0x02                     ; '\x02'
+  0x080003FB:  07           DC.B       0x07                     ; '\x07'
+  0x080003FC:  0D           DC.B       0x0D                     ; '\r'
+  0x080003FD:  16           DC.B       0x16                     ; '\x16'
+  0x080003FE:  69F1         LDR        R1, [R6, #28]
+  0x08000400:  F441 3100    ORR        R1, R1, #0x020000
+  0x08000404:  61F1         STR        R1, [R6, #28]
+  0x08000406:  E00E         B          .L2                      ; 0x08000426
+  0x08000408:  F104 0008    ADD.W      R0, R4, #8
+  0x0800040C:  2102         MOVS       R1, #2
+  0x0800040E:  F001 FD8D    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x08000412:  E004         B          .L1                      ; 0x0800041E
+  0x08000414:  F104 0028    ADD.W      R0, R4, #40
+  0x08000418:  2102         MOVS       R1, #2
+  0x0800041A:  F001 FE0F    BL         RCCEx_PLL3_Config        ; 0x0800203C
+
    .L1:
+  0x0800041E:  EA5F 0800    MOVS.W     R8, R0
+  0x08000422:  D107         BNE        .L4                      ; 0x08000434
+  0x08000424:  6E60         LDR        R0, [R4, #100]
+
    .L2:
+  0x08000426:  6C31         LDR        R1, [R6, #64]
+  0x08000428:  F421 1140    BIC        R1, R1, #0x300000
+  0x0800042C:  4308         ORRS       R0, R1
+  0x0800042E:  6430         STR        R0, [R6, #64]
+
    .L3:
+  0x08000430:  F04F 0800    MOV.W      R8, #0
+
    .L4:
+  0x08000434:  7860         LDRB       R0, [R4, #1]
+  0x08000436:  07C0         LSLS       R0, R0, #31
+  0x08000438:  D101         BNE        .L5                      ; 0x0800043E
+  0x0800043A:  4645         MOV        R5, R8
+  0x0800043C:  E024         B          .L9                      ; 0x08000488
+
    .L5:
+  0x0800043E:  6DA0         LDR        R0, [R4, #88]
+  0x08000440:  2804         CMP        R0, #4
+  0x08000442:  D835         BHI        .L11                     ; 0x080004B0
+  0x08000444:  4645         MOV        R5, R8
+  0x08000446:  E8DF F000    TBB        [PC, R0]
+  0x0800044A:  03           DC.B       0x03                     ; '\x03'
+  0x0800044B:  11           DC.B       0x11                     ; '\x11'
+  0x0800044C:  0B           DC.B       0x0B                     ; '\v'
+  0x0800044D:  17           DC.B       0x17                     ; '\x17'
+  0x0800044E:  17           DC.B       0x17                     ; '\x17'
+  0x0800044F:  00           DC.B       0x00                     ; '\0'
+  0x08000450:  69F0         LDR        R0, [R6, #28]
+  0x08000452:  F440 3000    ORR        R0, R0, #0x020000
+  0x08000456:  61F0         STR        R0, [R6, #28]
+  0x08000458:  E00E         B          .L8                      ; 0x08000478
+
    .L6:
+  0x0800045A:  F04F 0801    MOV.W      R8, #1
+  0x0800045E:  E7E9         B          .L4                      ; 0x08000434
+  0x08000460:  F104 0028    ADD.W      R0, R4, #40
+  0x08000464:  2100         MOVS       R1, #0
+  0x08000466:  F001 FDE9    BL         RCCEx_PLL3_Config        ; 0x0800203C
+  0x0800046A:  E004         B          .L7                      ; 0x08000476
+  0x0800046C:  F104 0008    ADD.W      R0, R4, #8
+  0x08000470:  2100         MOVS       R1, #0
+  0x08000472:  F001 FD5B    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+
    .L7:
+  0x08000476:  4605         MOV        R5, R0
+
    .L8:
+  0x08000478:  462F         MOV        R7, R5
+  0x0800047A:  B935         CBNZ       R5, .L10                 ; 0x0800048A
+  0x0800047C:  6C30         LDR        R0, [R6, #64]
+  0x0800047E:  6DA1         LDR        R1, [R4, #88]
+  0x08000480:  F020 0007    BIC        R0, R0, #7
+  0x08000484:  4308         ORRS       R0, R1
+  0x08000486:  6430         STR        R0, [R6, #64]
+
    .L9:
+  0x08000488:  4647         MOV        R7, R8
+
    .L10:
+  0x0800048A:  7860         LDRB       R0, [R4, #1]
+  0x0800048C:  0740         LSLS       R0, R0, #29
+  0x0800048E:  D52A         BPL        .L15                     ; 0x080004E6
+  0x08000490:  F8D4 00A4    LDR.W      R0, [R4, #164]
+  0x08000494:  EA4F 5070    ROR        R0, R0, #21
+  0x08000498:  2805         CMP        R0, #5
+  0x0800049A:  D812         BHI        .L12                     ; 0x080004C2
+  0x0800049C:  E8DF F000    TBB        [PC, R0]
+  0x080004A0:  03           DC.B       0x03                     ; '\x03'
+  0x080004A1:  14           DC.B       0x14                     ; '\x14'
+  0x080004A2:  0B           DC.B       0x0B                     ; '\v'
+  0x080004A3:  1A           DC.B       0x1A                     ; '\x1A'
+  0x080004A4:  1A           DC.B       0x1A                     ; '\x1A'
+  0x080004A5:  1A           DC.B       0x1A                     ; '\x1A'
+  0x080004A6:  69F0         LDR        R0, [R6, #28]
+  0x080004A8:  F440 3000    ORR        R0, R0, #0x020000
+  0x080004AC:  61F0         STR        R0, [R6, #28]
+  0x080004AE:  E011         B          .L14                     ; 0x080004D4
+
    .L11:
+  0x080004B0:  2501         MOVS       R5, #1
+  0x080004B2:  2701         MOVS       R7, #1
+  0x080004B4:  E7E9         B          .L10                     ; 0x0800048A
+  0x080004B6:  F104 0028    ADD.W      R0, R4, #40
+  0x080004BA:  2100         MOVS       R1, #0
+  0x080004BC:  F001 FDBE    BL         RCCEx_PLL3_Config        ; 0x0800203C
+  0x080004C0:  E007         B          .L13                     ; 0x080004D2
+
    .L12:
+  0x080004C2:  2501         MOVS       R5, #1
+  0x080004C4:  46A8         MOV        R8, R5
+  0x080004C6:  E00F         B          .L16                     ; 0x080004E8
+  0x080004C8:  F104 0008    ADD.W      R0, R4, #8
+  0x080004CC:  2100         MOVS       R1, #0
+  0x080004CE:  F001 FD2D    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+
    .L13:
+  0x080004D2:  4605         MOV        R5, R0
+
    .L14:
+  0x080004D4:  46A8         MOV        R8, R5
+  0x080004D6:  B93D         CBNZ       R5, .L16                 ; 0x080004E8
+  0x080004D8:  6CB0         LDR        R0, [R6, #72]
+  0x080004DA:  F8D4 10A4    LDR.W      R1, [R4, #164]
+  0x080004DE:  F420 0060    BIC        R0, R0, #0xE00000
+  0x080004E2:  4308         ORRS       R0, R1
+  0x080004E4:  64B0         STR        R0, [R6, #72]
+
    .L15:
+  0x080004E6:  46B8         MOV        R8, R7
+
    .L16:
+  0x080004E8:  7860         LDRB       R0, [R4, #1]
+  0x080004EA:  0700         LSLS       R0, R0, #28
+  0x080004EC:  D527         BPL        .L20                     ; 0x0800053E
+  0x080004EE:  F8D4 00A8    LDR.W      R0, [R4, #168]
+  0x080004F2:  EA4F 6030    ROR        R0, R0, #24
+  0x080004F6:  2805         CMP        R0, #5
+  0x080004F8:  D80F         BHI        .L17                     ; 0x0800051A
+  0x080004FA:  E8DF F000    TBB        [PC, R0]
+  0x080004FE:  03           DC.B       0x03                     ; '\x03'
+  0x080004FF:  11           DC.B       0x11                     ; '\x11'
+  0x08000500:  08           DC.B       0x08                     ; '\b'
+  0x08000501:  17           DC.B       0x17                     ; '\x17'
+  0x08000502:  17           DC.B       0x17                     ; '\x17'
+  0x08000503:  17           DC.B       0x17                     ; '\x17'
+  0x08000504:  69F0         LDR        R0, [R6, #28]
+  0x08000506:  F440 3000    ORR        R0, R0, #0x020000
+  0x0800050A:  61F0         STR        R0, [R6, #28]
+  0x0800050C:  E00E         B          .L19                     ; 0x0800052C
+  0x0800050E:  F104 0028    ADD.W      R0, R4, #40
+  0x08000512:  2100         MOVS       R1, #0
+  0x08000514:  F001 FD92    BL         RCCEx_PLL3_Config        ; 0x0800203C
+  0x08000518:  E007         B          .L18                     ; 0x0800052A
+
    .L17:
+  0x0800051A:  2501         MOVS       R5, #1
+  0x0800051C:  2701         MOVS       R7, #1
+  0x0800051E:  E00F         B          .L21                     ; 0x08000540
+  0x08000520:  F104 0008    ADD.W      R0, R4, #8
+  0x08000524:  2100         MOVS       R1, #0
+  0x08000526:  F001 FD01    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+
    .L18:
+  0x0800052A:  4605         MOV        R5, R0
+
    .L19:
+  0x0800052C:  462F         MOV        R7, R5
+  0x0800052E:  B93D         CBNZ       R5, .L21                 ; 0x08000540
+  0x08000530:  6CB0         LDR        R0, [R6, #72]
+  0x08000532:  F8D4 10A8    LDR.W      R1, [R4, #168]
+  0x08000536:  F020 60E0    BIC        R0, R0, #0x07000000
+  0x0800053A:  4308         ORRS       R0, R1
+  0x0800053C:  64B0         STR        R0, [R6, #72]
+
    .L20:
+  0x0800053E:  4647         MOV        R7, R8
+
    .L21:
+  0x08000540:  78E0         LDRB       R0, [R4, #3]
+  0x08000542:  0780         LSLS       R0, R0, #30
+  0x08000544:  D51B         BPL        .L23                     ; 0x0800057E
+  0x08000546:  6CE0         LDR        R0, [R4, #76]
+  0x08000548:  EA4F 1030    ROR        R0, R0, #4
+  0x0800054C:  2803         CMP        R0, #3
+  0x0800054E:  D829         BHI        .L25                     ; 0x080005A4
+  0x08000550:  E8DF F000    TBB        [PC, R0]
+  0x08000554:  0D           DC.B       0x0D                     ; '\r'
+  0x08000555:  02           DC.B       0x02                     ; '\x02'
+  0x08000556:  07           DC.B       0x07                     ; '\x07'
+  0x08000557:  0D           DC.B       0x0D                     ; '\r'
+  0x08000558:  69F0         LDR        R0, [R6, #28]
+  0x0800055A:  F440 3000    ORR        R0, R0, #0x020000
+  0x0800055E:  61F0         STR        R0, [R6, #28]
+  0x08000560:  E005         B          .L22                     ; 0x0800056E
+  0x08000562:  F104 0008    ADD.W      R0, R4, #8
+  0x08000566:  2102         MOVS       R1, #2
+  0x08000568:  F001 FCE0    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x0800056C:  4605         MOV        R5, R0
+
    .L22:
+  0x0800056E:  46A8         MOV        R8, R5
+  0x08000570:  B935         CBNZ       R5, .L24                 ; 0x08000580
+  0x08000572:  6BF0         LDR        R0, [R6, #60]
+  0x08000574:  6CE1         LDR        R1, [R4, #76]
+  0x08000576:  F020 0030    BIC        R0, R0, #48
+  0x0800057A:  4308         ORRS       R0, R1
+  0x0800057C:  63F0         STR        R0, [R6, #60]
+
    .L23:
+  0x0800057E:  46B8         MOV        R8, R7
+
    .L24:
+  0x08000580:  7860         LDRB       R0, [R4, #1]
+  0x08000582:  06C0         LSLS       R0, R0, #27
+  0x08000584:  D525         BPL        .L28                     ; 0x080005D2
+  0x08000586:  6DE0         LDR        R0, [R4, #92]
+  0x08000588:  EA4F 3030    ROR        R0, R0, #12
+  0x0800058C:  2804         CMP        R0, #4
+  0x0800058E:  D835         BHI        .L30                     ; 0x080005FC
+  0x08000590:  E8DF F000    TBB        [PC, R0]
+  0x08000594:  03           DC.B       0x03                     ; '\x03'
+  0x08000595:  11           DC.B       0x11                     ; '\x11'
+  0x08000596:  0B           DC.B       0x0B                     ; '\v'
+  0x08000597:  17           DC.B       0x17                     ; '\x17'
+  0x08000598:  17           DC.B       0x17                     ; '\x17'
+  0x08000599:  00           DC.B       0x00                     ; '\0'
+  0x0800059A:  69F0         LDR        R0, [R6, #28]
+  0x0800059C:  F440 3000    ORR        R0, R0, #0x020000
+  0x080005A0:  61F0         STR        R0, [R6, #28]
+  0x080005A2:  E00E         B          .L27                     ; 0x080005C2
+
    .L25:
+  0x080005A4:  2501         MOVS       R5, #1
+  0x080005A6:  46A8         MOV        R8, R5
+  0x080005A8:  E7EA         B          .L24                     ; 0x08000580
+  0x080005AA:  F104 0028    ADD.W      R0, R4, #40
+  0x080005AE:  2100         MOVS       R1, #0
+  0x080005B0:  F001 FD44    BL         RCCEx_PLL3_Config        ; 0x0800203C
+  0x080005B4:  E004         B          .L26                     ; 0x080005C0
+  0x080005B6:  F104 0008    ADD.W      R0, R4, #8
+  0x080005BA:  2100         MOVS       R1, #0
+  0x080005BC:  F001 FCB6    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+
    .L26:
+  0x080005C0:  4605         MOV        R5, R0
+
    .L27:
+  0x080005C2:  462F         MOV        R7, R5
+  0x080005C4:  B935         CBNZ       R5, .L29                 ; 0x080005D4
+  0x080005C6:  6C30         LDR        R0, [R6, #64]
+  0x080005C8:  6DE1         LDR        R1, [R4, #92]
+  0x080005CA:  F420 40E0    BIC        R0, R0, #0x7000
+  0x080005CE:  4308         ORRS       R0, R1
+  0x080005D0:  6430         STR        R0, [R6, #64]
+
    .L28:
+  0x080005D2:  4647         MOV        R7, R8
+
    .L29:
+  0x080005D4:  7860         LDRB       R0, [R4, #1]
+  0x080005D6:  0680         LSLS       R0, R0, #26
+  0x080005D8:  D521         BPL        .L32                     ; 0x0800061E
+  0x080005DA:  6E20         LDR        R0, [R4, #96]
+  0x080005DC:  EA4F 4030    ROR        R0, R0, #16
+  0x080005E0:  2805         CMP        R0, #5
+  0x080005E2:  F200 82FB    BHI.W      .L110                    ; 0x08000BDC
+  0x080005E6:  E8DF F000    TBB        [PC, R0]
+  0x080005EA:  12           DC.B       0x12                     ; '\x12'
+  0x080005EB:  03           DC.B       0x03                     ; '\x03'
+  0x080005EC:  0C           DC.B       0x0C                     ; '\x0C'
+  0x080005ED:  12           DC.B       0x12                     ; '\x12'
+  0x080005EE:  12           DC.B       0x12                     ; '\x12'
+  0x080005EF:  12           DC.B       0x12                     ; '\x12'
+  0x080005F0:  F104 0008    ADD.W      R0, R4, #8
+  0x080005F4:  2101         MOVS       R1, #1
+  0x080005F6:  F001 FC99    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x080005FA:  E007         B          .L31                     ; 0x0800060C
+
    .L30:
+  0x080005FC:  2501         MOVS       R5, #1
+  0x080005FE:  2701         MOVS       R7, #1
+  0x08000600:  E7E8         B          .L29                     ; 0x080005D4
+  0x08000602:  F104 0028    ADD.W      R0, R4, #40
+  0x08000606:  2101         MOVS       R1, #1
+  0x08000608:  F001 FD18    BL         RCCEx_PLL3_Config        ; 0x0800203C
+
    .L31:
+  0x0800060C:  4605         MOV        R5, R0
+  0x0800060E:  46A8         MOV        R8, R5
+  0x08000610:  B935         CBNZ       R5, .L33                 ; 0x08000620
+  0x08000612:  6C30         LDR        R0, [R6, #64]
+  0x08000614:  6E21         LDR        R1, [R4, #96]
+  0x08000616:  F420 20E0    BIC        R0, R0, #0x070000
+  0x0800061A:  4308         ORRS       R0, R1
+  0x0800061C:  6430         STR        R0, [R6, #64]
+
    .L32:
+  0x0800061E:  46B8         MOV        R8, R7
+
    .L33:
+  0x08000620:  7860         LDRB       R0, [R4, #1]
+  0x08000622:  0640         LSLS       R0, R0, #25
+  0x08000624:  D520         BPL        .L35                     ; 0x08000668
+  0x08000626:  F8D4 00AC    LDR.W      R0, [R4, #172]
+  0x0800062A:  EA4F 7030    ROR        R0, R0, #28
+  0x0800062E:  2805         CMP        R0, #5
+  0x08000630:  F200 82D7    BHI.W      .L111                    ; 0x08000BE2
+  0x08000634:  E8DF F000    TBB        [PC, R0]
+  0x08000638:  0F           DC.B       0x0F                     ; '\x0F'
+  0x08000639:  03           DC.B       0x03                     ; '\x03'
+  0x0800063A:  09           DC.B       0x09                     ; '\t'
+  0x0800063B:  0F           DC.B       0x0F                     ; '\x0F'
+  0x0800063C:  0F           DC.B       0x0F                     ; '\x0F'
+  0x0800063D:  0F           DC.B       0x0F                     ; '\x0F'
+  0x0800063E:  F104 0008    ADD.W      R0, R4, #8
+  0x08000642:  2101         MOVS       R1, #1
+  0x08000644:  F001 FC72    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x08000648:  E004         B          .L34                     ; 0x08000654
+  0x0800064A:  F104 0028    ADD.W      R0, R4, #40
+  0x0800064E:  2101         MOVS       R1, #1
+  0x08000650:  F001 FCF4    BL         RCCEx_PLL3_Config        ; 0x0800203C
+
    .L34:
+  0x08000654:  4605         MOV        R5, R0
+  0x08000656:  462F         MOV        R7, R5
+  0x08000658:  B93D         CBNZ       R5, .L36                 ; 0x0800066A
+  0x0800065A:  6CB0         LDR        R0, [R6, #72]
+  0x0800065C:  F8D4 10AC    LDR.W      R1, [R4, #172]
+  0x08000660:  F020 40E0    BIC        R0, R0, #0x70000000
+  0x08000664:  4308         ORRS       R0, R1
+  0x08000666:  64B0         STR        R0, [R6, #72]
+
    .L35:
+  0x08000668:  4647         MOV        R7, R8
+
    .L36:
+  0x0800066A:  7860         LDRB       R0, [R4, #1]
+  0x0800066C:  0600         LSLS       R0, R0, #24
+  0x0800066E:  D51A         BPL        .L39                     ; 0x080006A6
+  0x08000670:  6EE0         LDR        R0, [R4, #108]
+  0x08000672:  B180         CBZ        R0, .L38                 ; 0x08000696
+  0x08000674:  F1B0 5F00    CMP.W      R0, #0x20000000
+  0x08000678:  D007         BEQ        .L37                     ; 0x0800068A
+  0x0800067A:  F1B0 5F80    CMP.W      R0, #0x10000000
+  0x0800067E:  D122         BNE        .L41                     ; 0x080006C6
+  0x08000680:  69F0         LDR        R0, [R6, #28]
+  0x08000682:  F440 3000    ORR        R0, R0, #0x020000
+  0x08000686:  61F0         STR        R0, [R6, #28]
+  0x08000688:  E005         B          .L38                     ; 0x08000696
+
    .L37:
+  0x0800068A:  F104 0008    ADD.W      R0, R4, #8
+  0x0800068E:  2101         MOVS       R1, #1
+  0x08000690:  F001 FC4C    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x08000694:  4605         MOV        R5, R0
+
    .L38:
+  0x08000696:  46A8         MOV        R8, R5
+  0x08000698:  B935         CBNZ       R5, .L40                 ; 0x080006A8
+  0x0800069A:  6C30         LDR        R0, [R6, #64]
+  0x0800069C:  6EE1         LDR        R1, [R4, #108]
+  0x0800069E:  F020 5040    BIC        R0, R0, #0x30000000
+  0x080006A2:  4308         ORRS       R0, R1
+  0x080006A4:  6430         STR        R0, [R6, #64]
+
    .L39:
+  0x080006A6:  46B8         MOV        R8, R7
+
    .L40:
+  0x080006A8:  78E0         LDRB       R0, [R4, #3]
+  0x080006AA:  07C0         LSLS       R0, R0, #31
+  0x080006AC:  D01C         BEQ        .L43                     ; 0x080006E8
+  0x080006AE:  6CA0         LDR        R0, [R4, #72]
+  0x080006B0:  2803         CMP        R0, #3
+  0x080006B2:  D84B         BHI        .L50                     ; 0x0800074C
+  0x080006B4:  E8DF F000    TBB        [PC, R0]
+  0x080006B8:  10           DC.B       0x10                     ; '\x10'
+  0x080006B9:  02           DC.B       0x02                     ; '\x02'
+  0x080006BA:  0A           DC.B       0x0A                     ; '\n'
+  0x080006BB:  10           DC.B       0x10                     ; '\x10'
+  0x080006BC:  69F0         LDR        R0, [R6, #28]
+  0x080006BE:  F440 3000    ORR        R0, R0, #0x020000
+  0x080006C2:  61F0         STR        R0, [R6, #28]
+  0x080006C4:  E008         B          .L42                     ; 0x080006D8
+
    .L41:
+  0x080006C6:  2501         MOVS       R5, #1
+  0x080006C8:  46A8         MOV        R8, R5
+  0x080006CA:  E7ED         B          .L40                     ; 0x080006A8
+  0x080006CC:  F104 0008    ADD.W      R0, R4, #8
+  0x080006D0:  2102         MOVS       R1, #2
+  0x080006D2:  F001 FC2B    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x080006D6:  4605         MOV        R5, R0
+
    .L42:
+  0x080006D8:  4629         MOV        R1, R5
+  0x080006DA:  B935         CBNZ       R5, .L44                 ; 0x080006EA
+  0x080006DC:  6BF0         LDR        R0, [R6, #60]
+  0x080006DE:  6CA1         LDR        R1, [R4, #72]
+  0x080006E0:  F020 0003    BIC        R0, R0, #3
+  0x080006E4:  4308         ORRS       R0, R1
+  0x080006E6:  63F0         STR        R0, [R6, #60]
+
    .L43:
+  0x080006E8:  4641         MOV        R1, R8
+
    .L44:
+  0x080006EA:  E9D4 0200    LDRD       R0, R2, [R4]
+  0x080006EE:  0242         LSLS       R2, R0, #9
+  0x080006F0:  D401         BMI        .L46                     ; 0x080006F6
+
    .L45:
+  0x080006F2:  4688         MOV        R8, R1
+  0x080006F4:  E017         B          .L49                     ; 0x08000726
+
    .L46:
+  0x080006F6:  F8D6 23F0    LDR.W      R2, [R6, #0x03F0]
+  0x080006FA:  F442 7280    ORR        R2, R2, #0x0100
+  0x080006FE:  F8C6 23F0    STR.W      R2, [R6, #0x03F0]
+  0x08000702:  F240 1224    MOVW       R2, #0x0124              ; 0x30000124 = uwTick
+  0x08000706:  F2C3 0200    MOVT       R2, #0x3000              ; 0x30000124 = uwTick
+  0x0800070A:  6813         LDR        R3, [R2]
+
    .L47:
+  0x0800070C:  F8D6 73F0    LDR.W      R7, [R6, #0x03F0]
+  0x08000710:  05FF         LSLS       R7, R7, #23
+  0x08000712:  D406         BMI        .L48                     ; 0x08000722
+  0x08000714:  6817         LDR        R7, [R2]
+  0x08000716:  1AFF         SUBS       R7, R7, R3
+  0x08000718:  2F64         CMP        R7, #100
+  0x0800071A:  D9F7         BLS        .L47                     ; 0x0800070C
+  0x0800071C:  2503         MOVS       R5, #3
+  0x0800071E:  46A8         MOV        R8, R5
+  0x08000720:  E001         B          .L49                     ; 0x08000726
+
    .L48:
+  0x08000722:  46A8         MOV        R8, R5
+  0x08000724:  B1AD         CBZ        R5, .L51                 ; 0x08000752
+
    .L49:
+  0x08000726:  07C0         LSLS       R0, R0, #31
+  0x08000728:  D062         BEQ        .L56                     ; 0x080007F0
+  0x0800072A:  6FA0         LDR        R0, [R4, #120]
+  0x0800072C:  EA4F 00F0    ROR        R0, R0, #3
+  0x08000730:  2805         CMP        R0, #5
+  0x08000732:  F200 8259    BHI.W      .L112                    ; 0x08000BE8
+  0x08000736:  E8DF F000    TBB        [PC, R0]
+  0x0800073A:  53           DC.B       0x53                     ; 'S'
+  0x0800073B:  03           DC.B       0x03                     ; '\x03'
+  0x0800073C:  4D           DC.B       0x4D                     ; 'M'
+  0x0800073D:  53           DC.B       0x53                     ; 'S'
+  0x0800073E:  53           DC.B       0x53                     ; 'S'
+  0x0800073F:  53           DC.B       0x53                     ; 'S'
+  0x08000740:  F104 0008    ADD.W      R0, R4, #8
+  0x08000744:  2101         MOVS       R1, #1
+  0x08000746:  F001 FBF1    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x0800074A:  E048         B          .L55                     ; 0x080007DE
+
    .L50:
+  0x0800074C:  2501         MOVS       R5, #1
+  0x0800074E:  2101         MOVS       R1, #1
+  0x08000750:  E7CB         B          .L44                     ; 0x080006EA
+
    .L51:
+  0x08000752:  6E33         LDR        R3, [R6, #96]
+  0x08000754:  F8D4 C0B0    LDR.W      R12, [R4, #176]
+  0x08000758:  EA83 030C    EOR.W      R3, R3, R12
+  0x0800075C:  F413 7F40    TST        R3, #0x0300
+  0x08000760:  D00B         BEQ        .L52                     ; 0x0800077A
+  0x08000762:  6E33         LDR        R3, [R6, #96]
+  0x08000764:  6E37         LDR        R7, [R6, #96]
+  0x08000766:  F447 3780    ORR        R7, R7, #0x010000
+  0x0800076A:  6637         STR        R7, [R6, #96]
+  0x0800076C:  6E37         LDR        R7, [R6, #96]
+  0x0800076E:  F423 7340    BIC        R3, R3, #0x0300
+  0x08000772:  F427 3780    BIC        R7, R7, #0x010000
+  0x08000776:  6637         STR        R7, [R6, #96]
+  0x08000778:  6633         STR        R3, [R6, #96]
+
    .L52:
+  0x0800077A:  F5BC 7F80    CMP.W      R12, #0x0100
+  0x0800077E:  D111         BNE        .L54                     ; 0x080007A4
+  0x08000780:  6817         LDR        R7, [R2]
+  0x08000782:  F241 3388    MOVW       R3, #0x1388
+  0x08000786:  2503         MOVS       R5, #3
+
    .L53:
+  0x08000788:  F8D6 8060    LDR.W      R8, [R6, #96]
+  0x0800078C:  EA5F 7888    LSLS.W     R8, R8, #30
+  0x08000790:  D408         BMI        .L54                     ; 0x080007A4
+  0x08000792:  F8D2 8000    LDR.W      R8, [R2]
+  0x08000796:  EBA8 0807    SUB.W      R8, R8, R7
+  0x0800079A:  4598         CMP        R8, R3
+  0x0800079C:  F04F 0803    MOV.W      R8, #3
+  0x080007A0:  D9F2         BLS        .L53                     ; 0x08000788
+  0x080007A2:  E7C0         B          .L49                     ; 0x08000726
+
    .L54:
+  0x080007A4:  6833         LDR        R3, [R6]
+  0x080007A6:  F64F 77CF    MOVW       R7, #0xFFCF
+  0x080007AA:  F40C 7240    AND        R2, R12, #0x0300
+  0x080007AE:  F423 537C    BIC        R3, R3, #0x3F00
+  0x080007B2:  F2C0 07FF    MOVT       R7, #255
+  0x080007B6:  EA07 171C    AND.W      R7, R7, R12, LSR #4
+  0x080007BA:  2500         MOVS       R5, #0
+  0x080007BC:  F5B2 7F40    CMP.W      R2, #0x0300
+  0x080007C0:  BF08         IT         EQ
+  0x080007C2:  433B         ORREQ      R3, R7
+  0x080007C4:  6033         STR        R3, [R6]
+  0x080007C6:  F36F 3C1F    BFC        R12, #12, #20
+  0x080007CA:  6E32         LDR        R2, [R6, #96]
+  0x080007CC:  EA42 020C    ORR.W      R2, R2, R12
+  0x080007D0:  6632         STR        R2, [R6, #96]
+  0x080007D2:  E78E         B          .L45                     ; 0x080006F2
+  0x080007D4:  F104 0028    ADD.W      R0, R4, #40
+  0x080007D8:  2101         MOVS       R1, #1
+  0x080007DA:  F001 FC2F    BL         RCCEx_PLL3_Config        ; 0x0800203C
+
    .L55:
+  0x080007DE:  4605         MOV        R5, R0
+  0x080007E0:  462F         MOV        R7, R5
+  0x080007E2:  B935         CBNZ       R5, .L57                 ; 0x080007F2
+  0x080007E4:  6C70         LDR        R0, [R6, #68]
+  0x080007E6:  6FA1         LDR        R1, [R4, #120]
+  0x080007E8:  F020 0038    BIC        R0, R0, #56
+  0x080007EC:  4308         ORRS       R0, R1
+  0x080007EE:  6470         STR        R0, [R6, #68]
+
    .L56:
+  0x080007F0:  4647         MOV        R7, R8
+
    .L57:
+  0x080007F2:  7820         LDRB       R0, [R4]
+  0x080007F4:  0780         LSLS       R0, R0, #30
+  0x080007F6:  D51C         BPL        .L59                     ; 0x08000832
+  0x080007F8:  6F60         LDR        R0, [R4, #116]
+  0x080007FA:  2805         CMP        R0, #5
+  0x080007FC:  F200 81F7    BHI.W      .L113                    ; 0x08000BEE
+  0x08000800:  E8DF F000    TBB        [PC, R0]
+  0x08000804:  0F           DC.B       0x0F                     ; '\x0F'
+  0x08000805:  03           DC.B       0x03                     ; '\x03'
+  0x08000806:  09           DC.B       0x09                     ; '\t'
+  0x08000807:  0F           DC.B       0x0F                     ; '\x0F'
+  0x08000808:  0F           DC.B       0x0F                     ; '\x0F'
+  0x08000809:  0F           DC.B       0x0F                     ; '\x0F'
+  0x0800080A:  F104 0008    ADD.W      R0, R4, #8
+  0x0800080E:  2101         MOVS       R1, #1
+  0x08000810:  F001 FB8C    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x08000814:  E004         B          .L58                     ; 0x08000820
+  0x08000816:  F104 0028    ADD.W      R0, R4, #40
+  0x0800081A:  2101         MOVS       R1, #1
+  0x0800081C:  F001 FC0E    BL         RCCEx_PLL3_Config        ; 0x0800203C
+
    .L58:
+  0x08000820:  4605         MOV        R5, R0
+  0x08000822:  46A8         MOV        R8, R5
+  0x08000824:  B935         CBNZ       R5, .L60                 ; 0x08000834
+  0x08000826:  6C70         LDR        R0, [R6, #68]
+  0x08000828:  6F61         LDR        R1, [R4, #116]
+  0x0800082A:  F020 0007    BIC        R0, R0, #7
+  0x0800082E:  4308         ORRS       R0, R1
+  0x08000830:  6470         STR        R0, [R6, #68]
+
    .L59:
+  0x08000832:  46B8         MOV        R8, R7
+
    .L60:
+  0x08000834:  7820         LDRB       R0, [R4]
+  0x08000836:  0740         LSLS       R0, R0, #29
+  0x08000838:  D51E         BPL        .L62                     ; 0x08000878
+  0x0800083A:  F8D4 0090    LDR.W      R0, [R4, #144]
+  0x0800083E:  2805         CMP        R0, #5
+  0x08000840:  F200 81D8    BHI.W      .L114                    ; 0x08000BF4
+  0x08000844:  E8DF F000    TBB        [PC, R0]
+  0x08000848:  0F           DC.B       0x0F                     ; '\x0F'
+  0x08000849:  03           DC.B       0x03                     ; '\x03'
+  0x0800084A:  09           DC.B       0x09                     ; '\t'
+  0x0800084B:  0F           DC.B       0x0F                     ; '\x0F'
+  0x0800084C:  0F           DC.B       0x0F                     ; '\x0F'
+  0x0800084D:  0F           DC.B       0x0F                     ; '\x0F'
+  0x0800084E:  F104 0008    ADD.W      R0, R4, #8
+  0x08000852:  2101         MOVS       R1, #1
+  0x08000854:  F001 FB6A    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x08000858:  E004         B          .L61                     ; 0x08000864
+  0x0800085A:  F104 0028    ADD.W      R0, R4, #40
+  0x0800085E:  2101         MOVS       R1, #1
+  0x08000860:  F001 FBEC    BL         RCCEx_PLL3_Config        ; 0x0800203C
+
    .L61:
+  0x08000864:  4605         MOV        R5, R0
+  0x08000866:  46A9         MOV        R9, R5
+  0x08000868:  B93D         CBNZ       R5, .L63                 ; 0x0800087A
+  0x0800086A:  6CB0         LDR        R0, [R6, #72]
+  0x0800086C:  F8D4 1090    LDR.W      R1, [R4, #144]
+  0x08000870:  F020 0007    BIC        R0, R0, #7
+  0x08000874:  4308         ORRS       R0, R1
+  0x08000876:  64B0         STR        R0, [R6, #72]
+
    .L62:
+  0x08000878:  46C1         MOV        R9, R8
+
    .L63:
+  0x0800087A:  7820         LDRB       R0, [R4]
+  0x0800087C:  0680         LSLS       R0, R0, #26
+  0x0800087E:  D520         BPL        .L65                     ; 0x080008C2
+  0x08000880:  F8D4 008C    LDR.W      R0, [R4, #140]
+  0x08000884:  EA4F 7030    ROR        R0, R0, #28
+  0x08000888:  2805         CMP        R0, #5
+  0x0800088A:  F200 81B6    BHI.W      .L115                    ; 0x08000BFA
+  0x0800088E:  E8DF F000    TBB        [PC, R0]
+  0x08000892:  0F           DC.B       0x0F                     ; '\x0F'
+  0x08000893:  03           DC.B       0x03                     ; '\x03'
+  0x08000894:  09           DC.B       0x09                     ; '\t'
+  0x08000895:  0F           DC.B       0x0F                     ; '\x0F'
+  0x08000896:  0F           DC.B       0x0F                     ; '\x0F'
+  0x08000897:  0F           DC.B       0x0F                     ; '\x0F'
+  0x08000898:  F104 0008    ADD.W      R0, R4, #8
+  0x0800089C:  2100         MOVS       R1, #0
+  0x0800089E:  F001 FB45    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x080008A2:  E004         B          .L64                     ; 0x080008AE
+  0x080008A4:  F104 0028    ADD.W      R0, R4, #40
+  0x080008A8:  2102         MOVS       R1, #2
+  0x080008AA:  F001 FBC7    BL         RCCEx_PLL3_Config        ; 0x0800203C
+
    .L64:
+  0x080008AE:  4605         MOV        R5, R0
+  0x080008B0:  462F         MOV        R7, R5
+  0x080008B2:  B93D         CBNZ       R5, .L66                 ; 0x080008C4
+  0x080008B4:  6C70         LDR        R0, [R6, #68]
+  0x080008B6:  F8D4 108C    LDR.W      R1, [R4, #140]
+  0x080008BA:  F020 40E0    BIC        R0, R0, #0x70000000
+  0x080008BE:  4308         ORRS       R0, R1
+  0x080008C0:  6470         STR        R0, [R6, #68]
+
    .L65:
+  0x080008C2:  464F         MOV        R7, R9
+
    .L66:
+  0x080008C4:  7820         LDRB       R0, [R4]
+  0x080008C6:  0640         LSLS       R0, R0, #25
+  0x080008C8:  D520         BPL        .L68                     ; 0x0800090C
+  0x080008CA:  F8D4 0098    LDR.W      R0, [R4, #152]
+  0x080008CE:  EA4F 20B0    ROR        R0, R0, #10
+  0x080008D2:  2805         CMP        R0, #5
+  0x080008D4:  F200 8194    BHI.W      .L116                    ; 0x08000C00
+  0x080008D8:  E8DF F000    TBB        [PC, R0]
+  0x080008DC:  0F           DC.B       0x0F                     ; '\x0F'
+  0x080008DD:  03           DC.B       0x03                     ; '\x03'
+  0x080008DE:  09           DC.B       0x09                     ; '\t'
+  0x080008DF:  0F           DC.B       0x0F                     ; '\x0F'
+  0x080008E0:  0F           DC.B       0x0F                     ; '\x0F'
+  0x080008E1:  0F           DC.B       0x0F                     ; '\x0F'
+  0x080008E2:  F104 0008    ADD.W      R0, R4, #8
+  0x080008E6:  2100         MOVS       R1, #0
+  0x080008E8:  F001 FB20    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x080008EC:  E004         B          .L67                     ; 0x080008F8
+  0x080008EE:  F104 0028    ADD.W      R0, R4, #40
+  0x080008F2:  2102         MOVS       R1, #2
+  0x080008F4:  F001 FBA2    BL         RCCEx_PLL3_Config        ; 0x0800203C
+
    .L67:
+  0x080008F8:  4605         MOV        R5, R0
+  0x080008FA:  46A8         MOV        R8, R5
+  0x080008FC:  B93D         CBNZ       R5, .L69                 ; 0x0800090E
+  0x080008FE:  6CB0         LDR        R0, [R6, #72]
+  0x08000900:  F8D4 1098    LDR.W      R1, [R4, #152]
+  0x08000904:  F420 50E0    BIC        R0, R0, #0x1C00
+  0x08000908:  4308         ORRS       R0, R1
+  0x0800090A:  64B0         STR        R0, [R6, #72]
+
    .L68:
+  0x0800090C:  46B8         MOV        R8, R7
+
    .L69:
+  0x0800090E:  7820         LDRB       R0, [R4]
+  0x08000910:  0600         LSLS       R0, R0, #24
+  0x08000912:  D520         BPL        .L71                     ; 0x08000956
+  0x08000914:  F8D4 009C    LDR.W      R0, [R4, #156]
+  0x08000918:  EA4F 3070    ROR        R0, R0, #13
+  0x0800091C:  2805         CMP        R0, #5
+  0x0800091E:  F200 8172    BHI.W      .L117                    ; 0x08000C06
+  0x08000922:  E8DF F000    TBB        [PC, R0]
+  0x08000926:  0F           DC.B       0x0F                     ; '\x0F'
+  0x08000927:  03           DC.B       0x03                     ; '\x03'
+  0x08000928:  09           DC.B       0x09                     ; '\t'
+  0x08000929:  0F           DC.B       0x0F                     ; '\x0F'
+  0x0800092A:  0F           DC.B       0x0F                     ; '\x0F'
+  0x0800092B:  0F           DC.B       0x0F                     ; '\x0F'
+  0x0800092C:  F104 0008    ADD.W      R0, R4, #8
+  0x08000930:  2100         MOVS       R1, #0
+  0x08000932:  F001 FAFB    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x08000936:  E004         B          .L70                     ; 0x08000942
+  0x08000938:  F104 0028    ADD.W      R0, R4, #40
+  0x0800093C:  2102         MOVS       R1, #2
+  0x0800093E:  F001 FB7D    BL         RCCEx_PLL3_Config        ; 0x0800203C
+
    .L70:
+  0x08000942:  4605         MOV        R5, R0
+  0x08000944:  462F         MOV        R7, R5
+  0x08000946:  B93D         CBNZ       R5, .L72                 ; 0x08000958
+  0x08000948:  6CB0         LDR        R0, [R6, #72]
+  0x0800094A:  F8D4 109C    LDR.W      R1, [R4, #156]
+  0x0800094E:  F420 4060    BIC        R0, R0, #0xE000
+  0x08000952:  4308         ORRS       R0, R1
+  0x08000954:  64B0         STR        R0, [R6, #72]
+
    .L71:
+  0x08000956:  4647         MOV        R7, R8
+
    .L72:
+  0x08000958:  E9D4 0100    LDRD       R0, R1, [R4]
+  0x0800095C:  0701         LSLS       R1, R0, #28
+  0x0800095E:  D515         BPL        .L74                     ; 0x0800098C
+  0x08000960:  F8D4 0080    LDR.W      R0, [R4, #128]
+  0x08000964:  F5B0 5F80    CMP.W      R0, #0x1000
+  0x08000968:  D109         BNE        .L73                     ; 0x0800097E
+  0x0800096A:  F104 0028    ADD.W      R0, R4, #40
+  0x0800096E:  2102         MOVS       R1, #2
+  0x08000970:  F001 FB64    BL         RCCEx_PLL3_Config        ; 0x0800203C
+  0x08000974:  2800         CMP        R0, #0
+  0x08000976:  BF18         IT         NE
+  0x08000978:  2701         MOVNE      R7, #1
+  0x0800097A:  F8D4 0080    LDR.W      R0, [R4, #128]
+
    .L73:
+  0x0800097E:  6C71         LDR        R1, [R6, #68]
+  0x08000980:  F421 5140    BIC        R1, R1, #0x3000
+  0x08000984:  4308         ORRS       R0, R1
+  0x08000986:  6470         STR        R0, [R6, #68]
+  0x08000988:  E9D4 0100    LDRD       R0, R1, [R4]
+
    .L74:
+  0x0800098C:  06C1         LSLS       R1, R0, #27
+  0x0800098E:  D515         BPL        .L76                     ; 0x080009BC
+  0x08000990:  F8D4 0094    LDR.W      R0, [R4, #148]
+  0x08000994:  F5B0 7F80    CMP.W      R0, #0x0100
+  0x08000998:  D109         BNE        .L75                     ; 0x080009AE
+  0x0800099A:  F104 0028    ADD.W      R0, R4, #40
+  0x0800099E:  2102         MOVS       R1, #2
+  0x080009A0:  F001 FB4C    BL         RCCEx_PLL3_Config        ; 0x0800203C
+  0x080009A4:  2800         CMP        R0, #0
+  0x080009A6:  BF18         IT         NE
+  0x080009A8:  2701         MOVNE      R7, #1
+  0x080009AA:  F8D4 0094    LDR.W      R0, [R4, #148]
+
    .L75:
+  0x080009AE:  6CB1         LDR        R1, [R6, #72]
+  0x080009B0:  F421 7140    BIC        R1, R1, #0x0300
+  0x080009B4:  4308         ORRS       R0, R1
+  0x080009B6:  64B0         STR        R0, [R6, #72]
+  0x080009B8:  E9D4 0100    LDRD       R0, R1, [R4]
+
    .L76:
+  0x080009BC:  0300         LSLS       R0, R0, #12
+  0x080009BE:  D51F         BPL        .L80                     ; 0x08000A00
+  0x080009C0:  F8D4 00A0    LDR.W      R0, [R4, #160]
+  0x080009C4:  F5B0 3F00    CMP.W      R0, #0x020000
+  0x080009C8:  D011         BEQ        .L79                     ; 0x080009EE
+  0x080009CA:  F5B0 3F80    CMP.W      R0, #0x010000
+  0x080009CE:  D008         BEQ        .L77                     ; 0x080009E2
+  0x080009D0:  2800         CMP        R0, #0
+  0x080009D2:  F040 80FB    BNE.W      .L107                    ; 0x08000BCC
+  0x080009D6:  F104 0008    ADD.W      R0, R4, #8
+  0x080009DA:  2100         MOVS       R1, #0
+  0x080009DC:  F001 FAA6    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x080009E0:  E004         B          .L78                     ; 0x080009EC
+
    .L77:
+  0x080009E2:  F104 0028    ADD.W      R0, R4, #40
+  0x080009E6:  2102         MOVS       R1, #2
+  0x080009E8:  F001 FB28    BL         RCCEx_PLL3_Config        ; 0x0800203C
+
    .L78:
+  0x080009EC:  4605         MOV        R5, R0
+
    .L79:
+  0x080009EE:  46A8         MOV        R8, R5
+  0x080009F0:  B93D         CBNZ       R5, .L81                 ; 0x08000A02
+  0x080009F2:  6CB0         LDR        R0, [R6, #72]
+  0x080009F4:  F8D4 10A0    LDR.W      R1, [R4, #160]
+  0x080009F8:  F420 3040    BIC        R0, R0, #0x030000
+  0x080009FC:  4308         ORRS       R0, R1
+  0x080009FE:  64B0         STR        R0, [R6, #72]
+
    .L80:
+  0x08000A00:  46B8         MOV        R8, R7
+
    .L81:
+  0x08000A02:  78A0         LDRB       R0, [R4, #2]
+  0x08000A04:  0740         LSLS       R0, R0, #29
+  0x08000A06:  D51F         BPL        .L84                     ; 0x08000A48
+  0x08000A08:  F8D4 0084    LDR.W      R0, [R4, #132]
+  0x08000A0C:  F5B0 1F40    CMP.W      R0, #0x300000
+  0x08000A10:  D011         BEQ        .L83                     ; 0x08000A36
+  0x08000A12:  F5B0 1F00    CMP.W      R0, #0x200000
+  0x08000A16:  D008         BEQ        .L82                     ; 0x08000A2A
+  0x08000A18:  F5B0 1F80    CMP.W      R0, #0x100000
+  0x08000A1C:  F040 80D9    BNE.W      .L108                    ; 0x08000BD2
+  0x08000A20:  69F0         LDR        R0, [R6, #28]
+  0x08000A22:  F440 3000    ORR        R0, R0, #0x020000
+  0x08000A26:  61F0         STR        R0, [R6, #28]
+  0x08000A28:  E005         B          .L83                     ; 0x08000A36
+
    .L82:
+  0x08000A2A:  F104 0028    ADD.W      R0, R4, #40
+  0x08000A2E:  2101         MOVS       R1, #1
+  0x08000A30:  F001 FB04    BL         RCCEx_PLL3_Config        ; 0x0800203C
+  0x08000A34:  4605         MOV        R5, R0
+
    .L83:
+  0x08000A36:  462F         MOV        R7, R5
+  0x08000A38:  B93D         CBNZ       R5, .L85                 ; 0x08000A4A
+  0x08000A3A:  6C70         LDR        R0, [R6, #68]
+  0x08000A3C:  F8D4 1084    LDR.W      R1, [R4, #132]
+  0x08000A40:  F420 1040    BIC        R0, R0, #0x300000
+  0x08000A44:  4308         ORRS       R0, R1
+  0x08000A46:  6470         STR        R0, [R6, #68]
+
    .L84:
+  0x08000A48:  4647         MOV        R7, R8
+
    .L85:
+  0x08000A4A:  78A0         LDRB       R0, [R4, #2]
+  0x08000A4C:  07C0         LSLS       R0, R0, #31
+  0x08000A4E:  D101         BNE        .L87                     ; 0x08000A54
+
    .L86:
+  0x08000A50:  46B8         MOV        R8, R7
+  0x08000A52:  E01A         B          .L91                     ; 0x08000A8A
+
    .L87:
+  0x08000A54:  6D20         LDR        R0, [R4, #80]
+  0x08000A56:  F5B0 3F80    CMP.W      R0, #0x010000
+  0x08000A5A:  D005         BEQ        .L88                     ; 0x08000A68
+  0x08000A5C:  B998         CBNZ       R0, .L90                 ; 0x08000A86
+  0x08000A5E:  69F0         LDR        R0, [R6, #28]
+  0x08000A60:  F440 3000    ORR        R0, R0, #0x020000
+  0x08000A64:  61F0         STR        R0, [R6, #28]
+  0x08000A66:  E005         B          .L89                     ; 0x08000A74
+
    .L88:
+  0x08000A68:  F104 0008    ADD.W      R0, R4, #8
+  0x08000A6C:  2102         MOVS       R1, #2
+  0x08000A6E:  F001 FA5D    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x08000A72:  4605         MOV        R5, R0
+
    .L89:
+  0x08000A74:  46A8         MOV        R8, R5
+  0x08000A76:  B945         CBNZ       R5, .L91                 ; 0x08000A8A
+  0x08000A78:  6BF0         LDR        R0, [R6, #60]
+  0x08000A7A:  6D21         LDR        R1, [R4, #80]
+  0x08000A7C:  F420 3080    BIC        R0, R0, #0x010000
+  0x08000A80:  4308         ORRS       R0, R1
+  0x08000A82:  63F0         STR        R0, [R6, #60]
+  0x08000A84:  E7E4         B          .L86                     ; 0x08000A50
+
    .L90:
+  0x08000A86:  2501         MOVS       R5, #1
+  0x08000A88:  46A8         MOV        R8, R5
+
    .L91:
+  0x08000A8A:  E9D4 1000    LDRD       R1, R0, [R4]
+  0x08000A8E:  008A         LSLS       R2, R1, #2
+  0x08000A90:  D50A         BPL        .L92                     ; 0x08000AA8
+  0x08000A92:  F104 0028    ADD.W      R0, R4, #40
+  0x08000A96:  2102         MOVS       R1, #2
+  0x08000A98:  F001 FAD0    BL         RCCEx_PLL3_Config        ; 0x0800203C
+  0x08000A9C:  2800         CMP        R0, #0
+  0x08000A9E:  BF18         IT         NE
+  0x08000AA0:  F04F 0801    MOVNE.W    R8, #1
+  0x08000AA4:  E9D4 1000    LDRD       R1, R0, [R4]
+
    .L92:
+  0x08000AA8:  038A         LSLS       R2, R1, #14
+  0x08000AAA:  D516         BPL        .L94                     ; 0x08000ADA
+  0x08000AAC:  6FE2         LDR        R2, [R4, #124]
+  0x08000AAE:  F06F 0301    MVN        R3, #1
+  0x08000AB2:  EB03 2332    ADD.W      R3, R3, R2, ROR #8
+  0x08000AB6:  2B02         CMP        R3, #2
+  0x08000AB8:  D309         BCC        .L93                     ; 0x08000ACE
+  0x08000ABA:  EA4F 2332    ROR        R3, R2, #8
+  0x08000ABE:  B133         CBZ        R3, .L93                 ; 0x08000ACE
+  0x08000AC0:  2B01         CMP        R3, #1
+  0x08000AC2:  F040 8089    BNE.W      .L109                    ; 0x08000BD8
+  0x08000AC6:  69F3         LDR        R3, [R6, #28]
+  0x08000AC8:  F443 3300    ORR        R3, R3, #0x020000
+  0x08000ACC:  61F3         STR        R3, [R6, #28]
+
    .L93:
+  0x08000ACE:  B92D         CBNZ       R5, .L95                 ; 0x08000ADC
+  0x08000AD0:  6C73         LDR        R3, [R6, #68]
+  0x08000AD2:  F423 7340    BIC        R3, R3, #0x0300
+  0x08000AD6:  431A         ORRS       R2, R3
+  0x08000AD8:  6472         STR        R2, [R6, #68]
+
    .L94:
+  0x08000ADA:  4645         MOV        R5, R8
+
    .L95:
+  0x08000ADC:  02CA         LSLS       R2, R1, #11
+  0x08000ADE:  D505         BPL        .L96                     ; 0x08000AEC
+  0x08000AE0:  6C32         LDR        R2, [R6, #64]
+  0x08000AE2:  6F23         LDR        R3, [R4, #112]
+  0x08000AE4:  F022 4200    BIC        R2, R2, #0x80000000
+  0x08000AE8:  431A         ORRS       R2, R3
+  0x08000AEA:  6432         STR        R2, [R6, #64]
+
    .L96:
+  0x08000AEC:  028A         LSLS       R2, R1, #10
+  0x08000AEE:  D505         BPL        .L97                     ; 0x08000AFC
+  0x08000AF0:  6C32         LDR        R2, [R6, #64]
+  0x08000AF2:  6EA3         LDR        R3, [R4, #104]
+  0x08000AF4:  F022 7280    BIC        R2, R2, #0x01000000
+  0x08000AF8:  431A         ORRS       R2, R3
+  0x08000AFA:  6432         STR        R2, [R6, #64]
+
    .L97:
+  0x08000AFC:  004A         LSLS       R2, R1, #1
+  0x08000AFE:  D508         BPL        .L98                     ; 0x08000B12
+  0x08000B00:  6832         LDR        R2, [R6]
+  0x08000B02:  F422 4200    BIC        R2, R2, #0x8000
+  0x08000B06:  6032         STR        R2, [R6]
+  0x08000B08:  F8D4 20B4    LDR.W      R2, [R4, #180]
+  0x08000B0C:  6833         LDR        R3, [R6]
+  0x08000B0E:  431A         ORRS       R2, R3
+  0x08000B10:  6032         STR        R2, [R6]
+
    .L98:
+  0x08000B12:  0FCA         LSRS       R2, R1, #31
+  0x08000B14:  D005         BEQ        .L99                     ; 0x08000B22
+  0x08000B16:  6BF2         LDR        R2, [R6, #60]
+  0x08000B18:  6D63         LDR        R3, [R4, #84]
+  0x08000B1A:  F022 5240    BIC        R2, R2, #0x30000000
+  0x08000B1E:  431A         ORRS       R2, R3
+  0x08000B20:  63F2         STR        R2, [R6, #60]
+
    .L99:
+  0x08000B22:  0209         LSLS       R1, R1, #8
+  0x08000B24:  D506         BPL        .L100                    ; 0x08000B34
+  0x08000B26:  6C71         LDR        R1, [R6, #68]
+  0x08000B28:  F8D4 2088    LDR.W      R2, [R4, #136]
+  0x08000B2C:  F421 0140    BIC        R1, R1, #0xC00000
+  0x08000B30:  4311         ORRS       R1, R2
+  0x08000B32:  6471         STR        R1, [R6, #68]
+
    .L100:
+  0x08000B34:  07C1         LSLS       R1, R0, #31
+  0x08000B36:  D009         BEQ        .L101                    ; 0x08000B4C
+  0x08000B38:  F104 0008    ADD.W      R0, R4, #8
+  0x08000B3C:  2100         MOVS       R1, #0
+  0x08000B3E:  F001 F9F5    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x08000B42:  2800         CMP        R0, #0
+  0x08000B44:  BF18         IT         NE
+  0x08000B46:  4605         MOVNE      R5, R0
+  0x08000B48:  E9D4 1000    LDRD       R1, R0, [R4]
+
    .L101:
+  0x08000B4C:  0781         LSLS       R1, R0, #30
+  0x08000B4E:  D509         BPL        .L102                    ; 0x08000B64
+  0x08000B50:  F104 0008    ADD.W      R0, R4, #8
+  0x08000B54:  2101         MOVS       R1, #1
+  0x08000B56:  F001 F9E9    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x08000B5A:  2800         CMP        R0, #0
+  0x08000B5C:  BF18         IT         NE
+  0x08000B5E:  4605         MOVNE      R5, R0
+  0x08000B60:  E9D4 1000    LDRD       R1, R0, [R4]
+
    .L102:
+  0x08000B64:  0741         LSLS       R1, R0, #29
+  0x08000B66:  D509         BPL        .L103                    ; 0x08000B7C
+  0x08000B68:  F104 0008    ADD.W      R0, R4, #8
+  0x08000B6C:  2102         MOVS       R1, #2
+  0x08000B6E:  F001 F9DD    BL         RCCEx_PLL2_Config        ; 0x08001F2C
+  0x08000B72:  2800         CMP        R0, #0
+  0x08000B74:  BF18         IT         NE
+  0x08000B76:  4605         MOVNE      R5, R0
+  0x08000B78:  E9D4 1000    LDRD       R1, R0, [R4]
+
    .L103:
+  0x08000B7C:  0701         LSLS       R1, R0, #28
+  0x08000B7E:  D509         BPL        .L104                    ; 0x08000B94
+  0x08000B80:  F104 0028    ADD.W      R0, R4, #40
+  0x08000B84:  2100         MOVS       R1, #0
+  0x08000B86:  F001 FA59    BL         RCCEx_PLL3_Config        ; 0x0800203C
+  0x08000B8A:  2800         CMP        R0, #0
+  0x08000B8C:  BF18         IT         NE
+  0x08000B8E:  4605         MOVNE      R5, R0
+  0x08000B90:  E9D4 1000    LDRD       R1, R0, [R4]
+
    .L104:
+  0x08000B94:  06C1         LSLS       R1, R0, #27
+  0x08000B96:  D509         BPL        .L105                    ; 0x08000BAC
+  0x08000B98:  F104 0028    ADD.W      R0, R4, #40
+  0x08000B9C:  2101         MOVS       R1, #1
+  0x08000B9E:  F001 FA4D    BL         RCCEx_PLL3_Config        ; 0x0800203C
+  0x08000BA2:  2800         CMP        R0, #0
+  0x08000BA4:  BF18         IT         NE
+  0x08000BA6:  4605         MOVNE      R5, R0
+  0x08000BA8:  E9D4 1000    LDRD       R1, R0, [R4]
+
    .L105:
+  0x08000BAC:  0680         LSLS       R0, R0, #26
+  0x08000BAE:  D507         BPL        .L106                    ; 0x08000BC0
+  0x08000BB0:  F104 0028    ADD.W      R0, R4, #40
+  0x08000BB4:  2102         MOVS       R1, #2
+  0x08000BB6:  F001 FA41    BL         RCCEx_PLL3_Config        ; 0x0800203C
+  0x08000BBA:  2800         CMP        R0, #0
+  0x08000BBC:  BF18         IT         NE
+  0x08000BBE:  2501         MOVNE      R5, #1
+
    .L106:
+  0x08000BC0:  2D00         CMP        R5, #0
+  0x08000BC2:  BF18         IT         NE
+  0x08000BC4:  2501         MOVNE      R5, #1
+  0x08000BC6:  4628         MOV        R0, R5
+  0x08000BC8:  E8BD 83F8    POP.W      {R3-R9, PC}
+
    .L107:
+  0x08000BCC:  2501         MOVS       R5, #1
+  0x08000BCE:  46A8         MOV        R8, R5
+  0x08000BD0:  E717         B          .L81                     ; 0x08000A02
+
    .L108:
+  0x08000BD2:  2501         MOVS       R5, #1
+  0x08000BD4:  2701         MOVS       R7, #1
+  0x08000BD6:  E738         B          .L85                     ; 0x08000A4A
+
    .L109:
+  0x08000BD8:  2501         MOVS       R5, #1
+  0x08000BDA:  E77F         B          .L95                     ; 0x08000ADC
+
    .L110:
+  0x08000BDC:  2501         MOVS       R5, #1
+  0x08000BDE:  46A8         MOV        R8, R5
+  0x08000BE0:  E51E         B          .L33                     ; 0x08000620
+
    .L111:
+  0x08000BE2:  2501         MOVS       R5, #1
+  0x08000BE4:  2701         MOVS       R7, #1
+  0x08000BE6:  E540         B          .L36                     ; 0x0800066A
+
    .L112:
+  0x08000BE8:  2501         MOVS       R5, #1
+  0x08000BEA:  2701         MOVS       R7, #1
+  0x08000BEC:  E601         B          .L57                     ; 0x080007F2
+
    .L113:
+  0x08000BEE:  2501         MOVS       R5, #1
+  0x08000BF0:  46A8         MOV        R8, R5
+  0x08000BF2:  E61F         B          .L60                     ; 0x08000834
+
    .L114:
+  0x08000BF4:  2501         MOVS       R5, #1
+  0x08000BF6:  46A9         MOV        R9, R5
+  0x08000BF8:  E63F         B          .L63                     ; 0x0800087A
+
    .L115:
+  0x08000BFA:  2501         MOVS       R5, #1
+  0x08000BFC:  2701         MOVS       R7, #1
+  0x08000BFE:  E661         B          .L66                     ; 0x080008C4
+
    .L116:
+  0x08000C00:  2501         MOVS       R5, #1
+  0x08000C02:  46A8         MOV        R8, R5
+  0x08000C04:  E683         B          .L69                     ; 0x0800090E
+
    .L117:
+  0x08000C06:  2501         MOVS       R5, #1
+  0x08000C08:  2701         MOVS       R7, #1
+  0x08000C0A:  E6A5         B          .L72                     ; 0x08000958
+

    Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4

    -
    _start:
-  0x080003D8:  4C03         LDR        R4, =0x08000BC0          ; [PC, #12] [0x080003E8] 
+
    _start:
+  0x08000C0C:  4C03         LDR        R4, =0x08002334          ; [PC, #12] [0x08000C1C] 
 
    .L1:
-  0x080003DA:  6820         LDR        R0, [R4]
-  0x080003DC:  3404         ADDS       R4, #4
-  0x080003DE:  4780         BLX        R0
-  0x080003E0:  E7FB         B          .L1                      ; 0x080003DA
-
    __SEGGER_init_done:
-__startup_complete:
-  0x080003E2:  F000 FAF8    BL         main                     ; 0x080009D6
-
    exit:
-  0x080003E6:  E7FE         B          exit                     ; 0x080003E6
-  0x080003E8:  08000BC0     DC.W       0x08000BC0               ; R_ARM_ABS32
+  0x08000C0E:  6820         LDR        R0, [R4]
+  0x08000C10:  3404         ADDS       R4, #4
+  0x08000C12:  4780         BLX        R0
+  0x08000C14:  E7FB         B          .L1                      ; 0x08000C0E
+
    __SEGGER_init_done:
+__startup_complete:
+  0x08000C16:  F000 FA7A    BL         main                     ; 0x0800110E
+
    exit:
+  0x08000C1A:  E7FE         B          exit                     ; 0x08000C1A
+  0x08000C1C:  08002334     DC.W       0x08002334               ; R_ARM_ABS32
    -

    Section .text.SystemClock_Config() from charger_lto.o, size=794, align=2

    +

    Section .text.libc.__aeabi_memclr from strasmops_arm.o (strops_unaligned_v7em_fpv5_d16_hard_t_le_eabi_balanced.a), size=104, align=4

    -
    SystemClock_Config():
-  0x080003EC:  B510         PUSH       {R4, LR}
-  0x080003EE:  B082         SUB        SP, SP, #8
-  0x080003F0:  F644 010C    MOVW       R1, #0x480C
-  0x080003F4:  F6C5 0102    MOVT       R1, #0x5802
-  0x080003F8:  6808         LDR        R0, [R1]
-  0x080003FA:  680A         LDR        R2, [R1]
-  0x080003FC:  0740         LSLS       R0, R0, #29
-  0x080003FE:  F240 0024    MOVW       R0, #36                  ; 0x30000024 = uwTick
-  0x08000402:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000024 = uwTick
-  0x08000406:  D50D         BPL        .L2                      ; 0x08000424
-  0x08000408:  2302         MOVS       R3, #2
-  0x0800040A:  F363 0202    BFI        R2, R3, #0, #3
-  0x0800040E:  600A         STR        R2, [R1]
-  0x08000410:  6802         LDR        R2, [R0]
+
    __aeabi_memclr:
+__aeabi_memclr8:
+__aeabi_memclr4:
+  0x08000C20:  2200         MOVS       R2, #0
+
    __aeabi_memset8:
+__aeabi_memset4:
+__aeabi_memset:
+  0x08000C22:  000B         MOVS       R3, R1
+  0x08000C24:  0011         MOVS       R1, R2
+  0x08000C26:  001A         MOVS       R2, R3
+
    memset:
+  0x08000C28:  4684         MOV        R12, R0
+  0x08000C2A:  B35A         CBZ        R2, .L7                  ; 0x08000C84
 
    .L1:
-  0x08000412:  F851 3C08    LDR        R3, [R1, #-8]
-  0x08000416:  049B         LSLS       R3, R3, #18
-  0x08000418:  D404         BMI        .L2                      ; 0x08000424
-  0x0800041A:  6803         LDR        R3, [R0]
-  0x0800041C:  1A9B         SUBS       R3, R3, R2
-  0x0800041E:  F5B3 7F7A    CMP.W      R3, #0x03E8
-  0x08000422:  D9F6         BLS        .L1                      ; 0x08000412
+  0x08000C2C:  0783         LSLS       R3, R0, #30
+  0x08000C2E:  D004         BEQ        .L2                      ; 0x08000C3A
+  0x08000C30:  F800 1B01    STRB       R1, [R0], #1
+  0x08000C34:  3A01         SUBS       R2, #1
+  0x08000C36:  D1F9         BNE        .L1                      ; 0x08000C2C
+  0x08000C38:  E024         B          .L7                      ; 0x08000C84
 
    .L2:
-  0x08000424:  2200         MOVS       R2, #0
-  0x08000426:  9201         STR        R2, [SP, #4]
-  0x08000428:  68CA         LDR        R2, [R1, #12]
-  0x0800042A:  2302         MOVS       R3, #2
-  0x0800042C:  F363 328F    BFI        R2, R3, #14, #2
-  0x08000430:  60CA         STR        R2, [R1, #12]
-  0x08000432:  68CA         LDR        R2, [R1, #12]
-  0x08000434:  F402 4240    AND        R2, R2, #0xC000
-  0x08000438:  9201         STR        R2, [SP, #4]
-  0x0800043A:  9A01         LDR        R2, [SP, #4]
+  0x08000C3A:  B2C9         UXTB       R1, R1
+  0x08000C3C:  EA41 2101    ORR.W      R1, R1, R1, LSL #8
+  0x08000C40:  EA41 4101    ORR.W      R1, R1, R1, LSL #16
+  0x08000C44:  2A20         CMP        R2, #32
+  0x08000C46:  D311         BCC        .L4                      ; 0x08000C6C
+  0x08000C48:  3A20         SUBS       R2, #32
+  0x08000C4A:  E92D 03F0    PUSH.W     {R4-R9}
+  0x08000C4E:  460B         MOV        R3, R1
+  0x08000C50:  460C         MOV        R4, R1
+  0x08000C52:  460D         MOV        R5, R1
+  0x08000C54:  460E         MOV        R6, R1
+  0x08000C56:  460F         MOV        R7, R1
+  0x08000C58:  4688         MOV        R8, R1
+  0x08000C5A:  4689         MOV        R9, R1
 
    .L3:
-  0x0800043C:  68CA         LDR        R2, [R1, #12]
-  0x0800043E:  0492         LSLS       R2, R2, #18
-  0x08000440:  D5FC         BPL        .L3                      ; 0x0800043C
-  0x08000442:  F244 4400    MOVW       R4, #0x4400
-  0x08000446:  F6C5 0402    MOVT       R4, #0x5802
-  0x0800044A:  F8D4 1400    LDR.W      R1, [R4, #0x0400]
-  0x0800044E:  F441 7180    ORR        R1, R1, #0x0100
-  0x08000452:  F8C4 1400    STR.W      R1, [R4, #0x0400]
-  0x08000456:  6F21         LDR        R1, [R4, #112]
-  0x08000458:  F021 0118    BIC        R1, R1, #24
-  0x0800045C:  6721         STR        R1, [R4, #112]
-  0x0800045E:  6921         LDR        R1, [R4, #16]
-  0x08000460:  F001 0238    AND        R2, R1, #56
-  0x08000464:  6AA1         LDR        R1, [R4, #40]
-  0x08000466:  2A10         CMP        R2, #16
-  0x08000468:  D007         BEQ        .L4                      ; 0x0800047A
-  0x0800046A:  2A18         CMP        R2, #24
-  0x0800046C:  F040 80F4    BNE.W      .L16                     ; 0x08000658
-  0x08000470:  F001 0103    AND        R1, R1, #3
-  0x08000474:  2902         CMP        R1, #2
-  0x08000476:  F040 80EF    BNE.W      .L16                     ; 0x08000658
+  0x08000C5C:  E8A0 03FA    STM.W      R0!, {R1, R3-R9}
+  0x08000C60:  3A20         SUBS       R2, #32
+  0x08000C62:  D2FB         BCS        .L3                      ; 0x08000C5C
+  0x08000C64:  E8BD 03F0    POP.W      {R4-R9}
+  0x08000C68:  3220         ADDS       R2, #32
+  0x08000C6A:  D00B         BEQ        .L7                      ; 0x08000C84
 
    .L4:
-  0x0800047A:  6821         LDR        R1, [R4]
+  0x08000C6C:  2A04         CMP        R2, #4
+  0x08000C6E:  D305         BCC        .L6                      ; 0x08000C7C
 
    .L5:
-  0x0800047C:  F8D4 1400    LDR.W      R1, [R4, #0x0400]
-  0x08000480:  F441 7180    ORR        R1, R1, #0x0100
-  0x08000484:  F8C4 1400    STR.W      R1, [R4, #0x0400]
-  0x08000488:  6801         LDR        R1, [R0]
+  0x08000C70:  F840 1B04    STR        R1, [R0], #4
+  0x08000C74:  3A04         SUBS       R2, #4
+  0x08000C76:  D005         BEQ        .L7                      ; 0x08000C84
+  0x08000C78:  2A04         CMP        R2, #4
+  0x08000C7A:  D2F9         BCS        .L5                      ; 0x08000C70
 
    .L6:
-  0x0800048A:  F8D4 2400    LDR.W      R2, [R4, #0x0400]
-  0x0800048E:  05D2         LSLS       R2, R2, #23
-  0x08000490:  D404         BMI        .L7                      ; 0x0800049C
-  0x08000492:  6802         LDR        R2, [R0]
-  0x08000494:  1A52         SUBS       R2, R2, R1
-  0x08000496:  2A64         CMP        R2, #100
-  0x08000498:  D9F7         BLS        .L6                      ; 0x0800048A
-  0x0800049A:  E132         B          .L22                     ; 0x08000702
+  0x08000C7C:  F800 1B01    STRB       R1, [R0], #1
+  0x08000C80:  3A01         SUBS       R2, #1
+  0x08000C82:  D1FB         BNE        .L6                      ; 0x08000C7C
 
    .L7:
-  0x0800049C:  6F21         LDR        R1, [R4, #112]
-  0x0800049E:  F241 3288    MOVW       R2, #0x1388
-  0x080004A2:  F041 0101    ORR        R1, R1, #1
-  0x080004A6:  6721         STR        R1, [R4, #112]
-  0x080004A8:  6801         LDR        R1, [R0]
+  0x08000C84:  4660         MOV        R0, R12
+  0x08000C86:  4770         BX         LR
+
    +

    Section .text.HAL_SPI_Init from charger_lto.o, size=1158, align=4

    +
    +
    HAL_SPI_Init:
+  0x08000C88:  E92D 4FF0    PUSH.W     {R4-R11, LR}
+  0x08000C8C:  B0B1         SUB        SP, SP, #196
+  0x08000C8E:  F240 0400    MOVW       R4, #0                   ; 0x30000000 = hspi4
+  0x08000C92:  F643 0100    MOVW       R1, #0x3800
+  0x08000C96:  F2C3 0400    MOVT       R4, #0x3000              ; 0x30000000 = hspi4
+  0x08000C9A:  2000         MOVS       R0, #0
+  0x08000C9C:  F2C4 0100    MOVT       R1, #0x4000
+  0x08000CA0:  6827         LDR        R7, [R4]
+  0x08000CA2:  62A0         STR        R0, [R4, #40]
+  0x08000CA4:  F501 4078    ADD.W      R0, R1, #0xF800
+  0x08000CA8:  428F         CMP        R7, R1
+  0x08000CAA:  F5A0 4574    SUB.W      R5, R0, #0xF400
+  0x08000CAE:  D004         BEQ        .L1                      ; 0x08000CBA
+  0x08000CB0:  42AF         CMP        R7, R5
+  0x08000CB2:  BF18         IT         NE
+  0x08000CB4:  4287         CMPNE      R7, R0
+  0x08000CB6:  F040 80D5    BNE.W      .L8                      ; 0x08000E64
+
    .L1:
+  0x08000CBA:  6BE2         LDR        R2, [R4, #60]
+  0x08000CBC:  2601         MOVS       R6, #1
+  0x08000CBE:  68E3         LDR        R3, [R4, #12]
+  0x08000CC0:  3308         ADDS       R3, #8
+  0x08000CC2:  EB06 1252    ADD.W      R2, R6, R2, LSR #5
+  0x08000CC6:  08DB         LSRS       R3, R3, #3
+  0x08000CC8:  428F         CMP        R7, R1
+  0x08000CCA:  FB03 F202    MUL        R2, R3, R2
+  0x08000CCE:  BF18         IT         NE
+  0x08000CD0:  4287         CMPNE      R7, R0
+  0x08000CD2:  F040 80BB    BNE.W      .L7                      ; 0x08000E4C
+
    .L2:
+  0x08000CD6:  2A10         CMP        R2, #16
+  0x08000CD8:  F200 80C8    BHI.W      .L9                      ; 0x08000E6C
+
    .L3:
+  0x08000CDC:  F894 0081    LDRB.W     R0, [R4, #129]
+  0x08000CE0:  2800         CMP        R0, #0
+  0x08000CE2:  F040 8181    BNE.W      .L26                     ; 0x08000FE8
+  0x08000CE6:  A80C         ADD        R0, SP, #48
+  0x08000CE8:  2190         MOVS       R1, #144
+  0x08000CEA:  2600         MOVS       R6, #0
+  0x08000CEC:  F884 6080    STRB.W     R6, [R4, #128]
+  0x08000CF0:  F7FF FF96    BL         __aeabi_memclr           ; 0x08000C20
+  0x08000CF4:  F505 4078    ADD.W      R0, R5, #0xF800
+  0x08000CF8:  4287         CMP        R7, R0
+  0x08000CFA:  F040 8175    BNE.W      .L26                     ; 0x08000FE8
+  0x08000CFE:  F44F 5000    MOV.W      R0, #0x2000
+  0x08000D02:  2102         MOVS       R1, #2
+  0x08000D04:  E9CD 0602    STRD       R0, R6, [SP, #8]
+  0x08000D08:  2003         MOVS       R0, #3
+  0x08000D0A:  9004         STR        R0, [SP, #16]
+  0x08000D0C:  2028         MOVS       R0, #40
+  0x08000D0E:  960B         STR        R6, [SP, #44]
+  0x08000D10:  E9CD 0105    STRD       R0, R1, [SP, #20]
+  0x08000D14:  200B         MOVS       R0, #11
+  0x08000D16:  E9CD 0107    STRD       R0, R1, [SP, #28]
+  0x08000D1A:  20C0         MOVS       R0, #192
+  0x08000D1C:  E9CD 0609    STRD       R0, R6, [SP, #36]
+  0x08000D20:  F44F 3080    MOV.W      R0, #0x010000
+  0x08000D24:  901A         STR        R0, [SP, #104]
+  0x08000D26:  A802         ADD        R0, SP, #8
+  0x08000D28:  F7FF FB56    BL         HAL_RCCEx_PeriphCLKConfig ; 0x080003D8
+  0x08000D2C:  2800         CMP        R0, #0
+  0x08000D2E:  F040 81ED    BNE.W      .L40                     ; 0x0800110C
+  0x08000D32:  F244 41E0    MOVW       R1, #0x44E0
+  0x08000D36:  F241 0C00    MOVW       R12, #0x1000
+  0x08000D3A:  F6C5 0102    MOVT       R1, #0x5802
+  0x08000D3E:  F6C5 0C02    MOVT       R12, #0x5802
+  0x08000D42:  F04F 0A01    MOV.W      R10, #1
+  0x08000D46:  F04F 0E0F    MOV.W      LR, #15
+  0x08000D4A:  6908         LDR        R0, [R1, #16]
+  0x08000D4C:  F04F 0B05    MOV.W      R11, #5
+  0x08000D50:  F440 5000    ORR        R0, R0, #0x2000
+  0x08000D54:  6108         STR        R0, [R1, #16]
+  0x08000D56:  6908         LDR        R0, [R1, #16]
+  0x08000D58:  2300         MOVS       R3, #0
+  0x08000D5A:  F400 5000    AND        R0, R0, #0x2000
+  0x08000D5E:  9001         STR        R0, [SP, #4]
+  0x08000D60:  9801         LDR        R0, [SP, #4]
+  0x08000D62:  6808         LDR        R0, [R1]
+  0x08000D64:  F040 0010    ORR        R0, R0, #16
+  0x08000D68:  6008         STR        R0, [R1]
+  0x08000D6A:  6809         LDR        R1, [R1]
+  0x08000D6C:  F001 0110    AND        R1, R1, #16
+  0x08000D70:  9101         STR        R1, [SP, #4]
+  0x08000D72:  9901         LDR        R1, [SP, #4]
+  0x08000D74:  2100         MOVS       R1, #0
+
    .L4:
+  0x08000D76:  FA0A F903    LSL.W      R9, R10, R3
+  0x08000D7A:  F419 4FB0    TST        R9, #0x5800
+  0x08000D7E:  D02B         BEQ        .L5                      ; 0x08000DD8
+  0x08000D80:  2003         MOVS       R0, #3
+  0x08000D82:  F8DC 8008    LDR.W      R8, [R12, #8]
+  0x08000D86:  FA00 F701    LSL.W      R7, R0, R1
+  0x08000D8A:  43C0         MVNS       R0, R0
+  0x08000D8C:  EA28 0507    BIC.W      R5, R8, R7
+  0x08000D90:  F8CC 5008    STR.W      R5, [R12, #8]
+  0x08000D94:  F8DC 5004    LDR.W      R5, [R12, #4]
+  0x08000D98:  EA25 0909    BIC.W      R9, R5, R9
+  0x08000D9C:  F8CC 9004    STR.W      R9, [R12, #4]
+  0x08000DA0:  F8DC 900C    LDR.W      R9, [R12, #12]
+  0x08000DA4:  EA00 0553    AND.W      R5, R0, R3, LSR #1
+  0x08000DA8:  EA29 0907    BIC.W      R9, R9, R7
+  0x08000DAC:  4465         ADD        R5, R12
+  0x08000DAE:  F8CC 900C    STR.W      R9, [R12, #12]
+  0x08000DB2:  F006 091C    AND        R9, R6, #28
+  0x08000DB6:  6A2A         LDR        R2, [R5, #32]
+  0x08000DB8:  FA0E F009    LSL.W      R0, LR, R9
+  0x08000DBC:  EA22 0000    BIC.W      R0, R2, R0
+  0x08000DC0:  FA0B F209    LSL.W      R2, R11, R9
+  0x08000DC4:  4310         ORRS       R0, R2
+  0x08000DC6:  6228         STR        R0, [R5, #32]
+  0x08000DC8:  F8DC 0000    LDR.W      R0, [R12]
+  0x08000DCC:  2202         MOVS       R2, #2
+  0x08000DCE:  43B8         BICS       R0, R7
+  0x08000DD0:  408A         LSLS       R2, R1
+  0x08000DD2:  4310         ORRS       R0, R2
+  0x08000DD4:  F8CC 0000    STR.W      R0, [R12]
+
    .L5:
+  0x08000DD8:  3301         ADDS       R3, #1
+  0x08000DDA:  3604         ADDS       R6, #4
+  0x08000DDC:  3102         ADDS       R1, #2
+  0x08000DDE:  2B0F         CMP        R3, #15
+  0x08000DE0:  D1C9         BNE        .L4                      ; 0x08000D76
+  0x08000DE2:  F240 0088    MOVW       R0, #136                 ; 0x30000088 = hdma_spi4_tx
+  0x08000DE6:  2154         MOVS       R1, #84
+  0x08000DE8:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000088 = hdma_spi4_tx
+  0x08000DEC:  2700         MOVS       R7, #0
+  0x08000DEE:  F240 1224    MOVW       R2, #0x0124              ; 0x30000124 = uwTick
+  0x08000DF2:  2508         MOVS       R5, #8
+  0x08000DF4:  6041         STR        R1, [R0, #4]
+  0x08000DF6:  2140         MOVS       R1, #64
+  0x08000DF8:  E9C0 1702    STRD       R1, R7, [R0, #8]
+  0x08000DFC:  F44F 6180    MOV.W      R1, #0x0400
+  0x08000E00:  6101         STR        R1, [R0, #16]
+  0x08000E02:  F44F 6100    MOV.W      R1, #0x0800
+  0x08000E06:  6141         STR        R1, [R0, #20]
+  0x08000E08:  F44F 5100    MOV.W      R1, #0x2000
+  0x08000E0C:  F2C3 0200    MOVT       R2, #0x3000              ; 0x30000124 = uwTick
+  0x08000E10:  F2C4 0502    MOVT       R5, #0x4002
+  0x08000E14:  2602         MOVS       R6, #2
+  0x08000E16:  E9C0 1706    STRD       R1, R7, [R0, #24]
+  0x08000E1A:  E9C0 7708    STRD       R7, R7, [R0, #32]
+  0x08000E1E:  4629         MOV        R1, R5
+  0x08000E20:  6813         LDR        R3, [R2]
+  0x08000E22:  F880 6035    STRB.W     R6, [R0, #53]
+  0x08000E26:  F851 6F08    LDR        R6, [R1, #8]!
+  0x08000E2A:  6001         STR        R1, [R0]
+  0x08000E2C:  F880 7034    STRB.W     R7, [R0, #52]
+  0x08000E30:  F026 0701    BIC        R7, R6, #1
+  0x08000E34:  600F         STR        R7, [R1]
+
    .L6:
+  0x08000E36:  68A9         LDR        R1, [R5, #8]
+  0x08000E38:  07C9         LSLS       R1, R1, #31
+  0x08000E3A:  D019         BEQ        .L10                     ; 0x08000E70
+  0x08000E3C:  6811         LDR        R1, [R2]
+  0x08000E3E:  1AC9         SUBS       R1, R1, R3
+  0x08000E40:  2905         CMP        R1, #5
+  0x08000E42:  D9F8         BLS        .L6                      ; 0x08000E36
+  0x08000E44:  F04F 0E03    MOV.W      LR, #3
+  0x08000E48:  2620         MOVS       R6, #32
+  0x08000E4A:  E06A         B          .L15                     ; 0x08000F22
+
    .L7:
+  0x08000E4C:  42AF         CMP        R7, R5
+  0x08000E4E:  BF18         IT         NE
+  0x08000E50:  2A08         CMPNE      R2, #8
+  0x08000E52:  D80B         BHI        .L9                      ; 0x08000E6C
+  0x08000E54:  F505 4074    ADD.W      R0, R5, #0xF400
+  0x08000E58:  4287         CMP        R7, R0
+  0x08000E5A:  BF18         IT         NE
+  0x08000E5C:  42AF         CMPNE      R7, R5
+  0x08000E5E:  F43F AF3A    BEQ.W      .L2                      ; 0x08000CD6
+  0x08000E62:  E73B         B          .L3                      ; 0x08000CDC
 
    .L8:
-  0x080004AA:  6F23         LDR        R3, [R4, #112]
-  0x080004AC:  079B         LSLS       R3, R3, #30
-  0x080004AE:  D404         BMI        .L9                      ; 0x080004BA
-  0x080004B0:  6803         LDR        R3, [R0]
-  0x080004B2:  1A5B         SUBS       R3, R3, R1
-  0x080004B4:  4293         CMP        R3, R2
-  0x080004B6:  D9F8         BLS        .L8                      ; 0x080004AA
-  0x080004B8:  E123         B          .L22                     ; 0x08000702
+  0x08000E64:  68E2         LDR        R2, [R4, #12]
+  0x08000E66:  2A0F         CMP        R2, #15
+  0x08000E68:  F67F AF27    BLS.W      .L1                      ; 0x08000CBA
 
    .L9:
-  0x080004BA:  6921         LDR        R1, [R4, #16]
-  0x080004BC:  F001 0138    AND        R1, R1, #56
-  0x080004C0:  2918         CMP        R1, #24
-  0x080004C2:  F040 80D7    BNE.W      .L18                     ; 0x08000674
-  0x080004C6:  6AA1         LDR        R1, [R4, #40]
-  0x080004C8:  F240 32F3    MOVW       R2, #0x03F3
-  0x080004CC:  4011         ANDS       R1, R2
-  0x080004CE:  F5B1 7FC9    CMP.W      R1, #0x0192
-  0x080004D2:  6B21         LDR        R1, [R4, #48]
-  0x080004D4:  F040 8115    BNE.W      .L22                     ; 0x08000702
-  0x080004D8:  460A         MOV        R2, R1
-  0x080004DA:  F36F 225F    BFC        R2, #9, #23
-  0x080004DE:  2AC7         CMP        R2, #199
-  0x080004E0:  F040 810F    BNE.W      .L22                     ; 0x08000702
-  0x080004E4:  F401 427E    AND        R2, R1, #0xFE00
-  0x080004E8:  F5B2 7F00    CMP.W      R2, #0x0200
-  0x080004EC:  F040 8109    BNE.W      .L22                     ; 0x08000702
-  0x080004F0:  F401 02FE    AND        R2, R1, #0x7F0000
-  0x080004F4:  F5B2 3F80    CMP.W      R2, #0x010000
-  0x080004F8:  F040 8103    BNE.W      .L22                     ; 0x08000702
-  0x080004FC:  F001 41FE    AND        R1, R1, #0x7F000000
-  0x08000500:  F1B1 7F80    CMP.W      R1, #0x01000000
-  0x08000504:  F040 80FD    BNE.W      .L22                     ; 0x08000702
-  0x08000508:  6B61         LDR        R1, [R4, #52]
-  0x0800050A:  F64F 72F8    MOVW       R2, #0xFFF8
-  0x0800050E:  4211         TST        R1, R2
-  0x08000510:  D010         BEQ        .L11                     ; 0x08000534
-  0x08000512:  6AE1         LDR        R1, [R4, #44]
-  0x08000514:  F021 0101    BIC        R1, R1, #1
-  0x08000518:  62E1         STR        R1, [R4, #44]
-  0x0800051A:  6801         LDR        R1, [R0]
+  0x08000E6C:  2001         MOVS       R0, #1
+  0x08000E6E:  E13D         B          .L36                     ; 0x080010EC
 
    .L10:
-  0x0800051C:  6802         LDR        R2, [R0]
-  0x0800051E:  428A         CMP        R2, R1
-  0x08000520:  D0FC         BEQ        .L10                     ; 0x0800051C
-  0x08000522:  6B61         LDR        R1, [R4, #52]
-  0x08000524:  F64F 72F8    MOVW       R2, #0xFFF8
-  0x08000528:  4391         BICS       R1, R2
-  0x0800052A:  6361         STR        R1, [R4, #52]
-  0x0800052C:  6AE1         LDR        R1, [R4, #44]
-  0x0800052E:  F041 0101    ORR        R1, R1, #1
-  0x08000532:  62E1         STR        R1, [R4, #44]
+  0x08000E70:  F248 023F    MOVW       R2, #0x803F
+  0x08000E74:  68A9         LDR        R1, [R5, #8]
+  0x08000E76:  F6CF 6210    MOVT       R2, #0xFE10
+  0x08000E7A:  400A         ANDS       R2, R1
+  0x08000E7C:  E9D0 3903    LDRD       R3, R9, [R0, #12]
+  0x08000E80:  431A         ORRS       R2, R3
+  0x08000E82:  E9D0 1E05    LDRD       R1, LR, [R0, #20]
+  0x08000E86:  EA42 0209    ORR.W      R2, R2, R9
+  0x08000E8A:  F8D0 9024    LDR.W      R9, [R0, #36]
+  0x08000E8E:  E9D0 6307    LDRD       R6, R3, [R0, #28]
+  0x08000E92:  4311         ORRS       R1, R2
+  0x08000E94:  4331         ORRS       R1, R6
+  0x08000E96:  E9D0 A70B    LDRD       R10, R7, [R0, #44]
+  0x08000E9A:  4319         ORRS       R1, R3
+  0x08000E9C:  F1B9 0F04    CMP.W      R9, #4
+  0x08000EA0:  EA47 020A    ORR.W      R2, R7, R10
+  0x08000EA4:  E9D0 8C01    LDRD       R8, R12, [R0, #4]
+  0x08000EA8:  BF08         IT         EQ
+  0x08000EAA:  4311         ORREQ      R1, R2
+  0x08000EAC:  F1A8 023F    SUB.W      R2, R8, #63
+  0x08000EB0:  EA41 010C    ORR.W      R1, R1, R12
+  0x08000EB4:  2A13         CMP        R2, #19
+  0x08000EB6:  EA41 030E    ORR.W      R3, R1, LR
+  0x08000EBA:  D807         BHI        .L11                     ; 0x08000ECC
+  0x08000EBC:  2101         MOVS       R1, #1
+  0x08000EBE:  4091         LSLS       R1, R2
+  0x08000EC0:  F240 320F    MOVW       R2, #0x030F
+  0x08000EC4:  F2C0 020F    MOVT       R2, #15
+  0x08000EC8:  4211         TST        R1, R2
+  0x08000ECA:  D104         BNE        .L12                     ; 0x08000ED6
 
    .L11:
-  0x08000534:  F242 0C00    MOVW       R12, #0x2000
-  0x08000538:  F2C5 2C00    MOVT       R12, #0x5200
-  0x0800053C:  F8DC 2000    LDR.W      R2, [R12]
-  0x08000540:  0712         LSLS       R2, R2, #28
-  0x08000542:  D10D         BNE        .L12                     ; 0x08000560
-  0x08000544:  F8DC 2000    LDR.W      R2, [R12]
-  0x08000548:  2301         MOVS       R3, #1
-  0x0800054A:  F363 0203    BFI        R2, R3, #0, #4
-  0x0800054E:  F8CC 2000    STR.W      R2, [R12]
-  0x08000552:  F8DC 2000    LDR.W      R2, [R12]
-  0x08000556:  F002 020F    AND        R2, R2, #15
-  0x0800055A:  2A01         CMP        R2, #1
-  0x0800055C:  F040 80D2    BNE.W      .L23                     ; 0x08000704
+  0x08000ECC:  F1A8 0129    SUB.W      R1, R8, #41
+  0x08000ED0:  2906         CMP        R1, #6
+  0x08000ED2:  F080 810E    BCS.W      .L37                     ; 0x080010F2
 
    .L12:
-  0x08000560:  69A2         LDR        R2, [R4, #24]
-  0x08000562:  69E2         LDR        R2, [R4, #28]
-  0x08000564:  69E2         LDR        R2, [R4, #28]
-  0x08000566:  6A22         LDR        R2, [R4, #32]
-  0x08000568:  69A2         LDR        R2, [R4, #24]
-  0x0800056A:  69A2         LDR        R2, [R4, #24]
-  0x0800056C:  F422 6270    BIC        R2, R2, #0x0F00
-  0x08000570:  61A2         STR        R2, [R4, #24]
-  0x08000572:  6822         LDR        R2, [R4]
-  0x08000574:  0192         LSLS       R2, R2, #6
-  0x08000576:  F140 80C5    BPL.W      .L23                     ; 0x08000704
-  0x0800057A:  6922         LDR        R2, [R4, #16]
-  0x0800057C:  2303         MOVS       R3, #3
-  0x0800057E:  F363 0202    BFI        R2, R3, #0, #3
-  0x08000582:  6122         STR        R2, [R4, #16]
-  0x08000584:  6802         LDR        R2, [R0]
-  0x08000586:  F241 3388    MOVW       R3, #0x1388
+  0x08000ED6:  F443 1380    ORR        R3, R3, #0x100000
 
    .L13:
-  0x0800058A:  6921         LDR        R1, [R4, #16]
-  0x0800058C:  F001 0138    AND        R1, R1, #56
-  0x08000590:  2918         CMP        R1, #24
-  0x08000592:  D004         BEQ        .L14                     ; 0x0800059E
-  0x08000594:  6801         LDR        R1, [R0]
-  0x08000596:  1A89         SUBS       R1, R1, R2
-  0x08000598:  4299         CMP        R1, R3
-  0x0800059A:  D9F6         BLS        .L13                     ; 0x0800058A
-  0x0800059C:  E0B2         B          .L23                     ; 0x08000704
+  0x08000EDA:  60AB         STR        R3, [R5, #8]
+  0x08000EDC:  F1B9 0F04    CMP.W      R9, #4
+  0x08000EE0:  69E9         LDR        R1, [R5, #28]
+  0x08000EE2:  F021 0107    BIC        R1, R1, #7
+  0x08000EE6:  EA49 0901    ORR.W      R9, R9, R1
+  0x08000EEA:  D12C         BNE        .L20                     ; 0x08000F46
+  0x08000EEC:  6A83         LDR        R3, [R0, #40]
+  0x08000EEE:  F1BA 0F00    CMP.W      R10, #0
+  0x08000EF2:  EA49 0903    ORR.W      R9, R9, R3
+  0x08000EF6:  D026         BEQ        .L20                     ; 0x08000F46
+  0x08000EF8:  F5BE 5F00    CMP.W      LR, #0x2000
+  0x08000EFC:  D008         BEQ        .L14                     ; 0x08000F10
+  0x08000EFE:  F1BE 0F00    CMP.W      LR, #0
+  0x08000F02:  D118         BNE        .L17                     ; 0x08000F36
+  0x08000F04:  2B02         CMP        R3, #2
+  0x08000F06:  D019         BEQ        .L18                     ; 0x08000F3C
+  0x08000F08:  2B01         CMP        R3, #1
+  0x08000F0A:  D00E         BEQ        .L16                     ; 0x08000F2A
+  0x08000F0C:  B1B3         CBZ        R3, .L18                 ; 0x08000F3C
+  0x08000F0E:  E01A         B          .L20                     ; 0x08000F46
 
    .L14:
-  0x0800059E:  69A0         LDR        R0, [R4, #24]
-  0x080005A0:  0700         LSLS       R0, R0, #28
-  0x080005A2:  BF1E         ITTT       NE
-  0x080005A4:  69A0         LDRNE      R0, [R4, #24]
-  0x080005A6:  F020 000F    BICNE      R0, R0, #15
-  0x080005AA:  61A0         STRNE      R0, [R4, #24]
-  0x080005AC:  F8DC 0000    LDR.W      R0, [R12]
-  0x080005B0:  F010 0F0E    TST        R0, #14
-  0x080005B4:  D00D         BEQ        .L15                     ; 0x080005D2
-  0x080005B6:  F8DC 0000    LDR.W      R0, [R12]
-  0x080005BA:  2101         MOVS       R1, #1
-  0x080005BC:  F361 0003    BFI        R0, R1, #0, #4
-  0x080005C0:  F8CC 0000    STR.W      R0, [R12]
-  0x080005C4:  F8DC 0000    LDR.W      R0, [R12]
-  0x080005C8:  F000 000F    AND        R0, R0, #15
-  0x080005CC:  2801         CMP        R0, #1
-  0x080005CE:  F040 8099    BNE.W      .L23                     ; 0x08000704
+  0x08000F10:  2B03         CMP        R3, #3
+  0x08000F12:  D818         BHI        .L20                     ; 0x08000F46
+  0x08000F14:  F04F 0E01    MOV.W      LR, #1
+  0x08000F18:  2640         MOVS       R6, #64
+  0x08000F1A:  E8DF F003    TBB        [PC, R3]
+  0x08000F1E:  02           DC.B       0x02                     ; '\x02'
+  0x08000F1F:  0F           DC.B       0x0F                     ; '\x0F'
+  0x08000F20:  02           DC.B       0x02                     ; '\x02'
+  0x08000F21:  06           DC.B       0x06                     ; '\x06'
 
    .L15:
-  0x080005D2:  69A0         LDR        R0, [R4, #24]
-  0x080005D4:  F010 0F70    TST        R0, #112
-  0x080005D8:  BF1E         ITTT       NE
-  0x080005DA:  69A0         LDRNE      R0, [R4, #24]
-  0x080005DC:  F020 0070    BICNE      R0, R0, #112
-  0x080005E0:  61A0         STRNE      R0, [R4, #24]
-  0x080005E2:  69E0         LDR        R0, [R4, #28]
-  0x080005E4:  F010 0F70    TST        R0, #112
-  0x080005E8:  BF1E         ITTT       NE
-  0x080005EA:  69E0         LDRNE      R0, [R4, #28]
-  0x080005EC:  F020 0070    BICNE      R0, R0, #112
-  0x080005F0:  61E0         STRNE      R0, [R4, #28]
-  0x080005F2:  69E0         LDR        R0, [R4, #28]
-  0x080005F4:  F410 6FE0    TST        R0, #0x0700
-  0x080005F8:  BF1E         ITTT       NE
-  0x080005FA:  69E0         LDRNE      R0, [R4, #28]
-  0x080005FC:  F420 60E0    BICNE      R0, R0, #0x0700
-  0x08000600:  61E0         STRNE      R0, [R4, #28]
-  0x08000602:  6A20         LDR        R0, [R4, #32]
-  0x08000604:  F010 0F70    TST        R0, #112
-  0x08000608:  BF1E         ITTT       NE
-  0x0800060A:  6A20         LDRNE      R0, [R4, #32]
-  0x0800060C:  F020 0070    BICNE      R0, R0, #112
-  0x08000610:  6220         STRNE      R0, [R4, #32]
-  0x08000612:  F7FF FE5B    BL         HAL_RCC_GetSysClockFreq  ; 0x080002CC
-  0x08000616:  69A1         LDR        R1, [R4, #24]
-  0x08000618:  F640 32AE    MOVW       R2, #0x0BAE              ; 0x08000BAE = D1CorePrescTable
-  0x0800061C:  F6C0 0200    MOVT       R2, #0x0800              ; 0x08000BAE = D1CorePrescTable
-  0x08000620:  F3C1 2103    UBFX       R1, R1, #8, #4
-  0x08000624:  5C51         LDRB       R1, [R2, R1]
-  0x08000626:  F240 0228    MOVW       R2, #40                  ; 0x30000028 = uwTickPrio
-  0x0800062A:  F2C3 0200    MOVT       R2, #0x3000              ; 0x30000028 = uwTickPrio
-  0x0800062E:  69A3         LDR        R3, [R4, #24]
-  0x08000630:  F240 032C    MOVW       R3, #44                  ; 0x3000002C = SystemCoreClock
-  0x08000634:  F001 011F    AND        R1, R1, #31
-  0x08000638:  7812         LDRB       R2, [R2]
-  0x0800063A:  F2C3 0300    MOVT       R3, #0x3000              ; 0x3000002C = SystemCoreClock
-  0x0800063E:  FA20 F101    LSR.W      R1, R0, R1
-  0x08000642:  2010         MOVS       R0, #16
-  0x08000644:  2A00         CMP        R2, #0
-  0x08000646:  6019         STR        R1, [R3]
-  0x08000648:  BF18         IT         NE
-  0x0800064A:  200F         MOVNE      R0, #15
-  0x0800064C:  F000 FA63    BL         HAL_InitTick             ; 0x08000B16
-  0x08000650:  2800         CMP        R0, #0
-  0x08000652:  D157         BNE        .L23                     ; 0x08000704
-  0x08000654:  B002         ADD        SP, SP, #8
-  0x08000656:  BD10         POP        {R4, PC}
+  0x08000F22:  6546         STR        R6, [R0, #84]
+  0x08000F24:  F880 E035    STRB.W     LR, [R0, #53]
+  0x08000F28:  B672         CPSID      i
 
    .L16:
-  0x08000658:  6821         LDR        R1, [R4]
-  0x0800065A:  F441 3180    ORR        R1, R1, #0x010000
-  0x0800065E:  6021         STR        R1, [R4]
-  0x08000660:  6801         LDR        R1, [R0]
+  0x08000F2A:  F1AA 71C0    SUB.W      R1, R10, #0x01800000
+  0x08000F2E:  FAB1 F181    CLZ        R1, R1
+  0x08000F32:  094B         LSRS       R3, R1, #5
+  0x08000F34:  E004         B          .L19                     ; 0x08000F40
 
    .L17:
-  0x08000662:  6822         LDR        R2, [R4]
-  0x08000664:  0392         LSLS       R2, R2, #14
-  0x08000666:  F53F AF09    BMI.W      .L5                      ; 0x0800047C
-  0x0800066A:  6802         LDR        R2, [R0]
-  0x0800066C:  1A52         SUBS       R2, R2, R1
-  0x0800066E:  2A64         CMP        R2, #100
-  0x08000670:  D9F7         BLS        .L17                     ; 0x08000662
-  0x08000672:  E046         B          .L22                     ; 0x08000702
+  0x08000F36:  2B03         CMP        R3, #3
+  0x08000F38:  F040 80E2    BNE.W      .L38                     ; 0x08001100
 
    .L18:
-  0x08000674:  6821         LDR        R1, [R4]
-  0x08000676:  F021 7180    BIC        R1, R1, #0x01000000
-  0x0800067A:  6021         STR        R1, [R4]
-  0x0800067C:  6801         LDR        R1, [R0]
+  0x08000F3C:  F3CA 6300    UBFX       R3, R10, #24, #1
 
    .L19:
-  0x0800067E:  6822         LDR        R2, [R4]
-  0x08000680:  0192         LSLS       R2, R2, #6
-  0x08000682:  D504         BPL        .L20                     ; 0x0800068E
-  0x08000684:  6802         LDR        R2, [R0]
-  0x08000686:  1A52         SUBS       R2, R2, R1
-  0x08000688:  2A02         CMP        R2, #2
-  0x0800068A:  D9F8         BLS        .L19                     ; 0x0800067E
-  0x0800068C:  E039         B          .L22                     ; 0x08000702
+  0x08000F40:  2B00         CMP        R3, #0
+  0x08000F42:  F040 80DF    BNE.W      .L39                     ; 0x08001104
 
    .L20:
-  0x0800068E:  6AA1         LDR        R1, [R4, #40]
-  0x08000690:  F240 32F3    MOVW       R2, #0x03F3
-  0x08000694:  4391         BICS       R1, R2
-  0x08000696:  F64F 72F8    MOVW       R2, #0xFFF8
-  0x0800069A:  F501 71C9    ADD.W      R1, R1, #0x0192
-  0x0800069E:  62A1         STR        R1, [R4, #40]
-  0x080006A0:  F240 21C7    MOVW       R1, #0x02C7
-  0x080006A4:  F2C0 1101    MOVT       R1, #0x0101
-  0x080006A8:  6321         STR        R1, [R4, #48]
-  0x080006AA:  6AE1         LDR        R1, [R4, #44]
-  0x080006AC:  F021 0101    BIC        R1, R1, #1
-  0x080006B0:  62E1         STR        R1, [R4, #44]
-  0x080006B2:  6B61         LDR        R1, [R4, #52]
-  0x080006B4:  4391         BICS       R1, R2
-  0x080006B6:  6361         STR        R1, [R4, #52]
-  0x080006B8:  6AE1         LDR        R1, [R4, #44]
-  0x080006BA:  F021 010C    BIC        R1, R1, #12
-  0x080006BE:  62E1         STR        R1, [R4, #44]
-  0x080006C0:  6AE1         LDR        R1, [R4, #44]
-  0x080006C2:  F041 0102    ORR        R1, R1, #2
-  0x080006C6:  62E1         STR        R1, [R4, #44]
-  0x080006C8:  6AE1         LDR        R1, [R4, #44]
-  0x080006CA:  F441 3180    ORR        R1, R1, #0x010000
-  0x080006CE:  62E1         STR        R1, [R4, #44]
-  0x080006D0:  6AE1         LDR        R1, [R4, #44]
-  0x080006D2:  F441 3100    ORR        R1, R1, #0x020000
-  0x080006D6:  62E1         STR        R1, [R4, #44]
-  0x080006D8:  6AE1         LDR        R1, [R4, #44]
-  0x080006DA:  F441 2180    ORR        R1, R1, #0x040000
-  0x080006DE:  62E1         STR        R1, [R4, #44]
-  0x080006E0:  6AE1         LDR        R1, [R4, #44]
-  0x080006E2:  F041 0101    ORR        R1, R1, #1
-  0x080006E6:  62E1         STR        R1, [R4, #44]
-  0x080006E8:  6821         LDR        R1, [R4]
-  0x080006EA:  F041 7180    ORR        R1, R1, #0x01000000
-  0x080006EE:  6021         STR        R1, [R4]
-  0x080006F0:  6801         LDR        R1, [R0]
+  0x08000F46:  F640 0780    MOVW       R7, #0x0880
+  0x08000F4A:  F2C4 0702    MOVT       R7, #0x4002
+  0x08000F4E:  2100         MOVS       R1, #0
+  0x08000F50:  F2C4 0102    MOVT       R1, #0x4002
+  0x08000F54:  F8C5 901C    STR.W      R9, [R5, #28]
+  0x08000F58:  2300         MOVS       R3, #0
+  0x08000F5A:  E9C0 1316    STRD       R1, R3, [R0, #88]
+  0x08000F5E:  213F         MOVS       R1, #63
+  0x08000F60:  2601         MOVS       R6, #1
+  0x08000F62:  F1BC 0F80    CMP.W      R12, #128
+  0x08000F66:  6029         STR        R1, [R5]
+  0x08000F68:  F505 61FF    ADD.W      R1, R5, #0x07F8
+  0x08000F6C:  E9C0 1718    STRD       R1, R7, [R0, #96]
+  0x08000F70:  6686         STR        R6, [R0, #104]
+  0x08000F72:  D104         BNE        .L21                     ; 0x08000F7E
+  0x08000F74:  6043         STR        R3, [R0, #4]
+  0x08000F76:  F8C5 37F8    STR.W      R3, [R5, #0x07F8]
+  0x08000F7A:  607E         STR        R6, [R7, #4]
+  0x08000F7C:  E016         B          .L22                     ; 0x08000FAC
 
    .L21:
-  0x080006F2:  6822         LDR        R2, [R4]
-  0x080006F4:  0192         LSLS       R2, R2, #6
-  0x080006F6:  F53F AF1D    BMI.W      .L11                     ; 0x08000534
-  0x080006FA:  6802         LDR        R2, [R0]
-  0x080006FC:  1A52         SUBS       R2, R2, R1
-  0x080006FE:  2A02         CMP        R2, #2
-  0x08000700:  D9F7         BLS        .L21                     ; 0x080006F2
+  0x08000F7E:  F1A8 0101    SUB.W      R1, R8, #1
+  0x08000F82:  FA5F F388    UXTB       R3, R8
+  0x08000F86:  2907         CMP        R1, #7
+  0x08000F88:  F8C5 37F8    STR.W      R3, [R5, #0x07F8]
+  0x08000F8C:  607E         STR        R6, [R7, #4]
+  0x08000F8E:  D80D         BHI        .L22                     ; 0x08000FAC
+  0x08000F90:  3B01         SUBS       R3, #1
+  0x08000F92:  2B08         CMP        R3, #8
+  0x08000F94:  D20F         BCS        .L23                     ; 0x08000FB6
+  0x08000F96:  EB07 0188    ADD.W      R1, R7, R8, LSL #2
+  0x08000F9A:  F107 02C0    ADD.W      R2, R7, #192
+  0x08000F9E:  317C         ADDS       R1, #124
+  0x08000FA0:  FA06 F303    LSL.W      R3, R6, R3
+  0x08000FA4:  E9C0 121B    STRD       R1, R2, [R0, #108]
+  0x08000FA8:  6743         STR        R3, [R0, #116]
+  0x08000FAA:  E007         B          .L24                     ; 0x08000FBC
 
    .L22:
-  0x08000702:  B672         CPSID      i
+  0x08000FAC:  2100         MOVS       R1, #0
+  0x08000FAE:  6741         STR        R1, [R0, #116]
+  0x08000FB0:  E9C0 111B    STRD       R1, R1, [R0, #108]
+  0x08000FB4:  E005         B          .L25                     ; 0x08000FC2
 
    .L23:
-  0x08000704:  B672         CPSID      i
+  0x08000FB6:  F100 016C    ADD.W      R1, R0, #108
+  0x08000FBA:  C90E         LDM        R1, {R1-R3}
+
    .L24:
+  0x08000FBC:  2700         MOVS       R7, #0
+  0x08000FBE:  600F         STR        R7, [R1]
+  0x08000FC0:  6053         STR        R3, [R2, #4]
+
    .L25:
+  0x08000FC2:  2100         MOVS       R1, #0
+  0x08000FC4:  6541         STR        R1, [R0, #84]
+  0x08000FC6:  F880 6035    STRB.W     R6, [R0, #53]
+  0x08000FCA:  67A0         STR        R0, [R4, #120]
+  0x08000FCC:  6384         STR        R4, [R0, #56]
+  0x08000FCE:  F64E 500C    MOVW       R0, #0xED0C
+  0x08000FD2:  F2CE 0000    MOVT       R0, #0xE000
+  0x08000FD6:  F6A0 4204    SUBW       R2, R0, #0x0C04
+  0x08000FDA:  6800         LDR        R0, [R0]
+  0x08000FDC:  F882 134C    STRB.W     R1, [R2, #0x034C]
+  0x08000FE0:  F44F 1080    MOV.W      R0, #0x100000
+  0x08000FE4:  6010         STR        R0, [R2]
+  0x08000FE6:  6827         LDR        R7, [R4]
+
    .L26:
+  0x08000FE8:  2002         MOVS       R0, #2
+  0x08000FEA:  F884 0081    STRB.W     R0, [R4, #129]
+  0x08000FEE:  6838         LDR        R0, [R7]
+  0x08000FF0:  F020 0001    BIC        R0, R0, #1
+  0x08000FF4:  6038         STR        R0, [R7]
+  0x08000FF6:  68B8         LDR        R0, [R7, #8]
+  0x08000FF8:  F8D4 8018    LDR.W      R8, [R4, #24]
+  0x08000FFC:  F1B8 6F80    CMP.W      R8, #0x04000000
+  0x08001000:  F400 1EF8    AND        LR, R0, #0x1F0000
+  0x08001004:  F8D4 A004    LDR.W      R10, [R4, #4]
+  0x08001008:  D110         BNE        .L29                     ; 0x0800102C
+  0x0800100A:  F1BA 0F00    CMP.W      R10, #0
+  0x0800100E:  D005         BEQ        .L27                     ; 0x0800101C
+  0x08001010:  F5BA 0F80    CMP.W      R10, #0x400000
+  0x08001014:  D10A         BNE        .L29                     ; 0x0800102C
+  0x08001016:  6BA3         LDR        R3, [R4, #56]
+  0x08001018:  B973         CBNZ       R3, .L31                 ; 0x08001038
+  0x0800101A:  E003         B          .L28                     ; 0x08001024
+
    .L27:
+  0x0800101C:  6BA3         LDR        R3, [R4, #56]
+  0x0800101E:  F1B3 5F80    CMP.W      R3, #0x10000000
+  0x08001022:  D106         BNE        .L30                     ; 0x08001032
+
    .L28:
+  0x08001024:  683B         LDR        R3, [R7]
+  0x08001026:  F443 5380    ORR        R3, R3, #0x1000
+  0x0800102A:  603B         STR        R3, [R7]
+
    .L29:
+  0x0800102C:  EA5F 234A    LSLS.W     R3, R10, #9
+  0x08001030:  D402         BMI        .L31                     ; 0x08001038
+
    .L30:
+  0x08001032:  F04F 0C01    MOV.W      R12, #1
+  0x08001036:  E00B         B          .L32                     ; 0x08001050
+
    .L31:
+  0x08001038:  68E6         LDR        R6, [R4, #12]
+  0x0800103A:  F04F 0C00    MOV.W      R12, #0
+  0x0800103E:  2E07         CMP        R6, #7
+  0x08001040:  D306         BCC        .L32                     ; 0x08001050
+  0x08001042:  683B         LDR        R3, [R7]
+  0x08001044:  6D25         LDR        R5, [R4, #80]
+  0x08001046:  F423 7380    BIC        R3, R3, #0x0100
+  0x0800104A:  432B         ORRS       R3, R5
+  0x0800104C:  603B         STR        R3, [R7]
+  0x0800104E:  E004         B          .L33                     ; 0x0800105A
+
    .L32:
+  0x08001050:  683E         LDR        R6, [R7]
+  0x08001052:  F426 7680    BIC        R6, R6, #0x0100
+  0x08001056:  603E         STR        R6, [R7]
+  0x08001058:  68E6         LDR        R6, [R4, #12]
+
    .L33:
+  0x0800105A:  69E2         LDR        R2, [R4, #28]
+  0x0800105C:  EA46 060E    ORR.W      R6, R6, LR
+  0x08001060:  6AA1         LDR        R1, [R4, #40]
+  0x08001062:  4332         ORRS       R2, R6
+  0x08001064:  6BE6         LDR        R6, [R4, #60]
+  0x08001066:  4311         ORRS       R1, R2
+  0x08001068:  F8D4 B008    LDR.W      R11, [R4, #8]
+  0x0800106C:  4331         ORRS       R1, R6
+  0x0800106E:  E9D4 9304    LDRD       R9, R3, [R4, #16]
+  0x08001072:  60B9         STR        R1, [R7, #8]
+  0x08001074:  E9D4 150D    LDRD       R1, R5, [R4, #52]
+  0x08001078:  6A62         LDR        R2, [R4, #36]
+  0x0800107A:  4311         ORRS       R1, R2
+  0x0800107C:  6A22         LDR        R2, [R4, #32]
+  0x0800107E:  4329         ORRS       R1, R5
+  0x08001080:  EA41 0109    ORR.W      R1, R1, R9
+  0x08001084:  4319         ORRS       R1, R3
+  0x08001086:  E9D4 0612    LDRD       R0, R6, [R4, #72]
+  0x0800108A:  4311         ORRS       R1, R2
+  0x0800108C:  6DA2         LDR        R2, [R4, #88]
+  0x0800108E:  4331         ORRS       R1, R6
+  0x08001090:  EA41 010B    ORR.W      R1, R1, R11
+  0x08001094:  4308         ORRS       R0, R1
+  0x08001096:  4310         ORRS       R0, R2
+  0x08001098:  F1BA 0F00    CMP.W      R10, #0
+  0x0800109C:  EA40 0008    ORR.W      R0, R0, R8
+  0x080010A0:  EA40 000A    ORR.W      R0, R0, R10
+  0x080010A4:  60F8         STR        R0, [R7, #12]
+  0x080010A6:  D00D         BEQ        .L34                     ; 0x080010C4
+  0x080010A8:  6D38         LDR        R0, [R7, #80]
+  0x080010AA:  F1BC 0F00    CMP.W      R12, #0
+  0x080010AE:  F020 0001    BIC        R0, R0, #1
+  0x080010B2:  6538         STR        R0, [R7, #80]
+  0x080010B4:  D114         BNE        .L35                     ; 0x080010E0
+  0x080010B6:  68F8         LDR        R0, [R7, #12]
+  0x080010B8:  6D61         LDR        R1, [R4, #84]
+  0x080010BA:  F020 4000    BIC        R0, R0, #0x80000000
+  0x080010BE:  4308         ORRS       R0, R1
+  0x080010C0:  60F8         STR        R0, [R7, #12]
+  0x080010C2:  E00D         B          .L35                     ; 0x080010E0
+
    .L34:
+  0x080010C4:  68B8         LDR        R0, [R7, #8]
+  0x080010C6:  2101         MOVS       R1, #1
+  0x080010C8:  F361 20CC    BFI        R0, R1, #11, #2
+  0x080010CC:  60B8         STR        R0, [R7, #8]
+  0x080010CE:  68B8         LDR        R0, [R7, #8]
+  0x080010D0:  2102         MOVS       R1, #2
+  0x080010D2:  F361 204A    BFI        R0, R1, #9, #2
+  0x080010D6:  60B8         STR        R0, [R7, #8]
+  0x080010D8:  6D38         LDR        R0, [R7, #80]
+  0x080010DA:  F020 0001    BIC        R0, R0, #1
+  0x080010DE:  6538         STR        R0, [R7, #80]
+
    .L35:
+  0x080010E0:  2000         MOVS       R0, #0
+  0x080010E2:  F8C4 0084    STR.W      R0, [R4, #132]
+  0x080010E6:  2101         MOVS       R1, #1
+  0x080010E8:  F884 1081    STRB.W     R1, [R4, #129]
+
    .L36:
+  0x080010EC:  B031         ADD        SP, SP, #196
+  0x080010EE:  E8BD 8FF0    POP.W      {R4-R11, PC}
+
    .L37:
+  0x080010F2:  F028 0103    BIC        R1, R8, #3
+  0x080010F6:  2974         CMP        R1, #116
+  0x080010F8:  BF08         IT         EQ
+  0x080010FA:  F443 1380    ORREQ      R3, R3, #0x100000
+  0x080010FE:  E6EC         B          .L13                     ; 0x08000EDA
+
    .L38:
+  0x08001100:  F4BF AF21    BCS.W      .L20                     ; 0x08000F46
+
    .L39:
+  0x08001104:  F04F 0E01    MOV.W      LR, #1
+  0x08001108:  2640         MOVS       R6, #64
+  0x0800110A:  E70A         B          .L15                     ; 0x08000F22
+
    .L40:
+  0x0800110C:  B672         CPSID      i
+
    +

    Section .text.main from charger_lto.o, size=1566, align=2

    +
    +
    main:
+  0x0800110E:  B0AE         SUB        SP, SP, #184
+  0x08001110:  F64E 540C    MOVW       R4, #0xED0C
+  0x08001114:  F3BF 8F5F    DMB        SY
+  0x08001118:  F2CE 0400    MOVT       R4, #0xE000
+  0x0800111C:  69A0         LDR        R0, [R4, #24]
+  0x0800111E:  F420 3080    BIC        R0, R0, #0x010000
+  0x08001122:  61A0         STR        R0, [R4, #24]
+  0x08001124:  2000         MOVS       R0, #0
+  0x08001126:  F8C4 0088    STR.W      R0, [R4, #136]
+  0x0800112A:  F8C4 008C    STR.W      R0, [R4, #140]
+  0x0800112E:  F8D4 1094    LDR.W      R1, [R4, #148]
+  0x08001132:  F021 0101    BIC        R1, R1, #1
+  0x08001136:  F8C4 1094    STR.W      R1, [R4, #148]
+  0x0800113A:  F248 713F    MOVW       R1, #0x873F
+  0x0800113E:  F8C4 0090    STR.W      R0, [R4, #144]
+  0x08001142:  F2C1 0104    MOVT       R1, #0x1004
+  0x08001146:  F8C4 1094    STR.W      R1, [R4, #148]
+  0x0800114A:  2105         MOVS       R1, #5
+  0x0800114C:  F8C4 1088    STR.W      R1, [R4, #136]
+  0x08001150:  69A1         LDR        R1, [R4, #24]
+  0x08001152:  F441 3180    ORR        R1, R1, #0x010000
+  0x08001156:  61A1         STR        R1, [R4, #24]
+  0x08001158:  F3BF 8F4F    DSB        SY
+  0x0800115C:  F3BF 8F6F    ISB        SY
+  0x08001160:  68A1         LDR        R1, [R4, #8]
+  0x08001162:  0389         LSLS       R1, R1, #14
+  0x08001164:  D411         BMI        .L1                      ; 0x0800118A
+  0x08001166:  F3BF 8F4F    DSB        SY
+  0x0800116A:  F3BF 8F6F    ISB        SY
+  0x0800116E:  F8C4 0244    STR.W      R0, [R4, #0x0244]
+  0x08001172:  F3BF 8F4F    DSB        SY
+  0x08001176:  F3BF 8F6F    ISB        SY
+  0x0800117A:  68A0         LDR        R0, [R4, #8]
+  0x0800117C:  F440 3000    ORR        R0, R0, #0x020000
+  0x08001180:  60A0         STR        R0, [R4, #8]
+  0x08001182:  F3BF 8F4F    DSB        SY
+  0x08001186:  F3BF 8F6F    ISB        SY
+
    .L1:
+  0x0800118A:  68A0         LDR        R0, [R4, #8]
+  0x0800118C:  03C0         LSLS       R0, R0, #15
+  0x0800118E:  D425         BMI        .L4                      ; 0x080011DC
+  0x08001190:  2000         MOVS       R0, #0
+  0x08001192:  67A0         STR        R0, [R4, #120]
+  0x08001194:  F3BF 8F4F    DSB        SY
+  0x08001198:  F643 77E0    MOVW       R7, #0x3FE0
+  0x0800119C:  6F61         LDR        R1, [R4, #116]
+  0x0800119E:  F3C1 304E    UBFX       R0, R1, #13, #15
+  0x080011A2:  F3C1 02C9    UBFX       R2, R1, #3, #10
+  0x080011A6:  08C9         LSRS       R1, R1, #3
+  0x080011A8:  1C55         ADDS       R5, R2, #1
+  0x080011AA:  0143         LSLS       R3, R0, #5
+
    .L2:
+  0x080011AC:  EA03 0207    AND.W      R2, R3, R7
+  0x080011B0:  EB02 7681    ADD.W      R6, R2, R1, LSL #30
+  0x080011B4:  462A         MOV        R2, R5
+
    .L3:
+  0x080011B6:  3A01         SUBS       R2, #1
+  0x080011B8:  F8C4 6254    STR.W      R6, [R4, #0x0254]
+  0x080011BC:  F106 4640    ADD.W      R6, R6, #0xC0000000
+  0x080011C0:  D1F9         BNE        .L3                      ; 0x080011B6
+  0x080011C2:  3B20         SUBS       R3, #32
+  0x080011C4:  3801         SUBS       R0, #1
+  0x080011C6:  D2F1         BCS        .L2                      ; 0x080011AC
+  0x080011C8:  F3BF 8F4F    DSB        SY
+  0x080011CC:  68A0         LDR        R0, [R4, #8]
+  0x080011CE:  F440 3080    ORR        R0, R0, #0x010000
+  0x080011D2:  60A0         STR        R0, [R4, #8]
+  0x080011D4:  F3BF 8F4F    DSB        SY
+  0x080011D8:  F3BF 8F6F    ISB        SY
+
    .L4:
+  0x080011DC:  6820         LDR        R0, [R4]
+  0x080011DE:  F64F 01FF    MOVW       R1, #0xF8FF
+  0x080011E2:  4008         ANDS       R0, R1
+  0x080011E4:  F240 3100    MOVW       R1, #0x0300
+  0x080011E8:  F244 4500    MOVW       R5, #0x4400
+  0x080011EC:  F2C0 51FA    MOVT       R1, #0x05FA
+  0x080011F0:  F6C5 0502    MOVT       R5, #0x5802
+  0x080011F4:  4308         ORRS       R0, R1
+  0x080011F6:  6020         STR        R0, [R4]
+  0x080011F8:  F7FF F868    BL         HAL_RCC_GetSysClockFreq  ; 0x080002CC
+  0x080011FC:  69A9         LDR        R1, [R5, #24]
+  0x080011FE:  F242 3724    MOVW       R7, #0x2324              ; 0x08002324 = D1CorePrescTable
+  0x08001202:  F6C0 0700    MOVT       R7, #0x0800              ; 0x08002324 = D1CorePrescTable
+  0x08001206:  F240 182C    MOVW       R8, #0x012C              ; 0x3000012C = SystemCoreClock
+  0x0800120A:  F3C1 2103    UBFX       R1, R1, #8, #4
+  0x0800120E:  F2C3 0800    MOVT       R8, #0x3000              ; 0x3000012C = SystemCoreClock
+  0x08001212:  5C79         LDRB       R1, [R7, R1]
+  0x08001214:  F001 011F    AND        R1, R1, #31
+  0x08001218:  40C8         LSRS       R0, R1
+  0x0800121A:  69A9         LDR        R1, [R5, #24]
+  0x0800121C:  F8C8 0000    STR.W      R0, [R8]
+  0x08001220:  200F         MOVS       R0, #15
+  0x08001222:  F000 FC13    BL         HAL_InitTick             ; 0x08001A4C
+  0x08001226:  B958         CBNZ       R0, .L5                  ; 0x08001240
+  0x08001228:  F8D5 00F4    LDR.W      R0, [R5, #244]
+  0x0800122C:  F040 0002    ORR        R0, R0, #2
+  0x08001230:  F8C5 00F4    STR.W      R0, [R5, #244]
+  0x08001234:  F8D5 00F4    LDR.W      R0, [R5, #244]
+  0x08001238:  F000 0002    AND        R0, R0, #2
+  0x0800123C:  9000         STR        R0, [SP, #0]
+  0x0800123E:  9800         LDR        R0, [SP, #0]
+
    .L5:
+  0x08001240:  F205 400C    ADDW       R0, R5, #0x040C
+  0x08001244:  F240 1624    MOVW       R6, #0x0124              ; 0x30000124 = uwTick
+  0x08001248:  F2C3 0600    MOVT       R6, #0x3000              ; 0x30000124 = uwTick
+  0x0800124C:  6801         LDR        R1, [R0]
+  0x0800124E:  0749         LSLS       R1, R1, #29
+  0x08001250:  6801         LDR        R1, [R0]
+  0x08001252:  D50D         BPL        .L7                      ; 0x08001270
+  0x08001254:  2202         MOVS       R2, #2
+  0x08001256:  F362 0102    BFI        R1, R2, #0, #3
+  0x0800125A:  6001         STR        R1, [R0]
+  0x0800125C:  6831         LDR        R1, [R6]
+
    .L6:
+  0x0800125E:  F850 2C08    LDR        R2, [R0, #-8]
+  0x08001262:  0492         LSLS       R2, R2, #18
+  0x08001264:  D404         BMI        .L7                      ; 0x08001270
+  0x08001266:  6832         LDR        R2, [R6]
+  0x08001268:  1A52         SUBS       R2, R2, R1
+  0x0800126A:  F5B2 7F7A    CMP.W      R2, #0x03E8
+  0x0800126E:  D9F6         BLS        .L6                      ; 0x0800125E
+
    .L7:
+  0x08001270:  2100         MOVS       R1, #0
+  0x08001272:  9100         STR        R1, [SP, #0]
+  0x08001274:  68C1         LDR        R1, [R0, #12]
+  0x08001276:  2202         MOVS       R2, #2
+  0x08001278:  F362 318F    BFI        R1, R2, #14, #2
+  0x0800127C:  60C1         STR        R1, [R0, #12]
+  0x0800127E:  68C1         LDR        R1, [R0, #12]
+  0x08001280:  F401 4140    AND        R1, R1, #0xC000
+  0x08001284:  9100         STR        R1, [SP, #0]
+  0x08001286:  9900         LDR        R1, [SP, #0]
+
    .L8:
+  0x08001288:  68C1         LDR        R1, [R0, #12]
+  0x0800128A:  0489         LSLS       R1, R1, #18
+  0x0800128C:  D5FC         BPL        .L8                      ; 0x08001288
+  0x0800128E:  F8D5 0400    LDR.W      R0, [R5, #0x0400]
+  0x08001292:  F440 7080    ORR        R0, R0, #0x0100
+  0x08001296:  F8C5 0400    STR.W      R0, [R5, #0x0400]
+  0x0800129A:  6F28         LDR        R0, [R5, #112]
+  0x0800129C:  F020 0018    BIC        R0, R0, #24
+  0x080012A0:  6728         STR        R0, [R5, #112]
+  0x080012A2:  6928         LDR        R0, [R5, #16]
+  0x080012A4:  F000 0138    AND        R1, R0, #56
+  0x080012A8:  6AA8         LDR        R0, [R5, #40]
+  0x080012AA:  2910         CMP        R1, #16
+  0x080012AC:  D007         BEQ        .L9                      ; 0x080012BE
+  0x080012AE:  2918         CMP        R1, #24
+  0x080012B0:  F040 816C    BNE.W      .L28                     ; 0x0800158C
+  0x080012B4:  F000 0003    AND        R0, R0, #3
+  0x080012B8:  2802         CMP        R0, #2
+  0x080012BA:  F040 8167    BNE.W      .L28                     ; 0x0800158C
+
    .L9:
+  0x080012BE:  6828         LDR        R0, [R5]
+
    .L10:
+  0x080012C0:  F8D5 0400    LDR.W      R0, [R5, #0x0400]
+  0x080012C4:  F440 7080    ORR        R0, R0, #0x0100
+  0x080012C8:  F8C5 0400    STR.W      R0, [R5, #0x0400]
+  0x080012CC:  6830         LDR        R0, [R6]
+
    .L11:
+  0x080012CE:  F8D5 1400    LDR.W      R1, [R5, #0x0400]
+  0x080012D2:  05C9         LSLS       R1, R1, #23
+  0x080012D4:  D404         BMI        .L12                     ; 0x080012E0
+  0x080012D6:  6831         LDR        R1, [R6]
+  0x080012D8:  1A09         SUBS       R1, R1, R0
+  0x080012DA:  2964         CMP        R1, #100
+  0x080012DC:  D9F7         BLS        .L11                     ; 0x080012CE
+  0x080012DE:  E1AA         B          .L34                     ; 0x08001636
+
    .L12:
+  0x080012E0:  6F28         LDR        R0, [R5, #112]
+  0x080012E2:  F241 3188    MOVW       R1, #0x1388
+  0x080012E6:  F040 0001    ORR        R0, R0, #1
+  0x080012EA:  6728         STR        R0, [R5, #112]
+  0x080012EC:  6830         LDR        R0, [R6]
+
    .L13:
+  0x080012EE:  6F2A         LDR        R2, [R5, #112]
+  0x080012F0:  0792         LSLS       R2, R2, #30
+  0x080012F2:  D404         BMI        .L14                     ; 0x080012FE
+  0x080012F4:  6832         LDR        R2, [R6]
+  0x080012F6:  1A12         SUBS       R2, R2, R0
+  0x080012F8:  428A         CMP        R2, R1
+  0x080012FA:  D9F8         BLS        .L13                     ; 0x080012EE
+  0x080012FC:  E19B         B          .L34                     ; 0x08001636
+
    .L14:
+  0x080012FE:  6928         LDR        R0, [R5, #16]
+  0x08001300:  F000 0038    AND        R0, R0, #56
+  0x08001304:  2818         CMP        R0, #24
+  0x08001306:  F040 814F    BNE.W      .L30                     ; 0x080015A8
+  0x0800130A:  6AA8         LDR        R0, [R5, #40]
+  0x0800130C:  F240 31F3    MOVW       R1, #0x03F3
+  0x08001310:  4008         ANDS       R0, R1
+  0x08001312:  2852         CMP        R0, #82
+  0x08001314:  6B28         LDR        R0, [R5, #48]
+  0x08001316:  F040 818E    BNE.W      .L34                     ; 0x08001636
+  0x0800131A:  4601         MOV        R1, R0
+  0x0800131C:  F36F 215F    BFC        R1, #9, #23
+  0x08001320:  2927         CMP        R1, #39
+  0x08001322:  F040 8188    BNE.W      .L34                     ; 0x08001636
+  0x08001326:  F400 417E    AND        R1, R0, #0xFE00
+  0x0800132A:  F5B1 7F00    CMP.W      R1, #0x0200
+  0x0800132E:  F040 8182    BNE.W      .L34                     ; 0x08001636
+  0x08001332:  F400 01FE    AND        R1, R0, #0x7F0000
+  0x08001336:  F5B1 3F80    CMP.W      R1, #0x010000
+  0x0800133A:  F040 817C    BNE.W      .L34                     ; 0x08001636
+  0x0800133E:  F000 40FE    AND        R0, R0, #0x7F000000
+  0x08001342:  F1B0 7F80    CMP.W      R0, #0x01000000
+  0x08001346:  F040 8176    BNE.W      .L34                     ; 0x08001636
+  0x0800134A:  6B68         LDR        R0, [R5, #52]
+  0x0800134C:  F64F 71F8    MOVW       R1, #0xFFF8
+  0x08001350:  4208         TST        R0, R1
+  0x08001352:  D010         BEQ        .L16                     ; 0x08001376
+  0x08001354:  6AE8         LDR        R0, [R5, #44]
+  0x08001356:  F020 0001    BIC        R0, R0, #1
+  0x0800135A:  62E8         STR        R0, [R5, #44]
+  0x0800135C:  6830         LDR        R0, [R6]
+
    .L15:
+  0x0800135E:  6831         LDR        R1, [R6]
+  0x08001360:  4281         CMP        R1, R0
+  0x08001362:  D0FC         BEQ        .L15                     ; 0x0800135E
+  0x08001364:  6B68         LDR        R0, [R5, #52]
+  0x08001366:  F64F 71F8    MOVW       R1, #0xFFF8
+  0x0800136A:  4388         BICS       R0, R1
+  0x0800136C:  6368         STR        R0, [R5, #52]
+  0x0800136E:  6AE8         LDR        R0, [R5, #44]
+  0x08001370:  F040 0001    ORR        R0, R0, #1
+  0x08001374:  62E8         STR        R0, [R5, #44]
+
    .L16:
+  0x08001376:  F242 0000    MOVW       R0, #0x2000
+  0x0800137A:  F2C5 2000    MOVT       R0, #0x5200
+  0x0800137E:  6801         LDR        R1, [R0]
+  0x08001380:  0709         LSLS       R1, R1, #28
+  0x08001382:  D10A         BNE        .L17                     ; 0x0800139A
+  0x08001384:  6801         LDR        R1, [R0]
+  0x08001386:  2201         MOVS       R2, #1
+  0x08001388:  F362 0103    BFI        R1, R2, #0, #4
+  0x0800138C:  6001         STR        R1, [R0]
+  0x0800138E:  6801         LDR        R1, [R0]
+  0x08001390:  F001 010F    AND        R1, R1, #15
+  0x08001394:  2901         CMP        R1, #1
+  0x08001396:  F040 81C7    BNE.W      .L41                     ; 0x08001728
+
    .L17:
+  0x0800139A:  69A9         LDR        R1, [R5, #24]
+  0x0800139C:  69E9         LDR        R1, [R5, #28]
+  0x0800139E:  69E9         LDR        R1, [R5, #28]
+  0x080013A0:  6A29         LDR        R1, [R5, #32]
+  0x080013A2:  69A9         LDR        R1, [R5, #24]
+  0x080013A4:  69A9         LDR        R1, [R5, #24]
+  0x080013A6:  F421 6170    BIC        R1, R1, #0x0F00
+  0x080013AA:  61A9         STR        R1, [R5, #24]
+  0x080013AC:  6829         LDR        R1, [R5]
+  0x080013AE:  0189         LSLS       R1, R1, #6
+  0x080013B0:  F140 81BA    BPL.W      .L41                     ; 0x08001728
+  0x080013B4:  6929         LDR        R1, [R5, #16]
+  0x080013B6:  2203         MOVS       R2, #3
+  0x080013B8:  F362 0102    BFI        R1, R2, #0, #3
+  0x080013BC:  6129         STR        R1, [R5, #16]
+  0x080013BE:  6831         LDR        R1, [R6]
+  0x080013C0:  F241 3288    MOVW       R2, #0x1388
+
    .L18:
+  0x080013C4:  692B         LDR        R3, [R5, #16]
+  0x080013C6:  F003 0338    AND        R3, R3, #56
+  0x080013CA:  2B18         CMP        R3, #24
+  0x080013CC:  D004         BEQ        .L19                     ; 0x080013D8
+  0x080013CE:  6833         LDR        R3, [R6]
+  0x080013D0:  1A5B         SUBS       R3, R3, R1
+  0x080013D2:  4293         CMP        R3, R2
+  0x080013D4:  D9F6         BLS        .L18                     ; 0x080013C4
+  0x080013D6:  E1A7         B          .L41                     ; 0x08001728
+
    .L19:
+  0x080013D8:  69A9         LDR        R1, [R5, #24]
+  0x080013DA:  0709         LSLS       R1, R1, #28
+  0x080013DC:  D003         BEQ        .L20                     ; 0x080013E6
+  0x080013DE:  69A9         LDR        R1, [R5, #24]
+  0x080013E0:  F021 010F    BIC        R1, R1, #15
+  0x080013E4:  61A9         STR        R1, [R5, #24]
+
    .L20:
+  0x080013E6:  6801         LDR        R1, [R0]
+  0x080013E8:  F011 0F0E    TST        R1, #14
+  0x080013EC:  D00A         BEQ        .L21                     ; 0x08001404
+  0x080013EE:  6801         LDR        R1, [R0]
+  0x080013F0:  2201         MOVS       R2, #1
+  0x080013F2:  F362 0103    BFI        R1, R2, #0, #4
+  0x080013F6:  6001         STR        R1, [R0]
+  0x080013F8:  6800         LDR        R0, [R0]
+  0x080013FA:  F000 000F    AND        R0, R0, #15
+  0x080013FE:  2801         CMP        R0, #1
+  0x08001400:  F040 8192    BNE.W      .L41                     ; 0x08001728
+
    .L21:
+  0x08001404:  69A8         LDR        R0, [R5, #24]
+  0x08001406:  F010 0F70    TST        R0, #112
+  0x0800140A:  D003         BEQ        .L22                     ; 0x08001414
+  0x0800140C:  69A8         LDR        R0, [R5, #24]
+  0x0800140E:  F020 0070    BIC        R0, R0, #112
+  0x08001412:  61A8         STR        R0, [R5, #24]
+
    .L22:
+  0x08001414:  69E8         LDR        R0, [R5, #28]
+  0x08001416:  F010 0F70    TST        R0, #112
+  0x0800141A:  D003         BEQ        .L23                     ; 0x08001424
+  0x0800141C:  69E8         LDR        R0, [R5, #28]
+  0x0800141E:  F020 0070    BIC        R0, R0, #112
+  0x08001422:  61E8         STR        R0, [R5, #28]
+
    .L23:
+  0x08001424:  69E8         LDR        R0, [R5, #28]
+  0x08001426:  F410 6FE0    TST        R0, #0x0700
+  0x0800142A:  D003         BEQ        .L24                     ; 0x08001434
+  0x0800142C:  69E8         LDR        R0, [R5, #28]
+  0x0800142E:  F420 60E0    BIC        R0, R0, #0x0700
+  0x08001432:  61E8         STR        R0, [R5, #28]
+
    .L24:
+  0x08001434:  6A28         LDR        R0, [R5, #32]
+  0x08001436:  F010 0F70    TST        R0, #112
+  0x0800143A:  D003         BEQ        .L25                     ; 0x08001444
+  0x0800143C:  6A28         LDR        R0, [R5, #32]
+  0x0800143E:  F020 0070    BIC        R0, R0, #112
+  0x08001442:  6228         STR        R0, [R5, #32]
+
    .L25:
+  0x08001444:  F7FE FF42    BL         HAL_RCC_GetSysClockFreq  ; 0x080002CC
+  0x08001448:  69A9         LDR        R1, [R5, #24]
+  0x0800144A:  F240 1228    MOVW       R2, #0x0128              ; 0x30000128 = uwTickPrio
+  0x0800144E:  F2C3 0200    MOVT       R2, #0x3000              ; 0x30000128 = uwTickPrio
+  0x08001452:  F3C1 2103    UBFX       R1, R1, #8, #4
+  0x08001456:  5C79         LDRB       R1, [R7, R1]
+  0x08001458:  69AB         LDR        R3, [R5, #24]
+  0x0800145A:  7812         LDRB       R2, [R2]
+  0x0800145C:  F001 011F    AND        R1, R1, #31
+  0x08001460:  FA20 F101    LSR.W      R1, R0, R1
+  0x08001464:  2010         MOVS       R0, #16
+  0x08001466:  2A00         CMP        R2, #0
+  0x08001468:  F8C8 1000    STR.W      R1, [R8]
+  0x0800146C:  BF18         IT         NE
+  0x0800146E:  200F         MOVNE      R0, #15
+  0x08001470:  F000 FAEC    BL         HAL_InitTick             ; 0x08001A4C
+  0x08001474:  2800         CMP        R0, #0
+  0x08001476:  F040 8157    BNE.W      .L41                     ; 0x08001728
+  0x0800147A:  F8D5 00E0    LDR.W      R0, [R5, #224]
+  0x0800147E:  F240 1704    MOVW       R7, #0x0104              ; 0x30000100 = hrtc
+  0x08001482:  F040 0004    ORR        R0, R0, #4
+  0x08001486:  F8C5 00E0    STR.W      R0, [R5, #224]
+  0x0800148A:  F8D5 00E0    LDR.W      R0, [R5, #224]
+  0x0800148E:  F244 0808    MOVW       R8, #0x4008
+  0x08001492:  F000 0004    AND        R0, R0, #4
+  0x08001496:  9000         STR        R0, [SP, #0]
+  0x08001498:  9800         LDR        R0, [SP, #0]
+  0x0800149A:  F44F 6100    MOV.W      R1, #0x0800
+  0x0800149E:  F8D5 00E0    LDR.W      R0, [R5, #224]
+  0x080014A2:  F2C3 0700    MOVT       R7, #0x3000              ; 0x30000100 = hrtc
+  0x080014A6:  F040 0080    ORR        R0, R0, #128
+  0x080014AA:  F8C5 00E0    STR.W      R0, [R5, #224]
+  0x080014AE:  F8D5 00E0    LDR.W      R0, [R5, #224]
+  0x080014B2:  F6C5 0800    MOVT       R8, #0x5800
+  0x080014B6:  F000 0080    AND        R0, R0, #128
+  0x080014BA:  9000         STR        R0, [SP, #0]
+  0x080014BC:  9800         LDR        R0, [SP, #0]
+  0x080014BE:  F8D5 00E0    LDR.W      R0, [R5, #224]
+  0x080014C2:  F040 0010    ORR        R0, R0, #16
+  0x080014C6:  F8C5 00E0    STR.W      R0, [R5, #224]
+  0x080014CA:  F8D5 00E0    LDR.W      R0, [R5, #224]
+  0x080014CE:  F000 0010    AND        R0, R0, #16
+  0x080014D2:  9000         STR        R0, [SP, #0]
+  0x080014D4:  9800         LDR        R0, [SP, #0]
+  0x080014D6:  F8D5 00D8    LDR.W      R0, [R5, #216]
+  0x080014DA:  F040 0001    ORR        R0, R0, #1
+  0x080014DE:  F8C5 00D8    STR.W      R0, [R5, #216]
+  0x080014E2:  F8D5 00D8    LDR.W      R0, [R5, #216]
+  0x080014E6:  F000 0001    AND        R0, R0, #1
+  0x080014EA:  9000         STR        R0, [SP, #0]
+  0x080014EC:  9800         LDR        R0, [SP, #0]
+  0x080014EE:  6820         LDR        R0, [R4]
+  0x080014F0:  F24E 400B    MOVW       R0, #0xE40B
+  0x080014F4:  2400         MOVS       R4, #0
+  0x080014F6:  F2CE 0000    MOVT       R0, #0xE000
+  0x080014FA:  7004         STRB       R4, [R0]
+  0x080014FC:  F24E 1000    MOVW       R0, #0xE100
+  0x08001500:  F2CE 0000    MOVT       R0, #0xE000
+  0x08001504:  6001         STR        R1, [R0]
+  0x08001506:  217F         MOVS       R1, #127
+  0x08001508:  F1A8 0008    SUB.W      R0, R8, #8
+  0x0800150C:  E947 0401    STRD       R0, R4, [R7, #-4]
+  0x08001510:  6079         STR        R1, [R7, #4]
+  0x08001512:  21FF         MOVS       R1, #255
+  0x08001514:  E9C7 1402    STRD       R1, R4, [R7, #8]
+  0x08001518:  E9C7 4404    STRD       R4, R4, [R7, #16]
+  0x0800151C:  61BC         STR        R4, [R7, #24]
+  0x0800151E:  7F79         LDRB       R1, [R7, #29]
+  0x08001520:  B9B9         CBNZ       R1, .L26                 ; 0x08001552
+  0x08001522:  A802         ADD        R0, SP, #8
+  0x08001524:  21B0         MOVS       R1, #176
+  0x08001526:  773C         STRB       R4, [R7, #28]
+  0x08001528:  F7FF FB7A    BL         __aeabi_memclr           ; 0x08000C20
+  0x0800152C:  F44F 0080    MOV.W      R0, #0x400000
+  0x08001530:  E9CD 0400    STRD       R0, R4, [SP]
+  0x08001534:  F44F 7080    MOV.W      R0, #0x0100
+  0x08001538:  902C         STR        R0, [SP, #176]
+  0x0800153A:  4668         MOV        R0, SP
+  0x0800153C:  F7FE FF4C    BL         HAL_RCCEx_PeriphCLKConfig ; 0x080003D8
+  0x08001540:  2800         CMP        R0, #0
+  0x08001542:  F040 80F2    BNE.W      .L42                     ; 0x0800172A
+  0x08001546:  6F28         LDR        R0, [R5, #112]
+  0x08001548:  F440 4000    ORR        R0, R0, #0x8000
+  0x0800154C:  6728         STR        R0, [R5, #112]
+  0x0800154E:  F857 0C04    LDR        R0, [R7, #-4]
+
    .L26:
+  0x08001552:  2102         MOVS       R1, #2
+  0x08001554:  7779         STRB       R1, [R7, #29]
+  0x08001556:  68C1         LDR        R1, [R0, #12]
+  0x08001558:  06C9         LSLS       R1, R1, #27
+  0x0800155A:  F100 80B8    BMI.W      .L40                     ; 0x080016CE
+  0x0800155E:  21CA         MOVS       R1, #202
+  0x08001560:  6241         STR        R1, [R0, #36]
+  0x08001562:  2153         MOVS       R1, #83
+  0x08001564:  6241         STR        R1, [R0, #36]
+  0x08001566:  68C1         LDR        R1, [R0, #12]
+  0x08001568:  0649         LSLS       R1, R1, #25
+  0x0800156A:  D465         BMI        .L35                     ; 0x08001638
+  0x0800156C:  F04F 31FF    MOV.W      R1, #0xFFFFFFFF
+  0x08001570:  60C1         STR        R1, [R0, #12]
+  0x08001572:  6831         LDR        R1, [R6]
+
    .L27:
+  0x08001574:  68C2         LDR        R2, [R0, #12]
+  0x08001576:  0652         LSLS       R2, R2, #25
+  0x08001578:  D45E         BMI        .L35                     ; 0x08001638
+  0x0800157A:  6832         LDR        R2, [R6]
+  0x0800157C:  1A52         SUBS       R2, R2, R1
+  0x0800157E:  F5B2 7F7A    CMP.W      R2, #0x03E8
+  0x08001582:  D9F7         BLS        .L27                     ; 0x08001574
+  0x08001584:  2103         MOVS       R1, #3
+  0x08001586:  7779         STRB       R1, [R7, #29]
+  0x08001588:  68C0         LDR        R0, [R0, #12]
+  0x0800158A:  E087         B          .L37                     ; 0x0800169C
+
    .L28:
+  0x0800158C:  6828         LDR        R0, [R5]
+  0x0800158E:  F440 3080    ORR        R0, R0, #0x010000
+  0x08001592:  6028         STR        R0, [R5]
+  0x08001594:  6830         LDR        R0, [R6]
+
    .L29:
+  0x08001596:  6829         LDR        R1, [R5]
+  0x08001598:  0389         LSLS       R1, R1, #14
+  0x0800159A:  F53F AE91    BMI.W      .L10                     ; 0x080012C0
+  0x0800159E:  6831         LDR        R1, [R6]
+  0x080015A0:  1A09         SUBS       R1, R1, R0
+  0x080015A2:  2964         CMP        R1, #100
+  0x080015A4:  D9F7         BLS        .L29                     ; 0x08001596
+  0x080015A6:  E046         B          .L34                     ; 0x08001636
+
    .L30:
+  0x080015A8:  6828         LDR        R0, [R5]
+  0x080015AA:  F020 7080    BIC        R0, R0, #0x01000000
+  0x080015AE:  6028         STR        R0, [R5]
+  0x080015B0:  6830         LDR        R0, [R6]
+
    .L31:
+  0x080015B2:  6829         LDR        R1, [R5]
+  0x080015B4:  0189         LSLS       R1, R1, #6
+  0x080015B6:  D504         BPL        .L32                     ; 0x080015C2
+  0x080015B8:  6831         LDR        R1, [R6]
+  0x080015BA:  1A09         SUBS       R1, R1, R0
+  0x080015BC:  2902         CMP        R1, #2
+  0x080015BE:  D9F8         BLS        .L31                     ; 0x080015B2
+  0x080015C0:  E039         B          .L34                     ; 0x08001636
+
    .L32:
+  0x080015C2:  6AA8         LDR        R0, [R5, #40]
+  0x080015C4:  F240 31F3    MOVW       R1, #0x03F3
+  0x080015C8:  4388         BICS       R0, R1
+  0x080015CA:  F64F 71F8    MOVW       R1, #0xFFF8
+  0x080015CE:  3052         ADDS       R0, #82
+  0x080015D0:  62A8         STR        R0, [R5, #40]
+  0x080015D2:  F240 2027    MOVW       R0, #0x0227
+  0x080015D6:  F2C0 1001    MOVT       R0, #0x0101
+  0x080015DA:  6328         STR        R0, [R5, #48]
+  0x080015DC:  6AE8         LDR        R0, [R5, #44]
+  0x080015DE:  F020 0001    BIC        R0, R0, #1
+  0x080015E2:  62E8         STR        R0, [R5, #44]
+  0x080015E4:  6B68         LDR        R0, [R5, #52]
+  0x080015E6:  4388         BICS       R0, R1
+  0x080015E8:  6368         STR        R0, [R5, #52]
+  0x080015EA:  6AE8         LDR        R0, [R5, #44]
+  0x080015EC:  2102         MOVS       R1, #2
+  0x080015EE:  F361 0083    BFI        R0, R1, #2, #2
+  0x080015F2:  62E8         STR        R0, [R5, #44]
+  0x080015F4:  6AE8         LDR        R0, [R5, #44]
+  0x080015F6:  F020 0002    BIC        R0, R0, #2
+  0x080015FA:  62E8         STR        R0, [R5, #44]
+  0x080015FC:  6AE8         LDR        R0, [R5, #44]
+  0x080015FE:  F440 3080    ORR        R0, R0, #0x010000
+  0x08001602:  62E8         STR        R0, [R5, #44]
+  0x08001604:  6AE8         LDR        R0, [R5, #44]
+  0x08001606:  F440 3000    ORR        R0, R0, #0x020000
+  0x0800160A:  62E8         STR        R0, [R5, #44]
+  0x0800160C:  6AE8         LDR        R0, [R5, #44]
+  0x0800160E:  F440 2080    ORR        R0, R0, #0x040000
+  0x08001612:  62E8         STR        R0, [R5, #44]
+  0x08001614:  6AE8         LDR        R0, [R5, #44]
+  0x08001616:  F040 0001    ORR        R0, R0, #1
+  0x0800161A:  62E8         STR        R0, [R5, #44]
+  0x0800161C:  6828         LDR        R0, [R5]
+  0x0800161E:  F040 7080    ORR        R0, R0, #0x01000000
+  0x08001622:  6028         STR        R0, [R5]
+  0x08001624:  6830         LDR        R0, [R6]
+
    .L33:
+  0x08001626:  6829         LDR        R1, [R5]
+  0x08001628:  0189         LSLS       R1, R1, #6
+  0x0800162A:  F53F AEA4    BMI.W      .L16                     ; 0x08001376
+  0x0800162E:  6831         LDR        R1, [R6]
+  0x08001630:  1A09         SUBS       R1, R1, R0
+  0x08001632:  2902         CMP        R1, #2
+  0x08001634:  D9F7         BLS        .L33                     ; 0x08001626
+
    .L34:
+  0x08001636:  B672         CPSID      i
+
    .L35:
+  0x08001638:  6881         LDR        R1, [R0, #8]
+  0x0800163A:  F421 01E0    BIC        R1, R1, #0x700000
+  0x0800163E:  F021 0140    BIC        R1, R1, #64
+  0x08001642:  6081         STR        R1, [R0, #8]
+  0x08001644:  E897 004E    LDM.W      R7, {R1-R3, R6}
+  0x08001648:  4331         ORRS       R1, R6
+  0x0800164A:  697E         LDR        R6, [R7, #20]
+  0x0800164C:  4331         ORRS       R1, R6
+  0x0800164E:  6886         LDR        R6, [R0, #8]
+  0x08001650:  4331         ORRS       R1, R6
+  0x08001652:  6081         STR        R1, [R0, #8]
+  0x08001654:  EA43 4102    ORR.W      R1, R3, R2, LSL #16
+  0x08001658:  6101         STR        R1, [R0, #16]
+  0x0800165A:  F8D8 0004    LDR.W      R0, [R8, #4]
+  0x0800165E:  F020 0080    BIC        R0, R0, #128
+  0x08001662:  F8C8 0004    STR.W      R0, [R8, #4]
+  0x08001666:  F8D8 0000    LDR.W      R0, [R8]
+  0x0800166A:  0680         LSLS       R0, R0, #26
+  0x0800166C:  D405         BMI        .L36                     ; 0x0800167A
+  0x0800166E:  F000 FA1A    BL         HAL_RTC_WaitForSynchro   ; 0x08001AA6
+  0x08001672:  B1F0         CBZ        R0, .L39                 ; 0x080016B2
+  0x08001674:  2003         MOVS       R0, #3
+  0x08001676:  7778         STRB       R0, [R7, #29]
+  0x08001678:  E010         B          .L37                     ; 0x0800169C
+
    .L36:
+  0x0800167A:  F8D8 0000    LDR.W      R0, [R8]
+  0x0800167E:  F020 0020    BIC        R0, R0, #32
+  0x08001682:  F8C8 0000    STR.W      R0, [R8]
+  0x08001686:  F000 FA0E    BL         HAL_RTC_WaitForSynchro   ; 0x08001AA6
+  0x0800168A:  B160         CBZ        R0, .L38                 ; 0x080016A6
+  0x0800168C:  2003         MOVS       R0, #3
+  0x0800168E:  7778         STRB       R0, [R7, #29]
+  0x08001690:  F8D8 0000    LDR.W      R0, [R8]
+  0x08001694:  F040 0020    ORR        R0, R0, #32
+  0x08001698:  F8C8 0000    STR.W      R0, [R8]
+
    .L37:
+  0x0800169C:  F857 0C04    LDR        R0, [R7, #-4]
+  0x080016A0:  21FF         MOVS       R1, #255
+  0x080016A2:  6241         STR        R1, [R0, #36]
+  0x080016A4:  B672         CPSID      i
+
    .L38:
+  0x080016A6:  F8D8 0000    LDR.W      R0, [R8]
+  0x080016AA:  F040 0020    ORR        R0, R0, #32
+  0x080016AE:  F8C8 0000    STR.W      R0, [R8]
+
    .L39:
+  0x080016B2:  F857 0C04    LDR        R0, [R7, #-4]
+  0x080016B6:  6939         LDR        R1, [R7, #16]
+  0x080016B8:  69BA         LDR        R2, [R7, #24]
+  0x080016BA:  6CC3         LDR        R3, [R0, #76]
+  0x080016BC:  4311         ORRS       R1, R2
+  0x080016BE:  F023 0303    BIC        R3, R3, #3
+  0x080016C2:  64C3         STR        R3, [R0, #76]
+  0x080016C4:  6CC2         LDR        R2, [R0, #76]
+  0x080016C6:  4311         ORRS       R1, R2
+  0x080016C8:  64C1         STR        R1, [R0, #76]
+  0x080016CA:  21FF         MOVS       R1, #255
+  0x080016CC:  6241         STR        R1, [R0, #36]
+
    .L40:
+  0x080016CE:  2001         MOVS       R0, #1
+  0x080016D0:  F240 041C    MOVW       R4, #28                  ; 0x30000000 = hspi4
+  0x080016D4:  7778         STRB       R0, [R7, #29]
+  0x080016D6:  F2C3 0400    MOVT       R4, #0x3000              ; 0x30000000 = hspi4
+  0x080016DA:  F243 4000    MOVW       R0, #0x3400
+  0x080016DE:  2114         MOVS       R1, #20
+  0x080016E0:  F2C4 0001    MOVT       R0, #0x4001
+  0x080016E4:  F844 0C1C    STR        R0, [R4, #-28]
+  0x080016E8:  F44F 0080    MOV.W      R0, #0x400000
+  0x080016EC:  F844 0C18    STR        R0, [R4, #-24]
+  0x080016F0:  F44F 20C0    MOV.W      R0, #0x060000
+  0x080016F4:  F844 0C14    STR        R0, [R4, #-20]
+  0x080016F8:  2008         MOVS       R0, #8
+  0x080016FA:  F844 0C10    STR        R0, [R4, #-16]
+  0x080016FE:  2000         MOVS       R0, #0
+  0x08001700:  E944 0003    STRD       R0, R0, [R4, #-12]
+  0x08001704:  F04F 5000    MOV.W      R0, #0x20000000
+  0x08001708:  F844 0C04    STR        R0, [R4, #-4]
+  0x0800170C:  4620         MOV        R0, R4
+  0x0800170E:  F7FF FA87    BL         __aeabi_memclr           ; 0x08000C20
+  0x08001712:  F04F 4080    MOV.W      R0, #0x40000000
+  0x08001716:  61A0         STR        R0, [R4, #24]
+  0x08001718:  F104 001C    ADD.W      R0, R4, #28
+  0x0800171C:  2124         MOVS       R1, #36
+  0x0800171E:  F7FF FA7F    BL         __aeabi_memclr           ; 0x08000C20
+  0x08001722:  F7FF FAB1    BL         HAL_SPI_Init             ; 0x08000C88
+  0x08001726:  B672         CPSID      i
+
    .L41:
+  0x08001728:  B672         CPSID      i
+
    .L42:
+  0x0800172A:  B672         CPSID      i
+
    +

    Section .text.NMI_Handler from charger_lto.o, size=2, align=2

    +
    +
    NMI_Handler:
+HardFault_Handler:
+MemManage_Handler:
+BusFault_Handler:
+UsageFault_Handler:
+WWDG_IRQHandler:
+PVD_AVD_IRQHandler:
+TAMP_STAMP_IRQHandler:
+RTC_WKUP_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Stream1_IRQHandler:
+DMA1_Stream2_IRQHandler:
+DMA1_Stream3_IRQHandler:
+DMA1_Stream4_IRQHandler:
+DMA1_Stream5_IRQHandler:
+DMA1_Stream6_IRQHandler:
+ADC_IRQHandler:
+FDCAN1_IT0_IRQHandler:
+FDCAN2_IT0_IRQHandler:
+FDCAN1_IT1_IRQHandler:
+FDCAN2_IT1_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
+TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTC_Alarm_IRQHandler:
+TIM8_BRK_TIM12_IRQHandler:
+TIM8_UP_TIM13_IRQHandler:
+TIM8_TRG_COM_TIM14_IRQHandler:
+TIM8_CC_IRQHandler:
+DMA1_Stream7_IRQHandler:
+FMC_IRQHandler:
+SDMMC1_IRQHandler:
+TIM5_IRQHandler:
+SPI3_IRQHandler:
+UART4_IRQHandler:
+UART5_IRQHandler:
+TIM6_DAC_IRQHandler:
+TIM7_IRQHandler:
+DMA2_Stream0_IRQHandler:
+DMA2_Stream1_IRQHandler:
+DMA2_Stream2_IRQHandler:
+DMA2_Stream3_IRQHandler:
+DMA2_Stream4_IRQHandler:
+ETH_IRQHandler:
+ETH_WKUP_IRQHandler:
+FDCAN_CAL_IRQHandler:
+DMA2_Stream5_IRQHandler:
+DMA2_Stream6_IRQHandler:
+DMA2_Stream7_IRQHandler:
+USART6_IRQHandler:
+I2C3_EV_IRQHandler:
+I2C3_ER_IRQHandler:
+OTG_HS_EP1_OUT_IRQHandler:
+OTG_HS_EP1_IN_IRQHandler:
+OTG_HS_WKUP_IRQHandler:
+OTG_HS_IRQHandler:
+DCMI_PSSI_IRQHandler:
+RNG_IRQHandler:
+FPU_IRQHandler:
+UART7_IRQHandler:
+UART8_IRQHandler:
+SPI5_IRQHandler:
+SPI6_IRQHandler:
+SAI1_IRQHandler:
+LTDC_IRQHandler:
+LTDC_ER_IRQHandler:
+DMA2D_IRQHandler:
+OCTOSPI1_IRQHandler:
+LPTIM1_IRQHandler:
+CEC_IRQHandler:
+I2C4_EV_IRQHandler:
+I2C4_ER_IRQHandler:
+SPDIF_RX_IRQHandler:
+DMAMUX1_OVR_IRQHandler:
+DFSDM1_FLT0_IRQHandler:
+DFSDM1_FLT1_IRQHandler:
+DFSDM1_FLT2_IRQHandler:
+DFSDM1_FLT3_IRQHandler:
+SWPMI1_IRQHandler:
+TIM15_IRQHandler:
+TIM16_IRQHandler:
+TIM17_IRQHandler:
+MDIOS_WKUP_IRQHandler:
+MDIOS_IRQHandler:
+MDMA_IRQHandler:
+SDMMC2_IRQHandler:
+HSEM1_IRQHandler:
+ADC3_IRQHandler:
+DMAMUX2_OVR_IRQHandler:
+BDMA_Channel0_IRQHandler:
+BDMA_Channel1_IRQHandler:
+BDMA_Channel2_IRQHandler:
+BDMA_Channel3_IRQHandler:
+BDMA_Channel4_IRQHandler:
+BDMA_Channel5_IRQHandler:
+BDMA_Channel6_IRQHandler:
+BDMA_Channel7_IRQHandler:
+COMP1_IRQHandler:
+LPTIM2_IRQHandler:
+LPTIM3_IRQHandler:
+LPTIM4_IRQHandler:
+LPTIM5_IRQHandler:
+LPUART1_IRQHandler:
+CRS_IRQHandler:
+ECC_IRQHandler:
+SAI4_IRQHandler:
+DTS_IRQHandler:
+WAKEUP_PIN_IRQHandler:
+OCTOSPI2_IRQHandler:
+FMAC_IRQHandler:
+CORDIC_IRQHandler:
+UART9_IRQHandler:
+USART10_IRQHandler:
+I2C5_EV_IRQHandler:
+I2C5_ER_IRQHandler:
+FDCAN3_IT0_IRQHandler:
+FDCAN3_IT1_IRQHandler:
+TIM23_IRQHandler:
+TIM24_IRQHandler:
+  0x0800172C:  E7FE         B          NMI_Handler              ; Dedupe identical section .init.TIM24_IRQHandler
+
    +

    Section .text.SVC_Handler from charger_lto.o, size=2, align=2

    +
    +
    SVC_Handler:
+DebugMon_Handler:
+PendSV_Handler:
+  0x0800172E:  4770         BX         LR                       ; Dedupe identical section .text.PendSV_Handler
+
    +

    Section .text.SPI4_IRQHandler from charger_lto.o, size=630, align=2

    +
    +
    SPI4_IRQHandler:
+  0x08001730:  B538         PUSH       {R3-R5, LR}
+  0x08001732:  F240 0400    MOVW       R4, #0                   ; 0x30000000 = hspi4
+  0x08001736:  F2C3 0400    MOVT       R4, #0x3000              ; 0x30000000 = hspi4
+  0x0800173A:  6820         LDR        R0, [R4]
+  0x0800173C:  6902         LDR        R2, [R0, #16]
+  0x0800173E:  6943         LDR        R3, [R0, #20]
+  0x08001740:  6881         LDR        R1, [R0, #8]
+  0x08001742:  F894 5081    LDRB.W     R5, [R4, #129]
+  0x08001746:  051D         LSLS       R5, R3, #20
+  0x08001748:  D507         BPL        .L1                      ; 0x0800175A
+  0x0800174A:  F012 0508    ANDS       R5, R2, #8
+  0x0800174E:  BF1F         ITTTT      NE
+  0x08001750:  6981         LDRNE      R1, [R0, #24]
+  0x08001752:  F441 6100    ORRNE      R1, R1, #0x0800
+  0x08001756:  6181         STRNE      R1, [R0, #24]
+  0x08001758:  BD38         POPNE      {R3-R5, PC}
+
    .L1:
+  0x0800175A:  EA03 0502    AND.W      R5, R3, R2
+  0x0800175E:  F005 0264    AND        R2, R5, #100
+  0x08001762:  2A04         CMP        R2, #4
+  0x08001764:  D104         BNE        .L2                      ; 0x08001770
+  0x08001766:  6F61         LDR        R1, [R4, #116]
+  0x08001768:  4620         MOV        R0, R4
+  0x0800176A:  4788         BLX        R1
+  0x0800176C:  6F21         LDR        R1, [R4, #112]
+  0x0800176E:  E010         B          .L6                      ; 0x08001792
+
    .L2:
+  0x08001770:  F005 0245    AND        R2, R5, #69
+  0x08001774:  2A01         CMP        R2, #1
+  0x08001776:  D107         BNE        .L4                      ; 0x08001788
+  0x08001778:  6F21         LDR        R1, [R4, #112]
+  0x0800177A:  4620         MOV        R0, R4
+  0x0800177C:  4788         BLX        R1
+  0x0800177E:  F005 0022    AND        R0, R5, #34
+  0x08001782:  2802         CMP        R0, #2
+  0x08001784:  D004         BEQ        .L5                      ; 0x08001790
+
    .L3:
+  0x08001786:  BD38         POP        {R3-R5, PC}
+
    .L4:
+  0x08001788:  F005 0226    AND        R2, R5, #38
+  0x0800178C:  2A02         CMP        R2, #2
+  0x0800178E:  D104         BNE        .L7                      ; 0x0800179A
+
    .L5:
+  0x08001790:  6F61         LDR        R1, [R4, #116]
+
    .L6:
+  0x08001792:  4620         MOV        R0, R4
+  0x08001794:  E8BD 4038    POP.W      {R3-R5, LR}
+  0x08001798:  4708         BX         R1
+
    .L7:
+  0x0800179A:  072A         LSLS       R2, R5, #28
+  0x0800179C:  D46B         BMI        .L13                     ; 0x08001876
+  0x0800179E:  F415 7F58    TST        R5, #0x0360
+  0x080017A2:  D0F0         BEQ        .L3                      ; 0x08001786
+  0x080017A4:  066A         LSLS       R2, R5, #25
+  0x080017A6:  D509         BPL        .L8                      ; 0x080017BC
+  0x080017A8:  F8D4 2084    LDR.W      R2, [R4, #132]
+  0x080017AC:  F042 0204    ORR        R2, R2, #4
+  0x080017B0:  F8C4 2084    STR.W      R2, [R4, #132]
+  0x080017B4:  6982         LDR        R2, [R0, #24]
+  0x080017B6:  F042 0240    ORR        R2, R2, #64
+  0x080017BA:  6182         STR        R2, [R0, #24]
+
    .L8:
+  0x080017BC:  05AA         LSLS       R2, R5, #22
+  0x080017BE:  D509         BPL        .L9                      ; 0x080017D4
+  0x080017C0:  F8D4 2084    LDR.W      R2, [R4, #132]
+  0x080017C4:  F042 0201    ORR        R2, R2, #1
+  0x080017C8:  F8C4 2084    STR.W      R2, [R4, #132]
+  0x080017CC:  6982         LDR        R2, [R0, #24]
+  0x080017CE:  F442 7200    ORR        R2, R2, #0x0200
+  0x080017D2:  6182         STR        R2, [R0, #24]
+
    .L9:
+  0x080017D4:  05EA         LSLS       R2, R5, #23
+  0x080017D6:  D509         BPL        .L10                     ; 0x080017EC
+  0x080017D8:  F8D4 2084    LDR.W      R2, [R4, #132]
+  0x080017DC:  F042 0208    ORR        R2, R2, #8
+  0x080017E0:  F8C4 2084    STR.W      R2, [R4, #132]
+  0x080017E4:  6982         LDR        R2, [R0, #24]
+  0x080017E6:  F442 7280    ORR        R2, R2, #0x0100
+  0x080017EA:  6182         STR        R2, [R0, #24]
+
    .L10:
+  0x080017EC:  06AA         LSLS       R2, R5, #26
+  0x080017EE:  D509         BPL        .L11                     ; 0x08001804
+  0x080017F0:  F8D4 2084    LDR.W      R2, [R4, #132]
+  0x080017F4:  F042 0280    ORR        R2, R2, #128
+  0x080017F8:  F8C4 2084    STR.W      R2, [R4, #132]
+  0x080017FC:  6982         LDR        R2, [R0, #24]
+  0x080017FE:  F042 0220    ORR        R2, R2, #32
+  0x08001802:  6182         STR        R2, [R0, #24]
+
    .L11:
+  0x08001804:  F8D4 2084    LDR.W      R2, [R4, #132]
+  0x08001808:  2A00         CMP        R2, #0
+  0x0800180A:  D0BC         BEQ        .L3                      ; 0x08001786
+  0x0800180C:  6802         LDR        R2, [R0]
+  0x0800180E:  F401 4140    AND        R1, R1, #0xC000
+  0x08001812:  F022 0201    BIC        R2, R2, #1
+  0x08001816:  6002         STR        R2, [R0]
+  0x08001818:  6902         LDR        R2, [R0, #16]
+  0x0800181A:  F240 336B    MOVW       R3, #0x036B
+  0x0800181E:  F5B1 4F40    CMP.W      R1, #0xC000
+  0x08001822:  EA22 0103    BIC.W      R1, R2, R3
+  0x08001826:  6101         STR        R1, [R0, #16]
+  0x08001828:  F040 80B9    BNE.W      .L23                     ; 0x0800199E
+  0x0800182C:  6881         LDR        R1, [R0, #8]
+  0x0800182E:  F242 25F9    MOVW       R5, #0x22F9              ; 0x080022F9 = SPI_DMAAbortOnError
+  0x08001832:  F421 4140    BIC        R1, R1, #0xC000
+  0x08001836:  6081         STR        R1, [R0, #8]
+  0x08001838:  6FE0         LDR        R0, [R4, #124]
+  0x0800183A:  F6C0 0500    MOVT       R5, #0x0800              ; 0x080022F9 = SPI_DMAAbortOnError
+  0x0800183E:  B150         CBZ        R0, .L12                 ; 0x08001856
+  0x08001840:  6505         STR        R5, [R0, #80]
+  0x08001842:  F000 FC83    BL         HAL_DMA_Abort_IT         ; 0x0800214C
+  0x08001846:  2800         CMP        R0, #0
+  0x08001848:  BF1E         ITTT       NE
+  0x0800184A:  F8D4 0084    LDRNE.W    R0, [R4, #132]
+  0x0800184E:  F040 0040    ORRNE      R0, R0, #64
+  0x08001852:  F8C4 0084    STRNE.W    R0, [R4, #132]
+
    .L12:
+  0x08001856:  6FA0         LDR        R0, [R4, #120]
+  0x08001858:  2800         CMP        R0, #0
+  0x0800185A:  D094         BEQ        .L3                      ; 0x08001786
+  0x0800185C:  6505         STR        R5, [R0, #80]
+  0x0800185E:  F000 FC75    BL         HAL_DMA_Abort_IT         ; 0x0800214C
+  0x08001862:  2800         CMP        R0, #0
+  0x08001864:  BF08         IT         EQ
+  0x08001866:  BD38         POPEQ      {R3-R5, PC}
+  0x08001868:  F8D4 0084    LDR.W      R0, [R4, #132]
+  0x0800186C:  F040 0040    ORR        R0, R0, #64
+  0x08001870:  F8C4 0084    STR.W      R0, [R4, #132]
+  0x08001874:  BD38         POP        {R3-R5, PC}
+
    .L13:
+  0x08001876:  6981         LDR        R1, [R0, #24]
+  0x08001878:  F041 0108    ORR        R1, R1, #8
+  0x0800187C:  6181         STR        R1, [R0, #24]
+  0x0800187E:  6981         LDR        R1, [R0, #24]
+  0x08001880:  F041 0110    ORR        R1, R1, #16
+  0x08001884:  6181         STR        R1, [R0, #24]
+  0x08001886:  6981         LDR        R1, [R0, #24]
+  0x08001888:  F441 6100    ORR        R1, R1, #0x0800
+  0x0800188C:  6181         STR        R1, [R0, #24]
+  0x0800188E:  6901         LDR        R1, [R0, #16]
+  0x08001890:  F021 0108    BIC        R1, R1, #8
+  0x08001894:  6101         STR        R1, [R0, #16]
+  0x08001896:  6881         LDR        R1, [R0, #8]
+  0x08001898:  F411 4F40    TST        R1, #0xC000
+  0x0800189C:  D124         BNE        .L18                     ; 0x080018E8
+  0x0800189E:  F8B4 106A    LDRH.W     R1, [R4, #106]
+  0x080018A2:  B309         CBZ        R1, .L18                 ; 0x080018E8
+
    .L14:
+  0x080018A4:  68E1         LDR        R1, [R4, #12]
+  0x080018A6:  2910         CMP        R1, #16
+  0x080018A8:  D305         BCC        .L15                     ; 0x080018B6
+  0x080018AA:  6822         LDR        R2, [R4]
+  0x080018AC:  6E61         LDR        R1, [R4, #100]
+  0x080018AE:  6B12         LDR        R2, [R2, #48]
+  0x080018B0:  F841 2B04    STR        R2, [R1], #4
+  0x080018B4:  E00D         B          .L17                     ; 0x080018D2
+
    .L15:
+  0x080018B6:  2908         CMP        R1, #8
+  0x080018B8:  D304         BCC        .L16                     ; 0x080018C4
+  0x080018BA:  8E02         LDRH       R2, [R0, #48]
+  0x080018BC:  6E61         LDR        R1, [R4, #100]
+  0x080018BE:  F821 2B02    STRH       R2, [R1], #2
+  0x080018C2:  E006         B          .L17                     ; 0x080018D2
+
    .L16:
+  0x080018C4:  6821         LDR        R1, [R4]
+  0x080018C6:  F891 1030    LDRB.W     R1, [R1, #48]
+  0x080018CA:  6E62         LDR        R2, [R4, #100]
+  0x080018CC:  7011         STRB       R1, [R2]
+  0x080018CE:  6E61         LDR        R1, [R4, #100]
+  0x080018D0:  3101         ADDS       R1, #1
+
    .L17:
+  0x080018D2:  6661         STR        R1, [R4, #100]
+  0x080018D4:  F8B4 106A    LDRH.W     R1, [R4, #106]
+  0x080018D8:  3901         SUBS       R1, #1
+  0x080018DA:  F8A4 106A    STRH.W     R1, [R4, #106]
+  0x080018DE:  F8B4 106A    LDRH.W     R1, [R4, #106]
+  0x080018E2:  2900         CMP        R1, #0
+  0x080018E4:  D1DE         BNE        .L14                     ; 0x080018A4
+  0x080018E6:  6820         LDR        R0, [R4]
+
    .L18:
+  0x080018E8:  6941         LDR        R1, [R0, #20]
+  0x080018EA:  6982         LDR        R2, [R0, #24]
+  0x080018EC:  F042 0208    ORR        R2, R2, #8
+  0x080018F0:  6182         STR        R2, [R0, #24]
+  0x080018F2:  6982         LDR        R2, [R0, #24]
+  0x080018F4:  F240 336F    MOVW       R3, #0x036F
+  0x080018F8:  F042 0210    ORR        R2, R2, #16
+  0x080018FC:  6182         STR        R2, [R0, #24]
+  0x080018FE:  6802         LDR        R2, [R0]
+  0x08001900:  F022 0201    BIC        R2, R2, #1
+  0x08001904:  6002         STR        R2, [R0]
+  0x08001906:  6902         LDR        R2, [R0, #16]
+  0x08001908:  439A         BICS       R2, R3
+  0x0800190A:  6102         STR        R2, [R0, #16]
+  0x0800190C:  6882         LDR        R2, [R0, #8]
+  0x0800190E:  F422 4240    BIC        R2, R2, #0xC000
+  0x08001912:  6082         STR        R2, [R0, #8]
+  0x08001914:  F894 2081    LDRB.W     R2, [R4, #129]
+  0x08001918:  2A04         CMP        R2, #4
+  0x0800191A:  BF18         IT         NE
+  0x0800191C:  F011 0220    ANDSNE     R2, R1, #32
+  0x08001920:  D009         BEQ        .L19                     ; 0x08001936
+  0x08001922:  F8D4 2084    LDR.W      R2, [R4, #132]
+  0x08001926:  F042 0280    ORR        R2, R2, #128
+  0x0800192A:  F8C4 2084    STR.W      R2, [R4, #132]
+  0x0800192E:  6982         LDR        R2, [R0, #24]
+  0x08001930:  F042 0220    ORR        R2, R2, #32
+  0x08001934:  6182         STR        R2, [R0, #24]
+
    .L19:
+  0x08001936:  F894 2081    LDRB.W     R2, [R4, #129]
+  0x0800193A:  2A03         CMP        R2, #3
+  0x0800193C:  BF18         IT         NE
+  0x0800193E:  F011 0240    ANDSNE     R2, R1, #64
+  0x08001942:  D009         BEQ        .L20                     ; 0x08001958
+  0x08001944:  F8D4 2084    LDR.W      R2, [R4, #132]
+  0x08001948:  F042 0204    ORR        R2, R2, #4
+  0x0800194C:  F8C4 2084    STR.W      R2, [R4, #132]
+  0x08001950:  6982         LDR        R2, [R0, #24]
+  0x08001952:  F042 0240    ORR        R2, R2, #64
+  0x08001956:  6182         STR        R2, [R0, #24]
+
    .L20:
+  0x08001958:  058A         LSLS       R2, R1, #22
+  0x0800195A:  D509         BPL        .L21                     ; 0x08001970
+  0x0800195C:  F8D4 2084    LDR.W      R2, [R4, #132]
+  0x08001960:  F042 0201    ORR        R2, R2, #1
+  0x08001964:  F8C4 2084    STR.W      R2, [R4, #132]
+  0x08001968:  6982         LDR        R2, [R0, #24]
+  0x0800196A:  F442 7200    ORR        R2, R2, #0x0200
+  0x0800196E:  6182         STR        R2, [R0, #24]
+
    .L21:
+  0x08001970:  05C9         LSLS       R1, R1, #23
+  0x08001972:  D509         BPL        .L22                     ; 0x08001988
+  0x08001974:  F8D4 1084    LDR.W      R1, [R4, #132]
+  0x08001978:  F041 0108    ORR        R1, R1, #8
+  0x0800197C:  F8C4 1084    STR.W      R1, [R4, #132]
+  0x08001980:  6981         LDR        R1, [R0, #24]
+  0x08001982:  F441 7180    ORR        R1, R1, #0x0100
+  0x08001986:  6181         STR        R1, [R0, #24]
+
    .L22:
+  0x08001988:  2000         MOVS       R0, #0
+  0x0800198A:  F8A4 0062    STRH.W     R0, [R4, #98]
+  0x0800198E:  F8A4 006A    STRH.W     R0, [R4, #106]
+  0x08001992:  2001         MOVS       R0, #1
+  0x08001994:  F884 0081    STRB.W     R0, [R4, #129]
+  0x08001998:  F8D4 0084    LDR.W      R0, [R4, #132]
+  0x0800199C:  BD38         POP        {R3-R5, PC}
+
    .L23:
+  0x0800199E:  2001         MOVS       R0, #1
+  0x080019A0:  F884 0081    STRB.W     R0, [R4, #129]
+  0x080019A4:  BD38         POP        {R3-R5, PC}

    Section .text.SystemInit from charger_lto.o, size=166, align=2

    -
    SystemInit:
-  0x08000706:  F64E 5088    MOVW       R0, #0xED88
-  0x0800070A:  F242 0300    MOVW       R3, #0x2000
-  0x0800070E:  F2CE 0000    MOVT       R0, #0xE000
-  0x08000712:  F2C5 2300    MOVT       R3, #0x5200
-  0x08000716:  6802         LDR        R2, [R0]
-  0x08000718:  F442 0270    ORR        R2, R2, #0xF00000
-  0x0800071C:  6002         STR        R2, [R0]
-  0x0800071E:  6818         LDR        R0, [R3]
-  0x08000720:  F000 000F    AND        R0, R0, #15
-  0x08000724:  2806         CMP        R0, #6
-  0x08000726:  D804         BHI        .L1                      ; 0x08000732
-  0x08000728:  6818         LDR        R0, [R3]
-  0x0800072A:  2207         MOVS       R2, #7
-  0x0800072C:  F362 0003    BFI        R0, R2, #0, #4
-  0x08000730:  6018         STR        R0, [R3]
+
    SystemInit:
+  0x080019A6:  F64E 5088    MOVW       R0, #0xED88
+  0x080019AA:  F242 0300    MOVW       R3, #0x2000
+  0x080019AE:  F2CE 0000    MOVT       R0, #0xE000
+  0x080019B2:  F2C5 2300    MOVT       R3, #0x5200
+  0x080019B6:  6802         LDR        R2, [R0]
+  0x080019B8:  F442 0270    ORR        R2, R2, #0xF00000
+  0x080019BC:  6002         STR        R2, [R0]
+  0x080019BE:  6818         LDR        R0, [R3]
+  0x080019C0:  F000 000F    AND        R0, R0, #15
+  0x080019C4:  2806         CMP        R0, #6
+  0x080019C6:  D804         BHI        .L1                      ; 0x080019D2
+  0x080019C8:  6818         LDR        R0, [R3]
+  0x080019CA:  2207         MOVS       R2, #7
+  0x080019CC:  F362 0003    BFI        R0, R2, #0, #4
+  0x080019D0:  6018         STR        R0, [R3]
 
    .L1:
-  0x08000732:  F244 4000    MOVW       R0, #0x4400
-  0x08000736:  F64E 517F    MOVW       R1, #0xED7F
-  0x0800073A:  F6C5 0002    MOVT       R0, #0x5802
-  0x0800073E:  F6CE 21F6    MOVT       R1, #0xEAF6
-  0x08000742:  6802         LDR        R2, [R0]
-  0x08000744:  F042 0201    ORR        R2, R2, #1
-  0x08000748:  6002         STR        R2, [R0]
-  0x0800074A:  2200         MOVS       R2, #0
-  0x0800074C:  6102         STR        R2, [R0, #16]
-  0x0800074E:  F8D0 C000    LDR.W      R12, [R0]
-  0x08000752:  EA01 010C    AND.W      R1, R1, R12
-  0x08000756:  6001         STR        R1, [R0]
-  0x08000758:  6819         LDR        R1, [R3]
-  0x0800075A:  0709         LSLS       R1, R1, #28
-  0x0800075C:  D505         BPL        .L2                      ; 0x0800076A
-  0x0800075E:  6819         LDR        R1, [R3]
-  0x08000760:  F04F 0C07    MOV.W      R12, #7
-  0x08000764:  F36C 0103    BFI        R1, R12, #0, #4
-  0x08000768:  6019         STR        R1, [R3]
+  0x080019D2:  F244 4000    MOVW       R0, #0x4400
+  0x080019D6:  F64E 517F    MOVW       R1, #0xED7F
+  0x080019DA:  F6C5 0002    MOVT       R0, #0x5802
+  0x080019DE:  F6CE 21F6    MOVT       R1, #0xEAF6
+  0x080019E2:  6802         LDR        R2, [R0]
+  0x080019E4:  F042 0201    ORR        R2, R2, #1
+  0x080019E8:  6002         STR        R2, [R0]
+  0x080019EA:  2200         MOVS       R2, #0
+  0x080019EC:  6102         STR        R2, [R0, #16]
+  0x080019EE:  F8D0 C000    LDR.W      R12, [R0]
+  0x080019F2:  EA01 010C    AND.W      R1, R1, R12
+  0x080019F6:  6001         STR        R1, [R0]
+  0x080019F8:  6819         LDR        R1, [R3]
+  0x080019FA:  0709         LSLS       R1, R1, #28
+  0x080019FC:  D505         BPL        .L2                      ; 0x08001A0A
+  0x080019FE:  6819         LDR        R1, [R3]
+  0x08001A00:  F04F 0C07    MOV.W      R12, #7
+  0x08001A04:  F36C 0103    BFI        R1, R12, #0, #4
+  0x08001A08:  6019         STR        R1, [R3]
 
    .L2:
-  0x0800076A:  F240 2100    MOVW       R1, #0x0200
-  0x0800076E:  6182         STR        R2, [R0, #24]
-  0x08000770:  F2C0 2102    MOVT       R1, #0x0202
-  0x08000774:  61C2         STR        R2, [R0, #28]
-  0x08000776:  6202         STR        R2, [R0, #32]
-  0x08000778:  6281         STR        R1, [R0, #40]
-  0x0800077A:  2100         MOVS       R1, #0
-  0x0800077C:  F2C0 11FF    MOVT       R1, #0x01FF
-  0x08000780:  62C1         STR        R1, [R0, #44]
-  0x08000782:  F240 2180    MOVW       R1, #0x0280
-  0x08000786:  F2C0 1101    MOVT       R1, #0x0101
-  0x0800078A:  6301         STR        R1, [R0, #48]
-  0x0800078C:  6342         STR        R2, [R0, #52]
-  0x0800078E:  6381         STR        R1, [R0, #56]
-  0x08000790:  63C2         STR        R2, [R0, #60]
-  0x08000792:  6401         STR        R1, [R0, #64]
-  0x08000794:  6442         STR        R2, [R0, #68]
-  0x08000796:  6801         LDR        R1, [R0]
-  0x08000798:  F421 2180    BIC        R1, R1, #0x040000
-  0x0800079C:  6001         STR        R1, [R0]
-  0x0800079E:  6602         STR        R2, [R0, #96]
-  0x080007A0:  F503 5000    ADD.W      R0, R3, #0x2000
-  0x080007A4:  F243 01D2    MOVW       R1, #0x30D2
-  0x080007A8:  6001         STR        R1, [R0]
-  0x080007AA:  4770         BX         LR
+  0x08001A0A:  F240 2100    MOVW       R1, #0x0200
+  0x08001A0E:  6182         STR        R2, [R0, #24]
+  0x08001A10:  F2C0 2102    MOVT       R1, #0x0202
+  0x08001A14:  61C2         STR        R2, [R0, #28]
+  0x08001A16:  6202         STR        R2, [R0, #32]
+  0x08001A18:  6281         STR        R1, [R0, #40]
+  0x08001A1A:  2100         MOVS       R1, #0
+  0x08001A1C:  F2C0 11FF    MOVT       R1, #0x01FF
+  0x08001A20:  62C1         STR        R1, [R0, #44]
+  0x08001A22:  F240 2180    MOVW       R1, #0x0280
+  0x08001A26:  F2C0 1101    MOVT       R1, #0x0101
+  0x08001A2A:  6301         STR        R1, [R0, #48]
+  0x08001A2C:  6342         STR        R2, [R0, #52]
+  0x08001A2E:  6381         STR        R1, [R0, #56]
+  0x08001A30:  63C2         STR        R2, [R0, #60]
+  0x08001A32:  6401         STR        R1, [R0, #64]
+  0x08001A34:  6442         STR        R2, [R0, #68]
+  0x08001A36:  6801         LDR        R1, [R0]
+  0x08001A38:  F421 2180    BIC        R1, R1, #0x040000
+  0x08001A3C:  6001         STR        R1, [R0]
+  0x08001A3E:  6602         STR        R2, [R0, #96]
+  0x08001A40:  F503 5000    ADD.W      R0, R3, #0x2000
+  0x08001A44:  F243 01D2    MOVW       R1, #0x30D2
+  0x08001A48:  6001         STR        R1, [R0]
+  0x08001A4A:  4770         BX         LR
    -

    Section .text.NMI_Handler from charger_lto.o, size=2, align=2

    +

    Section .text.HAL_InitTick from charger_lto.o, size=90, align=2

    -
    NMI_Handler:
-HardFault_Handler:
-MemManage_Handler:
-BusFault_Handler:
-UsageFault_Handler:
-WWDG_IRQHandler:
-PVD_AVD_IRQHandler:
-TAMP_STAMP_IRQHandler:
-RTC_WKUP_IRQHandler:
-FLASH_IRQHandler:
-RCC_IRQHandler:
-EXTI0_IRQHandler:
-EXTI1_IRQHandler:
-EXTI2_IRQHandler:
-EXTI3_IRQHandler:
-EXTI4_IRQHandler:
-DMA1_Stream0_IRQHandler:
-DMA1_Stream1_IRQHandler:
-DMA1_Stream2_IRQHandler:
-DMA1_Stream3_IRQHandler:
-DMA1_Stream4_IRQHandler:
-DMA1_Stream5_IRQHandler:
-DMA1_Stream6_IRQHandler:
-ADC_IRQHandler:
-FDCAN1_IT0_IRQHandler:
-FDCAN2_IT0_IRQHandler:
-FDCAN1_IT1_IRQHandler:
-FDCAN2_IT1_IRQHandler:
-EXTI9_5_IRQHandler:
-TIM1_BRK_IRQHandler:
-TIM1_UP_IRQHandler:
-TIM1_TRG_COM_IRQHandler:
-TIM1_CC_IRQHandler:
-TIM2_IRQHandler:
-TIM3_IRQHandler:
-TIM4_IRQHandler:
-I2C1_EV_IRQHandler:
-I2C1_ER_IRQHandler:
-I2C2_EV_IRQHandler:
-I2C2_ER_IRQHandler:
-SPI1_IRQHandler:
-SPI2_IRQHandler:
-USART1_IRQHandler:
-USART2_IRQHandler:
-USART3_IRQHandler:
-EXTI15_10_IRQHandler:
-RTC_Alarm_IRQHandler:
-TIM8_BRK_TIM12_IRQHandler:
-TIM8_UP_TIM13_IRQHandler:
-TIM8_TRG_COM_TIM14_IRQHandler:
-TIM8_CC_IRQHandler:
-DMA1_Stream7_IRQHandler:
-FMC_IRQHandler:
-SDMMC1_IRQHandler:
-TIM5_IRQHandler:
-SPI3_IRQHandler:
-UART4_IRQHandler:
-UART5_IRQHandler:
-TIM6_DAC_IRQHandler:
-TIM7_IRQHandler:
-DMA2_Stream0_IRQHandler:
-DMA2_Stream1_IRQHandler:
-DMA2_Stream2_IRQHandler:
-DMA2_Stream3_IRQHandler:
-DMA2_Stream4_IRQHandler:
-ETH_IRQHandler:
-ETH_WKUP_IRQHandler:
-FDCAN_CAL_IRQHandler:
-DMA2_Stream5_IRQHandler:
-DMA2_Stream6_IRQHandler:
-DMA2_Stream7_IRQHandler:
-USART6_IRQHandler:
-I2C3_EV_IRQHandler:
-I2C3_ER_IRQHandler:
-OTG_HS_EP1_OUT_IRQHandler:
-OTG_HS_EP1_IN_IRQHandler:
-OTG_HS_WKUP_IRQHandler:
-OTG_HS_IRQHandler:
-DCMI_PSSI_IRQHandler:
-RNG_IRQHandler:
-FPU_IRQHandler:
-UART7_IRQHandler:
-UART8_IRQHandler:
-SPI4_IRQHandler:
-SPI5_IRQHandler:
-SPI6_IRQHandler:
-SAI1_IRQHandler:
-LTDC_IRQHandler:
-LTDC_ER_IRQHandler:
-DMA2D_IRQHandler:
-OCTOSPI1_IRQHandler:
-LPTIM1_IRQHandler:
-CEC_IRQHandler:
-I2C4_EV_IRQHandler:
-I2C4_ER_IRQHandler:
-SPDIF_RX_IRQHandler:
-DMAMUX1_OVR_IRQHandler:
-DFSDM1_FLT0_IRQHandler:
-DFSDM1_FLT1_IRQHandler:
-DFSDM1_FLT2_IRQHandler:
-DFSDM1_FLT3_IRQHandler:
-SWPMI1_IRQHandler:
-TIM15_IRQHandler:
-TIM16_IRQHandler:
-TIM17_IRQHandler:
-MDIOS_WKUP_IRQHandler:
-MDIOS_IRQHandler:
-MDMA_IRQHandler:
-SDMMC2_IRQHandler:
-HSEM1_IRQHandler:
-ADC3_IRQHandler:
-DMAMUX2_OVR_IRQHandler:
-BDMA_Channel0_IRQHandler:
-BDMA_Channel1_IRQHandler:
-BDMA_Channel2_IRQHandler:
-BDMA_Channel3_IRQHandler:
-BDMA_Channel4_IRQHandler:
-BDMA_Channel5_IRQHandler:
-BDMA_Channel6_IRQHandler:
-BDMA_Channel7_IRQHandler:
-COMP1_IRQHandler:
-LPTIM2_IRQHandler:
-LPTIM3_IRQHandler:
-LPTIM4_IRQHandler:
-LPTIM5_IRQHandler:
-LPUART1_IRQHandler:
-CRS_IRQHandler:
-ECC_IRQHandler:
-SAI4_IRQHandler:
-DTS_IRQHandler:
-WAKEUP_PIN_IRQHandler:
-OCTOSPI2_IRQHandler:
-FMAC_IRQHandler:
-CORDIC_IRQHandler:
-UART9_IRQHandler:
-USART10_IRQHandler:
-I2C5_EV_IRQHandler:
-I2C5_ER_IRQHandler:
-FDCAN3_IT0_IRQHandler:
-FDCAN3_IT1_IRQHandler:
-TIM23_IRQHandler:
-TIM24_IRQHandler:
-  0x080007AC:  E7FE         B          NMI_Handler              ; Dedupe identical section .init.TIM24_IRQHandler
-
    -

    Section .text.SVC_Handler from charger_lto.o, size=2, align=2

    -
    -
    SVC_Handler:
-DebugMon_Handler:
-PendSV_Handler:
-  0x080007AE:  4770         BX         LR                       ; Dedupe identical section .text.PendSV_Handler
-
    -

    Section .text.HAL_Init from charger_lto.o, size=114, align=2

    -
    -
    HAL_Init:
-  0x080007B0:  B510         PUSH       {R4, LR}
-  0x080007B2:  B082         SUB        SP, SP, #8
-  0x080007B4:  F64E 500C    MOVW       R0, #0xED0C
-  0x080007B8:  F64F 02FF    MOVW       R2, #0xF8FF
-  0x080007BC:  F2CE 0000    MOVT       R0, #0xE000
-  0x080007C0:  F244 4418    MOVW       R4, #0x4418
-  0x080007C4:  F6C5 0402    MOVT       R4, #0x5802
-  0x080007C8:  6801         LDR        R1, [R0]
-  0x080007CA:  4011         ANDS       R1, R2
-  0x080007CC:  F240 3200    MOVW       R2, #0x0300
-  0x080007D0:  F2C0 52FA    MOVT       R2, #0x05FA
-  0x080007D4:  4311         ORRS       R1, R2
-  0x080007D6:  6001         STR        R1, [R0]
-  0x080007D8:  F7FF FD78    BL         HAL_RCC_GetSysClockFreq  ; 0x080002CC
-  0x080007DC:  6821         LDR        R1, [R4]
-  0x080007DE:  F640 32AE    MOVW       R2, #0x0BAE              ; 0x08000BAE = D1CorePrescTable
-  0x080007E2:  F6C0 0200    MOVT       R2, #0x0800              ; 0x08000BAE = D1CorePrescTable
-  0x080007E6:  F3C1 2103    UBFX       R1, R1, #8, #4
-  0x080007EA:  5C51         LDRB       R1, [R2, R1]
-  0x080007EC:  6822         LDR        R2, [R4]
-  0x080007EE:  F001 011F    AND        R1, R1, #31
-  0x080007F2:  40C8         LSRS       R0, R1
-  0x080007F4:  F240 012C    MOVW       R1, #44                  ; 0x3000002C = SystemCoreClock
-  0x080007F8:  F2C3 0100    MOVT       R1, #0x3000              ; 0x3000002C = SystemCoreClock
-  0x080007FC:  6008         STR        R0, [R1]
-  0x080007FE:  200F         MOVS       R0, #15
-  0x08000800:  F000 F989    BL         HAL_InitTick             ; 0x08000B16
-  0x08000804:  B958         CBNZ       R0, .L1                  ; 0x0800081E
-  0x08000806:  F8D4 00DC    LDR.W      R0, [R4, #220]
-  0x0800080A:  F040 0002    ORR        R0, R0, #2
-  0x0800080E:  F8C4 00DC    STR.W      R0, [R4, #220]
-  0x08000812:  F8D4 00DC    LDR.W      R0, [R4, #220]
-  0x08000816:  F000 0002    AND        R0, R0, #2
-  0x0800081A:  9001         STR        R0, [SP, #4]
-  0x0800081C:  9801         LDR        R0, [SP, #4]
+
    HAL_InitTick:
+  0x08001A4C:  B510         PUSH       {R4, LR}
+  0x08001A4E:  F240 112C    MOVW       R1, #0x012C              ; 0x3000012C = SystemCoreClock
+  0x08001A52:  F644 52D3    MOVW       R2, #0x4DD3
+  0x08001A56:  F2C3 0100    MOVT       R1, #0x3000              ; 0x3000012C = SystemCoreClock
+  0x08001A5A:  F2C1 0262    MOVT       R2, #0x1062
+  0x08001A5E:  2401         MOVS       R4, #1
+  0x08001A60:  6809         LDR        R1, [R1]
+  0x08001A62:  FBA1 1202    UMULL      R1, R2, R1, R2
+  0x08001A66:  1EA1         SUBS       R1, R4, #2
+  0x08001A68:  EB01 1192    ADD.W      R1, R1, R2, LSR #6
+  0x08001A6C:  0E0A         LSRS       R2, R1, #24
+  0x08001A6E:  D118         BNE        .L1                      ; 0x08001AA2
+  0x08001A70:  F24E 0210    MOVW       R2, #0xE010
+  0x08001A74:  23F0         MOVS       R3, #240
+  0x08001A76:  F2CE 0200    MOVT       R2, #0xE000
+  0x08001A7A:  6051         STR        R1, [R2, #4]
+  0x08001A7C:  F602 5113    ADDW       R1, R2, #0x0D13
+  0x08001A80:  700B         STRB       R3, [R1]
+  0x08001A82:  2100         MOVS       R1, #0
+  0x08001A84:  6091         STR        R1, [R2, #8]
+  0x08001A86:  2107         MOVS       R1, #7
+  0x08001A88:  280F         CMP        R0, #15
+  0x08001A8A:  6011         STR        R1, [R2]
+  0x08001A8C:  D809         BHI        .L1                      ; 0x08001AA2
+  0x08001A8E:  1EA0         SUBS       R0, R4, #2
+  0x08001A90:  210F         MOVS       R1, #15
+  0x08001A92:  F000 FA25    BL         HAL_NVIC_SetPriority     ; 0x08001EE0
+  0x08001A96:  F240 1028    MOVW       R0, #0x0128              ; 0x30000128 = uwTickPrio
+  0x08001A9A:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000128 = uwTickPrio
+  0x08001A9E:  7004         STRB       R4, [R0]
+  0x08001AA0:  2400         MOVS       R4, #0
 
    .L1:
-  0x0800081E:  B002         ADD        SP, SP, #8
-  0x08000820:  BD10         POP        {R4, PC}
-
    -

    Section .text.HAL_RTC_Init from charger_lto.o, size=382, align=2

    -
    -
    HAL_RTC_Init:
-  0x08000822:  B570         PUSH       {R4-R6, LR}
-  0x08000824:  F240 0604    MOVW       R6, #4                   ; 0x30000000 = hrtc
-  0x08000828:  F2C3 0600    MOVT       R6, #0x3000              ; 0x30000000 = hrtc
-  0x0800082C:  7F70         LDRB       R0, [R6, #29]
-  0x0800082E:  2800         CMP        R0, #0
-  0x08000830:  F856 0C04    LDR        R0, [R6, #-4]
-  0x08000834:  D149         BNE        .L7                      ; 0x080008CA
-  0x08000836:  F244 0100    MOVW       R1, #0x4000
-  0x0800083A:  F6C5 0100    MOVT       R1, #0x5800
-  0x0800083E:  4288         CMP        R0, R1
-  0x08000840:  F04F 0100    MOV.W      R1, #0
-  0x08000844:  7731         STRB       R1, [R6, #28]
-  0x08000846:  D140         BNE        .L7                      ; 0x080008CA
-  0x08000848:  F244 4110    MOVW       R1, #0x4410
-  0x0800084C:  F6C5 0102    MOVT       R1, #0x5802
-  0x08000850:  F8D1 23F0    LDR.W      R2, [R1, #0x03F0]
-  0x08000854:  F442 7280    ORR        R2, R2, #0x0100
-  0x08000858:  F8C1 23F0    STR.W      R2, [R1, #0x03F0]
-  0x0800085C:  F240 0224    MOVW       R2, #36                  ; 0x30000024 = uwTick
-  0x08000860:  F2C3 0200    MOVT       R2, #0x3000              ; 0x30000024 = uwTick
-  0x08000864:  6813         LDR        R3, [R2]
-
    .L1:
-  0x08000866:  F8D1 53F0    LDR.W      R5, [R1, #0x03F0]
-  0x0800086A:  05ED         LSLS       R5, R5, #23
-  0x0800086C:  D404         BMI        .L2                      ; 0x08000878
-  0x0800086E:  6815         LDR        R5, [R2]
-  0x08000870:  1AED         SUBS       R5, R5, R3
-  0x08000872:  2D64         CMP        R5, #100
-  0x08000874:  D9F7         BLS        .L1                      ; 0x08000866
-  0x08000876:  E01B         B          .L5                      ; 0x080008B0
-
    .L2:
-  0x08000878:  6E0B         LDR        R3, [R1, #96]
-  0x0800087A:  F403 7340    AND        R3, R3, #0x0300
-  0x0800087E:  F5B3 7F80    CMP.W      R3, #0x0100
-  0x08000882:  D00B         BEQ        .L3                      ; 0x0800089C
-  0x08000884:  6E0B         LDR        R3, [R1, #96]
-  0x08000886:  6E0D         LDR        R5, [R1, #96]
-  0x08000888:  F445 3580    ORR        R5, R5, #0x010000
-  0x0800088C:  660D         STR        R5, [R1, #96]
-  0x0800088E:  6E0D         LDR        R5, [R1, #96]
-  0x08000890:  F423 7340    BIC        R3, R3, #0x0300
-  0x08000894:  F425 3580    BIC        R5, R5, #0x010000
-  0x08000898:  660D         STR        R5, [R1, #96]
-  0x0800089A:  660B         STR        R3, [R1, #96]
-
    .L3:
-  0x0800089C:  6813         LDR        R3, [R2]
-  0x0800089E:  F241 3589    MOVW       R5, #0x1389
-
    .L4:
-  0x080008A2:  6E0C         LDR        R4, [R1, #96]
-  0x080008A4:  07A4         LSLS       R4, R4, #30
-  0x080008A6:  D404         BMI        .L6                      ; 0x080008B2
-  0x080008A8:  6814         LDR        R4, [R2]
-  0x080008AA:  1AE4         SUBS       R4, R4, R3
-  0x080008AC:  42AC         CMP        R4, R5
-  0x080008AE:  D3F8         BCC        .L4                      ; 0x080008A2
-
    .L5:
-  0x080008B0:  B672         CPSID      i
-
    .L6:
-  0x080008B2:  680A         LDR        R2, [R1]
-  0x080008B4:  F422 527C    BIC        R2, R2, #0x3F00
-  0x080008B8:  600A         STR        R2, [R1]
-  0x080008BA:  6E0A         LDR        R2, [R1, #96]
-  0x080008BC:  F442 7280    ORR        R2, R2, #0x0100
-  0x080008C0:  660A         STR        R2, [R1, #96]
-  0x080008C2:  6E0A         LDR        R2, [R1, #96]
-  0x080008C4:  F442 4200    ORR        R2, R2, #0x8000
-  0x080008C8:  660A         STR        R2, [R1, #96]
-
    .L7:
-  0x080008CA:  2102         MOVS       R1, #2
-  0x080008CC:  7771         STRB       R1, [R6, #29]
-  0x080008CE:  68C1         LDR        R1, [R0, #12]
-  0x080008D0:  06C9         LSLS       R1, R1, #27
-  0x080008D2:  D461         BMI        .L14                     ; 0x08000998
-  0x080008D4:  21CA         MOVS       R1, #202
-  0x080008D6:  6241         STR        R1, [R0, #36]
-  0x080008D8:  2153         MOVS       R1, #83
-  0x080008DA:  6241         STR        R1, [R0, #36]
-  0x080008DC:  68C1         LDR        R1, [R0, #12]
-  0x080008DE:  0649         LSLS       R1, R1, #25
-  0x080008E0:  D413         BMI        .L9                      ; 0x0800090A
-  0x080008E2:  F04F 31FF    MOV.W      R1, #0xFFFFFFFF
-  0x080008E6:  60C1         STR        R1, [R0, #12]
-  0x080008E8:  F240 0124    MOVW       R1, #36                  ; 0x30000024 = uwTick
-  0x080008EC:  F2C3 0100    MOVT       R1, #0x3000              ; 0x30000024 = uwTick
-  0x080008F0:  680A         LDR        R2, [R1]
-
    .L8:
-  0x080008F2:  68C3         LDR        R3, [R0, #12]
-  0x080008F4:  065B         LSLS       R3, R3, #25
-  0x080008F6:  D408         BMI        .L9                      ; 0x0800090A
-  0x080008F8:  680B         LDR        R3, [R1]
-  0x080008FA:  1A9B         SUBS       R3, R3, R2
-  0x080008FC:  F5B3 7F7A    CMP.W      R3, #0x03E8
-  0x08000900:  D9F7         BLS        .L8                      ; 0x080008F2
-  0x08000902:  2103         MOVS       R1, #3
-  0x08000904:  7771         STRB       R1, [R6, #29]
-  0x08000906:  68C0         LDR        R0, [R0, #12]
-  0x08000908:  E02E         B          .L11                     ; 0x08000968
-
    .L9:
-  0x0800090A:  6881         LDR        R1, [R0, #8]
-  0x0800090C:  F244 0508    MOVW       R5, #0x4008
-  0x08000910:  F421 01E0    BIC        R1, R1, #0x700000
-  0x08000914:  F6C5 0500    MOVT       R5, #0x5800
-  0x08000918:  F021 0140    BIC        R1, R1, #64
-  0x0800091C:  6081         STR        R1, [R0, #8]
-  0x0800091E:  E896 001E    LDM.W      R6, {R1-R4}
-  0x08000922:  4321         ORRS       R1, R4
-  0x08000924:  6974         LDR        R4, [R6, #20]
-  0x08000926:  4321         ORRS       R1, R4
-  0x08000928:  6884         LDR        R4, [R0, #8]
-  0x0800092A:  4321         ORRS       R1, R4
-  0x0800092C:  6081         STR        R1, [R0, #8]
-  0x0800092E:  EA43 4102    ORR.W      R1, R3, R2, LSL #16
-  0x08000932:  6101         STR        R1, [R0, #16]
-  0x08000934:  6868         LDR        R0, [R5, #4]
-  0x08000936:  F020 0080    BIC        R0, R0, #128
-  0x0800093A:  6068         STR        R0, [R5, #4]
-  0x0800093C:  6828         LDR        R0, [R5]
-  0x0800093E:  0680         LSLS       R0, R0, #26
-  0x08000940:  D405         BMI        .L10                     ; 0x0800094E
-  0x08000942:  F000 F82D    BL         HAL_RTC_WaitForSynchro   ; 0x080009A0
-  0x08000946:  B1C8         CBZ        R0, .L13                 ; 0x0800097C
-  0x08000948:  2003         MOVS       R0, #3
-  0x0800094A:  7770         STRB       R0, [R6, #29]
-  0x0800094C:  E00C         B          .L11                     ; 0x08000968
-
    .L10:
-  0x0800094E:  6828         LDR        R0, [R5]
-  0x08000950:  F020 0020    BIC        R0, R0, #32
-  0x08000954:  6028         STR        R0, [R5]
-  0x08000956:  F000 F823    BL         HAL_RTC_WaitForSynchro   ; 0x080009A0
-  0x0800095A:  B158         CBZ        R0, .L12                 ; 0x08000974
-  0x0800095C:  2003         MOVS       R0, #3
-  0x0800095E:  7770         STRB       R0, [R6, #29]
-  0x08000960:  6828         LDR        R0, [R5]
-  0x08000962:  F040 0020    ORR        R0, R0, #32
-  0x08000966:  6028         STR        R0, [R5]
-
    .L11:
-  0x08000968:  F856 0C04    LDR        R0, [R6, #-4]
-  0x0800096C:  21FF         MOVS       R1, #255
-  0x0800096E:  6241         STR        R1, [R0, #36]
-  0x08000970:  2003         MOVS       R0, #3
-  0x08000972:  BD70         POP        {R4-R6, PC}
-
    .L12:
-  0x08000974:  6828         LDR        R0, [R5]
-  0x08000976:  F040 0020    ORR        R0, R0, #32
-  0x0800097A:  6028         STR        R0, [R5]
-
    .L13:
-  0x0800097C:  F856 0C04    LDR        R0, [R6, #-4]
-  0x08000980:  6931         LDR        R1, [R6, #16]
-  0x08000982:  69B2         LDR        R2, [R6, #24]
-  0x08000984:  6CC3         LDR        R3, [R0, #76]
-  0x08000986:  4311         ORRS       R1, R2
-  0x08000988:  F023 0303    BIC        R3, R3, #3
-  0x0800098C:  64C3         STR        R3, [R0, #76]
-  0x0800098E:  6CC2         LDR        R2, [R0, #76]
-  0x08000990:  4311         ORRS       R1, R2
-  0x08000992:  64C1         STR        R1, [R0, #76]
-  0x08000994:  21FF         MOVS       R1, #255
-  0x08000996:  6241         STR        R1, [R0, #36]
-
    .L14:
-  0x08000998:  2001         MOVS       R0, #1
-  0x0800099A:  7770         STRB       R0, [R6, #29]
-  0x0800099C:  2000         MOVS       R0, #0
-  0x0800099E:  BD70         POP        {R4-R6, PC}
+  0x08001AA2:  4620         MOV        R0, R4
+  0x08001AA4:  BD10         POP        {R4, PC}

    Section .text.HAL_RTC_WaitForSynchro from charger_lto.o, size=54, align=2

    -
    HAL_RTC_WaitForSynchro:
-  0x080009A0:  F240 0000    MOVW       R0, #0                   ; 0x30000000 = hrtc
-  0x080009A4:  F64F 715F    MOVW       R1, #0xFF5F
-  0x080009A8:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000000 = hrtc
-  0x080009AC:  F2C0 0103    MOVT       R1, #3
-  0x080009B0:  6800         LDR        R0, [R0]
-  0x080009B2:  60C1         STR        R1, [R0, #12]
-  0x080009B4:  F240 0124    MOVW       R1, #36                  ; 0x30000024 = uwTick
-  0x080009B8:  F2C3 0100    MOVT       R1, #0x3000              ; 0x30000024 = uwTick
-  0x080009BC:  680A         LDR        R2, [R1]
+
    HAL_RTC_WaitForSynchro:
+  0x08001AA6:  F240 1000    MOVW       R0, #0x0100              ; 0x30000100 = hrtc
+  0x08001AAA:  F64F 715F    MOVW       R1, #0xFF5F
+  0x08001AAE:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000100 = hrtc
+  0x08001AB2:  F2C0 0103    MOVT       R1, #3
+  0x08001AB6:  6800         LDR        R0, [R0]
+  0x08001AB8:  60C1         STR        R1, [R0, #12]
+  0x08001ABA:  F240 1124    MOVW       R1, #0x0124              ; 0x30000124 = uwTick
+  0x08001ABE:  F2C3 0100    MOVT       R1, #0x3000              ; 0x30000124 = uwTick
+  0x08001AC2:  680A         LDR        R2, [R1]
 
    .L1:
-  0x080009BE:  68C3         LDR        R3, [R0, #12]
-  0x080009C0:  069B         LSLS       R3, R3, #26
-  0x080009C2:  D406         BMI        .L2                      ; 0x080009D2
-  0x080009C4:  680B         LDR        R3, [R1]
-  0x080009C6:  1A9B         SUBS       R3, R3, R2
-  0x080009C8:  F5B3 7F7A    CMP.W      R3, #0x03E8
-  0x080009CC:  D9F7         BLS        .L1                      ; 0x080009BE
-  0x080009CE:  2003         MOVS       R0, #3
-  0x080009D0:  4770         BX         LR
+  0x08001AC4:  68C3         LDR        R3, [R0, #12]
+  0x08001AC6:  069B         LSLS       R3, R3, #26
+  0x08001AC8:  D406         BMI        .L2                      ; 0x08001AD8
+  0x08001ACA:  680B         LDR        R3, [R1]
+  0x08001ACC:  1A9B         SUBS       R3, R3, R2
+  0x08001ACE:  F5B3 7F7A    CMP.W      R3, #0x03E8
+  0x08001AD2:  D9F7         BLS        .L1                      ; 0x08001AC4
+  0x08001AD4:  2003         MOVS       R0, #3
+  0x08001AD6:  4770         BX         LR
 
    .L2:
-  0x080009D2:  2000         MOVS       R0, #0
-  0x080009D4:  4770         BX         LR
-
    -

    Section .text.main from charger_lto.o, size=304, align=2

    -
    -
    main:
-  0x080009D6:  F64E 5014    MOVW       R0, #0xED14
-  0x080009DA:  F3BF 8F5F    DMB        SY
-  0x080009DE:  F2CE 0000    MOVT       R0, #0xE000
-  0x080009E2:  6901         LDR        R1, [R0, #16]
-  0x080009E4:  F421 3180    BIC        R1, R1, #0x010000
-  0x080009E8:  6101         STR        R1, [R0, #16]
-  0x080009EA:  2100         MOVS       R1, #0
-  0x080009EC:  F8C0 1080    STR.W      R1, [R0, #128]
-  0x080009F0:  F8C0 1084    STR.W      R1, [R0, #132]
-  0x080009F4:  F8D0 208C    LDR.W      R2, [R0, #140]
-  0x080009F8:  F022 0201    BIC        R2, R2, #1
-  0x080009FC:  F8C0 208C    STR.W      R2, [R0, #140]
-  0x08000A00:  F248 723F    MOVW       R2, #0x873F
-  0x08000A04:  F8C0 1088    STR.W      R1, [R0, #136]
-  0x08000A08:  F2C1 0204    MOVT       R2, #0x1004
-  0x08000A0C:  F8C0 208C    STR.W      R2, [R0, #140]
-  0x08000A10:  2205         MOVS       R2, #5
-  0x08000A12:  F8C0 2080    STR.W      R2, [R0, #128]
-  0x08000A16:  6902         LDR        R2, [R0, #16]
-  0x08000A18:  F442 3280    ORR        R2, R2, #0x010000
-  0x08000A1C:  6102         STR        R2, [R0, #16]
-  0x08000A1E:  F3BF 8F4F    DSB        SY
-  0x08000A22:  F3BF 8F6F    ISB        SY
-  0x08000A26:  6802         LDR        R2, [R0]
-  0x08000A28:  0392         LSLS       R2, R2, #14
-  0x08000A2A:  D411         BMI        .L1                      ; 0x08000A50
-  0x08000A2C:  F3BF 8F4F    DSB        SY
-  0x08000A30:  F3BF 8F6F    ISB        SY
-  0x08000A34:  F8C0 123C    STR.W      R1, [R0, #0x023C]
-  0x08000A38:  F3BF 8F4F    DSB        SY
-  0x08000A3C:  F3BF 8F6F    ISB        SY
-  0x08000A40:  6801         LDR        R1, [R0]
-  0x08000A42:  F441 3100    ORR        R1, R1, #0x020000
-  0x08000A46:  6001         STR        R1, [R0]
-  0x08000A48:  F3BF 8F4F    DSB        SY
-  0x08000A4C:  F3BF 8F6F    ISB        SY
-
    .L1:
-  0x08000A50:  B082         SUB        SP, SP, #8
-  0x08000A52:  6801         LDR        R1, [R0]
-  0x08000A54:  03C9         LSLS       R1, R1, #15
-  0x08000A56:  D426         BMI        .L4                      ; 0x08000AA6
-  0x08000A58:  2100         MOVS       R1, #0
-  0x08000A5A:  6701         STR        R1, [R0, #112]
-  0x08000A5C:  F3BF 8F4F    DSB        SY
-  0x08000A60:  F643 7EE0    MOVW       LR, #0x3FE0
-  0x08000A64:  6EC2         LDR        R2, [R0, #108]
-  0x08000A66:  EA4F 0CD2    LSR.W      R12, R2, #3
-  0x08000A6A:  F3C2 314E    UBFX       R1, R2, #13, #15
-  0x08000A6E:  F3C2 03C9    UBFX       R3, R2, #3, #10
-  0x08000A72:  3301         ADDS       R3, #1
-  0x08000A74:  014A         LSLS       R2, R1, #5
-
    .L2:
-  0x08000A76:  EA02 040E    AND.W      R4, R2, LR
-  0x08000A7A:  461D         MOV        R5, R3
-  0x08000A7C:  EB04 748C    ADD.W      R4, R4, R12, LSL #30
-
    .L3:
-  0x08000A80:  3D01         SUBS       R5, #1
-  0x08000A82:  F8C0 424C    STR.W      R4, [R0, #0x024C]
-  0x08000A86:  F104 4440    ADD.W      R4, R4, #0xC0000000
-  0x08000A8A:  D1F9         BNE        .L3                      ; 0x08000A80
-  0x08000A8C:  3A20         SUBS       R2, #32
-  0x08000A8E:  3901         SUBS       R1, #1
-  0x08000A90:  D2F1         BCS        .L2                      ; 0x08000A76
-  0x08000A92:  F3BF 8F4F    DSB        SY
-  0x08000A96:  6801         LDR        R1, [R0]
-  0x08000A98:  F441 3180    ORR        R1, R1, #0x010000
-  0x08000A9C:  6001         STR        R1, [R0]
-  0x08000A9E:  F3BF 8F4F    DSB        SY
-  0x08000AA2:  F3BF 8F6F    ISB        SY
-
    .L4:
-  0x08000AA6:  F7FF FE83    BL         HAL_Init                 ; 0x080007B0
-  0x08000AAA:  F7FF FC9F    BL         SystemClock_Config()     ; 0x080003EC
-  0x08000AAE:  F244 40E0    MOVW       R0, #0x44E0
-  0x08000AB2:  F6C5 0002    MOVT       R0, #0x5802
-  0x08000AB6:  6801         LDR        R1, [R0]
-  0x08000AB8:  F041 0104    ORR        R1, R1, #4
-  0x08000ABC:  6001         STR        R1, [R0]
-  0x08000ABE:  6801         LDR        R1, [R0]
-  0x08000AC0:  F001 0104    AND        R1, R1, #4
-  0x08000AC4:  9101         STR        R1, [SP, #4]
-  0x08000AC6:  9901         LDR        R1, [SP, #4]
-  0x08000AC8:  6801         LDR        R1, [R0]
-  0x08000ACA:  F041 0180    ORR        R1, R1, #128
-  0x08000ACE:  6001         STR        R1, [R0]
-  0x08000AD0:  6800         LDR        R0, [R0]
-  0x08000AD2:  F244 0100    MOVW       R1, #0x4000
-  0x08000AD6:  F000 0080    AND        R0, R0, #128
-  0x08000ADA:  9000         STR        R0, [SP, #0]
-  0x08000ADC:  F240 0000    MOVW       R0, #0                   ; 0x30000000 = hrtc
-  0x08000AE0:  9A00         LDR        R2, [SP, #0]
-  0x08000AE2:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000000 = hrtc
-  0x08000AE6:  F6C5 0100    MOVT       R1, #0x5800
-  0x08000AEA:  227F         MOVS       R2, #127
-  0x08000AEC:  6001         STR        R1, [R0]
-  0x08000AEE:  2100         MOVS       R1, #0
-  0x08000AF0:  E9C0 1201    STRD       R1, R2, [R0, #4]
-  0x08000AF4:  22FF         MOVS       R2, #255
-  0x08000AF6:  61C1         STR        R1, [R0, #28]
-  0x08000AF8:  E9C0 2103    STRD       R2, R1, [R0, #12]
-  0x08000AFC:  E9C0 1105    STRD       R1, R1, [R0, #20]
-  0x08000B00:  F7FF FE8F    BL         HAL_RTC_Init             ; 0x08000822
-  0x08000B04:  B672         CPSID      i
+  0x08001AD8:  2000         MOVS       R0, #0
+  0x08001ADA:  4770         BX         LR

    Section .text.SysTick_Handler from charger_lto.o, size=16, align=2

    -
    SysTick_Handler:
-  0x08000B06:  F240 0024    MOVW       R0, #36                  ; 0x30000024 = uwTick
-  0x08000B0A:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000024 = uwTick
-  0x08000B0E:  6801         LDR        R1, [R0]
-  0x08000B10:  3101         ADDS       R1, #1
-  0x08000B12:  6001         STR        R1, [R0]
-  0x08000B14:  4770         BX         LR
+
    SysTick_Handler:
+  0x08001ADC:  F240 1024    MOVW       R0, #0x0124              ; 0x30000124 = uwTick
+  0x08001AE0:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000124 = uwTick
+  0x08001AE4:  6801         LDR        R1, [R0]
+  0x08001AE6:  3101         ADDS       R1, #1
+  0x08001AE8:  6001         STR        R1, [R0]
+  0x08001AEA:  4770         BX         LR
    -

    Section .text.HAL_InitTick from charger_lto.o, size=128, align=2

    +

    Section .text.DMA1_Stream0_IRQHandler from charger_lto.o, size=1012, align=2

    -
    HAL_InitTick:
-  0x08000B16:  F240 012C    MOVW       R1, #44                  ; 0x3000002C = SystemCoreClock
-  0x08000B1A:  F644 52D3    MOVW       R2, #0x4DD3
-  0x08000B1E:  F2C3 0100    MOVT       R1, #0x3000              ; 0x3000002C = SystemCoreClock
-  0x08000B22:  F2C1 0262    MOVT       R2, #0x1062
-  0x08000B26:  6809         LDR        R1, [R1]
-  0x08000B28:  FBA1 1202    UMULL      R1, R2, R1, R2
-  0x08000B2C:  F04F 31FF    MOV.W      R1, #0xFFFFFFFF
-  0x08000B30:  EB01 1292    ADD.W      R2, R1, R2, LSR #6
-  0x08000B34:  0E11         LSRS       R1, R2, #24
-  0x08000B36:  D001         BEQ        .L1                      ; 0x08000B3C
-  0x08000B38:  2001         MOVS       R0, #1
-  0x08000B3A:  4770         BX         LR
+
    DMA1_Stream0_IRQHandler:
+  0x08001AEC:  E92D 47F0    PUSH.W     {R4-R10, LR}
+  0x08001AF0:  B082         SUB        SP, SP, #8
+  0x08001AF2:  2000         MOVS       R0, #0
+  0x08001AF4:  9001         STR        R0, [SP, #4]
+  0x08001AF6:  F240 102C    MOVW       R0, #0x012C              ; 0x3000012C = SystemCoreClock
+  0x08001AFA:  F240 0488    MOVW       R4, #136                 ; 0x30000088 = hdma_spi4_tx
+  0x08001AFE:  F2C3 0000    MOVT       R0, #0x3000              ; 0x3000012C = SystemCoreClock
+  0x08001B02:  F2C3 0400    MOVT       R4, #0x3000              ; 0x30000088 = hdma_spi4_tx
+  0x08001B06:  F248 12B5    MOVW       R2, #0x81B5
+  0x08001B0A:  F240 486F    MOVW       R8, #0x046F
+  0x08001B0E:  6801         LDR        R1, [R0]
+  0x08001B10:  F6C1 324E    MOVT       R2, #0x1B4E
+  0x08001B14:  6DA5         LDR        R5, [R4, #88]
+  0x08001B16:  F2C4 0802    MOVT       R8, #0x4002
+  0x08001B1A:  6820         LDR        R0, [R4]
+  0x08001B1C:  FBA1 1A02    UMULL      R1, R10, R1, R2
+  0x08001B20:  4540         CMP        R0, R8
+  0x08001B22:  682F         LDR        R7, [R5]
+  0x08001B24:  6829         LDR        R1, [R5]
+  0x08001B26:  DC08         BGT        .L1                      ; 0x08001B3A
+  0x08001B28:  F5A8 7174    SUB.W      R1, R8, #0x03D0
+  0x08001B2C:  4288         CMP        R0, R1
+  0x08001B2E:  DC11         BGT        .L2                      ; 0x08001B54
+  0x08001B30:  3948         SUBS       R1, #72
+  0x08001B32:  4288         CMP        R0, R1
+  0x08001B34:  DC25         BGT        .L4                      ; 0x08001B82
+  0x08001B36:  3947         SUBS       R1, #71
+  0x08001B38:  E024         B          .L5                      ; 0x08001B84
 
    .L1:
-  0x08000B3C:  F24E 0310    MOVW       R3, #0xE010
-  0x08000B40:  280F         CMP        R0, #15
-  0x08000B42:  F2CE 0300    MOVT       R3, #0xE000
-  0x08000B46:  F04F 0001    MOV.W      R0, #1
-  0x08000B4A:  F603 4CFC    ADDW       R12, R3, #0x0CFC
-  0x08000B4E:  605A         STR        R2, [R3, #4]
-  0x08000B50:  F04F 02F0    MOV.W      R2, #240
-  0x08000B54:  F88C 2017    STRB.W     R2, [R12, #23]
-  0x08000B58:  F04F 0207    MOV.W      R2, #7
-  0x08000B5C:  6099         STR        R1, [R3, #8]
-  0x08000B5E:  601A         STR        R2, [R3]
-  0x08000B60:  BF88         IT         HI
-  0x08000B62:  4770         BXHI       LR
-  0x08000B64:  F8DC 2000    LDR.W      R2, [R12]
-  0x08000B68:  43C9         MVNS       R1, R1
-  0x08000B6A:  F3C2 2202    UBFX       R2, R2, #8, #3
-  0x08000B6E:  F082 0307    EOR        R3, R2, #7
-  0x08000B72:  2B04         CMP        R3, #4
-  0x08000B74:  BF28         IT         CS
-  0x08000B76:  2304         MOVCS      R3, #4
-  0x08000B78:  4099         LSLS       R1, R3
-  0x08000B7A:  43C9         MVNS       R1, R1
-  0x08000B7C:  3A03         SUBS       R2, #3
-  0x08000B7E:  BF28         IT         CS
-  0x08000B80:  4091         LSLCS      R1, R2
-  0x08000B82:  0109         LSLS       R1, R1, #4
-  0x08000B84:  F88C 1017    STRB.W     R1, [R12, #23]
-  0x08000B88:  F240 0128    MOVW       R1, #40                  ; 0x30000028 = uwTickPrio
-  0x08000B8C:  F2C3 0100    MOVT       R1, #0x3000              ; 0x30000028 = uwTickPrio
-  0x08000B90:  7008         STRB       R0, [R1]
-  0x08000B92:  2000         MOVS       R0, #0
-  0x08000B94:  4770         BX         LR
+  0x08001B3A:  F245 422F    MOVW       R2, #0x542F
+  0x08001B3E:  F6C5 0202    MOVT       R2, #0x5802
+  0x08001B42:  4290         CMP        R0, R2
+  0x08001B44:  DC14         BGT        .L3                      ; 0x08001B70
+  0x08001B46:  F108 0248    ADD.W      R2, R8, #72
+  0x08001B4A:  4290         CMP        R0, R2
+  0x08001B4C:  DC3B         BGT        .L9                      ; 0x08001BC6
+  0x08001B4E:  F1A2 0147    SUB.W      R1, R2, #71
+  0x08001B52:  E017         B          .L5                      ; 0x08001B84
+
    .L2:
+  0x08001B54:  F501 7162    ADD.W      R1, R1, #0x0388
+  0x08001B58:  4288         CMP        R0, R1
+  0x08001B5A:  DC12         BGT        .L4                      ; 0x08001B82
+  0x08001B5C:  F2A1 3187    SUBW       R1, R1, #0x0387
+  0x08001B60:  4288         CMP        R0, R1
+  0x08001B62:  D018         BEQ        .L7                      ; 0x08001B96
+  0x08001B64:  3118         ADDS       R1, #24
+  0x08001B66:  4288         CMP        R0, R1
+  0x08001B68:  D015         BEQ        .L7                      ; 0x08001B96
+  0x08001B6A:  F501 7156    ADD.W      R1, R1, #0x0358
+  0x08001B6E:  E00F         B          .L6                      ; 0x08001B90
+
    .L3:
+  0x08001B70:  323C         ADDS       R2, #60
+  0x08001B72:  4290         CMP        R0, R2
+  0x08001B74:  BFD4         ITE        LE
+  0x08001B76:  3A3B         SUBLE      R2, #59
+  0x08001B78:  3201         ADDGT      R2, #1
+  0x08001B7A:  4290         CMP        R0, R2
+  0x08001B7C:  D030         BEQ        .L11                     ; 0x08001BE0
+  0x08001B7E:  3214         ADDS       R2, #20
+  0x08001B80:  E028         B          .L10                     ; 0x08001BD4
+
    .L4:
+  0x08001B82:  3101         ADDS       R1, #1
+
    .L5:
+  0x08001B84:  4288         CMP        R0, R1
+  0x08001B86:  D006         BEQ        .L7                      ; 0x08001B96
+  0x08001B88:  3118         ADDS       R1, #24
+  0x08001B8A:  4288         CMP        R0, R1
+  0x08001B8C:  D003         BEQ        .L7                      ; 0x08001B96
+  0x08001B8E:  3118         ADDS       R1, #24
+
    .L6:
+  0x08001B90:  4288         CMP        R0, R1
+  0x08001B92:  F040 8198    BNE.W      .L55                     ; 0x08001EC6
+
    .L7:
+  0x08001B96:  6DE1         LDR        R1, [R4, #92]
+  0x08001B98:  2208         MOVS       R2, #8
+  0x08001B9A:  F001 011F    AND        R1, R1, #31
+  0x08001B9E:  F1A8 0960    SUB.W      R9, R8, #96
+  0x08001BA2:  408A         LSLS       R2, R1
+  0x08001BA4:  423A         TST        R2, R7
+  0x08001BA6:  D067         BEQ        .L16                     ; 0x08001C78
+  0x08001BA8:  2304         MOVS       R3, #4
+  0x08001BAA:  4548         CMP        R0, R9
+  0x08001BAC:  DC06         BGT        .L8                      ; 0x08001BBC
+  0x08001BAE:  F5A8 6680    SUB.W      R6, R8, #0x0400
+  0x08001BB2:  42B0         CMP        R0, R6
+  0x08001BB4:  BFD4         ITE        LE
+  0x08001BB6:  3E30         SUBLE      R6, #48
+  0x08001BB8:  3630         ADDGT      R6, #48
+  0x08001BBA:  E047         B          .L14                     ; 0x08001C4C
+
    .L8:
+  0x08001BBC:  4540         CMP        R0, R8
+  0x08001BBE:  DC43         BGT        .L13                     ; 0x08001C48
+  0x08001BC0:  F1A8 0630    SUB.W      R6, R8, #48
+  0x08001BC4:  E042         B          .L14                     ; 0x08001C4C
+
    .L9:
+  0x08001BC6:  3201         ADDS       R2, #1
+  0x08001BC8:  4290         CMP        R0, R2
+  0x08001BCA:  D0E4         BEQ        .L7                      ; 0x08001B96
+  0x08001BCC:  F245 4208    MOVW       R2, #0x5408
+  0x08001BD0:  F6C5 0202    MOVT       R2, #0x5802
+
    .L10:
+  0x08001BD4:  4290         CMP        R0, R2
+  0x08001BD6:  D003         BEQ        .L11                     ; 0x08001BE0
+  0x08001BD8:  3214         ADDS       R2, #20
+  0x08001BDA:  4290         CMP        R0, R2
+  0x08001BDC:  F040 8173    BNE.W      .L55                     ; 0x08001EC6
+
    .L11:
+  0x08001BE0:  6802         LDR        R2, [R0]
+  0x08001BE2:  6DE3         LDR        R3, [R4, #92]
+  0x08001BE4:  F003 031F    AND        R3, R3, #31
+  0x08001BE8:  2704         MOVS       R7, #4
+  0x08001BEA:  409F         LSLS       R7, R3
+  0x08001BEC:  420F         TST        R7, R1
+  0x08001BEE:  BF18         IT         NE
+  0x08001BF0:  F012 0604    ANDSNE     R6, R2, #4
+  0x08001BF4:  D11C         BNE        .L12                     ; 0x08001C30
+  0x08001BF6:  2702         MOVS       R7, #2
+  0x08001BF8:  409F         LSLS       R7, R3
+  0x08001BFA:  420F         TST        R7, R1
+  0x08001BFC:  BF18         IT         NE
+  0x08001BFE:  F012 0602    ANDSNE     R6, R2, #2
+  0x08001C02:  F040 80B7    BNE.W      .L33                     ; 0x08001D74
+  0x08001C06:  40D9         LSRS       R1, R3
+  0x08001C08:  0709         LSLS       R1, R1, #28
+  0x08001C0A:  F140 815C    BPL.W      .L55                     ; 0x08001EC6
+  0x08001C0E:  F012 0108    ANDS       R1, R2, #8
+  0x08001C12:  F000 8158    BEQ.W      .L55                     ; 0x08001EC6
+  0x08001C16:  6801         LDR        R1, [R0]
+  0x08001C18:  F021 010E    BIC        R1, R1, #14
+  0x08001C1C:  6001         STR        R1, [R0]
+  0x08001C1E:  2001         MOVS       R0, #1
+  0x08001C20:  FA00 F103    LSL.W      R1, R0, R3
+  0x08001C24:  6069         STR        R1, [R5, #4]
+  0x08001C26:  6560         STR        R0, [R4, #84]
+  0x08001C28:  F884 0035    STRB.W     R0, [R4, #53]
+  0x08001C2C:  6CE1         LDR        R1, [R4, #76]
+  0x08001C2E:  E100         B          .L44                     ; 0x08001E32
+
    .L12:
+  0x08001C30:  0411         LSLS       R1, R2, #16
+  0x08001C32:  606F         STR        R7, [R5, #4]
+  0x08001C34:  F100 80B0    BMI.W      .L34                     ; 0x08001D98
+  0x08001C38:  0691         LSLS       R1, R2, #26
+  0x08001C3A:  F100 80B1    BMI.W      .L35                     ; 0x08001DA0
+  0x08001C3E:  6801         LDR        R1, [R0]
+  0x08001C40:  F021 0104    BIC        R1, R1, #4
+  0x08001C44:  6001         STR        R1, [R0]
+  0x08001C46:  E0AB         B          .L35                     ; 0x08001DA0
+
    .L13:
+  0x08001C48:  F108 0630    ADD.W      R6, R8, #48
+
    .L14:
+  0x08001C4C:  42B0         CMP        R0, R6
+  0x08001C4E:  BFCC         ITE        GT
+  0x08001C50:  3601         ADDGT      R6, #1
+  0x08001C52:  3E2F         SUBLE      R6, #47
+  0x08001C54:  42B0         CMP        R0, R6
+  0x08001C56:  D003         BEQ        .L15                     ; 0x08001C60
+  0x08001C58:  3618         ADDS       R6, #24
+  0x08001C5A:  42B0         CMP        R0, R6
+  0x08001C5C:  BF18         IT         NE
+  0x08001C5E:  2308         MOVNE      R3, #8
+
    .L15:
+  0x08001C60:  6806         LDR        R6, [R0]
+  0x08001C62:  421E         TST        R6, R3
+  0x08001C64:  D008         BEQ        .L16                     ; 0x08001C78
+  0x08001C66:  6803         LDR        R3, [R0]
+  0x08001C68:  F023 0304    BIC        R3, R3, #4
+  0x08001C6C:  6003         STR        R3, [R0]
+  0x08001C6E:  60AA         STR        R2, [R5, #8]
+  0x08001C70:  6D62         LDR        R2, [R4, #84]
+  0x08001C72:  F042 0201    ORR        R2, R2, #1
+  0x08001C76:  6562         STR        R2, [R4, #84]
+
    .L16:
+  0x08001C78:  2201         MOVS       R2, #1
+  0x08001C7A:  408A         LSLS       R2, R1
+  0x08001C7C:  423A         TST        R2, R7
+  0x08001C7E:  D021         BEQ        .L21                     ; 0x08001CC4
+  0x08001C80:  4548         CMP        R0, R9
+  0x08001C82:  DC06         BGT        .L17                     ; 0x08001C92
+  0x08001C84:  F5A8 6380    SUB.W      R3, R8, #0x0400
+  0x08001C88:  4298         CMP        R0, R3
+  0x08001C8A:  BFD4         ITE        LE
+  0x08001C8C:  3B30         SUBLE      R3, #48
+  0x08001C8E:  3330         ADDGT      R3, #48
+  0x08001C90:  E006         B          .L19                     ; 0x08001CA0
+
    .L17:
+  0x08001C92:  4540         CMP        R0, R8
+  0x08001C94:  DC02         BGT        .L18                     ; 0x08001C9C
+  0x08001C96:  F1A8 0330    SUB.W      R3, R8, #48
+  0x08001C9A:  E001         B          .L19                     ; 0x08001CA0
+
    .L18:
+  0x08001C9C:  F108 0330    ADD.W      R3, R8, #48
+
    .L19:
+  0x08001CA0:  4298         CMP        R0, R3
+  0x08001CA2:  BFD4         ITE        LE
+  0x08001CA4:  3B2F         SUBLE      R3, #47
+  0x08001CA6:  3301         ADDGT      R3, #1
+  0x08001CA8:  4298         CMP        R0, R3
+  0x08001CAA:  D003         BEQ        .L20                     ; 0x08001CB4
+  0x08001CAC:  3318         ADDS       R3, #24
+  0x08001CAE:  4298         CMP        R0, R3
+  0x08001CB0:  F040 8112    BNE.W      .L58                     ; 0x08001ED8
+
    .L20:
+  0x08001CB4:  6943         LDR        R3, [R0, #20]
+  0x08001CB6:  061B         LSLS       R3, R3, #24
+  0x08001CB8:  D504         BPL        .L21                     ; 0x08001CC4
+  0x08001CBA:  60AA         STR        R2, [R5, #8]
+  0x08001CBC:  6D62         LDR        R2, [R4, #84]
+  0x08001CBE:  F042 0202    ORR        R2, R2, #2
+  0x08001CC2:  6562         STR        R2, [R4, #84]
+
    .L21:
+  0x08001CC4:  2204         MOVS       R2, #4
+  0x08001CC6:  408A         LSLS       R2, R1
+  0x08001CC8:  423A         TST        R2, R7
+  0x08001CCA:  D021         BEQ        .L26                     ; 0x08001D10
+  0x08001CCC:  4548         CMP        R0, R9
+  0x08001CCE:  DC06         BGT        .L22                     ; 0x08001CDE
+  0x08001CD0:  F5A8 6380    SUB.W      R3, R8, #0x0400
+  0x08001CD4:  4298         CMP        R0, R3
+  0x08001CD6:  BFD4         ITE        LE
+  0x08001CD8:  3B30         SUBLE      R3, #48
+  0x08001CDA:  3330         ADDGT      R3, #48
+  0x08001CDC:  E006         B          .L24                     ; 0x08001CEC
+
    .L22:
+  0x08001CDE:  4540         CMP        R0, R8
+  0x08001CE0:  DC02         BGT        .L23                     ; 0x08001CE8
+  0x08001CE2:  F1A8 0330    SUB.W      R3, R8, #48
+  0x08001CE6:  E001         B          .L24                     ; 0x08001CEC
+
    .L23:
+  0x08001CE8:  F108 0330    ADD.W      R3, R8, #48
+
    .L24:
+  0x08001CEC:  4298         CMP        R0, R3
+  0x08001CEE:  BFD4         ITE        LE
+  0x08001CF0:  3B2F         SUBLE      R3, #47
+  0x08001CF2:  3301         ADDGT      R3, #1
+  0x08001CF4:  4298         CMP        R0, R3
+  0x08001CF6:  D003         BEQ        .L25                     ; 0x08001D00
+  0x08001CF8:  3318         ADDS       R3, #24
+  0x08001CFA:  4298         CMP        R0, R3
+  0x08001CFC:  F040 80EE    BNE.W      .L59                     ; 0x08001EDC
+
    .L25:
+  0x08001D00:  6803         LDR        R3, [R0]
+  0x08001D02:  079B         LSLS       R3, R3, #30
+  0x08001D04:  D504         BPL        .L26                     ; 0x08001D10
+  0x08001D06:  60AA         STR        R2, [R5, #8]
+  0x08001D08:  6D62         LDR        R2, [R4, #84]
+  0x08001D0A:  F042 0204    ORR        R2, R2, #4
+  0x08001D0E:  6562         STR        R2, [R4, #84]
+
    .L26:
+  0x08001D10:  2210         MOVS       R2, #16
+  0x08001D12:  408A         LSLS       R2, R1
+  0x08001D14:  423A         TST        R2, R7
+  0x08001D16:  D04C         BEQ        .L38                     ; 0x08001DB2
+  0x08001D18:  2308         MOVS       R3, #8
+  0x08001D1A:  4548         CMP        R0, R9
+  0x08001D1C:  DC06         BGT        .L27                     ; 0x08001D2C
+  0x08001D1E:  F5A8 6680    SUB.W      R6, R8, #0x0400
+  0x08001D22:  42B0         CMP        R0, R6
+  0x08001D24:  BFD4         ITE        LE
+  0x08001D26:  3E30         SUBLE      R6, #48
+  0x08001D28:  3630         ADDGT      R6, #48
+  0x08001D2A:  E006         B          .L29                     ; 0x08001D3A
+
    .L27:
+  0x08001D2C:  4540         CMP        R0, R8
+  0x08001D2E:  DC02         BGT        .L28                     ; 0x08001D36
+  0x08001D30:  F1A8 0630    SUB.W      R6, R8, #48
+  0x08001D34:  E001         B          .L29                     ; 0x08001D3A
+
    .L28:
+  0x08001D36:  F108 0630    ADD.W      R6, R8, #48
+
    .L29:
+  0x08001D3A:  42B0         CMP        R0, R6
+  0x08001D3C:  BFCC         ITE        GT
+  0x08001D3E:  3601         ADDGT      R6, #1
+  0x08001D40:  3E2F         SUBLE      R6, #47
+  0x08001D42:  42B0         CMP        R0, R6
+  0x08001D44:  D003         BEQ        .L30                     ; 0x08001D4E
+  0x08001D46:  3618         ADDS       R6, #24
+  0x08001D48:  42B0         CMP        R0, R6
+  0x08001D4A:  BF18         IT         NE
+  0x08001D4C:  2304         MOVNE      R3, #4
+
    .L30:
+  0x08001D4E:  6806         LDR        R6, [R0]
+  0x08001D50:  421E         TST        R6, R3
+  0x08001D52:  D02E         BEQ        .L38                     ; 0x08001DB2
+  0x08001D54:  60AA         STR        R2, [R5, #8]
+  0x08001D56:  6802         LDR        R2, [R0]
+  0x08001D58:  0352         LSLS       R2, R2, #13
+  0x08001D5A:  6802         LDR        R2, [R0]
+  0x08001D5C:  D406         BMI        .L31                     ; 0x08001D6C
+  0x08001D5E:  05D2         LSLS       R2, R2, #23
+  0x08001D60:  D406         BMI        .L32                     ; 0x08001D70
+  0x08001D62:  6802         LDR        R2, [R0]
+  0x08001D64:  F022 0208    BIC        R2, R2, #8
+  0x08001D68:  6002         STR        R2, [R0]
+  0x08001D6A:  E001         B          .L32                     ; 0x08001D70
+
    .L31:
+  0x08001D6C:  0310         LSLS       R0, R2, #12
+  0x08001D6E:  D419         BMI        .L36                     ; 0x08001DA4
+
    .L32:
+  0x08001D70:  6C22         LDR        R2, [R4, #64]
+  0x08001D72:  E018         B          .L37                     ; 0x08001DA6
+
    .L33:
+  0x08001D74:  0411         LSLS       R1, R2, #16
+  0x08001D76:  606F         STR        R7, [R5, #4]
+  0x08001D78:  F100 80A8    BMI.W      .L56                     ; 0x08001ECC
+  0x08001D7C:  0691         LSLS       R1, R2, #26
+  0x08001D7E:  F100 80A9    BMI.W      .L57                     ; 0x08001ED4
+  0x08001D82:  6801         LDR        R1, [R0]
+  0x08001D84:  F021 010A    BIC        R1, R1, #10
+  0x08001D88:  6001         STR        R1, [R0]
+  0x08001D8A:  2001         MOVS       R0, #1
+  0x08001D8C:  F884 0035    STRB.W     R0, [R4, #53]
+  0x08001D90:  2000         MOVS       R0, #0
+  0x08001D92:  F884 0034    STRB.W     R0, [R4, #52]
+  0x08001D96:  E09D         B          .L57                     ; 0x08001ED4
+
    .L34:
+  0x08001D98:  03D0         LSLS       R0, R2, #15
+  0x08001D9A:  D401         BMI        .L35                     ; 0x08001DA0
+  0x08001D9C:  6CA1         LDR        R1, [R4, #72]
+  0x08001D9E:  E089         B          .L53                     ; 0x08001EB4
+
    .L35:
+  0x08001DA0:  6C21         LDR        R1, [R4, #64]
+  0x08001DA2:  E087         B          .L53                     ; 0x08001EB4
+
    .L36:
+  0x08001DA4:  6CA2         LDR        R2, [R4, #72]
+
    .L37:
+  0x08001DA6:  B122         CBZ        R2, .L38                 ; 0x08001DB2
+  0x08001DA8:  4620         MOV        R0, R4
+  0x08001DAA:  4790         BLX        R2
+  0x08001DAC:  6DE0         LDR        R0, [R4, #92]
+  0x08001DAE:  F000 011F    AND        R1, R0, #31
+
    .L38:
+  0x08001DB2:  2020         MOVS       R0, #32
+  0x08001DB4:  FA00 F201    LSL.W      R2, R0, R1
+  0x08001DB8:  423A         TST        R2, R7
+  0x08001DBA:  D05A         BEQ        .L49                     ; 0x08001E72
+  0x08001DBC:  6820         LDR        R0, [R4]
+  0x08001DBE:  2310         MOVS       R3, #16
+  0x08001DC0:  4548         CMP        R0, R9
+  0x08001DC2:  DC06         BGT        .L39                     ; 0x08001DD2
+  0x08001DC4:  F5A8 6780    SUB.W      R7, R8, #0x0400
+  0x08001DC8:  42B8         CMP        R0, R7
+  0x08001DCA:  BFD4         ITE        LE
+  0x08001DCC:  3F30         SUBLE      R7, #48
+  0x08001DCE:  3730         ADDGT      R7, #48
+  0x08001DD0:  E006         B          .L41                     ; 0x08001DE0
+
    .L39:
+  0x08001DD2:  4540         CMP        R0, R8
+  0x08001DD4:  DC02         BGT        .L40                     ; 0x08001DDC
+  0x08001DD6:  F1A8 0730    SUB.W      R7, R8, #48
+  0x08001DDA:  E001         B          .L41                     ; 0x08001DE0
+
    .L40:
+  0x08001DDC:  F108 0730    ADD.W      R7, R8, #48
+
    .L41:
+  0x08001DE0:  42B8         CMP        R0, R7
+  0x08001DE2:  BFCC         ITE        GT
+  0x08001DE4:  3701         ADDGT      R7, #1
+  0x08001DE6:  3F2F         SUBLE      R7, #47
+  0x08001DE8:  42B8         CMP        R0, R7
+  0x08001DEA:  D003         BEQ        .L42                     ; 0x08001DF4
+  0x08001DEC:  3718         ADDS       R7, #24
+  0x08001DEE:  42B8         CMP        R0, R7
+  0x08001DF0:  BF18         IT         NE
+  0x08001DF2:  2302         MOVNE      R3, #2
+
    .L42:
+  0x08001DF4:  6807         LDR        R7, [R0]
+  0x08001DF6:  421F         TST        R7, R3
+  0x08001DF8:  D03B         BEQ        .L49                     ; 0x08001E72
+  0x08001DFA:  60AA         STR        R2, [R5, #8]
+  0x08001DFC:  F894 2035    LDRB.W     R2, [R4, #53]
+  0x08001E00:  2A04         CMP        R2, #4
+  0x08001E02:  6802         LDR        R2, [R0]
+  0x08001E04:  D11A         BNE        .L45                     ; 0x08001E3C
+  0x08001E06:  F022 0216    BIC        R2, R2, #22
+  0x08001E0A:  6002         STR        R2, [R0]
+  0x08001E0C:  6942         LDR        R2, [R0, #20]
+  0x08001E0E:  F022 0280    BIC        R2, R2, #128
+  0x08001E12:  6142         STR        R2, [R0, #20]
+  0x08001E14:  6C22         LDR        R2, [R4, #64]
+  0x08001E16:  6CA3         LDR        R3, [R4, #72]
+  0x08001E18:  431A         ORRS       R2, R3
+  0x08001E1A:  D003         BEQ        .L43                     ; 0x08001E24
+  0x08001E1C:  6802         LDR        R2, [R0]
+  0x08001E1E:  F022 0208    BIC        R2, R2, #8
+  0x08001E22:  6002         STR        R2, [R0]
+
    .L43:
+  0x08001E24:  203F         MOVS       R0, #63
+  0x08001E26:  4088         LSLS       R0, R1
+  0x08001E28:  60A8         STR        R0, [R5, #8]
+  0x08001E2A:  2001         MOVS       R0, #1
+  0x08001E2C:  F884 0035    STRB.W     R0, [R4, #53]
+  0x08001E30:  6D21         LDR        R1, [R4, #80]
+
    .L44:
+  0x08001E32:  2000         MOVS       R0, #0
+  0x08001E34:  F884 0034    STRB.W     R0, [R4, #52]
+  0x08001E38:  BBE9         CBNZ       R1, .L54                 ; 0x08001EB6
+  0x08001E3A:  E044         B          .L55                     ; 0x08001EC6
+
    .L45:
+  0x08001E3C:  0351         LSLS       R1, R2, #13
+  0x08001E3E:  6801         LDR        R1, [R0]
+  0x08001E40:  D40C         BMI        .L46                     ; 0x08001E5C
+  0x08001E42:  05C9         LSLS       R1, R1, #23
+  0x08001E44:  D40E         BMI        .L47                     ; 0x08001E64
+  0x08001E46:  6801         LDR        R1, [R0]
+  0x08001E48:  F021 0110    BIC        R1, R1, #16
+  0x08001E4C:  6001         STR        R1, [R0]
+  0x08001E4E:  2001         MOVS       R0, #1
+  0x08001E50:  F884 0035    STRB.W     R0, [R4, #53]
+  0x08001E54:  2000         MOVS       R0, #0
+  0x08001E56:  F884 0034    STRB.W     R0, [R4, #52]
+  0x08001E5A:  E003         B          .L47                     ; 0x08001E64
+
    .L46:
+  0x08001E5C:  0308         LSLS       R0, R1, #12
+  0x08001E5E:  D401         BMI        .L47                     ; 0x08001E64
+  0x08001E60:  6C61         LDR        R1, [R4, #68]
+  0x08001E62:  E000         B          .L48                     ; 0x08001E66
+
    .L47:
+  0x08001E64:  6BE1         LDR        R1, [R4, #60]
+
    .L48:
+  0x08001E66:  B121         CBZ        R1, .L49                 ; 0x08001E72
+  0x08001E68:  F240 0088    MOVW       R0, #136                 ; 0x30000088 = hdma_spi4_tx
+  0x08001E6C:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000088 = hdma_spi4_tx
+  0x08001E70:  4788         BLX        R1
+
    .L49:
+  0x08001E72:  6D60         LDR        R0, [R4, #84]
+  0x08001E74:  B338         CBZ        R0, .L55                 ; 0x08001EC6
+  0x08001E76:  6D60         LDR        R0, [R4, #84]
+  0x08001E78:  07C0         LSLS       R0, R0, #31
+  0x08001E7A:  D01A         BEQ        .L52                     ; 0x08001EB2
+  0x08001E7C:  2004         MOVS       R0, #4
+  0x08001E7E:  F884 0035    STRB.W     R0, [R4, #53]
+  0x08001E82:  6820         LDR        R0, [R4]
+  0x08001E84:  6801         LDR        R1, [R0]
+  0x08001E86:  F021 0101    BIC        R1, R1, #1
+  0x08001E8A:  6001         STR        R1, [R0]
+
    .L50:
+  0x08001E8C:  9901         LDR        R1, [SP, #4]
+  0x08001E8E:  3101         ADDS       R1, #1
+  0x08001E90:  9101         STR        R1, [SP, #4]
+  0x08001E92:  EBB1 2F9A    CMP.W      R1, R10, LSR #10
+  0x08001E96:  D802         BHI        .L51                     ; 0x08001E9E
+  0x08001E98:  6801         LDR        R1, [R0]
+  0x08001E9A:  07C9         LSLS       R1, R1, #31
+  0x08001E9C:  D1F6         BNE        .L50                     ; 0x08001E8C
+
    .L51:
+  0x08001E9E:  6800         LDR        R0, [R0]
+  0x08001EA0:  07C0         LSLS       R0, R0, #31
+  0x08001EA2:  BF14         ITE        NE
+  0x08001EA4:  2003         MOVNE      R0, #3
+  0x08001EA6:  2001         MOVEQ      R0, #1
+  0x08001EA8:  F884 0035    STRB.W     R0, [R4, #53]
+  0x08001EAC:  2000         MOVS       R0, #0
+  0x08001EAE:  F884 0034    STRB.W     R0, [R4, #52]
+
    .L52:
+  0x08001EB2:  6CE1         LDR        R1, [R4, #76]
+
    .L53:
+  0x08001EB4:  B139         CBZ        R1, .L55                 ; 0x08001EC6
+
    .L54:
+  0x08001EB6:  F240 0088    MOVW       R0, #136                 ; 0x30000088 = hdma_spi4_tx
+  0x08001EBA:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000088 = hdma_spi4_tx
+  0x08001EBE:  B002         ADD        SP, SP, #8
+  0x08001EC0:  E8BD 47F0    POP.W      {R4-R10, LR}
+  0x08001EC4:  4708         BX         R1
+
    .L55:
+  0x08001EC6:  B002         ADD        SP, SP, #8
+  0x08001EC8:  E8BD 87F0    POP.W      {R4-R10, PC}
+
    .L56:
+  0x08001ECC:  03D0         LSLS       R0, R2, #15
+  0x08001ECE:  D401         BMI        .L57                     ; 0x08001ED4
+  0x08001ED0:  6C61         LDR        R1, [R4, #68]
+  0x08001ED2:  E7EF         B          .L53                     ; 0x08001EB4
+
    .L57:
+  0x08001ED4:  6BE1         LDR        R1, [R4, #60]
+  0x08001ED6:  E7ED         B          .L53                     ; 0x08001EB4
+
    .L58:
+  0x08001ED8:  6802         LDR        R2, [R0]
+  0x08001EDA:  E6F3         B          .L21                     ; 0x08001CC4
+
    .L59:
+  0x08001EDC:  6802         LDR        R2, [R0]
+  0x08001EDE:  E717         B          .L26                     ; 0x08001D10
+
    +

    Section .text.HAL_NVIC_SetPriority from charger_lto.o, size=76, align=2

    +
    +
    HAL_NVIC_SetPriority:
+  0x08001EE0:  B500         PUSH       {LR}
+  0x08001EE2:  F64E 5C0C    MOVW       R12, #0xED0C
+  0x08001EE6:  F04F 3EFF    MOV.W      LR, #0xFFFFFFFF
+  0x08001EEA:  F2CE 0C00    MOVT       R12, #0xE000
+  0x08001EEE:  F8DC 3000    LDR.W      R3, [R12]
+  0x08001EF2:  F3C3 2302    UBFX       R3, R3, #8, #3
+  0x08001EF6:  F083 0207    EOR        R2, R3, #7
+  0x08001EFA:  2A04         CMP        R2, #4
+  0x08001EFC:  BF28         IT         CS
+  0x08001EFE:  2204         MOVCS      R2, #4
+  0x08001F00:  FA0E F202    LSL.W      R2, LR, R2
+  0x08001F04:  4391         BICS       R1, R2
+  0x08001F06:  3B03         SUBS       R3, #3
+  0x08001F08:  F000 020F    AND        R2, R0, #15
+  0x08001F0C:  BF28         IT         CS
+  0x08001F0E:  4099         LSLCS      R1, R3
+  0x08001F10:  F100 4360    ADD.W      R3, R0, #0xE0000000
+  0x08001F14:  3A04         SUBS       R2, #4
+  0x08001F16:  F503 4364    ADD.W      R3, R3, #0xE400
+  0x08001F1A:  4462         ADD        R2, R12
+  0x08001F1C:  2800         CMP        R0, #0
+  0x08001F1E:  EA4F 1001    LSL.W      R0, R1, #4
+  0x08001F22:  BF48         IT         MI
+  0x08001F24:  F102 030C    ADDMI.W    R3, R2, #12
+  0x08001F28:  7018         STRB       R0, [R3]
+  0x08001F2A:  BD00         POP        {PC}
+
    +

    Section .text.RCCEx_PLL2_Config from charger_lto.o, size=272, align=2

    +
    +
    RCCEx_PLL2_Config:
+  0x08001F2C:  B570         PUSH       {R4-R6, LR}
+  0x08001F2E:  F244 4300    MOVW       R3, #0x4400
+  0x08001F32:  F6C5 0302    MOVT       R3, #0x5802
+  0x08001F36:  F8D3 E028    LDR.W      LR, [R3, #40]
+  0x08001F3A:  F00E 0E03    AND        LR, LR, #3
+  0x08001F3E:  F1BE 0F03    CMP.W      LR, #3
+  0x08001F42:  BF04         ITT        EQ
+  0x08001F44:  2001         MOVEQ      R0, #1
+  0x08001F46:  BD70         POPEQ      {R4-R6, PC}
+  0x08001F48:  F240 1C24    MOVW       R12, #0x0124             ; 0x30000124 = uwTick
+  0x08001F4C:  F8D3 E000    LDR.W      LR, [R3]
+  0x08001F50:  F2C3 0C00    MOVT       R12, #0x3000             ; 0x30000124 = uwTick
+  0x08001F54:  F02E 6E80    BIC        LR, LR, #0x04000000
+  0x08001F58:  F8C3 E000    STR.W      LR, [R3]
+  0x08001F5C:  F8DC E000    LDR.W      LR, [R12]
+
    .L1:
+  0x08001F60:  681A         LDR        R2, [R3]
+  0x08001F62:  0112         LSLS       R2, R2, #4
+  0x08001F64:  D506         BPL        .L2                      ; 0x08001F74
+  0x08001F66:  F8DC 2000    LDR.W      R2, [R12]
+  0x08001F6A:  EBA2 020E    SUB.W      R2, R2, LR
+  0x08001F6E:  2A02         CMP        R2, #2
+  0x08001F70:  D9F6         BLS        .L1                      ; 0x08001F60
+  0x08001F72:  E05F         B          .L4                      ; 0x08002034
+
    .L2:
+  0x08001F74:  6A9A         LDR        R2, [R3, #40]
+  0x08001F76:  2901         CMP        R1, #1
+  0x08001F78:  E9D0 E400    LDRD       LR, R4, [R0]
+  0x08001F7C:  F422 327C    BIC        R2, R2, #0x03F000
+  0x08001F80:  E9D0 5602    LDRD       R5, R6, [R0, #8]
+  0x08001F84:  EA42 320E    ORR.W      R2, R2, LR, LSL #12
+  0x08001F88:  629A         STR        R2, [R3, #40]
+  0x08001F8A:  F44F 427E    MOV.W      R2, #0xFE00
+  0x08001F8E:  F1A4 0E01    SUB.W      LR, R4, #1
+  0x08001F92:  EB02 2245    ADD.W      R2, R2, R5, LSL #9
+  0x08001F96:  6904         LDR        R4, [R0, #16]
+  0x08001F98:  F36F 2E5F    BFC        LR, #9, #23
+  0x08001F9C:  F04F 45FE    MOV.W      R5, #0x7F000000
+  0x08001FA0:  FA1E F282    UXTAH      R2, LR, R2
+  0x08001FA4:  F44F 0EFE    MOV.W      LR, #0x7F0000
+  0x08001FA8:  EB0E 4E06    ADD.W      LR, LR, R6, LSL #16
+  0x08001FAC:  F40E 0EFE    AND        LR, LR, #0x7F0000
+  0x08001FB0:  EB05 6404    ADD.W      R4, R5, R4, LSL #24
+  0x08001FB4:  4472         ADD        R2, LR
+  0x08001FB6:  F004 4EFE    AND        LR, R4, #0x7F000000
+  0x08001FBA:  4472         ADD        R2, LR
+  0x08001FBC:  639A         STR        R2, [R3, #56]
+  0x08001FBE:  6ADA         LDR        R2, [R3, #44]
+  0x08001FC0:  F8D0 E014    LDR.W      LR, [R0, #20]
+  0x08001FC4:  F022 02C0    BIC        R2, R2, #192
+  0x08001FC8:  EA42 020E    ORR.W      R2, R2, LR
+  0x08001FCC:  62DA         STR        R2, [R3, #44]
+  0x08001FCE:  6ADA         LDR        R2, [R3, #44]
+  0x08001FD0:  F8D0 E018    LDR.W      LR, [R0, #24]
+  0x08001FD4:  F022 0220    BIC        R2, R2, #32
+  0x08001FD8:  EA42 020E    ORR.W      R2, R2, LR
+  0x08001FDC:  62DA         STR        R2, [R3, #44]
+  0x08001FDE:  6ADA         LDR        R2, [R3, #44]
+  0x08001FE0:  F64F 7EF8    MOVW       LR, #0xFFF8
+  0x08001FE4:  F022 0210    BIC        R2, R2, #16
+  0x08001FE8:  62DA         STR        R2, [R3, #44]
+  0x08001FEA:  6BDA         LDR        R2, [R3, #60]
+  0x08001FEC:  69C0         LDR        R0, [R0, #28]
+  0x08001FEE:  EA22 020E    BIC.W      R2, R2, LR
+  0x08001FF2:  EA42 00C0    ORR.W      R0, R2, R0, LSL #3
+  0x08001FF6:  63D8         STR        R0, [R3, #60]
+  0x08001FF8:  6AD8         LDR        R0, [R3, #44]
+  0x08001FFA:  F040 0010    ORR        R0, R0, #16
+  0x08001FFE:  62D8         STR        R0, [R3, #44]
+  0x08002000:  F44F 1000    MOV.W      R0, #0x200000
+  0x08002004:  BF08         IT         EQ
+  0x08002006:  F44F 1080    MOVEQ.W    R0, #0x100000
+  0x0800200A:  2900         CMP        R1, #0
+  0x0800200C:  6AD9         LDR        R1, [R3, #44]
+  0x0800200E:  BF08         IT         EQ
+  0x08002010:  F44F 2000    MOVEQ.W    R0, #0x080000
+  0x08002014:  4308         ORRS       R0, R1
+  0x08002016:  62D8         STR        R0, [R3, #44]
+  0x08002018:  6818         LDR        R0, [R3]
+  0x0800201A:  F040 6080    ORR        R0, R0, #0x04000000
+  0x0800201E:  6018         STR        R0, [R3]
+  0x08002020:  F8DC 0000    LDR.W      R0, [R12]
+
    .L3:
+  0x08002024:  6819         LDR        R1, [R3]
+  0x08002026:  0109         LSLS       R1, R1, #4
+  0x08002028:  D406         BMI        .L5                      ; 0x08002038
+  0x0800202A:  F8DC 1000    LDR.W      R1, [R12]
+  0x0800202E:  1A09         SUBS       R1, R1, R0
+  0x08002030:  2903         CMP        R1, #3
+  0x08002032:  D3F7         BCC        .L3                      ; 0x08002024
+
    .L4:
+  0x08002034:  2003         MOVS       R0, #3
+  0x08002036:  BD70         POP        {R4-R6, PC}
+
    .L5:
+  0x08002038:  2000         MOVS       R0, #0
+  0x0800203A:  BD70         POP        {R4-R6, PC}
+
    +

    Section .text.RCCEx_PLL3_Config from charger_lto.o, size=272, align=2

    +
    +
    RCCEx_PLL3_Config:
+  0x0800203C:  B570         PUSH       {R4-R6, LR}
+  0x0800203E:  F244 4300    MOVW       R3, #0x4400
+  0x08002042:  F6C5 0302    MOVT       R3, #0x5802
+  0x08002046:  F8D3 E028    LDR.W      LR, [R3, #40]
+  0x0800204A:  F00E 0E03    AND        LR, LR, #3
+  0x0800204E:  F1BE 0F03    CMP.W      LR, #3
+  0x08002052:  BF04         ITT        EQ
+  0x08002054:  2001         MOVEQ      R0, #1
+  0x08002056:  BD70         POPEQ      {R4-R6, PC}
+  0x08002058:  F240 1C24    MOVW       R12, #0x0124             ; 0x30000124 = uwTick
+  0x0800205C:  F8D3 E000    LDR.W      LR, [R3]
+  0x08002060:  F2C3 0C00    MOVT       R12, #0x3000             ; 0x30000124 = uwTick
+  0x08002064:  F02E 5E80    BIC        LR, LR, #0x10000000
+  0x08002068:  F8C3 E000    STR.W      LR, [R3]
+  0x0800206C:  F8DC E000    LDR.W      LR, [R12]
+
    .L1:
+  0x08002070:  681A         LDR        R2, [R3]
+  0x08002072:  0092         LSLS       R2, R2, #2
+  0x08002074:  D506         BPL        .L2                      ; 0x08002084
+  0x08002076:  F8DC 2000    LDR.W      R2, [R12]
+  0x0800207A:  EBA2 020E    SUB.W      R2, R2, LR
+  0x0800207E:  2A02         CMP        R2, #2
+  0x08002080:  D9F6         BLS        .L1                      ; 0x08002070
+  0x08002082:  E05F         B          .L4                      ; 0x08002144
+
    .L2:
+  0x08002084:  6A9A         LDR        R2, [R3, #40]
+  0x08002086:  2901         CMP        R1, #1
+  0x08002088:  E9D0 E400    LDRD       LR, R4, [R0]
+  0x0800208C:  F022 727C    BIC        R2, R2, #0x03F00000
+  0x08002090:  E9D0 5602    LDRD       R5, R6, [R0, #8]
+  0x08002094:  EA42 520E    ORR.W      R2, R2, LR, LSL #20
+  0x08002098:  629A         STR        R2, [R3, #40]
+  0x0800209A:  F44F 427E    MOV.W      R2, #0xFE00
+  0x0800209E:  F1A4 0E01    SUB.W      LR, R4, #1
+  0x080020A2:  EB02 2245    ADD.W      R2, R2, R5, LSL #9
+  0x080020A6:  6904         LDR        R4, [R0, #16]
+  0x080020A8:  F36F 2E5F    BFC        LR, #9, #23
+  0x080020AC:  F04F 45FE    MOV.W      R5, #0x7F000000
+  0x080020B0:  FA1E F282    UXTAH      R2, LR, R2
+  0x080020B4:  F44F 0EFE    MOV.W      LR, #0x7F0000
+  0x080020B8:  EB0E 4E06    ADD.W      LR, LR, R6, LSL #16
+  0x080020BC:  F40E 0EFE    AND        LR, LR, #0x7F0000
+  0x080020C0:  EB05 6404    ADD.W      R4, R5, R4, LSL #24
+  0x080020C4:  4472         ADD        R2, LR
+  0x080020C6:  F004 4EFE    AND        LR, R4, #0x7F000000
+  0x080020CA:  4472         ADD        R2, LR
+  0x080020CC:  641A         STR        R2, [R3, #64]
+  0x080020CE:  6ADA         LDR        R2, [R3, #44]
+  0x080020D0:  F8D0 E014    LDR.W      LR, [R0, #20]
+  0x080020D4:  F422 6240    BIC        R2, R2, #0x0C00
+  0x080020D8:  EA42 020E    ORR.W      R2, R2, LR
+  0x080020DC:  62DA         STR        R2, [R3, #44]
+  0x080020DE:  6ADA         LDR        R2, [R3, #44]
+  0x080020E0:  F8D0 E018    LDR.W      LR, [R0, #24]
+  0x080020E4:  F422 7200    BIC        R2, R2, #0x0200
+  0x080020E8:  EA42 020E    ORR.W      R2, R2, LR
+  0x080020EC:  62DA         STR        R2, [R3, #44]
+  0x080020EE:  6ADA         LDR        R2, [R3, #44]
+  0x080020F0:  F64F 7EF8    MOVW       LR, #0xFFF8
+  0x080020F4:  F422 7280    BIC        R2, R2, #0x0100
+  0x080020F8:  62DA         STR        R2, [R3, #44]
+  0x080020FA:  6C5A         LDR        R2, [R3, #68]
+  0x080020FC:  69C0         LDR        R0, [R0, #28]
+  0x080020FE:  EA22 020E    BIC.W      R2, R2, LR
+  0x08002102:  EA42 00C0    ORR.W      R0, R2, R0, LSL #3
+  0x08002106:  6458         STR        R0, [R3, #68]
+  0x08002108:  6AD8         LDR        R0, [R3, #44]
+  0x0800210A:  F440 7080    ORR        R0, R0, #0x0100
+  0x0800210E:  62D8         STR        R0, [R3, #44]
+  0x08002110:  F04F 7080    MOV.W      R0, #0x01000000
+  0x08002114:  BF08         IT         EQ
+  0x08002116:  F44F 0000    MOVEQ.W    R0, #0x800000
+  0x0800211A:  2900         CMP        R1, #0
+  0x0800211C:  6AD9         LDR        R1, [R3, #44]
+  0x0800211E:  BF08         IT         EQ
+  0x08002120:  F44F 0080    MOVEQ.W    R0, #0x400000
+  0x08002124:  4308         ORRS       R0, R1
+  0x08002126:  62D8         STR        R0, [R3, #44]
+  0x08002128:  6818         LDR        R0, [R3]
+  0x0800212A:  F040 5080    ORR        R0, R0, #0x10000000
+  0x0800212E:  6018         STR        R0, [R3]
+  0x08002130:  F8DC 0000    LDR.W      R0, [R12]
+
    .L3:
+  0x08002134:  6819         LDR        R1, [R3]
+  0x08002136:  0089         LSLS       R1, R1, #2
+  0x08002138:  D406         BMI        .L5                      ; 0x08002148
+  0x0800213A:  F8DC 1000    LDR.W      R1, [R12]
+  0x0800213E:  1A09         SUBS       R1, R1, R0
+  0x08002140:  2903         CMP        R1, #3
+  0x08002142:  D3F7         BCC        .L3                      ; 0x08002134
+
    .L4:
+  0x08002144:  2003         MOVS       R0, #3
+  0x08002146:  BD70         POP        {R4-R6, PC}
+
    .L5:
+  0x08002148:  2000         MOVS       R0, #0
+  0x0800214A:  BD70         POP        {R4-R6, PC}
+
    +

    Section .text.HAL_DMA_Abort_IT from charger_lto.o, size=428, align=2

    +
    +
    HAL_DMA_Abort_IT:
+  0x0800214C:  F890 1035    LDRB.W     R1, [R0, #53]
+  0x08002150:  2902         CMP        R1, #2
+  0x08002152:  D116         BNE        .L1                      ; 0x08002182
+  0x08002154:  B580         PUSH       {R7, LR}
+  0x08002156:  F240 420F    MOVW       R2, #0x040F
+  0x0800215A:  6801         LDR        R1, [R0]
+  0x0800215C:  F2C4 0202    MOVT       R2, #0x4002
+  0x08002160:  4291         CMP        R1, R2
+  0x08002162:  DC12         BGT        .L2                      ; 0x0800218A
+  0x08002164:  F5A2 7C68    SUB.W      R12, R2, #0x03A0
+  0x08002168:  4561         CMP        R1, R12
+  0x0800216A:  DC1D         BGT        .L3                      ; 0x080021A8
+  0x0800216C:  F5A2 7C74    SUB.W      R12, R2, #0x03D0
+  0x08002170:  4561         CMP        R1, R12
+  0x08002172:  DC2F         BGT        .L5                      ; 0x080021D4
+  0x08002174:  F2A2 3CFF    SUBW       R12, R2, #0x03FF
+  0x08002178:  4561         CMP        R1, R12
+  0x0800217A:  D048         BEQ        .L10                     ; 0x0800220E
+  0x0800217C:  F2A2 3CE7    SUBW       R12, R2, #0x03E7
+  0x08002180:  E043         B          .L9                      ; 0x0800220A
+
    .L1:
+  0x08002182:  2180         MOVS       R1, #128
+  0x08002184:  6541         STR        R1, [R0, #84]
+  0x08002186:  2101         MOVS       R1, #1
+  0x08002188:  E063         B          .L19                     ; 0x08002252
+
    .L2:
+  0x0800218A:  F102 0C60    ADD.W      R12, R2, #96
+  0x0800218E:  4561         CMP        R1, R12
+  0x08002190:  DC15         BGT        .L4                      ; 0x080021BE
+  0x08002192:  F102 0C30    ADD.W      R12, R2, #48
+  0x08002196:  4561         CMP        R1, R12
+  0x08002198:  DC23         BGT        .L6                      ; 0x080021E2
+  0x0800219A:  F102 0C01    ADD.W      R12, R2, #1
+  0x0800219E:  4561         CMP        R1, R12
+  0x080021A0:  D035         BEQ        .L10                     ; 0x0800220E
+  0x080021A2:  F102 0C19    ADD.W      R12, R2, #25
+  0x080021A6:  E030         B          .L9                      ; 0x0800220A
+
    .L3:
+  0x080021A8:  F5A2 7C5C    SUB.W      R12, R2, #0x0370
+  0x080021AC:  4561         CMP        R1, R12
+  0x080021AE:  DC1F         BGT        .L7                      ; 0x080021F0
+  0x080021B0:  F2A2 3C9F    SUBW       R12, R2, #0x039F
+  0x080021B4:  4561         CMP        R1, R12
+  0x080021B6:  D02A         BEQ        .L10                     ; 0x0800220E
+  0x080021B8:  F2A2 3C87    SUBW       R12, R2, #0x0387
+  0x080021BC:  E025         B          .L9                      ; 0x0800220A
+
    .L4:
+  0x080021BE:  F102 0C90    ADD.W      R12, R2, #144
+  0x080021C2:  4561         CMP        R1, R12
+  0x080021C4:  DC1B         BGT        .L8                      ; 0x080021FE
+  0x080021C6:  F102 0C61    ADD.W      R12, R2, #97
+  0x080021CA:  4561         CMP        R1, R12
+  0x080021CC:  D01F         BEQ        .L10                     ; 0x0800220E
+  0x080021CE:  F102 0C79    ADD.W      R12, R2, #121
+  0x080021D2:  E01A         B          .L9                      ; 0x0800220A
+
    .L5:
+  0x080021D4:  F2A2 3CCF    SUBW       R12, R2, #0x03CF
+  0x080021D8:  4561         CMP        R1, R12
+  0x080021DA:  D018         BEQ        .L10                     ; 0x0800220E
+  0x080021DC:  F2A2 3CB7    SUBW       R12, R2, #0x03B7
+  0x080021E0:  E013         B          .L9                      ; 0x0800220A
+
    .L6:
+  0x080021E2:  F102 0C31    ADD.W      R12, R2, #49
+  0x080021E6:  4561         CMP        R1, R12
+  0x080021E8:  D011         BEQ        .L10                     ; 0x0800220E
+  0x080021EA:  F102 0C49    ADD.W      R12, R2, #73
+  0x080021EE:  E00C         B          .L9                      ; 0x0800220A
+
    .L7:
+  0x080021F0:  F2A2 3C6F    SUBW       R12, R2, #0x036F
+  0x080021F4:  4561         CMP        R1, R12
+  0x080021F6:  D00A         BEQ        .L10                     ; 0x0800220E
+  0x080021F8:  F2A2 3C57    SUBW       R12, R2, #0x0357
+  0x080021FC:  E005         B          .L9                      ; 0x0800220A
+
    .L8:
+  0x080021FE:  F102 0CA9    ADD.W      R12, R2, #169
+  0x08002202:  4561         CMP        R1, R12
+  0x08002204:  D003         BEQ        .L10                     ; 0x0800220E
+  0x08002206:  F102 0C91    ADD.W      R12, R2, #145
+
    .L9:
+  0x0800220A:  4561         CMP        R1, R12
+  0x0800220C:  D128         BNE        .L21                     ; 0x08002260
+
    .L10:
+  0x0800220E:  4291         CMP        R1, R2
+  0x08002210:  F04F 0204    MOV.W      R2, #4
+  0x08002214:  F880 2035    STRB.W     R2, [R0, #53]
+  0x08002218:  DC06         BGT        .L11                     ; 0x08002228
+  0x0800221A:  206F         MOVS       R0, #111
+  0x0800221C:  F2C4 0002    MOVT       R0, #0x4002
+  0x08002220:  4281         CMP        R1, R0
+  0x08002222:  DD07         BLE        .L12                     ; 0x08002234
+  0x08002224:  3030         ADDS       R0, #48
+  0x08002226:  E006         B          .L13                     ; 0x08002236
+
    .L11:
+  0x08002228:  F240 406F    MOVW       R0, #0x046F
+  0x0800222C:  F2C4 0002    MOVT       R0, #0x4002
+  0x08002230:  4281         CMP        R1, R0
+  0x08002232:  DC03         BGT        .L14                     ; 0x0800223C
+
    .L12:
+  0x08002234:  3830         SUBS       R0, #48
+
    .L13:
+  0x08002236:  4281         CMP        R1, R0
+  0x08002238:  DD03         BLE        .L15                     ; 0x08002242
+  0x0800223A:  E003         B          .L16                     ; 0x08002244
+
    .L14:
+  0x0800223C:  3030         ADDS       R0, #48
+  0x0800223E:  4281         CMP        R1, R0
+  0x08002240:  DC09         BGT        .L20                     ; 0x08002256
+
    .L15:
+  0x08002242:  382F         SUBS       R0, #47
+
    .L16:
+  0x08002244:  6808         LDR        R0, [R1]
+  0x08002246:  F020 0001    BIC        R0, R0, #1
+  0x0800224A:  6008         STR        R0, [R1]
+
    .L17:
+  0x0800224C:  2100         MOVS       R1, #0
+
    .L18:
+  0x0800224E:  E8BD 4008    POP.W      {R3, LR}
+
    .L19:
+  0x08002252:  4608         MOV        R0, R1
+  0x08002254:  4770         BX         LR
+
    .L20:
+  0x08002256:  3019         ADDS       R0, #25
+  0x08002258:  4281         CMP        R1, R0
+  0x0800225A:  BF18         IT         NE
+  0x0800225C:  3818         SUBNE      R0, #24
+  0x0800225E:  E7F1         B          .L16                     ; 0x08002244
+
    .L21:
+  0x08002260:  680A         LDR        R2, [R1]
+  0x08002262:  F022 020E    BIC        R2, R2, #14
+  0x08002266:  600A         STR        R2, [R1]
+  0x08002268:  F245 4257    MOVW       R2, #0x5457
+  0x0800226C:  F6C5 0202    MOVT       R2, #0x5802
+  0x08002270:  4291         CMP        R1, R2
+  0x08002272:  680A         LDR        R2, [R1]
+  0x08002274:  F022 0201    BIC        R2, R2, #1
+  0x08002278:  600A         STR        R2, [R1]
+  0x0800227A:  DC07         BGT        .L22                     ; 0x0800228C
+  0x0800227C:  F245 422F    MOVW       R2, #0x542F
+  0x08002280:  F6C5 0202    MOVT       R2, #0x5802
+  0x08002284:  4291         CMP        R1, R2
+  0x08002286:  DD07         BLE        .L23                     ; 0x08002298
+  0x08002288:  3201         ADDS       R2, #1
+  0x0800228A:  E006         B          .L24                     ; 0x0800229A
+
    .L22:
+  0x0800228C:  F245 427F    MOVW       R2, #0x547F
+  0x08002290:  F6C5 0202    MOVT       R2, #0x5802
+  0x08002294:  4291         CMP        R1, R2
+  0x08002296:  DC04         BGT        .L25                     ; 0x080022A2
+
    .L23:
+  0x08002298:  3A27         SUBS       R2, #39
+
    .L24:
+  0x0800229A:  4291         CMP        R1, R2
+  0x0800229C:  D007         BEQ        .L27                     ; 0x080022AE
+  0x0800229E:  3214         ADDS       R2, #20
+  0x080022A0:  E003         B          .L26                     ; 0x080022AA
+
    .L25:
+  0x080022A2:  3215         ADDS       R2, #21
+  0x080022A4:  4291         CMP        R1, R2
+  0x080022A6:  D002         BEQ        .L27                     ; 0x080022AE
+  0x080022A8:  3A14         SUBS       R2, #20
+
    .L26:
+  0x080022AA:  4291         CMP        R1, R2
+  0x080022AC:  D119         BNE        .L28                     ; 0x080022E2
+
    .L27:
+  0x080022AE:  E9D0 1318    LDRD       R1, R3, [R0, #96]
+  0x080022B2:  E9D0 EC16    LDRD       LR, R12, [R0, #88]
+  0x080022B6:  680A         LDR        R2, [R1]
+  0x080022B8:  F422 7280    BIC        R2, R2, #0x0100
+  0x080022BC:  600A         STR        R2, [R1]
+  0x080022BE:  F00C 011F    AND        R1, R12, #31
+  0x080022C2:  2201         MOVS       R2, #1
+  0x080022C4:  FA02 F101    LSL.W      R1, R2, R1
+  0x080022C8:  F8CE 1004    STR.W      R1, [LR, #4]
+  0x080022CC:  6E81         LDR        R1, [R0, #104]
+  0x080022CE:  6059         STR        R1, [R3, #4]
+  0x080022D0:  6EC1         LDR        R1, [R0, #108]
+  0x080022D2:  B131         CBZ        R1, .L28                 ; 0x080022E2
+  0x080022D4:  680A         LDR        R2, [R1]
+  0x080022D6:  F422 7280    BIC        R2, R2, #0x0100
+  0x080022DA:  600A         STR        R2, [R1]
+  0x080022DC:  E9D0 121C    LDRD       R1, R2, [R0, #112]
+  0x080022E0:  604A         STR        R2, [R1, #4]
+
    .L28:
+  0x080022E2:  2101         MOVS       R1, #1
+  0x080022E4:  F880 1035    STRB.W     R1, [R0, #53]
+  0x080022E8:  6D02         LDR        R2, [R0, #80]
+  0x080022EA:  2100         MOVS       R1, #0
+  0x080022EC:  2A00         CMP        R2, #0
+  0x080022EE:  F880 1034    STRB.W     R1, [R0, #52]
+  0x080022F2:  D0AC         BEQ        .L18                     ; 0x0800224E
+  0x080022F4:  4790         BLX        R2
+  0x080022F6:  E7A9         B          .L17                     ; 0x0800224C
+
    +

    Section .text.SPI_DMAAbortOnError from charger_lto.o, size=20, align=2

    +
    +
    SPI_DMAAbortOnError:
+  0x080022F8:  6B80         LDR        R0, [R0, #56]
+  0x080022FA:  2100         MOVS       R1, #0
+  0x080022FC:  F8A0 106A    STRH.W     R1, [R0, #106]
+  0x08002300:  F8A0 1062    STRH.W     R1, [R0, #98]
+  0x08002304:  2101         MOVS       R1, #1
+  0x08002306:  F880 1081    STRB.W     R1, [R0, #129]
+  0x0800230A:  4770         BX         LR

    Section .init.Reset_Handler from Cortex_M_Startup.o, size=24, align=2

    -
    Reset_Handler:
-reset_handler:
-  0x08000B96:  F7FF FDB6    BL         SystemInit               ; 0x08000706
-  0x08000B9A:  F64E 5088    MOVW       R0, #0xED88
-  0x08000B9E:  F2CE 0000    MOVT       R0, #0xE000
-  0x08000BA2:  6801         LDR        R1, [R0]
-  0x08000BA4:  F451 0170    ORRS       R1, R1, #0xF00000
-  0x08000BA8:  6001         STR        R1, [R0]
-  0x08000BAA:  F7FF FC15    BL         _start                   ; 0x080003D8
+
    Reset_Handler:
+reset_handler:
+  0x0800230C:  F7FF FB4B    BL         SystemInit               ; 0x080019A6
+  0x08002310:  F64E 5088    MOVW       R0, #0xED88
+  0x08002314:  F2CE 0000    MOVT       R0, #0xE000
+  0x08002318:  6801         LDR        R1, [R0]
+  0x0800231A:  F451 0170    ORRS       R1, R1, #0xF00000
+  0x0800231E:  6001         STR        R1, [R0]
+  0x08002320:  F7FE FC74    BL         _start                   ; 0x08000C0C

    Section .rodata.D1CorePrescTable from charger_lto.o, size=16, align=1

    -
    D1CorePrescTable:
-  0x08000BAE:  00           DC.B       0x00                     ; '\0'
-  0x08000BAF:  00           DC.B       0x00                     ; '\0'
-  0x08000BB0:  00           DC.B       0x00                     ; '\0'
-  0x08000BB1:  00           DC.B       0x00                     ; '\0'
-  0x08000BB2:  00           DC.B       0x00                     ; '\0'
-  0x08000BB3:  00           DC.B       0x00                     ; '\0'
-  0x08000BB4:  00           DC.B       0x00                     ; '\0'
-  0x08000BB5:  00           DC.B       0x00                     ; '\0'
-  0x08000BB6:  01           DC.B       0x01                     ; '\x01'
-  0x08000BB7:  02           DC.B       0x02                     ; '\x02'
-  0x08000BB8:  03           DC.B       0x03                     ; '\x03'
-  0x08000BB9:  04           DC.B       0x04                     ; '\x04'
-  0x08000BBA:  06           DC.B       0x06                     ; '\x06'
-  0x08000BBB:  07           DC.B       0x07                     ; '\x07'
-  0x08000BBC:  08           DC.B       0x08                     ; '\b'
-  0x08000BBD:  09           DC.B       0x09                     ; '\t'
+
    D1CorePrescTable:
+  0x08002324:  00           DC.B       0x00                     ; '\0'
+  0x08002325:  00           DC.B       0x00                     ; '\0'
+  0x08002326:  00           DC.B       0x00                     ; '\0'
+  0x08002327:  00           DC.B       0x00                     ; '\0'
+  0x08002328:  00           DC.B       0x00                     ; '\0'
+  0x08002329:  00           DC.B       0x00                     ; '\0'
+  0x0800232A:  00           DC.B       0x00                     ; '\0'
+  0x0800232B:  00           DC.B       0x00                     ; '\0'
+  0x0800232C:  01           DC.B       0x01                     ; '\x01'
+  0x0800232D:  02           DC.B       0x02                     ; '\x02'
+  0x0800232E:  03           DC.B       0x03                     ; '\x03'
+  0x0800232F:  04           DC.B       0x04                     ; '\x04'
+  0x08002330:  06           DC.B       0x06                     ; '\x06'
+  0x08002331:  07           DC.B       0x07                     ; '\x07'
+  0x08002332:  08           DC.B       0x08                     ; '\b'
+  0x08002333:  09           DC.B       0x09                     ; '\t'

    Section .segger.init.table from [ Linker created ], size=32, align=4

    -  0x08000BC0:  08000BE5     DC.W       __SEGGER_init_zero
-  0x08000BC4:  00           DC.B       0x00                     ; '\0'
-  0x08000BC5:  00           DC.B       0x00                     ; '\0'
-  0x08000BC6:  00           DC.B       0x00                     ; '\0'
-  0x08000BC7:  30           DC.B       0x30                     ; '0'
-  0x08000BC8:  29           DC.B       0x29                     ; ')'
-  0x08000BC9:  00           DC.B       0x00                     ; '\0'
-  0x08000BCA:  00           DC.B       0x00                     ; '\0'
-  0x08000BCB:  00           DC.B       0x00                     ; '\0'
-  0x08000BCC:  08000BF7     DC.W       __SEGGER_init_copy
-  0x08000BD0:  2C           DC.B       0x2C                     ; ','
-  0x08000BD1:  00           DC.B       0x00                     ; '\0'
-  0x08000BD2:  00           DC.B       0x00                     ; '\0'
-  0x08000BD3:  30           DC.B       0x30                     ; '0'
-  0x08000BD4:  08000BE0     DC.W       0x08000BE0               ; R_ARM_ABS32
-  0x08000BD8:  04           DC.B       0x04                     ; '\x04'
-  0x08000BD9:  00           DC.B       0x00                     ; '\0'
-  0x08000BDA:  00           DC.B       0x00                     ; '\0'
-  0x08000BDB:  00           DC.B       0x00                     ; '\0'
-  0x08000BDC:  080003E3     DC.W       __SEGGER_init_done
+  0x08002334:  08002359     DC.W       __SEGGER_init_zero
+  0x08002338:  00           DC.B       0x00                     ; '\0'
+  0x08002339:  00           DC.B       0x00                     ; '\0'
+  0x0800233A:  00           DC.B       0x00                     ; '\0'
+  0x0800233B:  30           DC.B       0x30                     ; '0'
+  0x0800233C:  29           DC.B       0x29                     ; ')'
+  0x0800233D:  01           DC.B       0x01                     ; '\x01'
+  0x0800233E:  00           DC.B       0x00                     ; '\0'
+  0x0800233F:  00           DC.B       0x00                     ; '\0'
+  0x08002340:  0800236B     DC.W       __SEGGER_init_copy
+  0x08002344:  2C           DC.B       0x2C                     ; ','
+  0x08002345:  01           DC.B       0x01                     ; '\x01'
+  0x08002346:  00           DC.B       0x00                     ; '\0'
+  0x08002347:  30           DC.B       0x30                     ; '0'
+  0x08002348:  08002354     DC.W       0x08002354               ; R_ARM_ABS32
+  0x0800234C:  04           DC.B       0x04                     ; '\x04'
+  0x0800234D:  00           DC.B       0x00                     ; '\0'
+  0x0800234E:  00           DC.B       0x00                     ; '\0'
+  0x0800234F:  00           DC.B       0x00                     ; '\0'
+  0x08002350:  08000C17     DC.W       __SEGGER_init_done

    Section .segger.init.data from [ Linker created ], size=4, align=4

    -  0x08000BE0:  00           DC.B       0x00                     ; '\0'
-  0x08000BE1:  90           DC.B       0x90                     ; '\x90'
-  0x08000BE2:  D0           DC.B       0xD0                     ; '\xD0'
-  0x08000BE3:  03           DC.B       0x03                     ; '\x03'
+  0x08002354:  00           DC.B       0x00                     ; '\0'
+  0x08002355:  90           DC.B       0x90                     ; '\x90'
+  0x08002356:  D0           DC.B       0xD0                     ; '\xD0'
+  0x08002357:  03           DC.B       0x03                     ; '\x03'

    Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v7em_fpv5_d16_hard_t_le_eabi_balanced.a), size=18, align=2

    -
    __SEGGER_init_zero:
-  0x08000BE4:  6820         LDR        R0, [R4]
-  0x08000BE6:  6861         LDR        R1, [R4, #4]
-  0x08000BE8:  3408         ADDS       R4, #8
-  0x08000BEA:  2200         MOVS       R2, #0
-  0x08000BEC:  E000         B          .L2                      ; 0x08000BF0
+
    __SEGGER_init_zero:
+  0x08002358:  6820         LDR        R0, [R4]
+  0x0800235A:  6861         LDR        R1, [R4, #4]
+  0x0800235C:  3408         ADDS       R4, #8
+  0x0800235E:  2200         MOVS       R2, #0
+  0x08002360:  E000         B          .L2                      ; 0x08002364
 
    .L1:
-  0x08000BEE:  5442         STRB       R2, [R0, R1]
+  0x08002362:  5442         STRB       R2, [R0, R1]
 
    .L2:
-  0x08000BF0:  3901         SUBS       R1, #1
-  0x08000BF2:  D5FC         BPL        .L1                      ; 0x08000BEE
-  0x08000BF4:  4770         BX         LR
+  0x08002364:  3901         SUBS       R1, #1
+  0x08002366:  D5FC         BPL        .L1                      ; 0x08002362
+  0x08002368:  4770         BX         LR

    Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v7em_fpv5_d16_hard_t_le_eabi_balanced.a), size=20, align=2

    -
    __SEGGER_init_copy:
-  0x08000BF6:  6820         LDR        R0, [R4]
-  0x08000BF8:  6861         LDR        R1, [R4, #4]
-  0x08000BFA:  68A2         LDR        R2, [R4, #8]
-  0x08000BFC:  340C         ADDS       R4, #12
-  0x08000BFE:  E001         B          .L2                      ; 0x08000C04
+
    __SEGGER_init_copy:
+  0x0800236A:  6820         LDR        R0, [R4]
+  0x0800236C:  6861         LDR        R1, [R4, #4]
+  0x0800236E:  68A2         LDR        R2, [R4, #8]
+  0x08002370:  340C         ADDS       R4, #12
+  0x08002372:  E001         B          .L2                      ; 0x08002378
 
    .L1:
-  0x08000C00:  5C8B         LDRB       R3, [R1, R2]
-  0x08000C02:  5483         STRB       R3, [R0, R2]
+  0x08002374:  5C8B         LDRB       R3, [R1, R2]
+  0x08002376:  5483         STRB       R3, [R0, R2]
 
    .L2:
-  0x08000C04:  3A01         SUBS       R2, #1
-  0x08000C06:  D5FB         BPL        .L1                      ; 0x08000C00
-  0x08000C08:  4770         BX         LR
+  0x08002378:  3A01         SUBS       R2, #1
+  0x0800237A:  D5FB         BPL        .L1                      ; 0x08002374
+  0x0800237C:  4770         BX         LR
    -

    Section .bss.hrtc from charger_lto.o, size=36, align=4

    +

    Section .bss.hspi4 from charger_lto.o, size=136, align=4

    -
    hrtc:
+
    hspi4:
   0x30000000:  00           DC.B       0x00                     ; '\0'
   0x30000001:  00           DC.B       0x00                     ; '\0'
@@ -9011,41 +12243,310 @@
   0x30000012:  D0           DC.B       0xD0                     ; '\xD0'
   0x30000013:  03           DC.B       0x03                     ; '\x03'
-  0x30000014:  FF           DC.B       0xFF                     ; '\xFF'
-  0x30000015:  FF           DC.B       0xFF                     ; '\xFF'
-  0x30000016:  FF           DC.B       0xFF                     ; '\xFF'
-  0x30000017:  FF           DC.B       0xFF                     ; '\xFF'
-  0x30000018:  D6           DC.B       0xD6                     ; '\xD6'
-  0x30000019:  09           DC.B       0x09                     ; '\t'
+  0x30000014:  0E           DC.B       0x0E                     ; '\x0E'
+  0x30000015:  00           DC.B       0x00                     ; '\0'
+  0x30000016:  00           DC.B       0x00                     ; '\0'
+  0x30000017:  00           DC.B       0x00                     ; '\0'
+  0x30000018:  1C           DC.B       0x1C                     ; '\x1C'
+  0x30000019:  00           DC.B       0x00                     ; '\0'
   0x3000001A:  00           DC.B       0x00                     ; '\0'
-  0x3000001B:  08           DC.B       0x08                     ; '\b'
-  0x3000001C:  0C           DC.B       0x0C                     ; '\x0C'
+  0x3000001B:  00           DC.B       0x00                     ; '\0'
+  0x3000001C:  02           DC.B       0x02                     ; '\x02'
   0x3000001D:  00           DC.B       0x00                     ; '\0'
-  0x3000001E:  00           DC.B       0x00                     ; '\0'
-  0x3000001F:  00           DC.B       0x00                     ; '\0'
-  0x30000020:  1A           DC.B       0x1A                     ; '\x1A'
+  0x3000001E:  31           DC.B       0x31                     ; '1'
+  0x3000001F:  9F           DC.B       0x9F                     ; '\x9F'
+  0x30000020:  1C           DC.B       0x1C                     ; '\x1C'
   0x30000021:  00           DC.B       0x00                     ; '\0'
   0x30000022:  00           DC.B       0x00                     ; '\0'
   0x30000023:  00           DC.B       0x00                     ; '\0'
+  0x30000024:  58           DC.B       0x58                     ; 'X'
+  0x30000025:  00           DC.B       0x00                     ; '\0'
+  0x30000026:  00           DC.B       0x00                     ; '\0'
+  0x30000027:  00           DC.B       0x00                     ; '\0'
+  0x30000028:  38           DC.B       0x38                     ; '8'
+  0x30000029:  00           DC.B       0x00                     ; '\0'
+  0x3000002A:  31           DC.B       0x31                     ; '1'
+  0x3000002B:  9F           DC.B       0x9F                     ; '\x9F'
+  0x3000002C:  93           DC.B       0x93                     ; '\x93'
+  0x3000002D:  01           DC.B       0x01                     ; '\x01'
+  0x3000002E:  30           DC.B       0x30                     ; '0'
+  0x3000002F:  9F           DC.B       0x9F                     ; '\x9F'
+  0x30000030:  93           DC.B       0x93                     ; '\x93'
+  0x30000031:  01           DC.B       0x01                     ; '\x01'
+  0x30000032:  93           DC.B       0x93                     ; '\x93'
+  0x30000033:  02           DC.B       0x02                     ; '\x02'
+  0x30000034:  30           DC.B       0x30                     ; '0'
+  0x30000035:  9F           DC.B       0x9F                     ; '\x9F'
+  0x30000036:  93           DC.B       0x93                     ; '\x93'
+  0x30000037:  04           DC.B       0x04                     ; '\x04'
+  0x30000038:  4F           DC.B       0x4F                     ; 'O'
+  0x30000039:  9F           DC.B       0x9F                     ; '\x9F'
+  0x3000003A:  93           DC.B       0x93                     ; '\x93'
+  0x3000003B:  01           DC.B       0x01                     ; '\x01'
+  0x3000003C:  10           DC.B       0x10                     ; '\x10'
+  0x3000003D:  87           DC.B       0x87                     ; '\x87'
+  0x3000003E:  FF           DC.B       0xFF                     ; '\xFF'
+  0x3000003F:  FF           DC.B       0xFF                     ; '\xFF'
+  0x30000040:  FF           DC.B       0xFF                     ; '\xFF'
+  0x30000041:  FF           DC.B       0xFF                     ; '\xFF'
+  0x30000042:  FF           DC.B       0xFF                     ; '\xFF'
+  0x30000043:  FF           DC.B       0xFF                     ; '\xFF'
+  0x30000044:  FF           DC.B       0xFF                     ; '\xFF'
+  0x30000045:  FF           DC.B       0xFF                     ; '\xFF'
+  0x30000046:  01           DC.B       0x01                     ; '\x01'
+  0x30000047:  9F           DC.B       0x9F                     ; '\x9F'
+  0x30000048:  93           DC.B       0x93                     ; '\x93'
+  0x30000049:  01           DC.B       0x01                     ; '\x01'
+  0x3000004A:  30           DC.B       0x30                     ; '0'
+  0x3000004B:  9F           DC.B       0x9F                     ; '\x9F'
+  0x3000004C:  93           DC.B       0x93                     ; '\x93'
+  0x3000004D:  01           DC.B       0x01                     ; '\x01'
+  0x3000004E:  30           DC.B       0x30                     ; '0'
+  0x3000004F:  9F           DC.B       0x9F                     ; '\x9F'
+  0x30000050:  93           DC.B       0x93                     ; '\x93'
+  0x30000051:  01           DC.B       0x01                     ; '\x01'
+  0x30000052:  31           DC.B       0x31                     ; '1'
+  0x30000053:  9F           DC.B       0x9F                     ; '\x9F'
+  0x30000054:  93           DC.B       0x93                     ; '\x93'
+  0x30000055:  01           DC.B       0x01                     ; '\x01'
+  0x30000056:  31           DC.B       0x31                     ; '1'
+  0x30000057:  9F           DC.B       0x9F                     ; '\x9F'
+  0x30000058:  93           DC.B       0x93                     ; '\x93'
+  0x30000059:  01           DC.B       0x01                     ; '\x01'
+  0x3000005A:  30           DC.B       0x30                     ; '0'
+  0x3000005B:  9F           DC.B       0x9F                     ; '\x9F'
+  0x3000005C:  93           DC.B       0x93                     ; '\x93'
+  0x3000005D:  01           DC.B       0x01                     ; '\x01'
+  0x3000005E:  30           DC.B       0x30                     ; '0'
+  0x3000005F:  9F           DC.B       0x9F                     ; '\x9F'
+  0x30000060:  93           DC.B       0x93                     ; '\x93'
+  0x30000061:  01           DC.B       0x01                     ; '\x01'
+  0x30000062:  00           DC.B       0x00                     ; '\0'
+  0x30000063:  00           DC.B       0x00                     ; '\0'
+  0x30000064:  00           DC.B       0x00                     ; '\0'
+  0x30000065:  00           DC.B       0x00                     ; '\0'
+  0x30000066:  00           DC.B       0x00                     ; '\0'
+  0x30000067:  00           DC.B       0x00                     ; '\0'
+  0x30000068:  00           DC.B       0x00                     ; '\0'
+  0x30000069:  00           DC.B       0x00                     ; '\0'
+  0x3000006A:  90           DC.B       0x90                     ; '\x90'
+  0x3000006B:  00           DC.B       0x00                     ; '\0'
+  0x3000006C:  00           DC.B       0x00                     ; '\0'
+  0x3000006D:  00           DC.B       0x00                     ; '\0'
+  0x3000006E:  9A           DC.B       0x9A                     ; '\x9A'
+  0x3000006F:  00           DC.B       0x00                     ; '\0'
+  0x30000070:  00           DC.B       0x00                     ; '\0'
+  0x30000071:  00           DC.B       0x00                     ; '\0'
+  0x30000072:  01           DC.B       0x01                     ; '\x01'
+  0x30000073:  00           DC.B       0x00                     ; '\0'
+  0x30000074:  51           DC.B       0x51                     ; 'Q'
+  0x30000075:  00           DC.B       0x00                     ; '\0'
+  0x30000076:  00           DC.B       0x00                     ; '\0'
+  0x30000077:  00           DC.B       0x00                     ; '\0'
+  0x30000078:  00           DC.B       0x00                     ; '\0'
+  0x30000079:  00           DC.B       0x00                     ; '\0'
+  0x3000007A:  00           DC.B       0x00                     ; '\0'
+  0x3000007B:  00           DC.B       0x00                     ; '\0'
+  0x3000007C:  00           DC.B       0x00                     ; '\0'
+  0x3000007D:  94           DC.B       0x94                     ; '\x94'
+  0x3000007E:  00           DC.B       0x00                     ; '\0'
+  0x3000007F:  00           DC.B       0x00                     ; '\0'
+  0x30000080:  00           DC.B       0x00                     ; '\0'
+  0x30000081:  C0           DC.B       0xC0                     ; '\xC0'
+  0x30000082:  00           DC.B       0x00                     ; '\0'
+  0x30000083:  00           DC.B       0x00                     ; '\0'
+  0x30000084:  00           DC.B       0x00                     ; '\0'
+  0x30000085:  01           DC.B       0x01                     ; '\x01'
+  0x30000086:  00           DC.B       0x00                     ; '\0'
+  0x30000087:  50           DC.B       0x50                     ; 'P'
+
    +

    Section .bss.hdma_spi4_tx from charger_lto.o, size=120, align=4

    +
    +
    hdma_spi4_tx:
+  0x30000088:  00           DC.B       0x00                     ; '\0'
+  0x30000089:  00           DC.B       0x00                     ; '\0'
+  0x3000008A:  00           DC.B       0x00                     ; '\0'
+  0x3000008B:  00           DC.B       0x00                     ; '\0'
+  0x3000008C:  00           DC.B       0x00                     ; '\0'
+  0x3000008D:  00           DC.B       0x00                     ; '\0'
+  0x3000008E:  00           DC.B       0x00                     ; '\0'
+  0x3000008F:  00           DC.B       0x00                     ; '\0'
+  0x30000090:  01           DC.B       0x01                     ; '\x01'
+  0x30000091:  02           DC.B       0x02                     ; '\x02'
+  0x30000092:  03           DC.B       0x03                     ; '\x03'
+  0x30000093:  04           DC.B       0x04                     ; '\x04'
+  0x30000094:  06           DC.B       0x06                     ; '\x06'
+  0x30000095:  07           DC.B       0x07                     ; '\x07'
+  0x30000096:  08           DC.B       0x08                     ; '\b'
+  0x30000097:  09           DC.B       0x09                     ; '\t'
+  0x30000098:  00           DC.B       0x00                     ; '\0'
+  0x30000099:  90           DC.B       0x90                     ; '\x90'
+  0x3000009A:  D0           DC.B       0xD0                     ; '\xD0'
+  0x3000009B:  03           DC.B       0x03                     ; '\x03'
+  0x3000009C:  0E           DC.B       0x0E                     ; '\x0E'
+  0x3000009D:  00           DC.B       0x00                     ; '\0'
+  0x3000009E:  00           DC.B       0x00                     ; '\0'
+  0x3000009F:  00           DC.B       0x00                     ; '\0'
+  0x300000A0:  1C           DC.B       0x1C                     ; '\x1C'
+  0x300000A1:  00           DC.B       0x00                     ; '\0'
+  0x300000A2:  00           DC.B       0x00                     ; '\0'
+  0x300000A3:  00           DC.B       0x00                     ; '\0'
+  0x300000A4:  02           DC.B       0x02                     ; '\x02'
+  0x300000A5:  00           DC.B       0x00                     ; '\0'
+  0x300000A6:  31           DC.B       0x31                     ; '1'
+  0x300000A7:  9F           DC.B       0x9F                     ; '\x9F'
+  0x300000A8:  1C           DC.B       0x1C                     ; '\x1C'
+  0x300000A9:  00           DC.B       0x00                     ; '\0'
+  0x300000AA:  00           DC.B       0x00                     ; '\0'
+  0x300000AB:  00           DC.B       0x00                     ; '\0'
+  0x300000AC:  58           DC.B       0x58                     ; 'X'
+  0x300000AD:  00           DC.B       0x00                     ; '\0'
+  0x300000AE:  00           DC.B       0x00                     ; '\0'
+  0x300000AF:  00           DC.B       0x00                     ; '\0'
+  0x300000B0:  38           DC.B       0x38                     ; '8'
+  0x300000B1:  00           DC.B       0x00                     ; '\0'
+  0x300000B2:  31           DC.B       0x31                     ; '1'
+  0x300000B3:  9F           DC.B       0x9F                     ; '\x9F'
+  0x300000B4:  93           DC.B       0x93                     ; '\x93'
+  0x300000B5:  01           DC.B       0x01                     ; '\x01'
+  0x300000B6:  30           DC.B       0x30                     ; '0'
+  0x300000B7:  9F           DC.B       0x9F                     ; '\x9F'
+  0x300000B8:  93           DC.B       0x93                     ; '\x93'
+  0x300000B9:  01           DC.B       0x01                     ; '\x01'
+  0x300000BA:  93           DC.B       0x93                     ; '\x93'
+  0x300000BB:  02           DC.B       0x02                     ; '\x02'
+  0x300000BC:  30           DC.B       0x30                     ; '0'
+  0x300000BD:  9F           DC.B       0x9F                     ; '\x9F'
+  0x300000BE:  93           DC.B       0x93                     ; '\x93'
+  0x300000BF:  04           DC.B       0x04                     ; '\x04'
+  0x300000C0:  4F           DC.B       0x4F                     ; 'O'
+  0x300000C1:  9F           DC.B       0x9F                     ; '\x9F'
+  0x300000C2:  93           DC.B       0x93                     ; '\x93'
+  0x300000C3:  01           DC.B       0x01                     ; '\x01'
+  0x300000C4:  10           DC.B       0x10                     ; '\x10'
+  0x300000C5:  87           DC.B       0x87                     ; '\x87'
+  0x300000C6:  FF           DC.B       0xFF                     ; '\xFF'
+  0x300000C7:  FF           DC.B       0xFF                     ; '\xFF'
+  0x300000C8:  FF           DC.B       0xFF                     ; '\xFF'
+  0x300000C9:  FF           DC.B       0xFF                     ; '\xFF'
+  0x300000CA:  FF           DC.B       0xFF                     ; '\xFF'
+  0x300000CB:  FF           DC.B       0xFF                     ; '\xFF'
+  0x300000CC:  FF           DC.B       0xFF                     ; '\xFF'
+  0x300000CD:  FF           DC.B       0xFF                     ; '\xFF'
+  0x300000CE:  01           DC.B       0x01                     ; '\x01'
+  0x300000CF:  9F           DC.B       0x9F                     ; '\x9F'
+  0x300000D0:  93           DC.B       0x93                     ; '\x93'
+  0x300000D1:  01           DC.B       0x01                     ; '\x01'
+  0x300000D2:  30           DC.B       0x30                     ; '0'
+  0x300000D3:  9F           DC.B       0x9F                     ; '\x9F'
+  0x300000D4:  93           DC.B       0x93                     ; '\x93'
+  0x300000D5:  01           DC.B       0x01                     ; '\x01'
+  0x300000D6:  30           DC.B       0x30                     ; '0'
+  0x300000D7:  9F           DC.B       0x9F                     ; '\x9F'
+  0x300000D8:  93           DC.B       0x93                     ; '\x93'
+  0x300000D9:  01           DC.B       0x01                     ; '\x01'
+  0x300000DA:  31           DC.B       0x31                     ; '1'
+  0x300000DB:  9F           DC.B       0x9F                     ; '\x9F'
+  0x300000DC:  93           DC.B       0x93                     ; '\x93'
+  0x300000DD:  01           DC.B       0x01                     ; '\x01'
+  0x300000DE:  31           DC.B       0x31                     ; '1'
+  0x300000DF:  9F           DC.B       0x9F                     ; '\x9F'
+  0x300000E0:  93           DC.B       0x93                     ; '\x93'
+  0x300000E1:  01           DC.B       0x01                     ; '\x01'
+  0x300000E2:  30           DC.B       0x30                     ; '0'
+  0x300000E3:  9F           DC.B       0x9F                     ; '\x9F'
+  0x300000E4:  93           DC.B       0x93                     ; '\x93'
+  0x300000E5:  01           DC.B       0x01                     ; '\x01'
+  0x300000E6:  30           DC.B       0x30                     ; '0'
+  0x300000E7:  9F           DC.B       0x9F                     ; '\x9F'
+  0x300000E8:  93           DC.B       0x93                     ; '\x93'
+  0x300000E9:  01           DC.B       0x01                     ; '\x01'
+  0x300000EA:  00           DC.B       0x00                     ; '\0'
+  0x300000EB:  00           DC.B       0x00                     ; '\0'
+  0x300000EC:  00           DC.B       0x00                     ; '\0'
+  0x300000ED:  00           DC.B       0x00                     ; '\0'
+  0x300000EE:  00           DC.B       0x00                     ; '\0'
+  0x300000EF:  00           DC.B       0x00                     ; '\0'
+  0x300000F0:  00           DC.B       0x00                     ; '\0'
+  0x300000F1:  00           DC.B       0x00                     ; '\0'
+  0x300000F2:  90           DC.B       0x90                     ; '\x90'
+  0x300000F3:  00           DC.B       0x00                     ; '\0'
+  0x300000F4:  00           DC.B       0x00                     ; '\0'
+  0x300000F5:  00           DC.B       0x00                     ; '\0'
+  0x300000F6:  9A           DC.B       0x9A                     ; '\x9A'
+  0x300000F7:  00           DC.B       0x00                     ; '\0'
+  0x300000F8:  00           DC.B       0x00                     ; '\0'
+  0x300000F9:  00           DC.B       0x00                     ; '\0'
+  0x300000FA:  01           DC.B       0x01                     ; '\x01'
+  0x300000FB:  00           DC.B       0x00                     ; '\0'
+  0x300000FC:  51           DC.B       0x51                     ; 'Q'
+  0x300000FD:  00           DC.B       0x00                     ; '\0'
+  0x300000FE:  00           DC.B       0x00                     ; '\0'
+  0x300000FF:  00           DC.B       0x00                     ; '\0'
+
    +

    Section .bss.hrtc from charger_lto.o, size=36, align=4

    +
    +
    hrtc:
+  0x30000100:  00           DC.B       0x00                     ; '\0'
+  0x30000101:  00           DC.B       0x00                     ; '\0'
+  0x30000102:  00           DC.B       0x00                     ; '\0'
+  0x30000103:  00           DC.B       0x00                     ; '\0'
+  0x30000104:  00           DC.B       0x00                     ; '\0'
+  0x30000105:  00           DC.B       0x00                     ; '\0'
+  0x30000106:  00           DC.B       0x00                     ; '\0'
+  0x30000107:  00           DC.B       0x00                     ; '\0'
+  0x30000108:  01           DC.B       0x01                     ; '\x01'
+  0x30000109:  02           DC.B       0x02                     ; '\x02'
+  0x3000010A:  03           DC.B       0x03                     ; '\x03'
+  0x3000010B:  04           DC.B       0x04                     ; '\x04'
+  0x3000010C:  06           DC.B       0x06                     ; '\x06'
+  0x3000010D:  07           DC.B       0x07                     ; '\x07'
+  0x3000010E:  08           DC.B       0x08                     ; '\b'
+  0x3000010F:  09           DC.B       0x09                     ; '\t'
+  0x30000110:  00           DC.B       0x00                     ; '\0'
+  0x30000111:  90           DC.B       0x90                     ; '\x90'
+  0x30000112:  D0           DC.B       0xD0                     ; '\xD0'
+  0x30000113:  03           DC.B       0x03                     ; '\x03'
+  0x30000114:  0E           DC.B       0x0E                     ; '\x0E'
+  0x30000115:  00           DC.B       0x00                     ; '\0'
+  0x30000116:  00           DC.B       0x00                     ; '\0'
+  0x30000117:  00           DC.B       0x00                     ; '\0'
+  0x30000118:  1C           DC.B       0x1C                     ; '\x1C'
+  0x30000119:  00           DC.B       0x00                     ; '\0'
+  0x3000011A:  00           DC.B       0x00                     ; '\0'
+  0x3000011B:  00           DC.B       0x00                     ; '\0'
+  0x3000011C:  02           DC.B       0x02                     ; '\x02'
+  0x3000011D:  00           DC.B       0x00                     ; '\0'
+  0x3000011E:  31           DC.B       0x31                     ; '1'
+  0x3000011F:  9F           DC.B       0x9F                     ; '\x9F'
+  0x30000120:  1C           DC.B       0x1C                     ; '\x1C'
+  0x30000121:  00           DC.B       0x00                     ; '\0'
+  0x30000122:  00           DC.B       0x00                     ; '\0'
+  0x30000123:  00           DC.B       0x00                     ; '\0'

    Section .bss.uwTick from charger_lto.o, size=4, align=4

    -
    uwTick:
-  0x30000024:  00           DC.B       0x00                     ; '\0'
-  0x30000025:  00           DC.B       0x00                     ; '\0'
-  0x30000026:  00           DC.B       0x00                     ; '\0'
-  0x30000027:  00           DC.B       0x00                     ; '\0'
+
    uwTick:
+  0x30000124:  00           DC.B       0x00                     ; '\0'
+  0x30000125:  00           DC.B       0x00                     ; '\0'
+  0x30000126:  00           DC.B       0x00                     ; '\0'
+  0x30000127:  00           DC.B       0x00                     ; '\0'

    Section .bss.uwTickPrio from charger_lto.o, size=1, align=4

    -
    uwTickPrio:
-  0x30000028:  00           DC.B       0x00                     ; '\0'
+
    uwTickPrio:
+  0x30000128:  00           DC.B       0x00                     ; '\0'

    Section .data.SystemCoreClock from charger_lto.o, size=4, align=4

    -
    SystemCoreClock:
-  0x3000002C:  00           DC.B       0x00                     ; '\0'
-  0x3000002D:  90           DC.B       0x90                     ; '\x90'
-  0x3000002E:  D0           DC.B       0xD0                     ; '\xD0'
-  0x3000002F:  03           DC.B       0x03                     ; '\x03'
+
    SystemCoreClock:
+  0x3000012C:  00           DC.B       0x00                     ; '\0'
+  0x3000012D:  90           DC.B       0x90                     ; '\x90'
+  0x3000012E:  D0           DC.B       0xD0                     ; '\xD0'
+  0x3000012F:  03           DC.B       0x03                     ; '\x03'

    Section .bss.block.stack from [ Linker created ], size=8192, align=8

    @@ -9062,15 +12563,15 @@ Dedupe code - 286 + 282 Total: - 286 + 282

    LINK SUMMARY

    - 3 028 bytes read-only code + - 52 bytes read-only data = 3 080 bytes read-only (total) - 8 237 bytes read-write data + 9 034 bytes read-only code + + 52 bytes read-only data = 9 086 bytes read-only (total) + 8 493 bytes read-write data @@ -9087,6 +12588,6 @@ - - + + @@ -9095,6 +12596,6 @@ - - + + Index: /ctrl/firmware/Main/SES/charger.emProject =================================================================== --- /ctrl/firmware/Main/SES/charger.emProject (revision 44) +++ /ctrl/firmware/Main/SES/charger.emProject (revision 45) @@ -98,8 +98,11 @@ + + + @@ -107,4 +110,5 @@ +
    08000000-0807ffff 524 2883 080 0.59%521 208 99.41%9 086 1.73%515 202 98.27% 0 0.00%
    30000000-30007fff 32 7688 237 25.14%24 528 74.85%8 493 25.92%24 272 74.07% 3 0.01%