Index: /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c =================================================================== --- /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c (revision 44) +++ /ctrl/firmware/Main/CubeMX/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c (revision 44) @@ -0,0 +1,3935 @@ +/** + ****************************************************************************** + * @file stm32h7xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h7xx_hal.h" + +/** @addtogroup STM32H7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RCCEx_Private_defines RCCEx Private Defines + * @{ + */ +#define PLL2_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ +#define PLL3_TIMEOUT_VALUE PLL_TIMEOUT_VALUE /* 2 ms */ + +#define DIVIDER_P_UPDATE 0U +#define DIVIDER_Q_UPDATE 1U +#define DIVIDER_R_UPDATE 2U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider); +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register are set to their reset values. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*,SAI2A*, SAI2B*, SAI1, SPI123, + * USART234578, USART16 (USART16910*), RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC, + * SAI4A*, SAI4B*, SPI6, RTC). + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * (*) : Available on some STM32H7 lines only. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tmpreg; + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + + /*---------------------------- SPDIFRX configuration -------------------------------*/ + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + + switch (PeriphClkInit->SpdifrxClockSelection) + { + case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ + /* Enable PLL1Q Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + case RCC_SPDIFRXCLKSOURCE_HSI: + /* Internal OSC clock is used as source of SPDIFRX clock*/ + /* SPDIFRX clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPDIFRX clock*/ + __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SAI1 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + { + switch (PeriphClkInit->Sai1ClockSelection) + { + case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_PIN: + /* External clock is used as source of SAI1 clock*/ + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI1 clock*/ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(SAI3) + /*---------------------------- SAI2/3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) + { + switch (PeriphClkInit->Sai23ClockSelection) + { + case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_PIN: + /* External clock is used as source of SAI2/3 clock*/ + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI23CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ + /* SAI2/3 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2/3 clock*/ + __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) + /*---------------------------- SAI2A configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) + { + switch (PeriphClkInit->Sai2AClockSelection) + { + case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */ + /* Enable SAI2A Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_PIN: + /* External clock is used as source of SAI2A clock*/ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2ACLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI2A clock */ + /* SAI2A clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2A clock*/ + __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI2A*/ + +#if defined(RCC_CDCCIP1R_SAI2BSEL) + + /*---------------------------- SAI2B configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) + { + switch (PeriphClkInit->Sai2BClockSelection) + { + case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_PIN: + /* External clock is used as source of SAI2B clock*/ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + case RCC_SAI2BCLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI2B clock */ + /* SAI2B clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI2B clock*/ + __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI2B*/ + +#if defined(SAI4) + /*---------------------------- SAI4A configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) + { + switch (PeriphClkInit->Sai4AClockSelection) + { + case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_PIN: + /* External clock is used as source of SAI2 clock*/ + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4ACLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + +#if defined(RCC_VER_3_0) + case RCC_SAI4ACLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI4A clock */ + /* SAI4A clock source configuration done later after clock selection check */ + break; +#endif /* RCC_VER_3_0 */ + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI4A clock*/ + __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + /*---------------------------- SAI4B configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) + { + switch (PeriphClkInit->Sai4BClockSelection) + { + case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SAI1 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_PIN: + /* External clock is used as source of SAI2 clock*/ + /* SAI2 clock source configuration done later after clock selection check */ + break; + + case RCC_SAI4BCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; + +#if defined(RCC_VER_3_0) + case RCC_SAI4BCLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI4B clock */ + /* SAI4B clock source configuration done later after clock selection check */ + break; +#endif /* RCC_VER_3_0 */ + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SAI4B clock*/ + __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*SAI4*/ + +#if defined(QUADSPI) + /*---------------------------- QSPI configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) + { + switch (PeriphClkInit->QspiClockSelection) + { + case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ + /* Enable QSPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* QSPI clock source configuration done later after clock selection check */ + break; + + case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* QSPI clock source configuration done later after clock selection check */ + break; + + + case RCC_QSPICLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */ + /* QSPI clock source configuration done later after clock selection check */ + break; + + case RCC_QSPICLKSOURCE_D1HCLK: + /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of QSPI clock*/ + __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*QUADSPI*/ + +#if defined(OCTOSPI1) || defined(OCTOSPI2) + /*---------------------------- OCTOSPI configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) + { + switch (PeriphClkInit->OspiClockSelection) + { + case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ + /* Enable OSPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* OSPI clock source configuration done later after clock selection check */ + break; + + case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* OSPI clock source configuration done later after clock selection check */ + break; + + + case RCC_OSPICLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */ + /* OSPI clock source configuration done later after clock selection check */ + break; + + case RCC_OSPICLKSOURCE_HCLK: + /* HCLK clock selected as OSPI kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of OSPI clock*/ + __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*OCTOSPI*/ + + /*---------------------------- SPI1/2/3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) + { + switch (PeriphClkInit->Spi123ClockSelection) + { + case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ + /* Enable SPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_PIN: + /* External clock is used as source of SPI1/2/3 clock*/ + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI123CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI1/2/3 clock*/ + __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPI4/5 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) + { + switch (PeriphClkInit->Spi45ClockSelection) + { + case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for SPI4/5 */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of SPI4/5 clock*/ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of SPI4/5 clock */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI45CLKSOURCE_HSE: + /* HSE, oscillator is used as source of SPI4/5 clock */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI4/5 clock*/ + __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- SPI6 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) + { + switch (PeriphClkInit->Spi6ClockSelection) + { + case RCC_SPI6CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* SPI6 clock source configuration done later after clock selection check */ + break; + case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of SPI6 clock*/ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; + + case RCC_SPI6CLKSOURCE_HSE: + /* HSE, oscillator is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; +#if defined(RCC_SPI6CLKSOURCE_PIN) + case RCC_SPI6CLKSOURCE_PIN: + /* 2S_CKIN is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; +#endif + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SPI6 clock*/ + __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(DSI) + /*---------------------------- DSI configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) + { + switch (PeriphClkInit->DsiClockSelection) + { + + case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* DSI clock source configuration done later after clock selection check */ + break; + + case RCC_DSICLKSOURCE_PHY: + /* PHY is used as clock source for DSI*/ + /* DSI clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of DSI clock*/ + __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*DSI*/ + +#if defined(FDCAN1) || defined(FDCAN2) + /*---------------------------- FDCAN configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + { + switch (PeriphClkInit->FdcanClockSelection) + { + case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ + /* Enable FDCAN Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* FDCAN clock source configuration done later after clock selection check */ + break; + + case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + /* FDCAN clock source configuration done later after clock selection check */ + break; + + case RCC_FDCANCLKSOURCE_HSE: + /* HSE is used as clock source for FDCAN*/ + /* FDCAN clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of FDCAN clock*/ + __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } +#endif /*FDCAN1 || FDCAN2*/ + + /*---------------------------- FMC configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) + { + switch (PeriphClkInit->FmcClockSelection) + { + case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ + /* Enable FMC Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* FMC clock source configuration done later after clock selection check */ + break; + + case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* FMC clock source configuration done later after clock selection check */ + break; + + + case RCC_FMCCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of FMC clock */ + /* FMC clock source configuration done later after clock selection check */ + break; + + case RCC_FMCCLKSOURCE_HCLK: + /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of FMC clock*/ + __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- RTC configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + /* check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + + if (ret == HAL_OK) + { + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg; + } + + /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ + if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + ret = HAL_TIMEOUT; + break; + } + } + } + + if (ret == HAL_OK) + { + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + else + { + /* set overall return value */ + status = ret; + } + } + + + /*-------------------------- USART1/6 configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) + { + switch (PeriphClkInit->Usart16ClockSelection) + { + case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + case RCC_USART16CLKSOURCE_LSE: + /* LSE, oscillator is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART1/6 clock */ + __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) + { + switch (PeriphClkInit->Usart234578ClockSelection) + { + case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + case RCC_USART234578CLKSOURCE_LSE: + /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USART2/3/4/5/7/8 clock */ + __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*-------------------------- LPUART1 Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + { + switch (PeriphClkInit->Lpuart1ClockSelection) + { + case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPUART1CLKSOURCE_LSE: + /* LSE, oscillator is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPUART1 clock */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM1 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + switch (PeriphClkInit->Lptim1ClockSelection) + { + case RCC_LPTIM1CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for LPTIM1*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM1CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM1 clock*/ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM2 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) + { + switch (PeriphClkInit->Lptim2ClockSelection) + { + case RCC_LPTIM2CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM2CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM2CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM2 clock*/ + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*---------------------------- LPTIM345 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) + { + switch (PeriphClkInit->Lptim345ClockSelection) + { + + case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + case RCC_LPTIM345CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM345CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of LPTIM3/4/5 clock */ + __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/ +#if defined(I2C5) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection)); + + if ((PeriphClkInit->I2c1235ClockSelection) == RCC_I2C1235CLKSOURCE_PLL3) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); + + } +#else + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); + + if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); + + } +#endif /* I2C5 */ + + /*------------------------------ I2C4 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } + + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + + } + + /*---------------------------- ADC configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + switch (PeriphClkInit->AdcClockSelection) + { + + case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + /* ADC clock source configuration done later after clock selection check */ + break; + + case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + /* ADC clock source configuration done later after clock selection check */ + break; + + case RCC_ADCCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ + /* ADC clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of ADC clock*/ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + + /*------------------------------ USB Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + { + + switch (PeriphClkInit->UsbClockSelection) + { + case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ + /* Enable USB Clock output generated form System USB . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* USB clock source configuration done later after clock selection check */ + break; + + case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ + + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + + /* USB clock source configuration done later after clock selection check */ + break; + + case RCC_USBCLKSOURCE_HSI48: + /* HSI48 oscillator is used as source of USB clock */ + /* USB clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of USB clock*/ + __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*------------------------------------- SDMMC Configuration ------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); + + switch (PeriphClkInit->SdmmcClockSelection) + { + case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ + /* Enable SDMMC Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* SDMMC clock source configuration done later after clock selection check */ + break; + + case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ + + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + /* SDMMC clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of SDMMC clock*/ + __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + } + +#if defined(LTDC) + /*-------------------------------------- LTDC Configuration -----------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } + } +#endif /* LTDC */ + + /*------------------------------ RNG Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) + { + + switch (PeriphClkInit->RngClockSelection) + { + case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ + /* Enable RNG Clock output generated form System RNG . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + + /* RNG clock source configuration done later after clock selection check */ + break; + + case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/ + + /* RNG clock source configuration done later after clock selection check */ + break; + + case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/ + + /* RNG clock source configuration done later after clock selection check */ + break; + case RCC_RNGCLKSOURCE_HSI48: + /* HSI48 oscillator is used as source of RNG clock */ + /* RNG clock source configuration done later after clock selection check */ + break; + + default: + ret = HAL_ERROR; + break; + } + + if (ret == HAL_OK) + { + /* Set the source of RNG clock*/ + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + } + else + { + /* set overall return value */ + status = ret; + } + + } + + /*------------------------------ SWPMI1 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) + { + /* Check the parameters */ + assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); + + /* Configure the SWPMI1 interface clock source */ + __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); + } +#if defined(HRTIM1) + /*------------------------------ HRTIM1 clock Configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); + + /* Configure the HRTIM1 clock source */ + __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); + } +#endif /*HRTIM1*/ + /*------------------------------ DFSDM1 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + } + +#if defined(DFSDM2_BASE) + /*------------------------------ DFSDM2 Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); + + /* Configure the DFSDM2 interface clock source */ + __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection); + } +#endif /* DFSDM2 */ + + /*------------------------------------ TIM configuration --------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + + /*------------------------------------ CKPER configuration --------------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) + { + /* Check the parameters */ + assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); + + /* Configure the CKPER clock source */ + __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); + } + + /*------------------------------ CEC Configuration ------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC interface clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + + /*---------------------------- PLL2 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + /*---------------------------- PLL3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + if (status == HAL_OK) + { + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. + * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for the Extended Peripherals clocks : + * (SDMMC, CKPER, FMC, QSPI*, OSPI*, DSI*, SPI45, SPDIF, DFSDM1, DFSDM2*, FDCAN, SWPMI, SAI23*, SAI1, SPI123, + * USART234578, USART16, RNG, HRTIM1*, I2C123 (I2C1235*), USB, CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC. + * SAI4A*, SAI4B*, SPI6, RTC, TIM). + * @retval None + * + * (*) : Available on some STM32H7 lines only. + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = + RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 | + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | + RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | + RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM | + RCC_PERIPHCLK_CKPER; + +#if defined(I2C5) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235; +#else + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123; +#endif /*I2C5*/ +#if defined(RCC_CDCCIP1R_SAI2ASEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A; +#endif /* RCC_CDCCIP1R_SAI2ASEL */ +#if defined(RCC_CDCCIP1R_SAI2BSEL) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B; +#endif /* RCC_CDCCIP1R_SAI2BSEL */ +#if defined(SAI3) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23; +#endif /* SAI3 */ +#if defined(SAI4) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4A; + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI4B; +#endif /* SAI4 */ +#if defined(DFSDM2_BASE) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DFSDM2; +#endif /* DFSDM2 */ +#if defined(QUADSPI) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_QSPI; +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_OSPI; +#endif /* OCTOSPI1 || OCTOSPI2 */ +#if defined(HRTIM1) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1; +#endif /* HRTIM1 */ +#if defined(LTDC) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC; +#endif /* LTDC */ +#if defined(DSI) + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_DSI; +#endif /* DSI */ + + /* Get the PLL3 Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); + PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos); + PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos); + + /* Get the PLL2 Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos); + PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos); + PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos); + + /* Get the USART1 configuration --------------------------------------------*/ + PeriphClkInit->Usart16ClockSelection = __HAL_RCC_GET_USART16_SOURCE(); + /* Get the USART2/3/4/5/7/8 clock source -----------------------------------*/ + PeriphClkInit->Usart234578ClockSelection = __HAL_RCC_GET_USART234578_SOURCE(); + /* Get the LPUART1 clock source --------------------------------------------*/ + PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); +#if defined(I2C5) + /* Get the I2C1/2/3/5 clock source -----------------------------------------*/ + PeriphClkInit->I2c1235ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#else + /* Get the I2C1/2/3 clock source -------------------------------------------*/ + PeriphClkInit->I2c123ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#endif /*I2C5*/ + /* Get the LPTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + /* Get the LPTIM2 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); + /* Get the LPTIM3/4/5 clock source -----------------------------------------*/ + PeriphClkInit->Lptim345ClockSelection = __HAL_RCC_GET_LPTIM345_SOURCE(); + /* Get the SAI1 clock source -----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); +#if defined(SAI3) + /* Get the SAI2/3 clock source ---------------------------------------------*/ + PeriphClkInit->Sai23ClockSelection = __HAL_RCC_GET_SAI23_SOURCE(); +#endif /*SAI3*/ +#if defined(RCC_CDCCIP1R_SAI2ASEL_0) + /* Get the SAI2A clock source ---------------------------------------------*/ + PeriphClkInit->Sai2AClockSelection = __HAL_RCC_GET_SAI2A_SOURCE(); +#endif /*SAI2A*/ +#if defined(RCC_CDCCIP1R_SAI2BSEL_0) + /* Get the SAI2B clock source ---------------------------------------------*/ + PeriphClkInit->Sai2BClockSelection = __HAL_RCC_GET_SAI2B_SOURCE(); +#endif /*SAI2B*/ +#if defined(SAI4) + /* Get the SAI4A clock source ----------------------------------------------*/ + PeriphClkInit->Sai4AClockSelection = __HAL_RCC_GET_SAI4A_SOURCE(); + /* Get the SAI4B clock source ----------------------------------------------*/ + PeriphClkInit->Sai4BClockSelection = __HAL_RCC_GET_SAI4B_SOURCE(); +#endif /*SAI4*/ + /* Get the RTC clock source ------------------------------------------------*/ + PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + /* Get the USB clock source ------------------------------------------------*/ + PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); + /* Get the SDMMC clock source ----------------------------------------------*/ + PeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE(); + /* Get the RNG clock source ------------------------------------------------*/ + PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); +#if defined(HRTIM1) + /* Get the HRTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE(); +#endif /* HRTIM1 */ + /* Get the ADC clock source ------------------------------------------------*/ + PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); + /* Get the SWPMI1 clock source ---------------------------------------------*/ + PeriphClkInit->Swpmi1ClockSelection = __HAL_RCC_GET_SWPMI1_SOURCE(); + /* Get the DFSDM1 clock source ---------------------------------------------*/ + PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); +#if defined(DFSDM2_BASE) + /* Get the DFSDM2 clock source ---------------------------------------------*/ + PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE(); +#endif /* DFSDM2 */ + /* Get the SPDIFRX clock source --------------------------------------------*/ + PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE(); + /* Get the SPI1/2/3 clock source -------------------------------------------*/ + PeriphClkInit->Spi123ClockSelection = __HAL_RCC_GET_SPI123_SOURCE(); + /* Get the SPI4/5 clock source ---------------------------------------------*/ + PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE(); + /* Get the SPI6 clock source -----------------------------------------------*/ + PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE(); + /* Get the FDCAN clock source ----------------------------------------------*/ + PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE(); + /* Get the CEC clock source ------------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + /* Get the FMC clock source ------------------------------------------------*/ + PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE(); +#if defined(QUADSPI) + /* Get the QSPI clock source -----------------------------------------------*/ + PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE(); +#endif /* QUADSPI */ +#if defined(OCTOSPI1) || defined(OCTOSPI2) + /* Get the OSPI clock source -----------------------------------------------*/ + PeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); +#endif /* OCTOSPI1 || OCTOSPI2 */ + +#if defined(DSI) + /* Get the DSI clock source ------------------------------------------------*/ + PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); +#endif /*DSI*/ + + /* Get the CKPER clock source ----------------------------------------------*/ + PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE(); + + /* Get the TIM Prescaler configuration -------------------------------------*/ + if ((RCC->CFGR & RCC_CFGR_TIMPRE) == 0U) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk: Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_SAI1 : SAI1 peripheral clock + * @arg RCC_PERIPHCLK_SAI23 : SAI2/3 peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI2A : SAI2A peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI2B : SAI2B peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI4A : SAI4A peripheral clock (*) + * @arg RCC_PERIPHCLK_SAI4B : SAI4B peripheral clock (*) + * @arg RCC_PERIPHCLK_SPI123: SPI1/2/3 peripheral clock + * @arg RCC_PERIPHCLK_ADC : ADC peripheral clock + * @arg RCC_PERIPHCLK_SDMMC : SDMMC peripheral clock + * @arg RCC_PERIPHCLK_SPI6 : SPI6 peripheral clock + * @retval Frequency in KHz + * + * (*) : Available on some STM32H7 lines only. + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) +{ + PLL1_ClocksTypeDef pll1_clocks; + PLL2_ClocksTypeDef pll2_clocks; + PLL3_ClocksTypeDef pll3_clocks; + + /* This variable is used to store the clock frequency (value in Hz) */ + uint32_t frequency; + /* This variable is used to store the SAI and CKP clock source */ + uint32_t saiclocksource; + uint32_t ckpclocksource; + uint32_t srcclk; + + if (PeriphClk == RCC_PERIPHCLK_SAI1) + { + + saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } + +#if defined(SAI3) + else if (PeriphClk == RCC_PERIPHCLK_SAI23) + { + + saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } +#endif /* SAI3 */ + +#if defined(RCC_CDCCIP1R_SAI2ASEL) + + else if (PeriphClk == RCC_PERIPHCLK_SAI2A) + { + saiclocksource = __HAL_RCC_GET_SAI2A_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + + } +#endif + +#if defined(RCC_CDCCIP1R_SAI2BSEL_0) + else if (PeriphClk == RCC_PERIPHCLK_SAI2B) + { + + saiclocksource = __HAL_RCC_GET_SAI2B_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + break; + } + + case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } +#endif + +#if defined(SAI4) + else if (PeriphClk == RCC_PERIPHCLK_SAI4A) + { + + saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } + + else if (PeriphClk == RCC_PERIPHCLK_SAI4B) + { + + saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); + + switch (saiclocksource) + { + case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } +#endif /*SAI4*/ + else if (PeriphClk == RCC_PERIPHCLK_SPI123) + { + /* Get SPI1/2/3 clock source */ + srcclk = __HAL_RCC_GET_SPI123_SOURCE(); + + switch (srcclk) + { + case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI45) + { + /* Get SPI45 clock source */ + srcclk = __HAL_RCC_GET_SPI45_SOURCE(); + switch (srcclk) + { + case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + break; + } + case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) + { + frequency = CSI_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_ADC) + { + /* Get ADC clock source */ + srcclk = __HAL_RCC_GET_ADC_SOURCE(); + + switch (srcclk) + { + case RCC_ADCCLKSOURCE_PLL2: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_ADCCLKSOURCE_PLL3: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_R_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_ADCCLKSOURCE_CLKP: + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SDMMC) + { + /* Get SDMMC clock source */ + srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); + + switch (srcclk) + { + case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + } + else + { + frequency = 0; + } + break; + } + + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI6) + { + /* Get SPI6 clock source */ + srcclk = __HAL_RCC_GET_SPI6_SOURCE(); + + switch (srcclk) + { + case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ + { + frequency = HAL_RCCEx_GetD3PCLK1Freq(); + break; + } + case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) + { + frequency = CSI_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } +#if defined(RCC_SPI6CLKSOURCE_PIN) + case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } +#endif /* RCC_SPI6CLKSOURCE_PIN */ + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_FDCAN) + { + /* Get FDCAN clock source */ + srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); + + switch (srcclk) + { + case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + default : + { + frequency = 0; + break; + } + } + } + else + { + frequency = 0; + } + + return frequency; +} + + +/** + * @brief Returns the D1PCLK1 frequency + * @note Each time D1PCLK1 changes, this function must be called to update the + * right D1PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval D1PCLK1 frequency + */ +uint32_t HAL_RCCEx_GetD1PCLK1Freq(void) +{ +#if defined(RCC_D1CFGR_D1PPRE) + /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU)); +#else + /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU)); +#endif +} + +/** + * @brief Returns the D3PCLK1 frequency + * @note Each time D3PCLK1 changes, this function must be called to update the + * right D3PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval D3PCLK1 frequency + */ +uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) +{ +#if defined(RCC_D3CFGR_D3PPRE) + /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); +#else + /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); +#endif +} +/** +* @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency + * @note The PLL2 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL2CLK changes, this function must be called to update the + * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL2_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) +{ + uint32_t pllsource, pll2m, pll2fracen, hsivalue; + float_t fracn2, pll2vco; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N + PLL2xCLK = PLL2_VCO / PLL2x + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); + pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; + fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); + + if (pll2m != 0U) + { + switch (pllsource) + { + + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + } + else + { + pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + } + break; + + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; + } + PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; + PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; + PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; + } + else + { + PLL2_Clocks->PLL2_P_Frequency = 0U; + PLL2_Clocks->PLL2_Q_Frequency = 0U; + PLL2_Clocks->PLL2_R_Frequency = 0U; + } +} + +/** +* @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency + * @note The PLL3 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL3CLK changes, this function must be called to update the + * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL3_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) +{ + uint32_t pllsource, pll3m, pll3fracen, hsivalue; + float_t fracn3, pll3vco; + + /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N + PLL3xCLK = PLL3_VCO / PLLxR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; + pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; + fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); + + if (pll3m != 0U) + { + switch (pllsource) + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + } + else + { + pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + } + break; + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; + } + PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; + PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; + PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; + } + else + { + PLL3_Clocks->PLL3_P_Frequency = 0U; + PLL3_Clocks->PLL3_Q_Frequency = 0U; + PLL3_Clocks->PLL3_R_Frequency = 0U; + } + +} + +/** +* @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency + * @note The PLL1 clock frequencies computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * + * @note Each time PLL1CLK changes, this function must be called to update the + * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. + * @param PLL1_Clocks structure. + * @retval None + */ +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) +{ + uint32_t pllsource, pll1m, pll1fracen, hsivalue; + float_t fracn1, pll1vco; + + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); + pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; + fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); + + if (pll1m != 0U) + { + switch (pllsource) + { + + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + else + { + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + break; + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + + default: + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + + PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; + PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; + PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; + } + else + { + PLL1_Clocks->PLL1_P_Frequency = 0U; + PLL1_Clocks->PLL1_Q_Frequency = 0U; + PLL1_Clocks->PLL1_R_Frequency = 0U; + } + +} + +/** + * @brief Returns the main System frequency + * @note Each time System clock changes, this function must be called to update the + * right core clock value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System current Core Clock Frequency + * and updated within this function + * @retval HCLK frequency + */ +uint32_t HAL_RCCEx_GetD1SysClockFreq(void) +{ + uint32_t common_system_clock; + +#if defined(RCC_D1CFGR_D1CPRE) + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); +#else + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); +#endif + + /* Update the SystemD2Clock global variable */ +#if defined(RCC_D1CFGR_HPRE) + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); +#else + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); +#endif + +#if defined(DUAL_CORE) && defined(CORE_CM4) + SystemCoreClock = SystemD2Clock; +#else + SystemCoreClock = common_system_clock; +#endif /* DUAL_CORE && CORE_CM4 */ + + return common_system_clock; +} +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended System Control functions + * @brief Extended Peripheral Control functions + * @{ + */ +/** + * @brief Enables the LSE Clock Security System. + * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled + * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC + * clock with HAL_RCCEx_PeriphCLKConfig(). + * @retval None + */ +void HAL_RCCEx_EnableLSECSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; +} + +/** + * @brief Disables the LSE Clock Security System. + * @note LSE Clock Security System can only be disabled after a LSE failure detection. + * @retval None + */ +void HAL_RCCEx_DisableLSECSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + /* Disable LSE CSS IT if any */ + __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); +} + +/** + * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. + * @note LSE Clock Security System Interrupt is mapped on EXTI line 18 + * @retval None + */ +void HAL_RCCEx_EnableLSECSS_IT(void) +{ + /* Enable LSE CSS */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; + + /* Enable LSE CSS IT */ + __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); + + /* Enable IT on EXTI Line 18 */ +#if defined(DUAL_CORE) && defined(CORE_CM4) + __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT(); +#else + __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); +#endif /* DUAL_CORE && CORE_CM4 */ + __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); +} + +/** + * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock + * @param WakeUpClk: Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI oscillator selection + * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI oscillator selection + * @note This function shall not be called after the Clock Security System on HSE has been + * enabled. + * @retval None + */ +void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +/** + * @brief Configure the oscillator Kernel clock source for wakeup from Stop + * @param WakeUpClk: Kernel Wakeup clock + * This parameter can be one of the following values: + * @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI oscillator selection + * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection + * @retval None + */ +void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk) +{ + assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk)); + + __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk); +} + +#if defined(DUAL_CORE) +/** + * @brief Enable COREx boot independently of CMx_B option byte value + * @param RCC_BootCx: Boot Core to be enabled + * This parameter can be one of the following values: + * @arg RCC_BOOT_C1: CM7 core selection + * @arg RCC_BOOT_C2: CM4 core selection + * @note This bit can be set by software but is cleared by hardware after a system reset or STANDBY + * + * @retval None + */ +void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx) +{ + assert_param(IS_RCC_BOOT_CORE(RCC_BootCx)); + SET_BIT(RCC->GCR, RCC_BootCx) ; +} + +#endif /*DUAL_CORE*/ + +#if defined(DUAL_CORE) +/** + * @brief Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs + * @param RCC_WWDGx: WWDGx to be configured + * This parameter can be one of the following values: + * @arg RCC_WWDG1: WWDG1 generates system reset + * @arg RCC_WWDG2: WWDG2 generates system reset + * @note This bit can be set by software but is cleared by hardware during a system reset + * + * @retval None + */ +void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) +{ + assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); + SET_BIT(RCC->GCR, RCC_WWDGx) ; +} + +#else +#if defined(RCC_GCR_WW1RSC) +/** + * @brief Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs + * @param RCC_WWDGx: WWDGx to be configured + * This parameter can be one of the following values: + * @arg RCC_WWDG1: WWDG1 generates system reset + * @note This bit can be set by software but is cleared by hardware during a system reset + * + * @retval None + */ +void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx) +{ + assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx)); + SET_BIT(RCC->GCR, RCC_WWDGx) ; +} +#endif +#endif /*DUAL_CORE*/ + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions + * @brief Extended Clock Recovery System Control functions + * +@verbatim + =============================================================================== + ##### Extended Clock Recovery System Control functions ##### + =============================================================================== + [..] + For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: + + (#) In System clock config, HSI48 needs to be enabled + + (#) Enable CRS clock in IP MSP init which will use CRS functions + + (#) Call CRS functions as follows: + (##) Prepare synchronization configuration necessary for HSI48 calibration + (+++) Default values can be set for frequency Error Measurement (reload and error limit) + and also HSI48 oscillator smooth trimming. + (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate + directly reload value with target and synchronization frequencies values + (##) Call function HAL_RCCEx_CRSConfig which + (+++) Resets CRS registers to their default values. + (+++) Configures CRS registers with synchronization configuration + (+++) Enables automatic calibration and frequency error counter feature + Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the + periodic USB SOF will not be generated by the host. No SYNC signal will therefore be + provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock + precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs + should be used as SYNC signal. + + (##) A polling function is provided to wait for complete synchronization + (+++) Call function HAL_RCCEx_CRSWaitSynchronization() + (+++) According to CRS status, user can decide to adjust again the calibration or continue + application if synchronization is OK + + (#) User can retrieve information related to synchronization in calling function + HAL_RCCEx_CRSGetSynchronizationInfo() + + (#) Regarding synchronization status and synchronization information, user can try a new calibration + in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. + Note: When the SYNC event is detected during the down-counting phase (before reaching the zero value), + it means that the actual frequency is lower than the target (and so, that the TRIM value should be + incremented), while when it is detected during the up-counting phase it means that the actual frequency + is higher (and that the TRIM value should be decremented). + + (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go + through CRS Handler (CRS_IRQn/CRS_IRQHandler) + (++) Call function HAL_RCCEx_CRSConfig() + (++) Enable CRS_IRQn (thanks to NVIC functions) + (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) + (++) Implement CRS status management in the following user callbacks called from + HAL_RCCEx_CRS_IRQHandler(): + (+++) HAL_RCCEx_CRS_SyncOkCallback() + (+++) HAL_RCCEx_CRS_SyncWarnCallback() + (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() + (+++) HAL_RCCEx_CRS_ErrorCallback() + + (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). + This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) + +@endverbatim + * @{ + */ + +/** + * @brief Start automatic synchronization for polling mode + * @param pInit Pointer on RCC_CRSInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit) +{ + uint32_t value; + + /* Check the parameters */ + assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); + assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); + assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); + assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); + assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); + assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); + + /* CONFIGURATION */ + + /* Before configuration, reset CRS registers to their default values*/ + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); + + /* Set the SYNCDIV[2:0] bits according to Pre-scaler value */ + /* Set the SYNCSRC[1:0] bits according to Source value */ + /* Set the SYNCSPOL bit according to Polarity value */ + if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2)) + { + /* Use Rev.Y value of USB2 */ + value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity); + } + else + { + value = (pInit->Prescaler | pInit->Source | pInit->Polarity); + } + /* Set the RELOAD[15:0] bits according to ReloadValue value */ + value |= pInit->ReloadValue; + /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ + value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); + WRITE_REG(CRS->CFGR, value); + + /* Adjust HSI48 oscillator smooth trimming */ + /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); + + /* START AUTOMATIC SYNCHRONIZATION*/ + + /* Enable Automatic trimming & Frequency error counter */ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); +} + +/** + * @brief Generate the software synchronization event + * @retval None + */ +void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Return synchronization info + * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure + * @retval None + */ +void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) +{ + /* Check the parameter */ + assert_param(pSynchroInfo != (void *)NULL); + + /* Get the reload value */ + pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); + + /* Get HSI48 oscillator smooth trimming */ + pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); + + /* Get Frequency error capture */ + pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); + + /* Get Frequency error direction */ + pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** +* @brief Wait for CRS Synchronization status. +* @param Timeout Duration of the time-out +* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization +* frequency. +* @note If Time-out set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. +* @retval Combination of Synchronization status +* This parameter can be a combination of the following values: +* @arg @ref RCC_CRS_TIMEOUT +* @arg @ref RCC_CRS_SYNCOK +* @arg @ref RCC_CRS_SYNCWARN +* @arg @ref RCC_CRS_SYNCERR +* @arg @ref RCC_CRS_SYNCMISS +* @arg @ref RCC_CRS_TRIMOVF +*/ +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +{ + uint32_t crsstatus = RCC_CRS_NONE; + uint32_t tickstart; + + /* Get time-out */ + tickstart = HAL_GetTick(); + + /* Wait for CRS flag or time-out detection */ + do + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + crsstatus = RCC_CRS_TIMEOUT; + } + } + /* Check CRS SYNCOK flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + { + /* CRS SYNC event OK */ + crsstatus |= RCC_CRS_SYNCOK; + + /* Clear CRS SYNC event OK bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); + } + + /* Check CRS SYNCWARN flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + { + /* CRS SYNC warning */ + crsstatus |= RCC_CRS_SYNCWARN; + + /* Clear CRS SYNCWARN bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); + } + + /* Check CRS TRIM overflow flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_TRIMOVF; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); + } + + /* Check CRS Error flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + { + /* CRS SYNC Error */ + crsstatus |= RCC_CRS_SYNCERR; + + /* Clear CRS Error bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); + } + + /* Check CRS SYNC Missed flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + { + /* CRS SYNC Missed */ + crsstatus |= RCC_CRS_SYNCMISS; + + /* Clear CRS SYNC Missed bit */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); + } + + /* Check CRS Expected SYNC flag */ + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + { + /* frequency error counter reached a zero value */ + __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); + } + } + while (RCC_CRS_NONE == crsstatus); + + return crsstatus; +} + +/** + * @brief Handle the Clock Recovery System interrupt request. + * @retval None + */ +void HAL_RCCEx_CRS_IRQHandler(void) +{ + uint32_t crserror = RCC_CRS_NONE; + /* Get current IT flags and IT sources values */ + uint32_t itflags = READ_REG(CRS->ISR); + uint32_t itsources = READ_REG(CRS->CR); + + /* Check CRS SYNCOK flag */ + if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) + { + /* Clear CRS SYNC event OK flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); + + /* user callback */ + HAL_RCCEx_CRS_SyncOkCallback(); + } + /* Check CRS SYNCWARN flag */ + else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) + { + /* Clear CRS SYNCWARN flag */ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); + + /* user callback */ + HAL_RCCEx_CRS_SyncWarnCallback(); + } + /* Check CRS Expected SYNC flag */ + else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) + { + /* frequency error counter reached a zero value */ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); + + /* user callback */ + HAL_RCCEx_CRS_ExpectedSyncCallback(); + } + /* Check CRS Error flags */ + else + { + if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) + { + if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) + { + crserror |= RCC_CRS_SYNCERR; + } + if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) + { + crserror |= RCC_CRS_SYNCMISS; + } + if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) + { + crserror |= RCC_CRS_TRIMOVF; + } + + /* Clear CRS Error flags */ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); + + /* user error callback */ + HAL_RCCEx_CRS_ErrorCallback(crserror); + } + } +} + +/** + * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncOkCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file + */ +} + +/** + * @brief RCCEx Clock Recovery System Error interrupt callback. + * @param Error Combination of Error status. + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + * @retval none + */ +__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Error); + + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file + */ +} + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCCEx_Private_functions RCCEx Private Functions + * @{ + */ +/** + * @brief Configure the PLL2 VCI,VCO ranges, multiplication and division factors and enable it + * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that + * contains the configuration parameters as well as VCI, VCO clock ranges. + * @param Divider divider parameter to be updated + * @note PLL2 is temporary disabled to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider) +{ + + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_RCC_PLL2M_VALUE(pll2->PLL2M)); + assert_param(IS_RCC_PLL2N_VALUE(pll2->PLL2N)); + assert_param(IS_RCC_PLL2P_VALUE(pll2->PLL2P)); + assert_param(IS_RCC_PLL2R_VALUE(pll2->PLL2R)); + assert_param(IS_RCC_PLL2Q_VALUE(pll2->PLL2Q)); + assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE)); + assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL)); + assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); + + /* Check that PLL2 OSC clock source is already set */ + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) + { + return HAL_ERROR; + } + + + else + { + /* Disable PLL2. */ + __HAL_RCC_PLL2_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure PLL2 multiplication and division factors. */ + __HAL_RCC_PLL2_CONFIG(pll2->PLL2M, + pll2->PLL2N, + pll2->PLL2P, + pll2->PLL2Q, + pll2->PLL2R); + + /* Select PLL2 input reference frequency range: VCI */ + __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ; + + /* Select PLL2 output frequency range : VCO */ + __HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ; + + /* Disable PLL2FRACN . */ + __HAL_RCC_PLL2FRACN_DISABLE(); + + /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ + __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); + + /* Enable PLL2FRACN . */ + __HAL_RCC_PLL2FRACN_ENABLE(); + + /* Enable the PLL2 clock output */ + if (Divider == DIVIDER_P_UPDATE) + { + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); + } + else if (Divider == DIVIDER_Q_UPDATE) + { + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); + } + else + { + __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR); + } + + /* Enable PLL2. */ + __HAL_RCC_PLL2_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL2 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + } + + + return status; +} + + +/** + * @brief Configure the PLL3 VCI,VCO ranges, multiplication and division factors and enable it + * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that + * contains the configuration parameters as well as VCI, VCO clock ranges. + * @param Divider divider parameter to be updated + * @note PLL3 is temporary disabled to apply new parameters + * + * @retval HAL status + */ +static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_RCC_PLL3M_VALUE(pll3->PLL3M)); + assert_param(IS_RCC_PLL3N_VALUE(pll3->PLL3N)); + assert_param(IS_RCC_PLL3P_VALUE(pll3->PLL3P)); + assert_param(IS_RCC_PLL3R_VALUE(pll3->PLL3R)); + assert_param(IS_RCC_PLL3Q_VALUE(pll3->PLL3Q)); + assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE)); + assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL)); + assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); + + /* Check that PLL3 OSC clock source is already set */ + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) + { + return HAL_ERROR; + } + + + else + { + /* Disable PLL3. */ + __HAL_RCC_PLL3_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait till PLL3 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the PLL3 multiplication and division factors. */ + __HAL_RCC_PLL3_CONFIG(pll3->PLL3M, + pll3->PLL3N, + pll3->PLL3P, + pll3->PLL3Q, + pll3->PLL3R); + + /* Select PLL3 input reference frequency range: VCI */ + __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ; + + /* Select PLL3 output frequency range : VCO */ + __HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ; + + /* Disable PLL3FRACN . */ + __HAL_RCC_PLL3FRACN_DISABLE(); + + /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ + __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); + + /* Enable PLL3FRACN . */ + __HAL_RCC_PLL3FRACN_ENABLE(); + + /* Enable the PLL3 clock output */ + if (Divider == DIVIDER_P_UPDATE) + { + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); + } + else if (Divider == DIVIDER_Q_UPDATE) + { + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); + } + else + { + __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR); + } + + /* Enable PLL3. */ + __HAL_RCC_PLL3_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL3 is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + } + + + return status; +} + +/** + * @brief Handle the RCC LSE Clock Security System interrupt request. + * @retval None + */ +void HAL_RCCEx_LSECSS_IRQHandler(void) +{ + /* Check RCC LSE CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + { + + /* Clear RCC LSE CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); + + /* RCC LSE Clock Security System interrupt user callback */ + HAL_RCCEx_LSECSS_Callback(); + + } +} + +/** + * @brief RCCEx LSE Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCCEx_LSECSS_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file + */ +} + + + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + Index: /ctrl/firmware/Main/SES/Output/Release/Exe/charger.hex =================================================================== --- /ctrl/firmware/Main/SES/Output/Release/Exe/charger.hex (revision 43) +++ /ctrl/firmware/Main/SES/Output/Release/Exe/charger.hex (revision 44) @@ -1,48 +1,48 @@ :020000040800F2 -:10000000008000306F08000895050008950500087D -:1000100095050008950500089505000800000000FA -:10002000000000000000000000000000970500082C -:10003000970500080000000097050008DF0700088A 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/ctrl/firmware/Main/SES/Output/Release/Exe/charger.htm =================================================================== --- /ctrl/firmware/Main/SES/Output/Release/Exe/charger.htm (revision 43) +++ /ctrl/firmware/Main/SES/Output/Release/Exe/charger.htm (revision 44) @@ -122,10 +122,12 @@
  • Section .text.HAL_RCC_GetSysClockFreq from charger_lto.o, size=268, align=4
  • Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4
    • -
  • Section .text.main from charger_lto.o, size=258, align=2
    • +
  • Section .text.SystemClock_Config() from charger_lto.o, size=794, align=2
  • Section .text.SystemInit from charger_lto.o, size=166, align=2
  • Section .text.NMI_Handler from charger_lto.o, size=2, align=2
  • Section .text.SVC_Handler from charger_lto.o, size=2, align=2
  • Section .text.HAL_Init from charger_lto.o, size=114, align=2
    • -
  • Section .text.SystemClock_Config() from charger_lto.o, size=468, align=2
    • +
  • Section .text.HAL_RTC_Init from charger_lto.o, size=382, align=2
    • +
  • Section .text.HAL_RTC_WaitForSynchro from charger_lto.o, size=54, align=2
    • +
  • Section .text.main from charger_lto.o, size=304, align=2
  • Section .text.SysTick_Handler from charger_lto.o, size=16, align=2
  • Section .text.HAL_InitTick from charger_lto.o, size=128, align=2
    • @@ -136,4 +138,5 @@
  • Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v7em_fpv5_d16_hard_t_le_eabi_balanced.a), size=18, align=2
  • Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v7em_fpv5_d16_hard_t_le_eabi_balanced.a), size=20, align=2
    • +
  • Section .bss.hrtc from charger_lto.o, size=36, align=4
  • Section .bss.uwTick from charger_lto.o, size=4, align=4
  • Section .bss.uwTickPrio from charger_lto.o, size=1, align=4
    • @@ -414,48 +417,64 @@ + SystemClock_Config() + Code + 0x080003EC + 794 + 2 + charger_lto.o + + + SystemInit + Code + 0x08000706 + 166 + 2 + charger_lto.o + + + NMI_Handler + Code + 0x080007AC + 2 + 2 + charger_lto.o + + + SVC_Handler + Code + 0x080007AE + 2 + 2 + charger_lto.o + + + HAL_Init + Code + 0x080007B0 + 114 + 2 + charger_lto.o + + + HAL_RTC_Init + Code + 0x08000822 + 382 + 2 + charger_lto.o + + + HAL_RTC_WaitForSynchro + Code + 0x080009A0 + 54 + 2 + charger_lto.o + + main Code - 0x080003EC - 258 - 2 - charger_lto.o - - - SystemInit - Code - 0x080004EE - 166 - 2 - charger_lto.o - - - NMI_Handler - Code - 0x08000594 - 2 - 2 - charger_lto.o - - - SVC_Handler - Code - 0x08000596 - 2 - 2 - charger_lto.o - - - HAL_Init - Code - 0x08000598 - 114 - 2 - charger_lto.o - - - SystemClock_Config() - Code - 0x0800060A - 468 + 0x080009D6 + 304 2 charger_lto.o @@ -464,5 +483,5 @@ SysTick_Handler Code - 0x080007DE + 0x08000B06 16 2 @@ -472,5 +491,5 @@ HAL_InitTick Code - 0x080007EE + 0x08000B16 128 2 @@ -480,5 +499,5 @@ Reset_Handler Code - 0x0800086E + 0x08000B96 24 2 @@ -488,5 +507,5 @@ D1CorePrescTable Cnst - 0x08000886 + 0x08000BAE 16 1 @@ -496,5 +515,5 @@ [.rodata.block.tdata.copy] Cnst - 0x08000886 + 0x08000BAE 1 @@ -504,5 +523,5 @@ __SEGGER_init_table__ Cnst - 0x08000898 + 0x08000BC0 32 4 @@ -512,5 +531,5 @@ __SEGGER_init_data__ Cnst - 0x080008B8 + 0x08000BE0 4 4 @@ -520,5 +539,5 @@ __SEGGER_init_zero Code - 0x080008BC + 0x08000BE4 18 2 @@ -528,5 +547,5 @@ __SEGGER_init_copy Code - 0x080008CE + 0x08000BF6 20 2 @@ -545,7 +564,15 @@ + hrtc + Zero + 0x30000000 + 36 + 4 + charger_lto.o + + uwTick Zero - 0x30000000 + 0x30000024 4 4 @@ -555,5 +582,5 @@ uwTickPrio Zero - 0x30000004 + 0x30000028 1 4 @@ -563,5 +590,5 @@ SystemCoreClock Init - 0x30000008 + 0x3000002C 4 4 @@ -571,5 +598,5 @@ [.bss.block.heap] None - 0x30000008 + 0x30000030 8 @@ -606,5 +633,5 @@ [.bss.block.heap] None - 0x30000008 + 0x30000030 8 @@ -624,8 +651,8 @@ charger_lto.o - 1 422 + 2 230 16 4 - 5 + 41 @@ -652,8 +679,8 @@ Subtotal (4 objects) - 2 182 + 2 990 16 4 - 5 + 41 @@ -680,8 +707,8 @@ Total: - 2 220 + 3 028 52 4 - 8 197 + 8 233 @@ -711,8 +738,8 @@ Objects (4 files) - 2 182 + 2 990 16 4 - 5 + 41 @@ -725,8 +752,8 @@ Total: - 2 220 + 3 028 52 4 - 8 197 + 8 233 @@ -763,8 +790,8 @@ Objects (4 files) - 2 182 + 2 990 16 4 - 5 + 41 @@ -777,8 +804,8 @@ Total: - 2 220 + 3 028 52 4 - 8 197 + 8 233 @@ -795,5 +822,19 @@ SystemClock_Config() - 468 + 794 + + + + + + HAL_RTC_Init + 382 + + + + + + main + 304 @@ -808,11 +849,4 @@ - main - 258 - - - - - SystemInit 166 @@ -836,4 +870,11 @@ + HAL_RTC_WaitForSynchro + 54 + + + + + SysTick_Handler 16 @@ -871,4 +912,11 @@ + hrtc + + + + 36 + + uwTick @@ -886,8 +934,8 @@ Total: - 1 422 + 2 230 16 4 - 5 + 41 @@ -1006,8 +1054,8 @@ Grand total: - 2 220 + 3 028 16 4 - 5 + 41 @@ -1052,7 +1100,7 @@ - 080003ec-080004ed - main - 258 + 080003ec-08000705 + SystemClock_Config() + 794 2 Code @@ -1061,5 +1109,5 @@ - 080004ee-08000593 + 08000706-080007ab SystemInit 166 @@ -1070,5 +1118,5 @@ - 08000594-08000595 + 080007ac-080007ad NMI_Handler 2 @@ -1079,5 +1127,5 @@ - 08000596-08000597 + 080007ae-080007af SVC_Handler 2 @@ -1088,5 +1136,5 @@ - 08000598-08000609 + 080007b0-08000821 HAL_Init 114 @@ -1097,7 +1145,7 @@ - 0800060a-080007dd - SystemClock_Config() - 468 + 08000822-0800099f + HAL_RTC_Init + 382 2 Code @@ -1106,5 +1154,23 @@ - 080007de-080007ed + 080009a0-080009d5 + HAL_RTC_WaitForSynchro + 54 + 2 + Code + RX + charger_lto.o + + + 080009d6-08000b05 + main + 304 + 2 + Code + RX + charger_lto.o + + + 08000b06-08000b15 SysTick_Handler 16 @@ -1115,5 +1181,5 @@ - 080007ee-0800086d + 08000b16-08000b95 HAL_InitTick 128 @@ -1124,5 +1190,5 @@ - 0800086e-08000885 + 08000b96-08000bad Reset_Handler 24 @@ -1133,5 +1199,5 @@ - 08000886-08000895 + 08000bae-08000bbd D1CorePrescTable 16 @@ -1142,5 +1208,5 @@ - 08000896-08000897 + 08000bbe-08000bbf ( UNUSED .=.+2 ) 2 @@ -1151,5 +1217,5 @@ - 08000898-080008b7 + 08000bc0-08000bdf __SEGGER_init_table__ 32 @@ -1160,5 +1226,5 @@ - 080008b8-080008bb + 08000be0-08000be3 __SEGGER_init_data__ 4 @@ -1169,5 +1235,5 @@ - 080008bc-080008cd + 08000be4-08000bf5 __SEGGER_init_zero 18 @@ -1178,5 +1244,5 @@ - 080008ce-080008e1 + 08000bf6-08000c09 __SEGGER_init_copy 20 @@ -1187,7 +1253,7 @@ - 080008e2-2fffffff - ( UNUSED .=.+671086366 ) - 671 086 366 + 08000c0a-2fffffff + ( UNUSED .=.+671085558 ) + 671 085 558 - ---- @@ -1196,5 +1262,14 @@ - 30000000-30000003 + 30000000-30000023 + hrtc + 36 + 4 + Zero + ZI + charger_lto.o + + + 30000024-30000027 uwTick 4 @@ -1205,5 +1280,5 @@ - 30000004-30000004 + 30000028-30000028 uwTickPrio 1 @@ -1214,5 +1289,5 @@ - 30000005-30000007 + 30000029-3000002b ( ALIGN .=.+3 ) 3 @@ -1223,5 +1298,5 @@ - 30000008-3000000b + 3000002c-3000002f SystemCoreClock 4 @@ -1232,7 +1307,7 @@ - 3000000c-30005fff - ( UNUSED .=.+24564 ) - 24 564 + 30000030-30005fff + ( UNUSED .=.+24528 ) + 24 528 - ---- @@ -1259,15 +1334,15 @@ - 08000896-08000897 + 08000bbe-08000bbf 2 Unused memory between sections '.rodata.D1CorePrescTable' and '.segger.init.table' - 080008e2-2fffffff - 671 086 366 - Unused memory between sections '.segger.init.__SEGGER_init_copy' and '.bss.uwTick' - - - 30000005-30000007 + 08000c0a-2fffffff + 671 085 558 + Unused memory between sections '.segger.init.__SEGGER_init_copy' and '.bss.hrtc' + + + 30000029-3000002b 3 Filler between sections '.bss.uwTickPrio' and '.data.SystemCoreClock' as align=4 @@ -1279,6 +1354,6 @@ - 3000000c-30005fff - 24 564 + 30000030-30005fff + 24 528 Unused memory between sections '.data.SystemCoreClock' and '.bss.block.stack' @@ -1293,17 +1368,22 @@ - 30000000-30000003 + 30000000-30000023 + 36 + hrtc + + + 30000024-30000027 4 uwTick - 30000004-30000004 + 30000028-30000028 1 uwTickPrio - 30000000-30000004 - 5 - Total (2 sections) + 30000000-30000028 + 41 + Total (3 sections)

    Initialize by copy with packing=none

    @@ -1315,10 +1395,10 @@ - 30000008-3000000b + 3000002c-3000002f 4 SystemCoreClock - 30000008-3000000b + 3000002c-3000002f 4 Total (1 sections) @@ -1341,9 +1421,9 @@ Destination image + 45 bytes + + + Saving 9 bytes - - - Saving - -27 bytes @@ -1442,5 +1522,5 @@ ADC3_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1451,5 +1531,5 @@ ADC_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1460,5 +1540,5 @@ BDMA_Channel0_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1469,5 +1549,5 @@ BDMA_Channel1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1478,5 +1558,5 @@ BDMA_Channel2_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1487,5 +1567,5 @@ BDMA_Channel3_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1496,5 +1576,5 @@ BDMA_Channel4_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1505,5 +1585,5 @@ BDMA_Channel5_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1514,5 +1594,5 @@ BDMA_Channel6_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1523,5 +1603,5 @@ BDMA_Channel7_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1532,5 +1612,5 @@ BusFault_Handler - 0x08000595 + 0x080007AD 2 2 @@ -1541,5 +1621,5 @@ CEC_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1550,5 +1630,5 @@ COMP1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1559,5 +1639,5 @@ CORDIC_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1568,5 +1648,5 @@ CRS_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1577,5 +1657,5 @@ DCMI_PSSI_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1586,5 +1666,5 @@ DFSDM1_FLT0_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1595,5 +1675,5 @@ DFSDM1_FLT1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1604,5 +1684,5 @@ DFSDM1_FLT2_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1613,5 +1693,5 @@ DFSDM1_FLT3_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1622,5 +1702,5 @@ DMA1_Stream0_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1631,5 +1711,5 @@ DMA1_Stream1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1640,5 +1720,5 @@ DMA1_Stream2_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1649,5 +1729,5 @@ DMA1_Stream3_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1658,5 +1738,5 @@ DMA1_Stream4_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1667,5 +1747,5 @@ DMA1_Stream5_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1676,5 +1756,5 @@ DMA1_Stream6_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1685,5 +1765,5 @@ DMA1_Stream7_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1694,5 +1774,5 @@ DMA2D_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1703,5 +1783,5 @@ DMA2_Stream0_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1712,5 +1792,5 @@ DMA2_Stream1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1721,5 +1801,5 @@ DMA2_Stream2_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1730,5 +1810,5 @@ DMA2_Stream3_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1739,5 +1819,5 @@ DMA2_Stream4_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1748,5 +1828,5 @@ DMA2_Stream5_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1757,5 +1837,5 @@ DMA2_Stream6_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1766,5 +1846,5 @@ DMA2_Stream7_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1775,5 +1855,5 @@ DMAMUX1_OVR_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1784,5 +1864,5 @@ DMAMUX2_OVR_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1793,5 +1873,5 @@ DTS_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1802,5 +1882,5 @@ DebugMon_Handler - 0x08000597 + 0x080007AF 2 2 @@ -1811,5 +1891,5 @@ ECC_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1820,5 +1900,5 @@ ETH_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1829,5 +1909,5 @@ ETH_WKUP_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1838,5 +1918,5 @@ EXTI0_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1847,5 +1927,5 @@ EXTI15_10_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1856,5 +1936,5 @@ EXTI1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1865,5 +1945,5 @@ EXTI2_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1874,5 +1954,5 @@ EXTI3_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1883,5 +1963,5 @@ EXTI4_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1892,5 +1972,5 @@ EXTI9_5_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1901,5 +1981,5 @@ FDCAN1_IT0_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1910,5 +1990,5 @@ FDCAN1_IT1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1919,5 +1999,5 @@ FDCAN2_IT0_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1928,5 +2008,5 @@ FDCAN2_IT1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1937,5 +2017,5 @@ FDCAN3_IT0_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1946,5 +2026,5 @@ FDCAN3_IT1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1955,5 +2035,5 @@ FDCAN_CAL_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1964,5 +2044,5 @@ FLASH_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1973,5 +2053,5 @@ FMAC_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1982,5 +2062,5 @@ FMC_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -1991,5 +2071,5 @@ FPU_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2000,5 +2080,5 @@ HAL_Init - 0x08000599 + 0x080007B1 114 2 @@ -2009,5 +2089,5 @@ HAL_InitTick - 0x080007EF + 0x08000B17 128 2 @@ -2026,6 +2106,24 @@ + HAL_RTC_Init + 0x08000823 + 382 + 2 + Code + Lc + charger_lto.o + + + HAL_RTC_WaitForSynchro + 0x080009A1 + 54 + 2 + Code + Lc + charger_lto.o + + HSEM1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2036,5 +2134,5 @@ HardFault_Handler - 0x08000595 + 0x080007AD 2 2 @@ -2045,5 +2143,5 @@ I2C1_ER_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2054,5 +2152,5 @@ I2C1_EV_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2063,5 +2161,5 @@ I2C2_ER_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2072,5 +2170,5 @@ I2C2_EV_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2081,5 +2179,5 @@ I2C3_ER_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2090,5 +2188,5 @@ I2C3_EV_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2099,5 +2197,5 @@ I2C4_ER_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2108,5 +2206,5 @@ I2C4_EV_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2117,5 +2215,5 @@ I2C5_ER_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2126,5 +2224,5 @@ I2C5_EV_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2135,5 +2233,5 @@ LPTIM1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2144,5 +2242,5 @@ LPTIM2_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2153,5 +2251,5 @@ LPTIM3_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2162,5 +2260,5 @@ LPTIM4_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2171,5 +2269,5 @@ LPTIM5_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2180,5 +2278,5 @@ LPUART1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2189,5 +2287,5 @@ LTDC_ER_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2198,5 +2296,5 @@ LTDC_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2207,5 +2305,5 @@ MDIOS_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2216,5 +2314,5 @@ MDIOS_WKUP_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2225,5 +2323,5 @@ MDMA_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2234,5 +2332,5 @@ MemManage_Handler - 0x08000595 + 0x080007AD 2 2 @@ -2243,5 +2341,5 @@ NMI_Handler - 0x08000595 + 0x080007AD 2 2 @@ -2252,5 +2350,5 @@ OCTOSPI1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2261,5 +2359,5 @@ OCTOSPI2_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2270,5 +2368,5 @@ OTG_HS_EP1_IN_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2279,5 +2377,5 @@ OTG_HS_EP1_OUT_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2288,5 +2386,5 @@ OTG_HS_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2297,5 +2395,5 @@ OTG_HS_WKUP_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2306,5 +2404,5 @@ PVD_AVD_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2315,5 +2413,5 @@ PendSV_Handler - 0x08000597 + 0x080007AF 2 2 @@ -2324,5 +2422,5 @@ RCC_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2333,5 +2431,5 @@ RNG_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2342,5 +2440,5 @@ RTC_Alarm_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2351,5 +2449,5 @@ RTC_WKUP_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2360,5 +2458,5 @@ Reset_Handler - 0x0800086F + 0x08000B97 24 2 @@ -2369,5 +2467,5 @@ SAI1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2378,5 +2476,5 @@ SAI4_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2387,5 +2485,5 @@ SDMMC1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2396,5 +2494,5 @@ SDMMC2_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2405,5 +2503,5 @@ SPDIF_RX_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2414,5 +2512,5 @@ SPI1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2423,5 +2521,5 @@ SPI2_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2432,5 +2530,5 @@ SPI3_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2441,5 +2539,5 @@ SPI4_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2450,5 +2548,5 @@ SPI5_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2459,5 +2557,5 @@ SPI6_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2468,5 +2566,5 @@ SVC_Handler - 0x08000597 + 0x080007AF 2 2 @@ -2477,5 +2575,5 @@ SWPMI1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2486,5 +2584,5 @@ SysTick_Handler - 0x080007DF + 0x08000B07 16 2 @@ -2495,6 +2593,6 @@ SystemClock_Config() - 0x0800060B - 468 + 0x080003ED + 794 2 Code @@ -2504,5 +2602,5 @@ SystemInit - 0x080004EF + 0x08000707 166 2 @@ -2513,5 +2611,5 @@ TAMP_STAMP_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2522,5 +2620,5 @@ TIM15_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2531,5 +2629,5 @@ TIM16_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2540,5 +2638,5 @@ TIM17_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2549,5 +2647,5 @@ TIM1_BRK_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2558,5 +2656,5 @@ TIM1_CC_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2567,5 +2665,5 @@ TIM1_TRG_COM_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2576,5 +2674,5 @@ TIM1_UP_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2585,5 +2683,5 @@ TIM23_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2594,5 +2692,5 @@ TIM24_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2603,5 +2701,5 @@ TIM2_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2612,5 +2710,5 @@ TIM3_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2621,5 +2719,5 @@ TIM4_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2630,5 +2728,5 @@ TIM5_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2639,5 +2737,5 @@ TIM6_DAC_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2648,5 +2746,5 @@ TIM7_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2657,5 +2755,5 @@ TIM8_BRK_TIM12_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2666,5 +2764,5 @@ TIM8_CC_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2675,5 +2773,5 @@ TIM8_TRG_COM_TIM14_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2684,5 +2782,5 @@ TIM8_UP_TIM13_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2693,5 +2791,5 @@ UART4_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2702,5 +2800,5 @@ UART5_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2711,5 +2809,5 @@ UART7_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2720,5 +2818,5 @@ UART8_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2729,5 +2827,5 @@ UART9_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2738,5 +2836,5 @@ USART10_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2747,5 +2845,5 @@ USART1_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2756,5 +2854,5 @@ USART2_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2765,5 +2863,5 @@ USART3_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2774,5 +2872,5 @@ USART6_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2783,5 +2881,5 @@ UsageFault_Handler - 0x08000595 + 0x080007AD 2 2 @@ -2792,5 +2890,5 @@ WAKEUP_PIN_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2801,5 +2899,5 @@ WWDG_IRQHandler - 0x08000595 + 0x080007AD 2 @@ -2810,5 +2908,5 @@ __SEGGER_init_copy - 0x080008CF + 0x08000BF7 20 2 @@ -2828,5 +2926,5 @@ __SEGGER_init_zero - 0x080008BD + 0x08000BE5 18 2 @@ -2864,6 +2962,6 @@ main - 0x080003ED - 258 + 0x080009D7 + 304 2 Code @@ -2873,5 +2971,5 @@ reset_handler - 0x0800086F + 0x08000B97 24 2 @@ -2939,13 +3037,13 @@ 0x080003ED - main - 258 - 2 - Code - Gb - charger_lto.o - - - 0x080004EF + SystemClock_Config() + 794 + 2 + Code + Lc + charger_lto.o + + + 0x08000707 SystemInit 166 @@ -2956,5 +3054,5 @@ - 0x08000595 + 0x080007AD WWDG_IRQHandler @@ -2965,5 +3063,5 @@ - 0x08000595 + 0x080007AD WAKEUP_PIN_IRQHandler @@ -2974,5 +3072,5 @@ - 0x08000595 + 0x080007AD UsageFault_Handler 2 @@ -2983,5 +3081,5 @@ - 0x08000595 + 0x080007AD USART6_IRQHandler @@ -2992,5 +3090,5 @@ - 0x08000595 + 0x080007AD USART3_IRQHandler @@ -3001,5 +3099,5 @@ - 0x08000595 + 0x080007AD USART2_IRQHandler @@ -3010,5 +3108,5 @@ - 0x08000595 + 0x080007AD USART1_IRQHandler @@ -3019,5 +3117,5 @@ - 0x08000595 + 0x080007AD USART10_IRQHandler @@ -3028,5 +3126,5 @@ - 0x08000595 + 0x080007AD UART9_IRQHandler @@ -3037,5 +3135,5 @@ - 0x08000595 + 0x080007AD UART8_IRQHandler @@ -3046,5 +3144,5 @@ - 0x08000595 + 0x080007AD UART7_IRQHandler @@ -3055,5 +3153,5 @@ - 0x08000595 + 0x080007AD UART5_IRQHandler @@ -3064,5 +3162,5 @@ - 0x08000595 + 0x080007AD UART4_IRQHandler @@ -3073,5 +3171,5 @@ - 0x08000595 + 0x080007AD TIM8_UP_TIM13_IRQHandler @@ -3082,5 +3180,5 @@ - 0x08000595 + 0x080007AD TIM8_TRG_COM_TIM14_IRQHandler @@ -3091,5 +3189,5 @@ - 0x08000595 + 0x080007AD TIM8_CC_IRQHandler @@ -3100,5 +3198,5 @@ - 0x08000595 + 0x080007AD TIM8_BRK_TIM12_IRQHandler @@ -3109,5 +3207,5 @@ - 0x08000595 + 0x080007AD TIM7_IRQHandler @@ -3118,5 +3216,5 @@ - 0x08000595 + 0x080007AD TIM6_DAC_IRQHandler @@ -3127,5 +3225,5 @@ - 0x08000595 + 0x080007AD TIM5_IRQHandler @@ -3136,5 +3234,5 @@ - 0x08000595 + 0x080007AD TIM4_IRQHandler @@ -3145,5 +3243,5 @@ - 0x08000595 + 0x080007AD TIM3_IRQHandler @@ -3154,5 +3252,5 @@ - 0x08000595 + 0x080007AD TIM2_IRQHandler @@ -3163,5 +3261,5 @@ - 0x08000595 + 0x080007AD TIM24_IRQHandler @@ -3172,5 +3270,5 @@ - 0x08000595 + 0x080007AD TIM23_IRQHandler @@ -3181,5 +3279,5 @@ - 0x08000595 + 0x080007AD TIM1_UP_IRQHandler @@ -3190,5 +3288,5 @@ - 0x08000595 + 0x080007AD TIM1_TRG_COM_IRQHandler @@ -3199,5 +3297,5 @@ - 0x08000595 + 0x080007AD TIM1_CC_IRQHandler @@ -3208,5 +3306,5 @@ - 0x08000595 + 0x080007AD TIM1_BRK_IRQHandler @@ -3217,5 +3315,5 @@ - 0x08000595 + 0x080007AD TIM17_IRQHandler @@ -3226,5 +3324,5 @@ - 0x08000595 + 0x080007AD TIM16_IRQHandler @@ -3235,5 +3333,5 @@ - 0x08000595 + 0x080007AD TIM15_IRQHandler @@ -3244,5 +3342,5 @@ - 0x08000595 + 0x080007AD TAMP_STAMP_IRQHandler @@ -3253,5 +3351,5 @@ - 0x08000595 + 0x080007AD SWPMI1_IRQHandler @@ -3262,5 +3360,5 @@ - 0x08000595 + 0x080007AD SPI6_IRQHandler @@ -3271,5 +3369,5 @@ - 0x08000595 + 0x080007AD SPI5_IRQHandler @@ -3280,5 +3378,5 @@ - 0x08000595 + 0x080007AD SPI4_IRQHandler @@ -3289,5 +3387,5 @@ - 0x08000595 + 0x080007AD SPI3_IRQHandler @@ -3298,5 +3396,5 @@ - 0x08000595 + 0x080007AD SPI2_IRQHandler @@ -3307,5 +3405,5 @@ - 0x08000595 + 0x080007AD SPI1_IRQHandler @@ -3316,5 +3414,5 @@ - 0x08000595 + 0x080007AD SPDIF_RX_IRQHandler @@ -3325,5 +3423,5 @@ - 0x08000595 + 0x080007AD SDMMC2_IRQHandler @@ -3334,5 +3432,5 @@ - 0x08000595 + 0x080007AD SDMMC1_IRQHandler @@ -3343,5 +3441,5 @@ - 0x08000595 + 0x080007AD SAI4_IRQHandler @@ -3352,5 +3450,5 @@ - 0x08000595 + 0x080007AD SAI1_IRQHandler @@ -3361,5 +3459,5 @@ - 0x08000595 + 0x080007AD RTC_WKUP_IRQHandler @@ -3370,5 +3468,5 @@ - 0x08000595 + 0x080007AD RTC_Alarm_IRQHandler @@ -3379,5 +3477,5 @@ - 0x08000595 + 0x080007AD RNG_IRQHandler @@ -3388,5 +3486,5 @@ - 0x08000595 + 0x080007AD RCC_IRQHandler @@ -3397,5 +3495,5 @@ - 0x08000595 + 0x080007AD PVD_AVD_IRQHandler @@ -3406,5 +3504,5 @@ - 0x08000595 + 0x080007AD OTG_HS_WKUP_IRQHandler @@ -3415,5 +3513,5 @@ - 0x08000595 + 0x080007AD OTG_HS_IRQHandler @@ -3424,5 +3522,5 @@ - 0x08000595 + 0x080007AD OTG_HS_EP1_OUT_IRQHandler @@ -3433,5 +3531,5 @@ - 0x08000595 + 0x080007AD OTG_HS_EP1_IN_IRQHandler @@ -3442,5 +3540,5 @@ - 0x08000595 + 0x080007AD OCTOSPI2_IRQHandler @@ -3451,5 +3549,5 @@ - 0x08000595 + 0x080007AD OCTOSPI1_IRQHandler @@ -3460,5 +3558,5 @@ - 0x08000595 + 0x080007AD NMI_Handler 2 @@ -3469,5 +3567,5 @@ - 0x08000595 + 0x080007AD MemManage_Handler 2 @@ -3478,5 +3576,5 @@ - 0x08000595 + 0x080007AD MDMA_IRQHandler @@ -3487,5 +3585,5 @@ - 0x08000595 + 0x080007AD MDIOS_WKUP_IRQHandler @@ -3496,5 +3594,5 @@ - 0x08000595 + 0x080007AD MDIOS_IRQHandler @@ -3505,5 +3603,5 @@ - 0x08000595 + 0x080007AD LTDC_IRQHandler @@ -3514,5 +3612,5 @@ - 0x08000595 + 0x080007AD LTDC_ER_IRQHandler @@ -3523,5 +3621,5 @@ - 0x08000595 + 0x080007AD LPUART1_IRQHandler @@ -3532,5 +3630,5 @@ - 0x08000595 + 0x080007AD LPTIM5_IRQHandler @@ -3541,5 +3639,5 @@ - 0x08000595 + 0x080007AD LPTIM4_IRQHandler @@ -3550,5 +3648,5 @@ - 0x08000595 + 0x080007AD LPTIM3_IRQHandler @@ -3559,5 +3657,5 @@ - 0x08000595 + 0x080007AD LPTIM2_IRQHandler @@ -3568,5 +3666,5 @@ - 0x08000595 + 0x080007AD LPTIM1_IRQHandler @@ -3577,5 +3675,5 @@ - 0x08000595 + 0x080007AD I2C5_EV_IRQHandler @@ -3586,5 +3684,5 @@ - 0x08000595 + 0x080007AD I2C5_ER_IRQHandler @@ -3595,5 +3693,5 @@ - 0x08000595 + 0x080007AD I2C4_EV_IRQHandler @@ -3604,5 +3702,5 @@ - 0x08000595 + 0x080007AD I2C4_ER_IRQHandler @@ -3613,5 +3711,5 @@ - 0x08000595 + 0x080007AD I2C3_EV_IRQHandler @@ -3622,5 +3720,5 @@ - 0x08000595 + 0x080007AD I2C3_ER_IRQHandler @@ -3631,5 +3729,5 @@ - 0x08000595 + 0x080007AD I2C2_EV_IRQHandler @@ -3640,5 +3738,5 @@ - 0x08000595 + 0x080007AD I2C2_ER_IRQHandler @@ -3649,5 +3747,5 @@ - 0x08000595 + 0x080007AD I2C1_EV_IRQHandler @@ -3658,5 +3756,5 @@ - 0x08000595 + 0x080007AD I2C1_ER_IRQHandler @@ -3667,5 +3765,5 @@ - 0x08000595 + 0x080007AD HardFault_Handler 2 @@ -3676,5 +3774,5 @@ - 0x08000595 + 0x080007AD HSEM1_IRQHandler @@ -3685,5 +3783,5 @@ - 0x08000595 + 0x080007AD FPU_IRQHandler @@ -3694,5 +3792,5 @@ - 0x08000595 + 0x080007AD FMC_IRQHandler @@ -3703,5 +3801,5 @@ - 0x08000595 + 0x080007AD FMAC_IRQHandler @@ -3712,5 +3810,5 @@ - 0x08000595 + 0x080007AD FLASH_IRQHandler @@ -3721,5 +3819,5 @@ - 0x08000595 + 0x080007AD FDCAN_CAL_IRQHandler @@ -3730,5 +3828,5 @@ - 0x08000595 + 0x080007AD FDCAN3_IT1_IRQHandler @@ -3739,5 +3837,5 @@ - 0x08000595 + 0x080007AD FDCAN3_IT0_IRQHandler @@ -3748,5 +3846,5 @@ - 0x08000595 + 0x080007AD FDCAN2_IT1_IRQHandler @@ -3757,5 +3855,5 @@ - 0x08000595 + 0x080007AD FDCAN2_IT0_IRQHandler @@ -3766,5 +3864,5 @@ - 0x08000595 + 0x080007AD FDCAN1_IT1_IRQHandler @@ -3775,5 +3873,5 @@ - 0x08000595 + 0x080007AD FDCAN1_IT0_IRQHandler @@ -3784,5 +3882,5 @@ - 0x08000595 + 0x080007AD EXTI9_5_IRQHandler @@ -3793,5 +3891,5 @@ - 0x08000595 + 0x080007AD EXTI4_IRQHandler @@ -3802,5 +3900,5 @@ - 0x08000595 + 0x080007AD EXTI3_IRQHandler @@ -3811,5 +3909,5 @@ - 0x08000595 + 0x080007AD EXTI2_IRQHandler @@ -3820,5 +3918,5 @@ - 0x08000595 + 0x080007AD EXTI1_IRQHandler @@ -3829,5 +3927,5 @@ - 0x08000595 + 0x080007AD EXTI15_10_IRQHandler @@ -3838,5 +3936,5 @@ - 0x08000595 + 0x080007AD EXTI0_IRQHandler @@ -3847,5 +3945,5 @@ - 0x08000595 + 0x080007AD ETH_WKUP_IRQHandler @@ -3856,5 +3954,5 @@ - 0x08000595 + 0x080007AD ETH_IRQHandler @@ -3865,5 +3963,5 @@ - 0x08000595 + 0x080007AD ECC_IRQHandler @@ -3874,5 +3972,5 @@ - 0x08000595 + 0x080007AD DTS_IRQHandler @@ -3883,5 +3981,5 @@ - 0x08000595 + 0x080007AD DMAMUX2_OVR_IRQHandler @@ -3892,5 +3990,5 @@ - 0x08000595 + 0x080007AD DMAMUX1_OVR_IRQHandler @@ -3901,5 +3999,5 @@ - 0x08000595 + 0x080007AD DMA2_Stream7_IRQHandler @@ -3910,5 +4008,5 @@ - 0x08000595 + 0x080007AD DMA2_Stream6_IRQHandler @@ -3919,5 +4017,5 @@ - 0x08000595 + 0x080007AD DMA2_Stream5_IRQHandler @@ -3928,5 +4026,5 @@ - 0x08000595 + 0x080007AD DMA2_Stream4_IRQHandler @@ -3937,5 +4035,5 @@ - 0x08000595 + 0x080007AD DMA2_Stream3_IRQHandler @@ -3946,5 +4044,5 @@ - 0x08000595 + 0x080007AD DMA2_Stream2_IRQHandler @@ -3955,5 +4053,5 @@ - 0x08000595 + 0x080007AD DMA2_Stream1_IRQHandler @@ -3964,5 +4062,5 @@ - 0x08000595 + 0x080007AD DMA2_Stream0_IRQHandler @@ -3973,5 +4071,5 @@ - 0x08000595 + 0x080007AD DMA2D_IRQHandler @@ -3982,5 +4080,5 @@ - 0x08000595 + 0x080007AD DMA1_Stream7_IRQHandler @@ -3991,5 +4089,5 @@ - 0x08000595 + 0x080007AD DMA1_Stream6_IRQHandler @@ -4000,5 +4098,5 @@ - 0x08000595 + 0x080007AD DMA1_Stream5_IRQHandler @@ -4009,5 +4107,5 @@ - 0x08000595 + 0x080007AD DMA1_Stream4_IRQHandler @@ -4018,5 +4116,5 @@ - 0x08000595 + 0x080007AD DMA1_Stream3_IRQHandler @@ -4027,5 +4125,5 @@ - 0x08000595 + 0x080007AD DMA1_Stream2_IRQHandler @@ -4036,5 +4134,5 @@ - 0x08000595 + 0x080007AD DMA1_Stream1_IRQHandler @@ -4045,5 +4143,5 @@ - 0x08000595 + 0x080007AD DMA1_Stream0_IRQHandler @@ -4054,5 +4152,5 @@ - 0x08000595 + 0x080007AD DFSDM1_FLT3_IRQHandler @@ -4063,5 +4161,5 @@ - 0x08000595 + 0x080007AD DFSDM1_FLT2_IRQHandler @@ -4072,5 +4170,5 @@ - 0x08000595 + 0x080007AD DFSDM1_FLT1_IRQHandler @@ -4081,5 +4179,5 @@ - 0x08000595 + 0x080007AD DFSDM1_FLT0_IRQHandler @@ -4090,5 +4188,5 @@ - 0x08000595 + 0x080007AD DCMI_PSSI_IRQHandler @@ -4099,5 +4197,5 @@ - 0x08000595 + 0x080007AD CRS_IRQHandler @@ -4108,5 +4206,5 @@ - 0x08000595 + 0x080007AD CORDIC_IRQHandler @@ -4117,5 +4215,5 @@ - 0x08000595 + 0x080007AD COMP1_IRQHandler @@ -4126,5 +4224,5 @@ - 0x08000595 + 0x080007AD CEC_IRQHandler @@ -4135,5 +4233,5 @@ - 0x08000595 + 0x080007AD BusFault_Handler 2 @@ -4144,5 +4242,5 @@ - 0x08000595 + 0x080007AD BDMA_Channel7_IRQHandler @@ -4153,5 +4251,5 @@ - 0x08000595 + 0x080007AD BDMA_Channel6_IRQHandler @@ -4162,5 +4260,5 @@ - 0x08000595 + 0x080007AD BDMA_Channel5_IRQHandler @@ -4171,5 +4269,5 @@ - 0x08000595 + 0x080007AD BDMA_Channel4_IRQHandler @@ -4180,5 +4278,5 @@ - 0x08000595 + 0x080007AD BDMA_Channel3_IRQHandler @@ -4189,5 +4287,5 @@ - 0x08000595 + 0x080007AD BDMA_Channel2_IRQHandler @@ -4198,5 +4296,5 @@ - 0x08000595 + 0x080007AD BDMA_Channel1_IRQHandler @@ -4207,5 +4305,5 @@ - 0x08000595 + 0x080007AD BDMA_Channel0_IRQHandler @@ -4216,5 +4314,5 @@ - 0x08000595 + 0x080007AD ADC_IRQHandler @@ -4225,5 +4323,5 @@ - 0x08000595 + 0x080007AD ADC3_IRQHandler @@ -4234,5 +4332,5 @@ - 0x08000597 + 0x080007AF SVC_Handler 2 @@ -4243,5 +4341,5 @@ - 0x08000597 + 0x080007AF PendSV_Handler 2 @@ -4252,5 +4350,5 @@ - 0x08000597 + 0x080007AF DebugMon_Handler 2 @@ -4261,5 +4359,5 @@ - 0x08000599 + 0x080007B1 HAL_Init 114 @@ -4270,7 +4368,7 @@ - 0x0800060B - SystemClock_Config() - 468 + 0x08000823 + HAL_RTC_Init + 382 2 Code @@ -4279,5 +4377,23 @@ - 0x080007DF + 0x080009A1 + HAL_RTC_WaitForSynchro + 54 + 2 + Code + Lc + charger_lto.o + + + 0x080009D7 + main + 304 + 2 + Code + Gb + charger_lto.o + + + 0x08000B07 SysTick_Handler 16 @@ -4288,5 +4404,5 @@ - 0x080007EF + 0x08000B17 HAL_InitTick 128 @@ -4297,5 +4413,5 @@ - 0x0800086F + 0x08000B97 reset_handler 24 @@ -4306,5 +4422,5 @@ - 0x0800086F + 0x08000B97 Reset_Handler 24 @@ -4315,5 +4431,5 @@ - 0x080008BD + 0x08000BE5 __SEGGER_init_zero 18 @@ -4324,5 +4440,5 @@ - 0x080008CF + 0x08000BF7 __SEGGER_init_copy 20 @@ -4345,8 +4461,24 @@ SystemClock_Config() - 468 + 794 2 Code Lc + charger_lto.o + + + HAL_RTC_Init + 382 + 2 + Code + Lc + charger_lto.o + + + main + 304 + 2 + Code + Gb charger_lto.o @@ -4360,12 +4492,4 @@ - main - 258 - 2 - Code - Gb - charger_lto.o - - SystemInit 166 @@ -4386,4 +4510,12 @@ HAL_Init 114 + 2 + Code + Lc + charger_lto.o + + + HAL_RTC_WaitForSynchro + 54 2 Code @@ -5637,5 +5769,5 @@ SystemCoreClock - 0x30000008 + 0x3000002C 4 4 @@ -5645,6 +5777,15 @@ + hrtc + 0x30000000 + 36 + 4 + Zero + Lc + charger_lto.o + + uwTick - 0x30000000 + 0x30000024 4 4 @@ -5655,5 +5796,5 @@ uwTickPrio - 0x30000004 + 0x30000028 1 4 @@ -5676,4 +5817,13 @@ 0x30000000 + hrtc + 36 + 4 + Zero + Lc + charger_lto.o + + + 0x30000024 uwTick 4 @@ -5684,5 +5834,5 @@ - 0x30000004 + 0x30000028 uwTickPrio 1 @@ -5693,5 +5843,5 @@ - 0x30000008 + 0x3000002C SystemCoreClock 4 @@ -5711,4 +5861,12 @@ Bd Object File + + + hrtc + 36 + 4 + Zero + Lc + charger_lto.o @@ -5750,5 +5908,5 @@ D1CorePrescTable - 0x08000886 + 0x08000BAE 16 @@ -5759,5 +5917,5 @@ __SEGGER_init_data__ - 0x080008B8 + 0x08000BE0 [4] 4 @@ -5768,5 +5926,5 @@ __SEGGER_init_table__ - 0x08000898 + 0x08000BC0 [32] 4 @@ -5788,5 +5946,5 @@ - 0x08000886 + 0x08000BAE D1CorePrescTable 16 @@ -5797,5 +5955,5 @@ - 0x08000898 + 0x08000BC0 __SEGGER_init_table__ [32] @@ -5806,5 +5964,5 @@ - 0x080008B8 + 0x08000BE0 __SEGGER_init_data__ [4] @@ -6017,5 +6175,5 @@ __FLASH1_segment_used_end__ - 0x080008E2 + 0x08000C0A @@ -6026,5 +6184,5 @@ __FLASH1_segment_used_size__ - 0x000008E2 + 0x00000C0A @@ -6071,5 +6229,5 @@ __FLASH_segment_used_end__ - 0x080008E2 + 0x08000C0A @@ -6080,5 +6238,5 @@ __FLASH_segment_used_size__ - 0x000008E2 + 0x00000C0A @@ -6505,5 +6663,5 @@ - 0x000008E2 + 0x00000C0A __FLASH_segment_used_size__ @@ -6514,5 +6672,5 @@ - 0x000008E2 + 0x00000C0A __FLASH1_segment_used_size__ @@ -6694,5 +6852,5 @@ - 0x080008E2 + 0x08000C0A __FLASH_segment_used_end__ @@ -6703,5 +6861,5 @@ - 0x080008E2 + 0x08000C0A __FLASH1_segment_used_end__ @@ -7076,6 +7234,8 @@ HAL_Init SystemClock_Config() + HAL_RTC_Init HAL_RCC_GetSysClockFreq HAL_InitTick + HAL_RTC_WaitForSynchro main SystemInit @@ -7240,12 +7400,13 @@

    Section .vectors from stm32h723xx_Vectors.o, size=716, align=1024

    -
    _vectors:
+
    _vectors:
   0x08000000:  30008000     DC.W       0x30008000               ; R_ARM_ABS32
-  0x08000004:  0800086F     DC.W       Reset_Handler
-  0x08000008:  08000595     DC.W       NMI_Handler
-  0x0800000C:  08000595     DC.W       NMI_Handler
-  0x08000010:  08000595     DC.W       NMI_Handler
-  0x08000014:  08000595     DC.W       NMI_Handler
-  0x08000018:  08000595     DC.W       NMI_Handler
+  0x08000004:  08000B97     DC.W       Reset_Handler
+  0x08000008:  080007AD     DC.W       NMI_Handler
+  0x0800000C:  080007AD     DC.W       NMI_Handler
+  0x08000010:  080007AD     DC.W       NMI_Handler
+  0x08000014:  080007AD     DC.W       NMI_Handler
+  0x08000018:  080007AD     DC.W       NMI_Handler
   0x0800001C:  00           DC.B       0x00                     ; '\0'
   0x0800001D:  00           DC.B       0x00                     ; '\0'
@@ -7264,79 +7425,79 @@
   0x0800002A:  00           DC.B       0x00                     ; '\0'
   0x0800002B:  00           DC.B       0x00                     ; '\0'
-  0x0800002C:  08000597     DC.W       SVC_Handler
-  0x08000030:  08000597     DC.W       SVC_Handler
+  0x0800002C:  080007AF     DC.W       SVC_Handler
+  0x08000030:  080007AF     DC.W       SVC_Handler
   0x08000034:  00           DC.B       0x00                     ; '\0'
   0x08000035:  00           DC.B       0x00                     ; '\0'
   0x08000036:  00           DC.B       0x00                     ; '\0'
   0x08000037:  00           DC.B       0x00                     ; '\0'
-  0x08000038:  08000597     DC.W       SVC_Handler
-  0x0800003C:  080007DF     DC.W       SysTick_Handler
-  0x08000040:  08000595     DC.W       NMI_Handler
-  0x08000044:  08000595     DC.W       NMI_Handler
-  0x08000048:  08000595     DC.W       NMI_Handler
-  0x0800004C:  08000595     DC.W       NMI_Handler
-  0x08000050:  08000595     DC.W       NMI_Handler
-  0x08000054:  08000595     DC.W       NMI_Handler
-  0x08000058:  08000595     DC.W       NMI_Handler
-  0x0800005C:  08000595     DC.W       NMI_Handler
-  0x08000060:  08000595     DC.W       NMI_Handler
-  0x08000064:  08000595     DC.W       NMI_Handler
-  0x08000068:  08000595     DC.W       NMI_Handler
-  0x0800006C:  08000595     DC.W       NMI_Handler
-  0x08000070:  08000595     DC.W       NMI_Handler
-  0x08000074:  08000595     DC.W       NMI_Handler
-  0x08000078:  08000595     DC.W       NMI_Handler
-  0x0800007C:  08000595     DC.W       NMI_Handler
-  0x08000080:  08000595     DC.W       NMI_Handler
-  0x08000084:  08000595     DC.W       NMI_Handler
-  0x08000088:  08000595     DC.W       NMI_Handler
-  0x0800008C:  08000595     DC.W       NMI_Handler
-  0x08000090:  08000595     DC.W       NMI_Handler
-  0x08000094:  08000595     DC.W       NMI_Handler
-  0x08000098:  08000595     DC.W       NMI_Handler
-  0x0800009C:  08000595     DC.W       NMI_Handler
-  0x080000A0:  08000595     DC.W       NMI_Handler
-  0x080000A4:  08000595     DC.W       NMI_Handler
-  0x080000A8:  08000595     DC.W       NMI_Handler
-  0x080000AC:  08000595     DC.W       NMI_Handler
-  0x080000B0:  08000595     DC.W       NMI_Handler
-  0x080000B4:  08000595     DC.W       NMI_Handler
-  0x080000B8:  08000595     DC.W       NMI_Handler
-  0x080000BC:  08000595     DC.W       NMI_Handler
-  0x080000C0:  08000595     DC.W       NMI_Handler
-  0x080000C4:  08000595     DC.W       NMI_Handler
-  0x080000C8:  08000595     DC.W       NMI_Handler
-  0x080000CC:  08000595     DC.W       NMI_Handler
-  0x080000D0:  08000595     DC.W       NMI_Handler
-  0x080000D4:  08000595     DC.W       NMI_Handler
-  0x080000D8:  08000595     DC.W       NMI_Handler
-  0x080000DC:  08000595     DC.W       NMI_Handler
-  0x080000E0:  08000595     DC.W       NMI_Handler
-  0x080000E4:  08000595     DC.W       NMI_Handler
+  0x08000038:  080007AF     DC.W       SVC_Handler
+  0x0800003C:  08000B07     DC.W       SysTick_Handler
+  0x08000040:  080007AD     DC.W       NMI_Handler
+  0x08000044:  080007AD     DC.W       NMI_Handler
+  0x08000048:  080007AD     DC.W       NMI_Handler
+  0x0800004C:  080007AD     DC.W       NMI_Handler
+  0x08000050:  080007AD     DC.W       NMI_Handler
+  0x08000054:  080007AD     DC.W       NMI_Handler
+  0x08000058:  080007AD     DC.W       NMI_Handler
+  0x0800005C:  080007AD     DC.W       NMI_Handler
+  0x08000060:  080007AD     DC.W       NMI_Handler
+  0x08000064:  080007AD     DC.W       NMI_Handler
+  0x08000068:  080007AD     DC.W       NMI_Handler
+  0x0800006C:  080007AD     DC.W       NMI_Handler
+  0x08000070:  080007AD     DC.W       NMI_Handler
+  0x08000074:  080007AD     DC.W       NMI_Handler
+  0x08000078:  080007AD     DC.W       NMI_Handler
+  0x0800007C:  080007AD     DC.W       NMI_Handler
+  0x08000080:  080007AD     DC.W       NMI_Handler
+  0x08000084:  080007AD     DC.W       NMI_Handler
+  0x08000088:  080007AD     DC.W       NMI_Handler
+  0x0800008C:  080007AD     DC.W       NMI_Handler
+  0x08000090:  080007AD     DC.W       NMI_Handler
+  0x08000094:  080007AD     DC.W       NMI_Handler
+  0x08000098:  080007AD     DC.W       NMI_Handler
+  0x0800009C:  080007AD     DC.W       NMI_Handler
+  0x080000A0:  080007AD     DC.W       NMI_Handler
+  0x080000A4:  080007AD     DC.W       NMI_Handler
+  0x080000A8:  080007AD     DC.W       NMI_Handler
+  0x080000AC:  080007AD     DC.W       NMI_Handler
+  0x080000B0:  080007AD     DC.W       NMI_Handler
+  0x080000B4:  080007AD     DC.W       NMI_Handler
+  0x080000B8:  080007AD     DC.W       NMI_Handler
+  0x080000BC:  080007AD     DC.W       NMI_Handler
+  0x080000C0:  080007AD     DC.W       NMI_Handler
+  0x080000C4:  080007AD     DC.W       NMI_Handler
+  0x080000C8:  080007AD     DC.W       NMI_Handler
+  0x080000CC:  080007AD     DC.W       NMI_Handler
+  0x080000D0:  080007AD     DC.W       NMI_Handler
+  0x080000D4:  080007AD     DC.W       NMI_Handler
+  0x080000D8:  080007AD     DC.W       NMI_Handler
+  0x080000DC:  080007AD     DC.W       NMI_Handler
+  0x080000E0:  080007AD     DC.W       NMI_Handler
+  0x080000E4:  080007AD     DC.W       NMI_Handler
   0x080000E8:  00           DC.B       0x00                     ; '\0'
   0x080000E9:  00           DC.B       0x00                     ; '\0'
   0x080000EA:  00           DC.B       0x00                     ; '\0'
   0x080000EB:  00           DC.B       0x00                     ; '\0'
-  0x080000EC:  08000595     DC.W       NMI_Handler
-  0x080000F0:  08000595     DC.W       NMI_Handler
-  0x080000F4:  08000595     DC.W       NMI_Handler
-  0x080000F8:  08000595     DC.W       NMI_Handler
-  0x080000FC:  08000595     DC.W       NMI_Handler
-  0x08000100:  08000595     DC.W       NMI_Handler
-  0x08000104:  08000595     DC.W       NMI_Handler
-  0x08000108:  08000595     DC.W       NMI_Handler
-  0x0800010C:  08000595     DC.W       NMI_Handler
-  0x08000110:  08000595     DC.W       NMI_Handler
-  0x08000114:  08000595     DC.W       NMI_Handler
-  0x08000118:  08000595     DC.W       NMI_Handler
-  0x0800011C:  08000595     DC.W       NMI_Handler
-  0x08000120:  08000595     DC.W       NMI_Handler
-  0x08000124:  08000595     DC.W       NMI_Handler
-  0x08000128:  08000595     DC.W       NMI_Handler
-  0x0800012C:  08000595     DC.W       NMI_Handler
-  0x08000130:  08000595     DC.W       NMI_Handler
-  0x08000134:  08000595     DC.W       NMI_Handler
-  0x08000138:  08000595     DC.W       NMI_Handler
-  0x0800013C:  08000595     DC.W       NMI_Handler
+  0x080000EC:  080007AD     DC.W       NMI_Handler
+  0x080000F0:  080007AD     DC.W       NMI_Handler
+  0x080000F4:  080007AD     DC.W       NMI_Handler
+  0x080000F8:  080007AD     DC.W       NMI_Handler
+  0x080000FC:  080007AD     DC.W       NMI_Handler
+  0x08000100:  080007AD     DC.W       NMI_Handler
+  0x08000104:  080007AD     DC.W       NMI_Handler
+  0x08000108:  080007AD     DC.W       NMI_Handler
+  0x0800010C:  080007AD     DC.W       NMI_Handler
+  0x08000110:  080007AD     DC.W       NMI_Handler
+  0x08000114:  080007AD     DC.W       NMI_Handler
+  0x08000118:  080007AD     DC.W       NMI_Handler
+  0x0800011C:  080007AD     DC.W       NMI_Handler
+  0x08000120:  080007AD     DC.W       NMI_Handler
+  0x08000124:  080007AD     DC.W       NMI_Handler
+  0x08000128:  080007AD     DC.W       NMI_Handler
+  0x0800012C:  080007AD     DC.W       NMI_Handler
+  0x08000130:  080007AD     DC.W       NMI_Handler
+  0x08000134:  080007AD     DC.W       NMI_Handler
+  0x08000138:  080007AD     DC.W       NMI_Handler
+  0x0800013C:  080007AD     DC.W       NMI_Handler
   0x08000140:  00           DC.B       0x00                     ; '\0'
   0x08000141:  00           DC.B       0x00                     ; '\0'
@@ -7355,40 +7516,40 @@
   0x0800014E:  00           DC.B       0x00                     ; '\0'
   0x0800014F:  00           DC.B       0x00                     ; '\0'
-  0x08000150:  08000595     DC.W       NMI_Handler
-  0x08000154:  08000595     DC.W       NMI_Handler
-  0x08000158:  08000595     DC.W       NMI_Handler
-  0x0800015C:  08000595     DC.W       NMI_Handler
-  0x08000160:  08000595     DC.W       NMI_Handler
-  0x08000164:  08000595     DC.W       NMI_Handler
-  0x08000168:  08000595     DC.W       NMI_Handler
-  0x0800016C:  08000595     DC.W       NMI_Handler
-  0x08000170:  08000595     DC.W       NMI_Handler
-  0x08000174:  08000595     DC.W       NMI_Handler
-  0x08000178:  08000595     DC.W       NMI_Handler
+  0x08000150:  080007AD     DC.W       NMI_Handler
+  0x08000154:  080007AD     DC.W       NMI_Handler
+  0x08000158:  080007AD     DC.W       NMI_Handler
+  0x0800015C:  080007AD     DC.W       NMI_Handler
+  0x08000160:  080007AD     DC.W       NMI_Handler
+  0x08000164:  080007AD     DC.W       NMI_Handler
+  0x08000168:  080007AD     DC.W       NMI_Handler
+  0x0800016C:  080007AD     DC.W       NMI_Handler
+  0x08000170:  080007AD     DC.W       NMI_Handler
+  0x08000174:  080007AD     DC.W       NMI_Handler
+  0x08000178:  080007AD     DC.W       NMI_Handler
   0x0800017C:  00           DC.B       0x00                     ; '\0'
   0x0800017D:  00           DC.B       0x00                     ; '\0'
   0x0800017E:  00           DC.B       0x00                     ; '\0'
   0x0800017F:  00           DC.B       0x00                     ; '\0'
-  0x08000180:  08000595     DC.W       NMI_Handler
-  0x08000184:  08000595     DC.W       NMI_Handler
-  0x08000188:  08000595     DC.W       NMI_Handler
-  0x0800018C:  08000595     DC.W       NMI_Handler
-  0x08000190:  08000595     DC.W       NMI_Handler
-  0x08000194:  08000595     DC.W       NMI_Handler
-  0x08000198:  08000595     DC.W       NMI_Handler
-  0x0800019C:  08000595     DC.W       NMI_Handler
-  0x080001A0:  08000595     DC.W       NMI_Handler
-  0x080001A4:  08000595     DC.W       NMI_Handler
-  0x080001A8:  08000595     DC.W       NMI_Handler
+  0x08000180:  080007AD     DC.W       NMI_Handler
+  0x08000184:  080007AD     DC.W       NMI_Handler
+  0x08000188:  080007AD     DC.W       NMI_Handler
+  0x0800018C:  080007AD     DC.W       NMI_Handler
+  0x08000190:  080007AD     DC.W       NMI_Handler
+  0x08000194:  080007AD     DC.W       NMI_Handler
+  0x08000198:  080007AD     DC.W       NMI_Handler
+  0x0800019C:  080007AD     DC.W       NMI_Handler
+  0x080001A0:  080007AD     DC.W       NMI_Handler
+  0x080001A4:  080007AD     DC.W       NMI_Handler
+  0x080001A8:  080007AD     DC.W       NMI_Handler
   0x080001AC:  00           DC.B       0x00                     ; '\0'
   0x080001AD:  00           DC.B       0x00                     ; '\0'
   0x080001AE:  00           DC.B       0x00                     ; '\0'
   0x080001AF:  00           DC.B       0x00                     ; '\0'
-  0x080001B0:  08000595     DC.W       NMI_Handler
-  0x080001B4:  08000595     DC.W       NMI_Handler
-  0x080001B8:  08000595     DC.W       NMI_Handler
-  0x080001BC:  08000595     DC.W       NMI_Handler
-  0x080001C0:  08000595     DC.W       NMI_Handler
-  0x080001C4:  08000595     DC.W       NMI_Handler
+  0x080001B0:  080007AD     DC.W       NMI_Handler
+  0x080001B4:  080007AD     DC.W       NMI_Handler
+  0x080001B8:  080007AD     DC.W       NMI_Handler
+  0x080001BC:  080007AD     DC.W       NMI_Handler
+  0x080001C0:  080007AD     DC.W       NMI_Handler
+  0x080001C4:  080007AD     DC.W       NMI_Handler
   0x080001C8:  00           DC.B       0x00                     ; '\0'
   0x080001C9:  00           DC.B       0x00                     ; '\0'
@@ -7407,5 +7568,5 @@
   0x080001D6:  00           DC.B       0x00                     ; '\0'
   0x080001D7:  00           DC.B       0x00                     ; '\0'
-  0x080001D8:  08000595     DC.W       NMI_Handler
+  0x080001D8:  080007AD     DC.W       NMI_Handler
   0x080001DC:  00           DC.B       0x00                     ; '\0'
   0x080001DD:  00           DC.B       0x00                     ; '\0'
@@ -7436,63 +7597,63 @@
   0x080001F6:  00           DC.B       0x00                     ; '\0'
   0x080001F7:  00           DC.B       0x00                     ; '\0'
-  0x080001F8:  08000595     DC.W       NMI_Handler
-  0x080001FC:  08000595     DC.W       NMI_Handler
-  0x08000200:  08000595     DC.W       NMI_Handler
-  0x08000204:  08000595     DC.W       NMI_Handler
+  0x080001F8:  080007AD     DC.W       NMI_Handler
+  0x080001FC:  080007AD     DC.W       NMI_Handler
+  0x08000200:  080007AD     DC.W       NMI_Handler
+  0x08000204:  080007AD     DC.W       NMI_Handler
   0x08000208:  00           DC.B       0x00                     ; '\0'
   0x08000209:  00           DC.B       0x00                     ; '\0'
   0x0800020A:  00           DC.B       0x00                     ; '\0'
   0x0800020B:  00           DC.B       0x00                     ; '\0'
-  0x0800020C:  08000595     DC.W       NMI_Handler
-  0x08000210:  08000595     DC.W       NMI_Handler
-  0x08000214:  08000595     DC.W       NMI_Handler
-  0x08000218:  08000595     DC.W       NMI_Handler
-  0x0800021C:  08000595     DC.W       NMI_Handler
-  0x08000220:  08000595     DC.W       NMI_Handler
+  0x0800020C:  080007AD     DC.W       NMI_Handler
+  0x08000210:  080007AD     DC.W       NMI_Handler
+  0x08000214:  080007AD     DC.W       NMI_Handler
+  0x08000218:  080007AD     DC.W       NMI_Handler
+  0x0800021C:  080007AD     DC.W       NMI_Handler
+  0x08000220:  080007AD     DC.W       NMI_Handler
   0x08000224:  00           DC.B       0x00                     ; '\0'
   0x08000225:  00           DC.B       0x00                     ; '\0'
   0x08000226:  00           DC.B       0x00                     ; '\0'
   0x08000227:  00           DC.B       0x00                     ; '\0'
-  0x08000228:  08000595     DC.W       NMI_Handler
+  0x08000228:  080007AD     DC.W       NMI_Handler
   0x0800022C:  00           DC.B       0x00                     ; '\0'
   0x0800022D:  00           DC.B       0x00                     ; '\0'
   0x0800022E:  00           DC.B       0x00                     ; '\0'
   0x0800022F:  00           DC.B       0x00                     ; '\0'
-  0x08000230:  08000595     DC.W       NMI_Handler
-  0x08000234:  08000595     DC.W       NMI_Handler
+  0x08000230:  080007AD     DC.W       NMI_Handler
+  0x08000234:  080007AD     DC.W       NMI_Handler
   0x08000238:  00           DC.B       0x00                     ; '\0'
   0x08000239:  00           DC.B       0x00                     ; '\0'
   0x0800023A:  00           DC.B       0x00                     ; '\0'
   0x0800023B:  00           DC.B       0x00                     ; '\0'
-  0x0800023C:  08000595     DC.W       NMI_Handler
-  0x08000240:  08000595     DC.W       NMI_Handler
-  0x08000244:  08000595     DC.W       NMI_Handler
-  0x08000248:  08000595     DC.W       NMI_Handler
-  0x0800024C:  08000595     DC.W       NMI_Handler
-  0x08000250:  08000595     DC.W       NMI_Handler
-  0x08000254:  08000595     DC.W       NMI_Handler
-  0x08000258:  08000595     DC.W       NMI_Handler
-  0x0800025C:  08000595     DC.W       NMI_Handler
-  0x08000260:  08000595     DC.W       NMI_Handler
-  0x08000264:  08000595     DC.W       NMI_Handler
-  0x08000268:  08000595     DC.W       NMI_Handler
-  0x0800026C:  08000595     DC.W       NMI_Handler
-  0x08000270:  08000595     DC.W       NMI_Handler
-  0x08000274:  08000595     DC.W       NMI_Handler
-  0x08000278:  08000595     DC.W       NMI_Handler
+  0x0800023C:  080007AD     DC.W       NMI_Handler
+  0x08000240:  080007AD     DC.W       NMI_Handler
+  0x08000244:  080007AD     DC.W       NMI_Handler
+  0x08000248:  080007AD     DC.W       NMI_Handler
+  0x0800024C:  080007AD     DC.W       NMI_Handler
+  0x08000250:  080007AD     DC.W       NMI_Handler
+  0x08000254:  080007AD     DC.W       NMI_Handler
+  0x08000258:  080007AD     DC.W       NMI_Handler
+  0x0800025C:  080007AD     DC.W       NMI_Handler
+  0x08000260:  080007AD     DC.W       NMI_Handler
+  0x08000264:  080007AD     DC.W       NMI_Handler
+  0x08000268:  080007AD     DC.W       NMI_Handler
+  0x0800026C:  080007AD     DC.W       NMI_Handler
+  0x08000270:  080007AD     DC.W       NMI_Handler
+  0x08000274:  080007AD     DC.W       NMI_Handler
+  0x08000278:  080007AD     DC.W       NMI_Handler
   0x0800027C:  00           DC.B       0x00                     ; '\0'
   0x0800027D:  00           DC.B       0x00                     ; '\0'
   0x0800027E:  00           DC.B       0x00                     ; '\0'
   0x0800027F:  00           DC.B       0x00                     ; '\0'
-  0x08000280:  08000595     DC.W       NMI_Handler
-  0x08000284:  08000595     DC.W       NMI_Handler
-  0x08000288:  08000595     DC.W       NMI_Handler
-  0x0800028C:  08000595     DC.W       NMI_Handler
+  0x08000280:  080007AD     DC.W       NMI_Handler
+  0x08000284:  080007AD     DC.W       NMI_Handler
+  0x08000288:  080007AD     DC.W       NMI_Handler
+  0x0800028C:  080007AD     DC.W       NMI_Handler
   0x08000290:  00           DC.B       0x00                     ; '\0'
   0x08000291:  00           DC.B       0x00                     ; '\0'
   0x08000292:  00           DC.B       0x00                     ; '\0'
   0x08000293:  00           DC.B       0x00                     ; '\0'
-  0x08000294:  08000595     DC.W       NMI_Handler
-  0x08000298:  08000595     DC.W       NMI_Handler
+  0x08000294:  080007AD     DC.W       NMI_Handler
+  0x08000298:  080007AD     DC.W       NMI_Handler
   0x0800029C:  00           DC.B       0x00                     ; '\0'
   0x0800029D:  00           DC.B       0x00                     ; '\0'
@@ -7503,20 +7664,20 @@
   0x080002A2:  00           DC.B       0x00                     ; '\0'
   0x080002A3:  00           DC.B       0x00                     ; '\0'
-  0x080002A4:  08000595     DC.W       NMI_Handler
-  0x080002A8:  08000595     DC.W       NMI_Handler
-  0x080002AC:  08000595     DC.W       NMI_Handler
-  0x080002B0:  08000595     DC.W       NMI_Handler
-  0x080002B4:  08000595     DC.W       NMI_Handler
-  0x080002B8:  08000595     DC.W       NMI_Handler
-  0x080002BC:  08000595     DC.W       NMI_Handler
-  0x080002C0:  08000595     DC.W       NMI_Handler
-  0x080002C4:  08000595     DC.W       NMI_Handler
-  0x080002C8:  08000595     DC.W       NMI_Handler
+  0x080002A4:  080007AD     DC.W       NMI_Handler
+  0x080002A8:  080007AD     DC.W       NMI_Handler
+  0x080002AC:  080007AD     DC.W       NMI_Handler
+  0x080002B0:  080007AD     DC.W       NMI_Handler
+  0x080002B4:  080007AD     DC.W       NMI_Handler
+  0x080002B8:  080007AD     DC.W       NMI_Handler
+  0x080002BC:  080007AD     DC.W       NMI_Handler
+  0x080002C0:  080007AD     DC.W       NMI_Handler
+  0x080002C4:  080007AD     DC.W       NMI_Handler
+  0x080002C8:  080007AD     DC.W       NMI_Handler

    Section .text.HAL_RCC_GetSysClockFreq from charger_lto.o, size=268, align=4

    -
    HAL_RCC_GetSysClockFreq:
-_vectors_end:
+
    HAL_RCC_GetSysClockFreq:
+_vectors_end:
   0x080002CC:  F244 4100    MOVW       R1, #0x4400
   0x080002D0:  F6C5 0102    MOVT       R1, #0x5802
@@ -7615,6 +7776,7 @@
 
    Section .init._start from SEGGER_THUMB_Startup.o, size=20, align=4
    
 
    -
    _start:
-  0x080003D8:  4C03         LDR        R4, =0x08000898          ; [PC, #12] [0x080003E8] 
+
    _start:
+  0x080003D8:  4C03         LDR        R4, =0x08000BC0          ; [PC, #12] [0x080003E8] 
 
    .L1:
   0x080003DA:  6820         LDR        R0, [R4]
@@ -7622,736 +7784,1268 @@
   0x080003DE:  4780         BLX        R0
   0x080003E0:  E7FB         B          .L1                      ; 0x080003DA
-
    __SEGGER_init_done:
-__startup_complete:
-  0x080003E2:  F000 F803    BL         main                     ; 0x080003EC
-
    exit:
-  0x080003E6:  E7FE         B          exit                     ; 0x080003E6
-  0x080003E8:  08000898     DC.W       0x08000898               ; R_ARM_ABS32
+
    __SEGGER_init_done:
+__startup_complete:
+  0x080003E2:  F000 FAF8    BL         main                     ; 0x080009D6
+
    exit:
+  0x080003E6:  E7FE         B          exit                     ; 0x080003E6
+  0x080003E8:  08000BC0     DC.W       0x08000BC0               ; R_ARM_ABS32
 
    
-
    Section .text.main from charger_lto.o, size=258, align=2
    
+
    Section .text.SystemClock_Config() from charger_lto.o, size=794, align=2
    
 
    -
    main:
-  0x080003EC:  F64E 5014    MOVW       R0, #0xED14
-  0x080003F0:  F3BF 8F5F    DMB        SY
-  0x080003F4:  F2CE 0000    MOVT       R0, #0xE000
-  0x080003F8:  6901         LDR        R1, [R0, #16]
-  0x080003FA:  F421 3180    BIC        R1, R1, #0x010000
-  0x080003FE:  6101         STR        R1, [R0, #16]
-  0x08000400:  2100         MOVS       R1, #0
-  0x08000402:  F8C0 1080    STR.W      R1, [R0, #128]
-  0x08000406:  F8C0 1084    STR.W      R1, [R0, #132]
-  0x0800040A:  F8D0 208C    LDR.W      R2, [R0, #140]
-  0x0800040E:  F022 0201    BIC        R2, R2, #1
-  0x08000412:  F8C0 208C    STR.W      R2, [R0, #140]
-  0x08000416:  F248 723F    MOVW       R2, #0x873F
-  0x0800041A:  F8C0 1088    STR.W      R1, [R0, #136]
-  0x0800041E:  F2C1 0204    MOVT       R2, #0x1004
-  0x08000422:  F8C0 208C    STR.W      R2, [R0, #140]
-  0x08000426:  2205         MOVS       R2, #5
-  0x08000428:  F8C0 2080    STR.W      R2, [R0, #128]
-  0x0800042C:  6902         LDR        R2, [R0, #16]
-  0x0800042E:  F442 3280    ORR        R2, R2, #0x010000
-  0x08000432:  6102         STR        R2, [R0, #16]
-  0x08000434:  F3BF 8F4F    DSB        SY
-  0x08000438:  F3BF 8F6F    ISB        SY
-  0x0800043C:  6802         LDR        R2, [R0]
-  0x0800043E:  0392         LSLS       R2, R2, #14
-  0x08000440:  D411         BMI        .L1                      ; 0x08000466
-  0x08000442:  F3BF 8F4F    DSB        SY
-  0x08000446:  F3BF 8F6F    ISB        SY
-  0x0800044A:  F8C0 123C    STR.W      R1, [R0, #0x023C]
-  0x0800044E:  F3BF 8F4F    DSB        SY
-  0x08000452:  F3BF 8F6F    ISB        SY
-  0x08000456:  6801         LDR        R1, [R0]
-  0x08000458:  F441 3100    ORR        R1, R1, #0x020000
-  0x0800045C:  6001         STR        R1, [R0]
-  0x0800045E:  F3BF 8F4F    DSB        SY
-  0x08000462:  F3BF 8F6F    ISB        SY
+
    SystemClock_Config():
+  0x080003EC:  B510         PUSH       {R4, LR}
+  0x080003EE:  B082         SUB        SP, SP, #8
+  0x080003F0:  F644 010C    MOVW       R1, #0x480C
+  0x080003F4:  F6C5 0102    MOVT       R1, #0x5802
+  0x080003F8:  6808         LDR        R0, [R1]
+  0x080003FA:  680A         LDR        R2, [R1]
+  0x080003FC:  0740         LSLS       R0, R0, #29
+  0x080003FE:  F240 0024    MOVW       R0, #36                  ; 0x30000024 = uwTick
+  0x08000402:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000024 = uwTick
+  0x08000406:  D50D         BPL        .L2                      ; 0x08000424
+  0x08000408:  2302         MOVS       R3, #2
+  0x0800040A:  F363 0202    BFI        R2, R3, #0, #3
+  0x0800040E:  600A         STR        R2, [R1]
+  0x08000410:  6802         LDR        R2, [R0]
 
    .L1:
-  0x08000466:  B082         SUB        SP, SP, #8
-  0x08000468:  6801         LDR        R1, [R0]
-  0x0800046A:  03C9         LSLS       R1, R1, #15
-  0x0800046C:  D426         BMI        .L4                      ; 0x080004BC
-  0x0800046E:  2100         MOVS       R1, #0
-  0x08000470:  6701         STR        R1, [R0, #112]
-  0x08000472:  F3BF 8F4F    DSB        SY
-  0x08000476:  F643 7EE0    MOVW       LR, #0x3FE0
-  0x0800047A:  6EC2         LDR        R2, [R0, #108]
-  0x0800047C:  EA4F 0CD2    LSR.W      R12, R2, #3
-  0x08000480:  F3C2 314E    UBFX       R1, R2, #13, #15
-  0x08000484:  F3C2 03C9    UBFX       R3, R2, #3, #10
-  0x08000488:  3301         ADDS       R3, #1
-  0x0800048A:  014A         LSLS       R2, R1, #5
+  0x08000412:  F851 3C08    LDR        R3, [R1, #-8]
+  0x08000416:  049B         LSLS       R3, R3, #18
+  0x08000418:  D404         BMI        .L2                      ; 0x08000424
+  0x0800041A:  6803         LDR        R3, [R0]
+  0x0800041C:  1A9B         SUBS       R3, R3, R2
+  0x0800041E:  F5B3 7F7A    CMP.W      R3, #0x03E8
+  0x08000422:  D9F6         BLS        .L1                      ; 0x08000412
 
    .L2:
-  0x0800048C:  EA02 040E    AND.W      R4, R2, LR
-  0x08000490:  461D         MOV        R5, R3
-  0x08000492:  EB04 748C    ADD.W      R4, R4, R12, LSL #30
+  0x08000424:  2200         MOVS       R2, #0
+  0x08000426:  9201         STR        R2, [SP, #4]
+  0x08000428:  68CA         LDR        R2, [R1, #12]
+  0x0800042A:  2302         MOVS       R3, #2
+  0x0800042C:  F363 328F    BFI        R2, R3, #14, #2
+  0x08000430:  60CA         STR        R2, [R1, #12]
+  0x08000432:  68CA         LDR        R2, [R1, #12]
+  0x08000434:  F402 4240    AND        R2, R2, #0xC000
+  0x08000438:  9201         STR        R2, [SP, #4]
+  0x0800043A:  9A01         LDR        R2, [SP, #4]
 
    .L3:
-  0x08000496:  3D01         SUBS       R5, #1
-  0x08000498:  F8C0 424C    STR.W      R4, [R0, #0x024C]
-  0x0800049C:  F104 4440    ADD.W      R4, R4, #0xC0000000
-  0x080004A0:  D1F9         BNE        .L3                      ; 0x08000496
-  0x080004A2:  3A20         SUBS       R2, #32
-  0x080004A4:  3901         SUBS       R1, #1
-  0x080004A6:  D2F1         BCS        .L2                      ; 0x0800048C
-  0x080004A8:  F3BF 8F4F    DSB        SY
-  0x080004AC:  6801         LDR        R1, [R0]
-  0x080004AE:  F441 3180    ORR        R1, R1, #0x010000
-  0x080004B2:  6001         STR        R1, [R0]
-  0x080004B4:  F3BF 8F4F    DSB        SY
-  0x080004B8:  F3BF 8F6F    ISB        SY
+  0x0800043C:  68CA         LDR        R2, [R1, #12]
+  0x0800043E:  0492         LSLS       R2, R2, #18
+  0x08000440:  D5FC         BPL        .L3                      ; 0x0800043C
+  0x08000442:  F244 4400    MOVW       R4, #0x4400
+  0x08000446:  F6C5 0402    MOVT       R4, #0x5802
+  0x0800044A:  F8D4 1400    LDR.W      R1, [R4, #0x0400]
+  0x0800044E:  F441 7180    ORR        R1, R1, #0x0100
+  0x08000452:  F8C4 1400    STR.W      R1, [R4, #0x0400]
+  0x08000456:  6F21         LDR        R1, [R4, #112]
+  0x08000458:  F021 0118    BIC        R1, R1, #24
+  0x0800045C:  6721         STR        R1, [R4, #112]
+  0x0800045E:  6921         LDR        R1, [R4, #16]
+  0x08000460:  F001 0238    AND        R2, R1, #56
+  0x08000464:  6AA1         LDR        R1, [R4, #40]
+  0x08000466:  2A10         CMP        R2, #16
+  0x08000468:  D007         BEQ        .L4                      ; 0x0800047A
+  0x0800046A:  2A18         CMP        R2, #24
+  0x0800046C:  F040 80F4    BNE.W      .L16                     ; 0x08000658
+  0x08000470:  F001 0103    AND        R1, R1, #3
+  0x08000474:  2902         CMP        R1, #2
+  0x08000476:  F040 80EF    BNE.W      .L16                     ; 0x08000658
 
    .L4:
-  0x080004BC:  F000 F86C    BL         HAL_Init                 ; 0x08000598
-  0x080004C0:  F000 F8A3    BL         SystemClock_Config()     ; 0x0800060A
-  0x080004C4:  F244 40E0    MOVW       R0, #0x44E0
-  0x080004C8:  F6C5 0002    MOVT       R0, #0x5802
-  0x080004CC:  6801         LDR        R1, [R0]
-  0x080004CE:  F041 0104    ORR        R1, R1, #4
-  0x080004D2:  6001         STR        R1, [R0]
-  0x080004D4:  6801         LDR        R1, [R0]
-  0x080004D6:  F001 0104    AND        R1, R1, #4
-  0x080004DA:  9101         STR        R1, [SP, #4]
-  0x080004DC:  9901         LDR        R1, [SP, #4]
-  0x080004DE:  6801         LDR        R1, [R0]
-  0x080004E0:  F041 0180    ORR        R1, R1, #128
-  0x080004E4:  6001         STR        R1, [R0]
-  0x080004E6:  6800         LDR        R0, [R0]
-  0x080004E8:  F000 0080    AND        R0, R0, #128
-  0x080004EC:  9000         STR        R0, [SP, #0]
+  0x0800047A:  6821         LDR        R1, [R4]
+
    .L5:
+  0x0800047C:  F8D4 1400    LDR.W      R1, [R4, #0x0400]
+  0x08000480:  F441 7180    ORR        R1, R1, #0x0100
+  0x08000484:  F8C4 1400    STR.W      R1, [R4, #0x0400]
+  0x08000488:  6801         LDR        R1, [R0]
+
    .L6:
+  0x0800048A:  F8D4 2400    LDR.W      R2, [R4, #0x0400]
+  0x0800048E:  05D2         LSLS       R2, R2, #23
+  0x08000490:  D404         BMI        .L7                      ; 0x0800049C
+  0x08000492:  6802         LDR        R2, [R0]
+  0x08000494:  1A52         SUBS       R2, R2, R1
+  0x08000496:  2A64         CMP        R2, #100
+  0x08000498:  D9F7         BLS        .L6                      ; 0x0800048A
+  0x0800049A:  E132         B          .L22                     ; 0x08000702
+
    .L7:
+  0x0800049C:  6F21         LDR        R1, [R4, #112]
+  0x0800049E:  F241 3288    MOVW       R2, #0x1388
+  0x080004A2:  F041 0101    ORR        R1, R1, #1
+  0x080004A6:  6721         STR        R1, [R4, #112]
+  0x080004A8:  6801         LDR        R1, [R0]
+
    .L8:
+  0x080004AA:  6F23         LDR        R3, [R4, #112]
+  0x080004AC:  079B         LSLS       R3, R3, #30
+  0x080004AE:  D404         BMI        .L9                      ; 0x080004BA
+  0x080004B0:  6803         LDR        R3, [R0]
+  0x080004B2:  1A5B         SUBS       R3, R3, R1
+  0x080004B4:  4293         CMP        R3, R2
+  0x080004B6:  D9F8         BLS        .L8                      ; 0x080004AA
+  0x080004B8:  E123         B          .L22                     ; 0x08000702
+
    .L9:
+  0x080004BA:  6921         LDR        R1, [R4, #16]
+  0x080004BC:  F001 0138    AND        R1, R1, #56
+  0x080004C0:  2918         CMP        R1, #24
+  0x080004C2:  F040 80D7    BNE.W      .L18                     ; 0x08000674
+  0x080004C6:  6AA1         LDR        R1, [R4, #40]
+  0x080004C8:  F240 32F3    MOVW       R2, #0x03F3
+  0x080004CC:  4011         ANDS       R1, R2
+  0x080004CE:  F5B1 7FC9    CMP.W      R1, #0x0192
+  0x080004D2:  6B21         LDR        R1, [R4, #48]
+  0x080004D4:  F040 8115    BNE.W      .L22                     ; 0x08000702
+  0x080004D8:  460A         MOV        R2, R1
+  0x080004DA:  F36F 225F    BFC        R2, #9, #23
+  0x080004DE:  2AC7         CMP        R2, #199
+  0x080004E0:  F040 810F    BNE.W      .L22                     ; 0x08000702
+  0x080004E4:  F401 427E    AND        R2, R1, #0xFE00
+  0x080004E8:  F5B2 7F00    CMP.W      R2, #0x0200
+  0x080004EC:  F040 8109    BNE.W      .L22                     ; 0x08000702
+  0x080004F0:  F401 02FE    AND        R2, R1, #0x7F0000
+  0x080004F4:  F5B2 3F80    CMP.W      R2, #0x010000
+  0x080004F8:  F040 8103    BNE.W      .L22                     ; 0x08000702
+  0x080004FC:  F001 41FE    AND        R1, R1, #0x7F000000
+  0x08000500:  F1B1 7F80    CMP.W      R1, #0x01000000
+  0x08000504:  F040 80FD    BNE.W      .L22                     ; 0x08000702
+  0x08000508:  6B61         LDR        R1, [R4, #52]
+  0x0800050A:  F64F 72F8    MOVW       R2, #0xFFF8
+  0x0800050E:  4211         TST        R1, R2
+  0x08000510:  D010         BEQ        .L11                     ; 0x08000534
+  0x08000512:  6AE1         LDR        R1, [R4, #44]
+  0x08000514:  F021 0101    BIC        R1, R1, #1
+  0x08000518:  62E1         STR        R1, [R4, #44]
+  0x0800051A:  6801         LDR        R1, [R0]
+
    .L10:
+  0x0800051C:  6802         LDR        R2, [R0]
+  0x0800051E:  428A         CMP        R2, R1
+  0x08000520:  D0FC         BEQ        .L10                     ; 0x0800051C
+  0x08000522:  6B61         LDR        R1, [R4, #52]
+  0x08000524:  F64F 72F8    MOVW       R2, #0xFFF8
+  0x08000528:  4391         BICS       R1, R2
+  0x0800052A:  6361         STR        R1, [R4, #52]
+  0x0800052C:  6AE1         LDR        R1, [R4, #44]
+  0x0800052E:  F041 0101    ORR        R1, R1, #1
+  0x08000532:  62E1         STR        R1, [R4, #44]
+
    .L11:
+  0x08000534:  F242 0C00    MOVW       R12, #0x2000
+  0x08000538:  F2C5 2C00    MOVT       R12, #0x5200
+  0x0800053C:  F8DC 2000    LDR.W      R2, [R12]
+  0x08000540:  0712         LSLS       R2, R2, #28
+  0x08000542:  D10D         BNE        .L12                     ; 0x08000560
+  0x08000544:  F8DC 2000    LDR.W      R2, [R12]
+  0x08000548:  2301         MOVS       R3, #1
+  0x0800054A:  F363 0203    BFI        R2, R3, #0, #4
+  0x0800054E:  F8CC 2000    STR.W      R2, [R12]
+  0x08000552:  F8DC 2000    LDR.W      R2, [R12]
+  0x08000556:  F002 020F    AND        R2, R2, #15
+  0x0800055A:  2A01         CMP        R2, #1
+  0x0800055C:  F040 80D2    BNE.W      .L23                     ; 0x08000704
+
    .L12:
+  0x08000560:  69A2         LDR        R2, [R4, #24]
+  0x08000562:  69E2         LDR        R2, [R4, #28]
+  0x08000564:  69E2         LDR        R2, [R4, #28]
+  0x08000566:  6A22         LDR        R2, [R4, #32]
+  0x08000568:  69A2         LDR        R2, [R4, #24]
+  0x0800056A:  69A2         LDR        R2, [R4, #24]
+  0x0800056C:  F422 6270    BIC        R2, R2, #0x0F00
+  0x08000570:  61A2         STR        R2, [R4, #24]
+  0x08000572:  6822         LDR        R2, [R4]
+  0x08000574:  0192         LSLS       R2, R2, #6
+  0x08000576:  F140 80C5    BPL.W      .L23                     ; 0x08000704
+  0x0800057A:  6922         LDR        R2, [R4, #16]
+  0x0800057C:  2303         MOVS       R3, #3
+  0x0800057E:  F363 0202    BFI        R2, R3, #0, #3
+  0x08000582:  6122         STR        R2, [R4, #16]
+  0x08000584:  6802         LDR        R2, [R0]
+  0x08000586:  F241 3388    MOVW       R3, #0x1388
+
    .L13:
+  0x0800058A:  6921         LDR        R1, [R4, #16]
+  0x0800058C:  F001 0138    AND        R1, R1, #56
+  0x08000590:  2918         CMP        R1, #24
+  0x08000592:  D004         BEQ        .L14                     ; 0x0800059E
+  0x08000594:  6801         LDR        R1, [R0]
+  0x08000596:  1A89         SUBS       R1, R1, R2
+  0x08000598:  4299         CMP        R1, R3
+  0x0800059A:  D9F6         BLS        .L13                     ; 0x0800058A
+  0x0800059C:  E0B2         B          .L23                     ; 0x08000704
+
    .L14:
+  0x0800059E:  69A0         LDR        R0, [R4, #24]
+  0x080005A0:  0700         LSLS       R0, R0, #28
+  0x080005A2:  BF1E         ITTT       NE
+  0x080005A4:  69A0         LDRNE      R0, [R4, #24]
+  0x080005A6:  F020 000F    BICNE      R0, R0, #15
+  0x080005AA:  61A0         STRNE      R0, [R4, #24]
+  0x080005AC:  F8DC 0000    LDR.W      R0, [R12]
+  0x080005B0:  F010 0F0E    TST        R0, #14
+  0x080005B4:  D00D         BEQ        .L15                     ; 0x080005D2
+  0x080005B6:  F8DC 0000    LDR.W      R0, [R12]
+  0x080005BA:  2101         MOVS       R1, #1
+  0x080005BC:  F361 0003    BFI        R0, R1, #0, #4
+  0x080005C0:  F8CC 0000    STR.W      R0, [R12]
+  0x080005C4:  F8DC 0000    LDR.W      R0, [R12]
+  0x080005C8:  F000 000F    AND        R0, R0, #15
+  0x080005CC:  2801         CMP        R0, #1
+  0x080005CE:  F040 8099    BNE.W      .L23                     ; 0x08000704
+
    .L15:
+  0x080005D2:  69A0         LDR        R0, [R4, #24]
+  0x080005D4:  F010 0F70    TST        R0, #112
+  0x080005D8:  BF1E         ITTT       NE
+  0x080005DA:  69A0         LDRNE      R0, [R4, #24]
+  0x080005DC:  F020 0070    BICNE      R0, R0, #112
+  0x080005E0:  61A0         STRNE      R0, [R4, #24]
+  0x080005E2:  69E0         LDR        R0, [R4, #28]
+  0x080005E4:  F010 0F70    TST        R0, #112
+  0x080005E8:  BF1E         ITTT       NE
+  0x080005EA:  69E0         LDRNE      R0, [R4, #28]
+  0x080005EC:  F020 0070    BICNE      R0, R0, #112
+  0x080005F0:  61E0         STRNE      R0, [R4, #28]
+  0x080005F2:  69E0         LDR        R0, [R4, #28]
+  0x080005F4:  F410 6FE0    TST        R0, #0x0700
+  0x080005F8:  BF1E         ITTT       NE
+  0x080005FA:  69E0         LDRNE      R0, [R4, #28]
+  0x080005FC:  F420 60E0    BICNE      R0, R0, #0x0700
+  0x08000600:  61E0         STRNE      R0, [R4, #28]
+  0x08000602:  6A20         LDR        R0, [R4, #32]
+  0x08000604:  F010 0F70    TST        R0, #112
+  0x08000608:  BF1E         ITTT       NE
+  0x0800060A:  6A20         LDRNE      R0, [R4, #32]
+  0x0800060C:  F020 0070    BICNE      R0, R0, #112
+  0x08000610:  6220         STRNE      R0, [R4, #32]
+  0x08000612:  F7FF FE5B    BL         HAL_RCC_GetSysClockFreq  ; 0x080002CC
+  0x08000616:  69A1         LDR        R1, [R4, #24]
+  0x08000618:  F640 32AE    MOVW       R2, #0x0BAE              ; 0x08000BAE = D1CorePrescTable
+  0x0800061C:  F6C0 0200    MOVT       R2, #0x0800              ; 0x08000BAE = D1CorePrescTable
+  0x08000620:  F3C1 2103    UBFX       R1, R1, #8, #4
+  0x08000624:  5C51         LDRB       R1, [R2, R1]
+  0x08000626:  F240 0228    MOVW       R2, #40                  ; 0x30000028 = uwTickPrio
+  0x0800062A:  F2C3 0200    MOVT       R2, #0x3000              ; 0x30000028 = uwTickPrio
+  0x0800062E:  69A3         LDR        R3, [R4, #24]
+  0x08000630:  F240 032C    MOVW       R3, #44                  ; 0x3000002C = SystemCoreClock
+  0x08000634:  F001 011F    AND        R1, R1, #31
+  0x08000638:  7812         LDRB       R2, [R2]
+  0x0800063A:  F2C3 0300    MOVT       R3, #0x3000              ; 0x3000002C = SystemCoreClock
+  0x0800063E:  FA20 F101    LSR.W      R1, R0, R1
+  0x08000642:  2010         MOVS       R0, #16
+  0x08000644:  2A00         CMP        R2, #0
+  0x08000646:  6019         STR        R1, [R3]
+  0x08000648:  BF18         IT         NE
+  0x0800064A:  200F         MOVNE      R0, #15
+  0x0800064C:  F000 FA63    BL         HAL_InitTick             ; 0x08000B16
+  0x08000650:  2800         CMP        R0, #0
+  0x08000652:  D157         BNE        .L23                     ; 0x08000704
+  0x08000654:  B002         ADD        SP, SP, #8
+  0x08000656:  BD10         POP        {R4, PC}
+
    .L16:
+  0x08000658:  6821         LDR        R1, [R4]
+  0x0800065A:  F441 3180    ORR        R1, R1, #0x010000
+  0x0800065E:  6021         STR        R1, [R4]
+  0x08000660:  6801         LDR        R1, [R0]
+
    .L17:
+  0x08000662:  6822         LDR        R2, [R4]
+  0x08000664:  0392         LSLS       R2, R2, #14
+  0x08000666:  F53F AF09    BMI.W      .L5                      ; 0x0800047C
+  0x0800066A:  6802         LDR        R2, [R0]
+  0x0800066C:  1A52         SUBS       R2, R2, R1
+  0x0800066E:  2A64         CMP        R2, #100
+  0x08000670:  D9F7         BLS        .L17                     ; 0x08000662
+  0x08000672:  E046         B          .L22                     ; 0x08000702
+
    .L18:
+  0x08000674:  6821         LDR        R1, [R4]
+  0x08000676:  F021 7180    BIC        R1, R1, #0x01000000
+  0x0800067A:  6021         STR        R1, [R4]
+  0x0800067C:  6801         LDR        R1, [R0]
+
    .L19:
+  0x0800067E:  6822         LDR        R2, [R4]
+  0x08000680:  0192         LSLS       R2, R2, #6
+  0x08000682:  D504         BPL        .L20                     ; 0x0800068E
+  0x08000684:  6802         LDR        R2, [R0]
+  0x08000686:  1A52         SUBS       R2, R2, R1
+  0x08000688:  2A02         CMP        R2, #2
+  0x0800068A:  D9F8         BLS        .L19                     ; 0x0800067E
+  0x0800068C:  E039         B          .L22                     ; 0x08000702
+
    .L20:
+  0x0800068E:  6AA1         LDR        R1, [R4, #40]
+  0x08000690:  F240 32F3    MOVW       R2, #0x03F3
+  0x08000694:  4391         BICS       R1, R2
+  0x08000696:  F64F 72F8    MOVW       R2, #0xFFF8
+  0x0800069A:  F501 71C9    ADD.W      R1, R1, #0x0192
+  0x0800069E:  62A1         STR        R1, [R4, #40]
+  0x080006A0:  F240 21C7    MOVW       R1, #0x02C7
+  0x080006A4:  F2C0 1101    MOVT       R1, #0x0101
+  0x080006A8:  6321         STR        R1, [R4, #48]
+  0x080006AA:  6AE1         LDR        R1, [R4, #44]
+  0x080006AC:  F021 0101    BIC        R1, R1, #1
+  0x080006B0:  62E1         STR        R1, [R4, #44]
+  0x080006B2:  6B61         LDR        R1, [R4, #52]
+  0x080006B4:  4391         BICS       R1, R2
+  0x080006B6:  6361         STR        R1, [R4, #52]
+  0x080006B8:  6AE1         LDR        R1, [R4, #44]
+  0x080006BA:  F021 010C    BIC        R1, R1, #12
+  0x080006BE:  62E1         STR        R1, [R4, #44]
+  0x080006C0:  6AE1         LDR        R1, [R4, #44]
+  0x080006C2:  F041 0102    ORR        R1, R1, #2
+  0x080006C6:  62E1         STR        R1, [R4, #44]
+  0x080006C8:  6AE1         LDR        R1, [R4, #44]
+  0x080006CA:  F441 3180    ORR        R1, R1, #0x010000
+  0x080006CE:  62E1         STR        R1, [R4, #44]
+  0x080006D0:  6AE1         LDR        R1, [R4, #44]
+  0x080006D2:  F441 3100    ORR        R1, R1, #0x020000
+  0x080006D6:  62E1         STR        R1, [R4, #44]
+  0x080006D8:  6AE1         LDR        R1, [R4, #44]
+  0x080006DA:  F441 2180    ORR        R1, R1, #0x040000
+  0x080006DE:  62E1         STR        R1, [R4, #44]
+  0x080006E0:  6AE1         LDR        R1, [R4, #44]
+  0x080006E2:  F041 0101    ORR        R1, R1, #1
+  0x080006E6:  62E1         STR        R1, [R4, #44]
+  0x080006E8:  6821         LDR        R1, [R4]
+  0x080006EA:  F041 7180    ORR        R1, R1, #0x01000000
+  0x080006EE:  6021         STR        R1, [R4]
+  0x080006F0:  6801         LDR        R1, [R0]
+
    .L21:
+  0x080006F2:  6822         LDR        R2, [R4]
+  0x080006F4:  0192         LSLS       R2, R2, #6
+  0x080006F6:  F53F AF1D    BMI.W      .L11                     ; 0x08000534
+  0x080006FA:  6802         LDR        R2, [R0]
+  0x080006FC:  1A52         SUBS       R2, R2, R1
+  0x080006FE:  2A02         CMP        R2, #2
+  0x08000700:  D9F7         BLS        .L21                     ; 0x080006F2
+
    .L22:
+  0x08000702:  B672         CPSID      i
+
    .L23:
+  0x08000704:  B672         CPSID      i
 
    
 
    Section .text.SystemInit from charger_lto.o, size=166, align=2
    
 
    -
    SystemInit:
-  0x080004EE:  F64E 5088    MOVW       R0, #0xED88
-  0x080004F2:  F242 0300    MOVW       R3, #0x2000
-  0x080004F6:  F2CE 0000    MOVT       R0, #0xE000
-  0x080004FA:  F2C5 2300    MOVT       R3, #0x5200
-  0x080004FE:  6802         LDR        R2, [R0]
-  0x08000500:  F442 0270    ORR        R2, R2, #0xF00000
-  0x08000504:  6002         STR        R2, [R0]
-  0x08000506:  6818         LDR        R0, [R3]
-  0x08000508:  F000 000F    AND        R0, R0, #15
-  0x0800050C:  2806         CMP        R0, #6
-  0x0800050E:  D804         BHI        .L1                      ; 0x0800051A
-  0x08000510:  6818         LDR        R0, [R3]
-  0x08000512:  2207         MOVS       R2, #7
-  0x08000514:  F362 0003    BFI        R0, R2, #0, #4
-  0x08000518:  6018         STR        R0, [R3]
+
    SystemInit:
+  0x08000706:  F64E 5088    MOVW       R0, #0xED88
+  0x0800070A:  F242 0300    MOVW       R3, #0x2000
+  0x0800070E:  F2CE 0000    MOVT       R0, #0xE000
+  0x08000712:  F2C5 2300    MOVT       R3, #0x5200
+  0x08000716:  6802         LDR        R2, [R0]
+  0x08000718:  F442 0270    ORR        R2, R2, #0xF00000
+  0x0800071C:  6002         STR        R2, [R0]
+  0x0800071E:  6818         LDR        R0, [R3]
+  0x08000720:  F000 000F    AND        R0, R0, #15
+  0x08000724:  2806         CMP        R0, #6
+  0x08000726:  D804         BHI        .L1                      ; 0x08000732
+  0x08000728:  6818         LDR        R0, [R3]
+  0x0800072A:  2207         MOVS       R2, #7
+  0x0800072C:  F362 0003    BFI        R0, R2, #0, #4
+  0x08000730:  6018         STR        R0, [R3]
 
    .L1:
-  0x0800051A:  F244 4000    MOVW       R0, #0x4400
-  0x0800051E:  F64E 517F    MOVW       R1, #0xED7F
-  0x08000522:  F6C5 0002    MOVT       R0, #0x5802
-  0x08000526:  F6CE 21F6    MOVT       R1, #0xEAF6
-  0x0800052A:  6802         LDR        R2, [R0]
-  0x0800052C:  F042 0201    ORR        R2, R2, #1
-  0x08000530:  6002         STR        R2, [R0]
-  0x08000532:  2200         MOVS       R2, #0
-  0x08000534:  6102         STR        R2, [R0, #16]
-  0x08000536:  F8D0 C000    LDR.W      R12, [R0]
-  0x0800053A:  EA01 010C    AND.W      R1, R1, R12
-  0x0800053E:  6001         STR        R1, [R0]
-  0x08000540:  6819         LDR        R1, [R3]
-  0x08000542:  0709         LSLS       R1, R1, #28
-  0x08000544:  D505         BPL        .L2                      ; 0x08000552
-  0x08000546:  6819         LDR        R1, [R3]
-  0x08000548:  F04F 0C07    MOV.W      R12, #7
-  0x0800054C:  F36C 0103    BFI        R1, R12, #0, #4
-  0x08000550:  6019         STR        R1, [R3]
+  0x08000732:  F244 4000    MOVW       R0, #0x4400
+  0x08000736:  F64E 517F    MOVW       R1, #0xED7F
+  0x0800073A:  F6C5 0002    MOVT       R0, #0x5802
+  0x0800073E:  F6CE 21F6    MOVT       R1, #0xEAF6
+  0x08000742:  6802         LDR        R2, [R0]
+  0x08000744:  F042 0201    ORR        R2, R2, #1
+  0x08000748:  6002         STR        R2, [R0]
+  0x0800074A:  2200         MOVS       R2, #0
+  0x0800074C:  6102         STR        R2, [R0, #16]
+  0x0800074E:  F8D0 C000    LDR.W      R12, [R0]
+  0x08000752:  EA01 010C    AND.W      R1, R1, R12
+  0x08000756:  6001         STR        R1, [R0]
+  0x08000758:  6819         LDR        R1, [R3]
+  0x0800075A:  0709         LSLS       R1, R1, #28
+  0x0800075C:  D505         BPL        .L2                      ; 0x0800076A
+  0x0800075E:  6819         LDR        R1, [R3]
+  0x08000760:  F04F 0C07    MOV.W      R12, #7
+  0x08000764:  F36C 0103    BFI        R1, R12, #0, #4
+  0x08000768:  6019         STR        R1, [R3]
 
    .L2:
-  0x08000552:  F240 2100    MOVW       R1, #0x0200
-  0x08000556:  6182         STR        R2, [R0, #24]
-  0x08000558:  F2C0 2102    MOVT       R1, #0x0202
-  0x0800055C:  61C2         STR        R2, [R0, #28]
-  0x0800055E:  6202         STR        R2, [R0, #32]
-  0x08000560:  6281         STR        R1, [R0, #40]
-  0x08000562:  2100         MOVS       R1, #0
-  0x08000564:  F2C0 11FF    MOVT       R1, #0x01FF
-  0x08000568:  62C1         STR        R1, [R0, #44]
-  0x0800056A:  F240 2180    MOVW       R1, #0x0280
-  0x0800056E:  F2C0 1101    MOVT       R1, #0x0101
-  0x08000572:  6301         STR        R1, [R0, #48]
-  0x08000574:  6342         STR        R2, [R0, #52]
-  0x08000576:  6381         STR        R1, [R0, #56]
-  0x08000578:  63C2         STR        R2, [R0, #60]
-  0x0800057A:  6401         STR        R1, [R0, #64]
-  0x0800057C:  6442         STR        R2, [R0, #68]
-  0x0800057E:  6801         LDR        R1, [R0]
-  0x08000580:  F421 2180    BIC        R1, R1, #0x040000
-  0x08000584:  6001         STR        R1, [R0]
-  0x08000586:  6602         STR        R2, [R0, #96]
-  0x08000588:  F503 5000    ADD.W      R0, R3, #0x2000
-  0x0800058C:  F243 01D2    MOVW       R1, #0x30D2
-  0x08000590:  6001         STR        R1, [R0]
-  0x08000592:  4770         BX         LR
+  0x0800076A:  F240 2100    MOVW       R1, #0x0200
+  0x0800076E:  6182         STR        R2, [R0, #24]
+  0x08000770:  F2C0 2102    MOVT       R1, #0x0202
+  0x08000774:  61C2         STR        R2, [R0, #28]
+  0x08000776:  6202         STR        R2, [R0, #32]
+  0x08000778:  6281         STR        R1, [R0, #40]
+  0x0800077A:  2100         MOVS       R1, #0
+  0x0800077C:  F2C0 11FF    MOVT       R1, #0x01FF
+  0x08000780:  62C1         STR        R1, [R0, #44]
+  0x08000782:  F240 2180    MOVW       R1, #0x0280
+  0x08000786:  F2C0 1101    MOVT       R1, #0x0101
+  0x0800078A:  6301         STR        R1, [R0, #48]
+  0x0800078C:  6342         STR        R2, [R0, #52]
+  0x0800078E:  6381         STR        R1, [R0, #56]
+  0x08000790:  63C2         STR        R2, [R0, #60]
+  0x08000792:  6401         STR        R1, [R0, #64]
+  0x08000794:  6442         STR        R2, [R0, #68]
+  0x08000796:  6801         LDR        R1, [R0]
+  0x08000798:  F421 2180    BIC        R1, R1, #0x040000
+  0x0800079C:  6001         STR        R1, [R0]
+  0x0800079E:  6602         STR        R2, [R0, #96]
+  0x080007A0:  F503 5000    ADD.W      R0, R3, #0x2000
+  0x080007A4:  F243 01D2    MOVW       R1, #0x30D2
+  0x080007A8:  6001         STR        R1, [R0]
+  0x080007AA:  4770         BX         LR
 
    
 
    Section .text.NMI_Handler from charger_lto.o, size=2, align=2
    
 
    -
    NMI_Handler:
-HardFault_Handler:
-MemManage_Handler:
-BusFault_Handler:
-UsageFault_Handler:
-WWDG_IRQHandler:
-PVD_AVD_IRQHandler:
-TAMP_STAMP_IRQHandler:
-RTC_WKUP_IRQHandler:
-FLASH_IRQHandler:
-RCC_IRQHandler:
-EXTI0_IRQHandler:
-EXTI1_IRQHandler:
-EXTI2_IRQHandler:
-EXTI3_IRQHandler:
+
    NMI_Handler:
+HardFault_Handler:
+MemManage_Handler:
+BusFault_Handler:
+UsageFault_Handler:
+WWDG_IRQHandler:
+PVD_AVD_IRQHandler:
 EXTI4_IRQHandler:
-DMA1_Stream0_IRQHandler:
-DMA1_Stream1_IRQHandler:
-DMA1_Stream2_IRQHandler:
-DMA1_Stream3_IRQHandler:
-DMA1_Stream4_IRQHandler:
-DMA1_Stream5_IRQHandler:
-DMA1_Stream6_IRQHandler:
-ADC_IRQHandler:
-FDCAN1_IT0_IRQHandler:
-FDCAN2_IT0_IRQHandler:
-FDCAN1_IT1_IRQHandler:
-FDCAN2_IT1_IRQHandler:
-EXTI9_5_IRQHandler:
-TIM1_BRK_IRQHandler:
-TIM1_UP_IRQHandler:
-TIM1_TRG_COM_IRQHandler:
-TIM1_CC_IRQHandler:
-TIM2_IRQHandler:
-TIM3_IRQHandler:
-TIM4_IRQHandler:
-I2C1_EV_IRQHandler:
-I2C1_ER_IRQHandler:
-I2C2_EV_IRQHandler:
-I2C2_ER_IRQHandler:
-SPI1_IRQHandler:
-SPI2_IRQHandler:
-USART1_IRQHandler:
-USART2_IRQHandler:
-USART3_IRQHandler:
-EXTI15_10_IRQHandler:
-RTC_Alarm_IRQHandler:
-TIM8_BRK_TIM12_IRQHandler:
-TIM8_UP_TIM13_IRQHandler:
-TIM8_TRG_COM_TIM14_IRQHandler:
-TIM8_CC_IRQHandler:
-DMA1_Stream7_IRQHandler:
-FMC_IRQHandler:
-SDMMC1_IRQHandler:
-TIM5_IRQHandler:
-SPI3_IRQHandler:
-UART4_IRQHandler:
-UART5_IRQHandler:
+|
+Ÿ#">TAMP_STAMP_IRQHandler:
+RTC_WKUP_IRQHandler:
+FLASH_IRQHandler:
+RCC_IRQHandler:
+EXTI0_IRQHandler:
+EXTI1_IRQHandler:
+EXTI2_IRQHandler:
+EXTI3_IRQHandler:
+EXTI4_IRQHandler:
+DMA1_Stream0_IRQHandler:
+DMA1_Stream1_IRQHandler:
+DMA1_Stream2_IRQHandler:
+DMA1_Stream3_IRQHandler:
 TIM6_DAC_IRQHandler:
+}
+Ÿ#">DMA1_Stream4_IRQHandler:
+DMA1_Stream5_IRQHandler:
+DMA1_Stream6_IRQHandler:
+ADC_IRQHandler:
+FDCAN1_IT0_IRQHandler:
+FDCAN2_IT0_IRQHandler:
+FDCAN1_IT1_IRQHandler:
+FDCAN2_IT1_IRQHandler:
+EXTI9_5_IRQHandler:
+TIM1_BRK_IRQHandler:
+TIM1_UP_IRQHandler:
+TIM1_TRG_COM_IRQHandler:
 TIM7_IRQHandler:
-DMA2_Stream0_IRQHandler:
-DMA2_Stream1_IRQHandler:
-DMA2_Stream2_IRQHandler:
-DMA2_Stream3_IRQHandler:
-DMA2_Stream4_IRQHandler:
-ETH_IRQHandler:
-ETH_WKUP_IRQHandler:
-FDCAN_CAL_IRQHandler:
-DMA2_Stream5_IRQHandler:
-DMA2_Stream6_IRQHandler:
-DMA2_Stream7_IRQHandler:
-USART6_IRQHandler:
-I2C3_EV_IRQHandler:
-I2C3_ER_IRQHandler:
-OTG_HS_EP1_OUT_IRQHandler:
-OTG_HS_EP1_IN_IRQHandler:
-OTG_HS_WKUP_IRQHandler:
-OTG_HS_IRQHandler:
-DCMI_PSSI_IRQHandler:
-RNG_IRQHandler:
-FPU_IRQHandler:
-UART7_IRQHandler:
-UART8_IRQHandler:
-SPI4_IRQHandler:
-SPI5_IRQHandler:
-SPI6_IRQHandler:
-SAI1_IRQHandler:
-LTDC_IRQHandler:
-LTDC_ER_IRQHandler:
-DMA2D_IRQHandler:
-OCTOSPI1_IRQHandler:
-LPTIM1_IRQHandler:
-CEC_IRQHandler:
-I2C4_EV_IRQHandler:
-I2C4_ER_IRQHandler:
-SPDIF_RX_IRQHandler:
-DMAMUX1_OVR_IRQHandler:
-DFSDM1_FLT0_IRQHandler:
-DFSDM1_FLT1_IRQHandler:
-DFSDM1_FLT2_IRQHandler:
-DFSDM1_FLT3_IRQHandler:
-SWPMI1_IRQHandler:
-TIM15_IRQHandler:
-TIM16_IRQHandler:
-TIM17_IRQHandler:
-MDIOS_WKUP_IRQHandler:
-MDIOS_IRQHandler:
-MDMA_IRQHandler:
-SDMMC2_IRQHandler:
-HSEM1_IRQHandler:
-ADC3_IRQHandler:
-DMAMUX2_OVR_IRQHandler:
-BDMA_Channel0_IRQHandler:
-BDMA_Channel1_IRQHandler:
-BDMA_Channel2_IRQHandler:
-BDMA_Channel3_IRQHandler:
-BDMA_Channel4_IRQHandler:
-BDMA_Channel5_IRQHandler:
-BDMA_Channel6_IRQHandler:
-BDMA_Channel7_IRQHandler:
-COMP1_IRQHandler:
-LPTIM2_IRQHandler:
-LPTIM3_IRQHandler:
-LPTIM4_IRQHandler:
-LPTIM5_IRQHandler:
-LPUART1_IRQHandler:
-CRS_IRQHandler:
-ECC_IRQHandler:
-SAI4_IRQHandler:
-DTS_IRQHandler:
-WAKEUP_PIN_IRQHandler:
-OCTOSPI2_IRQHandler:
-FMAC_IRQHandler:
-CORDIC_IRQHandler:
-UART9_IRQHandler:
-USART10_IRQHandler:
+~
+Ÿ#">TIM1_CC_IRQHandler:
+TIM2_IRQHandler:
+TIM3_IRQHandler:
+TIM4_IRQHandler:
+I2C1_EV_IRQHandler:
+I2C1_ER_IRQHandler:
+I2C2_EV_IRQHandler:
+I2C2_ER_IRQHandler:
+SPI1_IRQHandler:
+SPI2_IRQHandler:
+USART1_IRQHandler:
+USART2_IRQHandler:
+USART3_IRQHandler:
+EXTI15_10_IRQHandler:
+RTC_Alarm_IRQHandler:
+TIM8_BRK_TIM12_IRQHandler:
+TIM8_UP_TIM13_IRQHandler:
+TIM8_TRG_COM_TIM14_IRQHandler:
 I2C5_EV_IRQHandler:
-I2C5_ER_IRQHandler:
-FDCAN3_IT0_IRQHandler:
-FDCAN3_IT1_IRQHandler:
-TIM23_IRQHandler:
-TIM24_IRQHandler:
-  0x08000594:  E7FE         B          NMI_Handler              ; Dedupe identical section .init.TIM24_IRQHandler
+
+Ÿ#">TIM8_CC_IRQHandler:
+DMA1_Stream7_IRQHandler:
+FMC_IRQHandler:
+SDMMC1_IRQHandler:
+TIM5_IRQHandler:
+SPI3_IRQHandler:
+UART4_IRQHandler:
+UART5_IRQHandler:
+TIM6_DAC_IRQHandler:
+TIM7_IRQHandler:
+DMA2_Stream0_IRQHandler:
+DMA2_Stream1_IRQHandler:
+DMA2_Stream2_IRQHandler:
+DMA2_Stream3_IRQHandler:
+DMA2_Stream4_IRQHandler:
+ETH_IRQHandler:
+ETH_WKUP_IRQHandler:
+FDCAN_CAL_IRQHandler:
+DMA2_Stream5_IRQHandler:
+DMA2_Stream6_IRQHandler:
+DMA2_Stream7_IRQHandler:
+USART6_IRQHandler:
+I2C3_EV_IRQHandler:
+I2C3_ER_IRQHandler:
+OTG_HS_EP1_OUT_IRQHandler:
+OTG_HS_EP1_IN_IRQHandler:
+OTG_HS_WKUP_IRQHandler:
+OTG_HS_IRQHandler:
+DCMI_PSSI_IRQHandler:
+RNG_IRQHandler:
+FPU_IRQHandler:
+UART7_IRQHandler:
+UART8_IRQHandler:
+SPI4_IRQHandler:
+SPI5_IRQHandler:
+SPI6_IRQHandler:
+SAI1_IRQHandler:
+LTDC_IRQHandler:
+LTDC_ER_IRQHandler:
+DMA2D_IRQHandler:
+OCTOSPI1_IRQHandler:
+LPTIM1_IRQHandler:
+CEC_IRQHandler:
+I2C4_EV_IRQHandler:
+I2C4_ER_IRQHandler:
+SPDIF_RX_IRQHandler:
+DMAMUX1_OVR_IRQHandler:
+DFSDM1_FLT0_IRQHandler:
+DFSDM1_FLT1_IRQHandler:
+DFSDM1_FLT2_IRQHandler:
+DFSDM1_FLT3_IRQHandler:
+SWPMI1_IRQHandler:
+TIM15_IRQHandler:
+TIM16_IRQHandler:
+TIM17_IRQHandler:
+MDIOS_WKUP_IRQHandler:
+MDIOS_IRQHandler:
+MDMA_IRQHandler:
+SDMMC2_IRQHandler:
+HSEM1_IRQHandler:
+ADC3_IRQHandler:
+DMAMUX2_OVR_IRQHandler:
+BDMA_Channel0_IRQHandler:
+BDMA_Channel1_IRQHandler:
+BDMA_Channel2_IRQHandler:
+BDMA_Channel3_IRQHandler:
+BDMA_Channel4_IRQHandler:
+BDMA_Channel5_IRQHandler:
+BDMA_Channel6_IRQHandler:
+BDMA_Channel7_IRQHandler:
+COMP1_IRQHandler:
+LPTIM2_IRQHandler:
+LPTIM3_IRQHandler:
+LPTIM4_IRQHandler:
+LPTIM5_IRQHandler:
+LPUART1_IRQHandler:
+CRS_IRQHandler:
+ECC_IRQHandler:
+SAI4_IRQHandler:
+DTS_IRQHandler:
+WAKEUP_PIN_IRQHandler:
+OCTOSPI2_IRQHandler:
+FMAC_IRQHandler:
+CORDIC_IRQHandler:
+UART9_IRQHandler:
+USART10_IRQHandler:
+I2C5_EV_IRQHandler:
+I2C5_ER_IRQHandler:
+FDCAN3_IT0_IRQHandler:
+FDCAN3_IT1_IRQHandler:
+TIM23_IRQHandler:
+TIM24_IRQHandler:
+  0x080007AC:  E7FE         B          NMI_Handler              ; Dedupe identical section .init.TIM24_IRQHandler
 
    
 
    Section .text.SVC_Handler from charger_lto.o, size=2, align=2
    
 
    -
    SVC_Handler:
-DebugMon_Handler:
-PendSV_Handler:
-  0x08000596:  4770         BX         LR                       ; Dedupe identical section .text.PendSV_Handler
+
    SVC_Handler:
+DebugMon_Handler:
+PendSV_Handler:
+  0x080007AE:  4770         BX         LR                       ; Dedupe identical section .text.PendSV_Handler
 
    
 
    Section .text.HAL_Init from charger_lto.o, size=114, align=2
    
 
    -
    HAL_Init:
-  0x08000598:  B510         PUSH       {R4, LR}
-  0x0800059A:  B082         SUB        SP, SP, #8
-  0x0800059C:  F64E 500C    MOVW       R0, #0xED0C
-  0x080005A0:  F64F 02FF    MOVW       R2, #0xF8FF
-  0x080005A4:  F2CE 0000    MOVT       R0, #0xE000
-  0x080005A8:  F244 4418    MOVW       R4, #0x4418
-  0x080005AC:  F6C5 0402    MOVT       R4, #0x5802
-  0x080005B0:  6801         LDR        R1, [R0]
-  0x080005B2:  4011         ANDS       R1, R2
-  0x080005B4:  F240 3200    MOVW       R2, #0x0300
-  0x080005B8:  F2C0 52FA    MOVT       R2, #0x05FA
-  0x080005BC:  4311         ORRS       R1, R2
-  0x080005BE:  6001         STR        R1, [R0]
-  0x080005C0:  F7FF FE84    BL         HAL_RCC_GetSysClockFreq  ; 0x080002CC
-  0x080005C4:  6821         LDR        R1, [R4]
-  0x080005C6:  F640 0286    MOVW       R2, #0x0886              ; 0x08000886 = D1CorePrescTable
-  0x080005CA:  F6C0 0200    MOVT       R2, #0x0800              ; 0x08000886 = D1CorePrescTable
-  0x080005CE:  F3C1 2103    UBFX       R1, R1, #8, #4
-  0x080005D2:  5C51         LDRB       R1, [R2, R1]
-  0x080005D4:  6822         LDR        R2, [R4]
-  0x080005D6:  F001 011F    AND        R1, R1, #31
-  0x080005DA:  40C8         LSRS       R0, R1
-  0x080005DC:  F240 0108    MOVW       R1, #8                   ; 0x30000008 = SystemCoreClock
-  0x080005E0:  F2C3 0100    MOVT       R1, #0x3000              ; 0x30000008 = SystemCoreClock
-  0x080005E4:  6008         STR        R0, [R1]
-  0x080005E6:  200F         MOVS       R0, #15
-  0x080005E8:  F000 F901    BL         HAL_InitTick             ; 0x080007EE
-  0x080005EC:  B958         CBNZ       R0, .L1                  ; 0x08000606
-  0x080005EE:  F8D4 00DC    LDR.W      R0, [R4, #220]
-  0x080005F2:  F040 0002    ORR        R0, R0, #2
-  0x080005F6:  F8C4 00DC    STR.W      R0, [R4, #220]
-  0x080005FA:  F8D4 00DC    LDR.W      R0, [R4, #220]
-  0x080005FE:  F000 0002    AND        R0, R0, #2
-  0x08000602:  9001         STR        R0, [SP, #4]
-  0x08000604:  9801         LDR        R0, [SP, #4]
+
    HAL_Init:
+  0x080007B0:  B510         PUSH       {R4, LR}
+  0x080007B2:  B082         SUB        SP, SP, #8
+  0x080007B4:  F64E 500C    MOVW       R0, #0xED0C
+  0x080007B8:  F64F 02FF    MOVW       R2, #0xF8FF
+  0x080007BC:  F2CE 0000    MOVT       R0, #0xE000
+  0x080007C0:  F244 4418    MOVW       R4, #0x4418
+  0x080007C4:  F6C5 0402    MOVT       R4, #0x5802
+  0x080007C8:  6801         LDR        R1, [R0]
+  0x080007CA:  4011         ANDS       R1, R2
+  0x080007CC:  F240 3200    MOVW       R2, #0x0300
+  0x080007D0:  F2C0 52FA    MOVT       R2, #0x05FA
+  0x080007D4:  4311         ORRS       R1, R2
+  0x080007D6:  6001         STR        R1, [R0]
+  0x080007D8:  F7FF FD78    BL         HAL_RCC_GetSysClockFreq  ; 0x080002CC
+  0x080007DC:  6821         LDR        R1, [R4]
+  0x080007DE:  F640 32AE    MOVW       R2, #0x0BAE              ; 0x08000BAE = D1CorePrescTable
+  0x080007E2:  F6C0 0200    MOVT       R2, #0x0800              ; 0x08000BAE = D1CorePrescTable
+  0x080007E6:  F3C1 2103    UBFX       R1, R1, #8, #4
+  0x080007EA:  5C51         LDRB       R1, [R2, R1]
+  0x080007EC:  6822         LDR        R2, [R4]
+  0x080007EE:  F001 011F    AND        R1, R1, #31
+  0x080007F2:  40C8         LSRS       R0, R1
+  0x080007F4:  F240 012C    MOVW       R1, #44                  ; 0x3000002C = SystemCoreClock
+  0x080007F8:  F2C3 0100    MOVT       R1, #0x3000              ; 0x3000002C = SystemCoreClock
+  0x080007FC:  6008         STR        R0, [R1]
+  0x080007FE:  200F         MOVS       R0, #15
+  0x08000800:  F000 F989    BL         HAL_InitTick             ; 0x08000B16
+  0x08000804:  B958         CBNZ       R0, .L1                  ; 0x0800081E
+  0x08000806:  F8D4 00DC    LDR.W      R0, [R4, #220]
+  0x0800080A:  F040 0002    ORR        R0, R0, #2
+  0x0800080E:  F8C4 00DC    STR.W      R0, [R4, #220]
+  0x08000812:  F8D4 00DC    LDR.W      R0, [R4, #220]
+  0x08000816:  F000 0002    AND        R0, R0, #2
+  0x0800081A:  9001         STR        R0, [SP, #4]
+  0x0800081C:  9801         LDR        R0, [SP, #4]
 
    .L1:
-  0x08000606:  B002         ADD        SP, SP, #8
-  0x08000608:  BD10         POP        {R4, PC}
+  0x0800081E:  B002         ADD        SP, SP, #8
+  0x08000820:  BD10         POP        {R4, PC}
 
    
-
    Section .text.SystemClock_Config() from charger_lto.o, size=468, align=2
    
+
    Section .text.HAL_RTC_Init from charger_lto.o, size=382, align=2
    
 
    -
    SystemClock_Config():
-  0x0800060A:  B510         PUSH       {R4, LR}
-  0x0800060C:  B082         SUB        SP, SP, #8
-  0x0800060E:  F644 010C    MOVW       R1, #0x480C
-  0x08000612:  F6C5 0102    MOVT       R1, #0x5802
-  0x08000616:  6808         LDR        R0, [R1]
-  0x08000618:  680A         LDR        R2, [R1]
-  0x0800061A:  0740         LSLS       R0, R0, #29
-  0x0800061C:  F240 0000    MOVW       R0, #0                   ; 0x30000000 = uwTick
-  0x08000620:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000000 = uwTick
-  0x08000624:  D50D         BPL        .L2                      ; 0x08000642
-  0x08000626:  2302         MOVS       R3, #2
-  0x08000628:  F363 0202    BFI        R2, R3, #0, #3
-  0x0800062C:  600A         STR        R2, [R1]
-  0x0800062E:  6802         LDR        R2, [R0]
+
    HAL_RTC_Init:
+  0x08000822:  B570         PUSH       {R4-R6, LR}
+  0x08000824:  F240 0604    MOVW       R6, #4                   ; 0x30000000 = hrtc
+  0x08000828:  F2C3 0600    MOVT       R6, #0x3000              ; 0x30000000 = hrtc
+  0x0800082C:  7F70         LDRB       R0, [R6, #29]
+  0x0800082E:  2800         CMP        R0, #0
+  0x08000830:  F856 0C04    LDR        R0, [R6, #-4]
+  0x08000834:  D149         BNE        .L7                      ; 0x080008CA
+  0x08000836:  F244 0100    MOVW       R1, #0x4000
+  0x0800083A:  F6C5 0100    MOVT       R1, #0x5800
+  0x0800083E:  4288         CMP        R0, R1
+  0x08000840:  F04F 0100    MOV.W      R1, #0
+  0x08000844:  7731         STRB       R1, [R6, #28]
+  0x08000846:  D140         BNE        .L7                      ; 0x080008CA
+  0x08000848:  F244 4110    MOVW       R1, #0x4410
+  0x0800084C:  F6C5 0102    MOVT       R1, #0x5802
+  0x08000850:  F8D1 23F0    LDR.W      R2, [R1, #0x03F0]
+  0x08000854:  F442 7280    ORR        R2, R2, #0x0100
+  0x08000858:  F8C1 23F0    STR.W      R2, [R1, #0x03F0]
+  0x0800085C:  F240 0224    MOVW       R2, #36                  ; 0x30000024 = uwTick
+  0x08000860:  F2C3 0200    MOVT       R2, #0x3000              ; 0x30000024 = uwTick
+  0x08000864:  6813         LDR        R3, [R2]
 
    .L1:
-  0x08000630:  F851 3C08    LDR        R3, [R1, #-8]
-  0x08000634:  049B         LSLS       R3, R3, #18
-  0x08000636:  D404         BMI        .L2                      ; 0x08000642
-  0x08000638:  6803         LDR        R3, [R0]
-  0x0800063A:  1A9B         SUBS       R3, R3, R2
-  0x0800063C:  F5B3 7F7A    CMP.W      R3, #0x03E8
-  0x08000640:  D9F6         BLS        .L1                      ; 0x08000630
+  0x08000866:  F8D1 53F0    LDR.W      R5, [R1, #0x03F0]
+  0x0800086A:  05ED         LSLS       R5, R5, #23
+  0x0800086C:  D404         BMI        .L2                      ; 0x08000878
+  0x0800086E:  6815         LDR        R5, [R2]
+  0x08000870:  1AED         SUBS       R5, R5, R3
+  0x08000872:  2D64         CMP        R5, #100
+  0x08000874:  D9F7         BLS        .L1                      ; 0x08000866
+  0x08000876:  E01B         B          .L5                      ; 0x080008B0
 
    .L2:
-  0x08000642:  2200         MOVS       R2, #0
-  0x08000644:  9201         STR        R2, [SP, #4]
-  0x08000646:  68CA         LDR        R2, [R1, #12]
-  0x08000648:  2301         MOVS       R3, #1
-  0x0800064A:  F363 328F    BFI        R2, R3, #14, #2
-  0x0800064E:  60CA         STR        R2, [R1, #12]
-  0x08000650:  68CA         LDR        R2, [R1, #12]
-  0x08000652:  F402 4240    AND        R2, R2, #0xC000
-  0x08000656:  9201         STR        R2, [SP, #4]
-  0x08000658:  9A01         LDR        R2, [SP, #4]
+  0x08000878:  6E0B         LDR        R3, [R1, #96]
+  0x0800087A:  F403 7340    AND        R3, R3, #0x0300
+  0x0800087E:  F5B3 7F80    CMP.W      R3, #0x0100
+  0x08000882:  D00B         BEQ        .L3                      ; 0x0800089C
+  0x08000884:  6E0B         LDR        R3, [R1, #96]
+  0x08000886:  6E0D         LDR        R5, [R1, #96]
+  0x08000888:  F445 3580    ORR        R5, R5, #0x010000
+  0x0800088C:  660D         STR        R5, [R1, #96]
+  0x0800088E:  6E0D         LDR        R5, [R1, #96]
+  0x08000890:  F423 7340    BIC        R3, R3, #0x0300
+  0x08000894:  F425 3580    BIC        R5, R5, #0x010000
+  0x08000898:  660D         STR        R5, [R1, #96]
+  0x0800089A:  660B         STR        R3, [R1, #96]
 
    .L3:
-  0x0800065A:  68CA         LDR        R2, [R1, #12]
-  0x0800065C:  0492         LSLS       R2, R2, #18
-  0x0800065E:  D5FC         BPL        .L3                      ; 0x0800065A
-  0x08000660:  F244 4400    MOVW       R4, #0x4400
-  0x08000664:  F6C5 0402    MOVT       R4, #0x5802
-  0x08000668:  6921         LDR        R1, [R4, #16]
-  0x0800066A:  F011 0238    ANDS       R2, R1, #56
-  0x0800066E:  6AA1         LDR        R1, [R4, #40]
-  0x08000670:  D013         BEQ        .L5                      ; 0x0800069A
-  0x08000672:  2A18         CMP        R2, #24
-  0x08000674:  BF08         IT         EQ
-  0x08000676:  EA5F 7181    LSLSEQ.W   R1, R1, #30
-  0x0800067A:  D00E         BEQ        .L5                      ; 0x0800069A
-  0x0800067C:  6821         LDR        R1, [R4]
-  0x0800067E:  F041 0101    ORR        R1, R1, #1
-  0x08000682:  F021 0118    BIC        R1, R1, #24
-  0x08000686:  6021         STR        R1, [R4]
-  0x08000688:  6801         LDR        R1, [R0]
+  0x0800089C:  6813         LDR        R3, [R2]
+  0x0800089E:  F241 3589    MOVW       R5, #0x1389
 
    .L4:
-  0x0800068A:  6822         LDR        R2, [R4]
-  0x0800068C:  0752         LSLS       R2, R2, #29
-  0x0800068E:  D414         BMI        .L8                      ; 0x080006BA
-  0x08000690:  6802         LDR        R2, [R0]
-  0x08000692:  1A52         SUBS       R2, R2, R1
-  0x08000694:  2A03         CMP        R2, #3
-  0x08000696:  D3F8         BCC        .L4                      ; 0x0800068A
-  0x08000698:  E00E         B          .L7                      ; 0x080006B8
+  0x080008A2:  6E0C         LDR        R4, [R1, #96]
+  0x080008A4:  07A4         LSLS       R4, R4, #30
+  0x080008A6:  D404         BMI        .L6                      ; 0x080008B2
+  0x080008A8:  6814         LDR        R4, [R2]
+  0x080008AA:  1AE4         SUBS       R4, R4, R3
+  0x080008AC:  42AC         CMP        R4, R5
+  0x080008AE:  D3F8         BCC        .L4                      ; 0x080008A2
 
    .L5:
-  0x0800069A:  6821         LDR        R1, [R4]
-  0x0800069C:  6821         LDR        R1, [R4]
-  0x0800069E:  F041 0101    ORR        R1, R1, #1
-  0x080006A2:  F021 0118    BIC        R1, R1, #24
-  0x080006A6:  6021         STR        R1, [R4]
-  0x080006A8:  6801         LDR        R1, [R0]
+  0x080008B0:  B672         CPSID      i
 
    .L6:
-  0x080006AA:  6822         LDR        R2, [R4]
-  0x080006AC:  0752         LSLS       R2, R2, #29
-  0x080006AE:  D404         BMI        .L8                      ; 0x080006BA
-  0x080006B0:  6802         LDR        R2, [R0]
-  0x080006B2:  1A52         SUBS       R2, R2, R1
-  0x080006B4:  2A02         CMP        R2, #2
-  0x080006B6:  D9F8         BLS        .L6                      ; 0x080006AA
+  0x080008B2:  680A         LDR        R2, [R1]
+  0x080008B4:  F422 527C    BIC        R2, R2, #0x3F00
+  0x080008B8:  600A         STR        R2, [R1]
+  0x080008BA:  6E0A         LDR        R2, [R1, #96]
+  0x080008BC:  F442 7280    ORR        R2, R2, #0x0100
+  0x080008C0:  660A         STR        R2, [R1, #96]
+  0x080008C2:  6E0A         LDR        R2, [R1, #96]
+  0x080008C4:  F442 4200    ORR        R2, R2, #0x8000
+  0x080008C8:  660A         STR        R2, [R1, #96]
 
    .L7:
-  0x080006B8:  B672         CPSID      i
+  0x080008CA:  2102         MOVS       R1, #2
+  0x080008CC:  7771         STRB       R1, [R6, #29]
+  0x080008CE:  68C1         LDR        R1, [R0, #12]
+  0x080008D0:  06C9         LSLS       R1, R1, #27
+  0x080008D2:  D461         BMI        .L14                     ; 0x08000998
+  0x080008D4:  21CA         MOVS       R1, #202
+  0x080008D6:  6241         STR        R1, [R0, #36]
+  0x080008D8:  2153         MOVS       R1, #83
+  0x080008DA:  6241         STR        R1, [R0, #36]
+  0x080008DC:  68C1         LDR        R1, [R0, #12]
+  0x080008DE:  0649         LSLS       R1, R1, #25
+  0x080008E0:  D413         BMI        .L9                      ; 0x0800090A
+  0x080008E2:  F04F 31FF    MOV.W      R1, #0xFFFFFFFF
+  0x080008E6:  60C1         STR        R1, [R0, #12]
+  0x080008E8:  F240 0124    MOVW       R1, #36                  ; 0x30000024 = uwTick
+  0x080008EC:  F2C3 0100    MOVT       R1, #0x3000              ; 0x30000024 = uwTick
+  0x080008F0:  680A         LDR        R2, [R1]
 
    .L8:
-  0x080006BA:  F242 0C00    MOVW       R12, #0x2000
-  0x080006BE:  6862         LDR        R2, [R4, #4]
-  0x080006C0:  F2C5 2C00    MOVT       R12, #0x5200
-  0x080006C4:  2340         MOVS       R3, #64
-  0x080006C6:  F363 621E    BFI        R2, R3, #24, #7
-  0x080006CA:  6062         STR        R2, [R4, #4]
-  0x080006CC:  F8DC 2000    LDR.W      R2, [R12]
-  0x080006D0:  0712         LSLS       R2, R2, #28
-  0x080006D2:  D10C         BNE        .L9                      ; 0x080006EE
-  0x080006D4:  F8DC 2000    LDR.W      R2, [R12]
-  0x080006D8:  2301         MOVS       R3, #1
-  0x080006DA:  F363 0203    BFI        R2, R3, #0, #4
-  0x080006DE:  F8CC 2000    STR.W      R2, [R12]
-  0x080006E2:  F8DC 2000    LDR.W      R2, [R12]
-  0x080006E6:  F002 020F    AND        R2, R2, #15
-  0x080006EA:  2A01         CMP        R2, #1
-  0x080006EC:  D176         BNE        .L13                     ; 0x080007DC
+  0x080008F2:  68C3         LDR        R3, [R0, #12]
+  0x080008F4:  065B         LSLS       R3, R3, #25
+  0x080008F6:  D408         BMI        .L9                      ; 0x0800090A
+  0x080008F8:  680B         LDR        R3, [R1]
+  0x080008FA:  1A9B         SUBS       R3, R3, R2
+  0x080008FC:  F5B3 7F7A    CMP.W      R3, #0x03E8
+  0x08000900:  D9F7         BLS        .L8                      ; 0x080008F2
+  0x08000902:  2103         MOVS       R1, #3
+  0x08000904:  7771         STRB       R1, [R6, #29]
+  0x08000906:  68C0         LDR        R0, [R0, #12]
+  0x08000908:  E02E         B          .L11                     ; 0x08000968
 
    .L9:
-  0x080006EE:  69A2         LDR        R2, [R4, #24]
-  0x080006F0:  69E2         LDR        R2, [R4, #28]
-  0x080006F2:  69E2         LDR        R2, [R4, #28]
-  0x080006F4:  6A22         LDR        R2, [R4, #32]
-  0x080006F6:  69A2         LDR        R2, [R4, #24]
-  0x080006F8:  69A2         LDR        R2, [R4, #24]
-  0x080006FA:  F422 6270    BIC        R2, R2, #0x0F00
-  0x080006FE:  61A2         STR        R2, [R4, #24]
-  0x08000700:  6822         LDR        R2, [R4]
-  0x08000702:  0752         LSLS       R2, R2, #29
-  0x08000704:  D56A         BPL        .L13                     ; 0x080007DC
-  0x08000706:  6922         LDR        R2, [R4, #16]
-  0x08000708:  F241 3388    MOVW       R3, #0x1388
-  0x0800070C:  F022 0207    BIC        R2, R2, #7
-  0x08000710:  6122         STR        R2, [R4, #16]
-  0x08000712:  6802         LDR        R2, [R0]
+  0x0800090A:  6881         LDR        R1, [R0, #8]
+  0x0800090C:  F244 0508    MOVW       R5, #0x4008
+  0x08000910:  F421 01E0    BIC        R1, R1, #0x700000
+  0x08000914:  F6C5 0500    MOVT       R5, #0x5800
+  0x08000918:  F021 0140    BIC        R1, R1, #64
+  0x0800091C:  6081         STR        R1, [R0, #8]
+  0x0800091E:  E896 001E    LDM.W      R6, {R1-R4}
+  0x08000922:  4321         ORRS       R1, R4
+  0x08000924:  6974         LDR        R4, [R6, #20]
+  0x08000926:  4321         ORRS       R1, R4
+  0x08000928:  6884         LDR        R4, [R0, #8]
+  0x0800092A:  4321         ORRS       R1, R4
+  0x0800092C:  6081         STR        R1, [R0, #8]
+  0x0800092E:  EA43 4102    ORR.W      R1, R3, R2, LSL #16
+  0x08000932:  6101         STR        R1, [R0, #16]
+  0x08000934:  6868         LDR        R0, [R5, #4]
+  0x08000936:  F020 0080    BIC        R0, R0, #128
+  0x0800093A:  6068         STR        R0, [R5, #4]
+  0x0800093C:  6828         LDR        R0, [R5]
+  0x0800093E:  0680         LSLS       R0, R0, #26
+  0x08000940:  D405         BMI        .L10                     ; 0x0800094E
+  0x08000942:  F000 F82D    BL         HAL_RTC_WaitForSynchro   ; 0x080009A0
+  0x08000946:  B1C8         CBZ        R0, .L13                 ; 0x0800097C
+  0x08000948:  2003         MOVS       R0, #3
+  0x0800094A:  7770         STRB       R0, [R6, #29]
+  0x0800094C:  E00C         B          .L11                     ; 0x08000968
 
    .L10:
-  0x08000714:  6921         LDR        R1, [R4, #16]
-  0x08000716:  F011 0F38    TST        R1, #56
-  0x0800071A:  D004         BEQ        .L11                     ; 0x08000726
-  0x0800071C:  6801         LDR        R1, [R0]
-  0x0800071E:  1A89         SUBS       R1, R1, R2
-  0x08000720:  4299         CMP        R1, R3
-  0x08000722:  D9F7         BLS        .L10                     ; 0x08000714
-  0x08000724:  E05A         B          .L13                     ; 0x080007DC
+  0x0800094E:  6828         LDR        R0, [R5]
+  0x08000950:  F020 0020    BIC        R0, R0, #32
+  0x08000954:  6028         STR        R0, [R5]
+  0x08000956:  F000 F823    BL         HAL_RTC_WaitForSynchro   ; 0x080009A0
+  0x0800095A:  B158         CBZ        R0, .L12                 ; 0x08000974
+  0x0800095C:  2003         MOVS       R0, #3
+  0x0800095E:  7770         STRB       R0, [R6, #29]
+  0x08000960:  6828         LDR        R0, [R5]
+  0x08000962:  F040 0020    ORR        R0, R0, #32
+  0x08000966:  6028         STR        R0, [R5]
 
    .L11:
-  0x08000726:  69A0         LDR        R0, [R4, #24]
-  0x08000728:  0700         LSLS       R0, R0, #28
-  0x0800072A:  BF1E         ITTT       NE
-  0x0800072C:  69A0         LDRNE      R0, [R4, #24]
-  0x0800072E:  F020 000F    BICNE      R0, R0, #15
-  0x08000732:  61A0         STRNE      R0, [R4, #24]
-  0x08000734:  F8DC 0000    LDR.W      R0, [R12]
-  0x08000738:  F010 0F0E    TST        R0, #14
-  0x0800073C:  D00C         BEQ        .L12                     ; 0x08000758
-  0x0800073E:  F8DC 0000    LDR.W      R0, [R12]
-  0x08000742:  2101         MOVS       R1, #1
-  0x08000744:  F361 0003    BFI        R0, R1, #0, #4
-  0x08000748:  F8CC 0000    STR.W      R0, [R12]
-  0x0800074C:  F8DC 0000    LDR.W      R0, [R12]
-  0x08000750:  F000 000F    AND        R0, R0, #15
-  0x08000754:  2801         CMP        R0, #1
-  0x08000756:  D141         BNE        .L13                     ; 0x080007DC
+  0x08000968:  F856 0C04    LDR        R0, [R6, #-4]
+  0x0800096C:  21FF         MOVS       R1, #255
+  0x0800096E:  6241         STR        R1, [R0, #36]
+  0x08000970:  2003         MOVS       R0, #3
+  0x08000972:  BD70         POP        {R4-R6, PC}
 
    .L12:
-  0x08000758:  69A0         LDR        R0, [R4, #24]
-  0x0800075A:  F010 0F70    TST        R0, #112
-  0x0800075E:  BF1E         ITTT       NE
-  0x08000760:  69A0         LDRNE      R0, [R4, #24]
-  0x08000762:  F020 0070    BICNE      R0, R0, #112
-  0x08000766:  61A0         STRNE      R0, [R4, #24]
-  0x08000768:  69E0         LDR        R0, [R4, #28]
-  0x0800076A:  F010 0F70    TST        R0, #112
-  0x0800076E:  BF1E         ITTT       NE
-  0x08000770:  69E0         LDRNE      R0, [R4, #28]
-  0x08000772:  F020 0070    BICNE      R0, R0, #112
-  0x08000776:  61E0         STRNE      R0, [R4, #28]
-  0x08000778:  69E0         LDR        R0, [R4, #28]
-  0x0800077A:  F410 6FE0    TST        R0, #0x0700
-  0x0800077E:  BF1E         ITTT       NE
-  0x08000780:  69E0         LDRNE      R0, [R4, #28]
-  0x08000782:  F420 60E0    BICNE      R0, R0, #0x0700
-  0x08000786:  61E0         STRNE      R0, [R4, #28]
-  0x08000788:  6A20         LDR        R0, [R4, #32]
-  0x0800078A:  F010 0F70    TST        R0, #112
-  0x0800078E:  BF1E         ITTT       NE
-  0x08000790:  6A20         LDRNE      R0, [R4, #32]
-  0x08000792:  F020 0070    BICNE      R0, R0, #112
-  0x08000796:  6220         STRNE      R0, [R4, #32]
-  0x08000798:  F7FF FD98    BL         HAL_RCC_GetSysClockFreq  ; 0x080002CC
-  0x0800079C:  69A1         LDR        R1, [R4, #24]
-  0x0800079E:  F640 0286    MOVW       R2, #0x0886              ; 0x08000886 = D1CorePrescTable
-  0x080007A2:  F6C0 0200    MOVT       R2, #0x0800              ; 0x08000886 = D1CorePrescTable
-  0x080007A6:  F3C1 2103    UBFX       R1, R1, #8, #4
-  0x080007AA:  5C51         LDRB       R1, [R2, R1]
-  0x080007AC:  F240 0204    MOVW       R2, #4                   ; 0x30000004 = uwTickPrio
-  0x080007B0:  F2C3 0200    MOVT       R2, #0x3000              ; 0x30000004 = uwTickPrio
-  0x080007B4:  69A3         LDR        R3, [R4, #24]
-  0x080007B6:  F240 0308    MOVW       R3, #8                   ; 0x30000008 = SystemCoreClock
-  0x080007BA:  F001 011F    AND        R1, R1, #31
-  0x080007BE:  7812         LDRB       R2, [R2]
-  0x080007C0:  F2C3 0300    MOVT       R3, #0x3000              ; 0x30000008 = SystemCoreClock
-  0x080007C4:  FA20 F101    LSR.W      R1, R0, R1
-  0x080007C8:  2010         MOVS       R0, #16
-  0x080007CA:  2A00         CMP        R2, #0
-  0x080007CC:  6019         STR        R1, [R3]
-  0x080007CE:  BF18         IT         NE
-  0x080007D0:  200F         MOVNE      R0, #15
-  0x080007D2:  F000 F80C    BL         HAL_InitTick             ; 0x080007EE
-  0x080007D6:  B908         CBNZ       R0, .L13                 ; 0x080007DC
-  0x080007D8:  B002         ADD        SP, SP, #8
-  0x080007DA:  BD10         POP        {R4, PC}
+  0x08000974:  6828         LDR        R0, [R5]
+  0x08000976:  F040 0020    ORR        R0, R0, #32
+  0x0800097A:  6028         STR        R0, [R5]
 
    .L13:
-  0x080007DC:  B672         CPSID      i
+  0x0800097C:  F856 0C04    LDR        R0, [R6, #-4]
+  0x08000980:  6931         LDR        R1, [R6, #16]
+  0x08000982:  69B2         LDR        R2, [R6, #24]
+  0x08000984:  6CC3         LDR        R3, [R0, #76]
+  0x08000986:  4311         ORRS       R1, R2
+  0x08000988:  F023 0303    BIC        R3, R3, #3
+  0x0800098C:  64C3         STR        R3, [R0, #76]
+  0x0800098E:  6CC2         LDR        R2, [R0, #76]
+  0x08000990:  4311         ORRS       R1, R2
+  0x08000992:  64C1         STR        R1, [R0, #76]
+  0x08000994:  21FF         MOVS       R1, #255
+  0x08000996:  6241         STR        R1, [R0, #36]
+
    .L14:
+  0x08000998:  2001         MOVS       R0, #1
+  0x0800099A:  7770         STRB       R0, [R6, #29]
+  0x0800099C:  2000         MOVS       R0, #0
+  0x0800099E:  BD70         POP        {R4-R6, PC}
+
    
+
    Section .text.HAL_RTC_WaitForSynchro from charger_lto.o, size=54, align=2
    
+
    +
    HAL_RTC_WaitForSynchro:
+  0x080009A0:  F240 0000    MOVW       R0, #0                   ; 0x30000000 = hrtc
+  0x080009A4:  F64F 715F    MOVW       R1, #0xFF5F
+  0x080009A8:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000000 = hrtc
+  0x080009AC:  F2C0 0103    MOVT       R1, #3
+  0x080009B0:  6800         LDR        R0, [R0]
+  0x080009B2:  60C1         STR        R1, [R0, #12]
+  0x080009B4:  F240 0124    MOVW       R1, #36                  ; 0x30000024 = uwTick
+  0x080009B8:  F2C3 0100    MOVT       R1, #0x3000              ; 0x30000024 = uwTick
+  0x080009BC:  680A         LDR        R2, [R1]
+
    .L1:
+  0x080009BE:  68C3         LDR        R3, [R0, #12]
+  0x080009C0:  069B         LSLS       R3, R3, #26
+  0x080009C2:  D406         BMI        .L2                      ; 0x080009D2
+  0x080009C4:  680B         LDR        R3, [R1]
+  0x080009C6:  1A9B         SUBS       R3, R3, R2
+  0x080009C8:  F5B3 7F7A    CMP.W      R3, #0x03E8
+  0x080009CC:  D9F7         BLS        .L1                      ; 0x080009BE
+  0x080009CE:  2003         MOVS       R0, #3
+  0x080009D0:  4770         BX         LR
+
    .L2:
+  0x080009D2:  2000         MOVS       R0, #0
+  0x080009D4:  4770         BX         LR
+
    
+
    Section .text.main from charger_lto.o, size=304, align=2
    
+
    +
    main:
+  0x080009D6:  F64E 5014    MOVW       R0, #0xED14
+  0x080009DA:  F3BF 8F5F    DMB        SY
+  0x080009DE:  F2CE 0000    MOVT       R0, #0xE000
+  0x080009E2:  6901         LDR        R1, [R0, #16]
+  0x080009E4:  F421 3180    BIC        R1, R1, #0x010000
+  0x080009E8:  6101         STR        R1, [R0, #16]
+  0x080009EA:  2100         MOVS       R1, #0
+  0x080009EC:  F8C0 1080    STR.W      R1, [R0, #128]
+  0x080009F0:  F8C0 1084    STR.W      R1, [R0, #132]
+  0x080009F4:  F8D0 208C    LDR.W      R2, [R0, #140]
+  0x080009F8:  F022 0201    BIC        R2, R2, #1
+  0x080009FC:  F8C0 208C    STR.W      R2, [R0, #140]
+  0x08000A00:  F248 723F    MOVW       R2, #0x873F
+  0x08000A04:  F8C0 1088    STR.W      R1, [R0, #136]
+  0x08000A08:  F2C1 0204    MOVT       R2, #0x1004
+  0x08000A0C:  F8C0 208C    STR.W      R2, [R0, #140]
+  0x08000A10:  2205         MOVS       R2, #5
+  0x08000A12:  F8C0 2080    STR.W      R2, [R0, #128]
+  0x08000A16:  6902         LDR        R2, [R0, #16]
+  0x08000A18:  F442 3280    ORR        R2, R2, #0x010000
+  0x08000A1C:  6102         STR        R2, [R0, #16]
+  0x08000A1E:  F3BF 8F4F    DSB        SY
+  0x08000A22:  F3BF 8F6F    ISB        SY
+  0x08000A26:  6802         LDR        R2, [R0]
+  0x08000A28:  0392         LSLS       R2, R2, #14
+  0x08000A2A:  D411         BMI        .L1                      ; 0x08000A50
+  0x08000A2C:  F3BF 8F4F    DSB        SY
+  0x08000A30:  F3BF 8F6F    ISB        SY
+  0x08000A34:  F8C0 123C    STR.W      R1, [R0, #0x023C]
+  0x08000A38:  F3BF 8F4F    DSB        SY
+  0x08000A3C:  F3BF 8F6F    ISB        SY
+  0x08000A40:  6801         LDR        R1, [R0]
+  0x08000A42:  F441 3100    ORR        R1, R1, #0x020000
+  0x08000A46:  6001         STR        R1, [R0]
+  0x08000A48:  F3BF 8F4F    DSB        SY
+  0x08000A4C:  F3BF 8F6F    ISB        SY
+
    .L1:
+  0x08000A50:  B082         SUB        SP, SP, #8
+  0x08000A52:  6801         LDR        R1, [R0]
+  0x08000A54:  03C9         LSLS       R1, R1, #15
+  0x08000A56:  D426         BMI        .L4                      ; 0x08000AA6
+  0x08000A58:  2100         MOVS       R1, #0
+  0x08000A5A:  6701         STR        R1, [R0, #112]
+  0x08000A5C:  F3BF 8F4F    DSB        SY
+  0x08000A60:  F643 7EE0    MOVW       LR, #0x3FE0
+  0x08000A64:  6EC2         LDR        R2, [R0, #108]
+  0x08000A66:  EA4F 0CD2    LSR.W      R12, R2, #3
+  0x08000A6A:  F3C2 314E    UBFX       R1, R2, #13, #15
+  0x08000A6E:  F3C2 03C9    UBFX       R3, R2, #3, #10
+  0x08000A72:  3301         ADDS       R3, #1
+  0x08000A74:  014A         LSLS       R2, R1, #5
+
    .L2:
+  0x08000A76:  EA02 040E    AND.W      R4, R2, LR
+  0x08000A7A:  461D         MOV        R5, R3
+  0x08000A7C:  EB04 748C    ADD.W      R4, R4, R12, LSL #30
+
    .L3:
+  0x08000A80:  3D01         SUBS       R5, #1
+  0x08000A82:  F8C0 424C    STR.W      R4, [R0, #0x024C]
+  0x08000A86:  F104 4440    ADD.W      R4, R4, #0xC0000000
+  0x08000A8A:  D1F9         BNE        .L3                      ; 0x08000A80
+  0x08000A8C:  3A20         SUBS       R2, #32
+  0x08000A8E:  3901         SUBS       R1, #1
+  0x08000A90:  D2F1         BCS        .L2                      ; 0x08000A76
+  0x08000A92:  F3BF 8F4F    DSB        SY
+  0x08000A96:  6801         LDR        R1, [R0]
+  0x08000A98:  F441 3180    ORR        R1, R1, #0x010000
+  0x08000A9C:  6001         STR        R1, [R0]
+  0x08000A9E:  F3BF 8F4F    DSB        SY
+  0x08000AA2:  F3BF 8F6F    ISB        SY
+
    .L4:
+  0x08000AA6:  F7FF FE83    BL         HAL_Init                 ; 0x080007B0
+  0x08000AAA:  F7FF FC9F    BL         SystemClock_Config()     ; 0x080003EC
+  0x08000AAE:  F244 40E0    MOVW       R0, #0x44E0
+  0x08000AB2:  F6C5 0002    MOVT       R0, #0x5802
+  0x08000AB6:  6801         LDR        R1, [R0]
+  0x08000AB8:  F041 0104    ORR        R1, R1, #4
+  0x08000ABC:  6001         STR        R1, [R0]
+  0x08000ABE:  6801         LDR        R1, [R0]
+  0x08000AC0:  F001 0104    AND        R1, R1, #4
+  0x08000AC4:  9101         STR        R1, [SP, #4]
+  0x08000AC6:  9901         LDR        R1, [SP, #4]
+  0x08000AC8:  6801         LDR        R1, [R0]
+  0x08000ACA:  F041 0180    ORR        R1, R1, #128
+  0x08000ACE:  6001         STR        R1, [R0]
+  0x08000AD0:  6800         LDR        R0, [R0]
+  0x08000AD2:  F244 0100    MOVW       R1, #0x4000
+  0x08000AD6:  F000 0080    AND        R0, R0, #128
+  0x08000ADA:  9000         STR        R0, [SP, #0]
+  0x08000ADC:  F240 0000    MOVW       R0, #0                   ; 0x30000000 = hrtc
+  0x08000AE0:  9A00         LDR        R2, [SP, #0]
+  0x08000AE2:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000000 = hrtc
+  0x08000AE6:  F6C5 0100    MOVT       R1, #0x5800
+  0x08000AEA:  227F         MOVS       R2, #127
+  0x08000AEC:  6001         STR        R1, [R0]
+  0x08000AEE:  2100         MOVS       R1, #0
+  0x08000AF0:  E9C0 1201    STRD       R1, R2, [R0, #4]
+  0x08000AF4:  22FF         MOVS       R2, #255
+  0x08000AF6:  61C1         STR        R1, [R0, #28]
+  0x08000AF8:  E9C0 2103    STRD       R2, R1, [R0, #12]
+  0x08000AFC:  E9C0 1105    STRD       R1, R1, [R0, #20]
+  0x08000B00:  F7FF FE8F    BL         HAL_RTC_Init             ; 0x08000822
+  0x08000B04:  B672         CPSID      i
 
    
 
    Section .text.SysTick_Handler from charger_lto.o, size=16, align=2
    
 
    -
    SysTick_Handler:
-  0x080007DE:  F240 0000    MOVW       R0, #0                   ; 0x30000000 = uwTick
-  0x080007E2:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000000 = uwTick
-  0x080007E6:  6801         LDR        R1, [R0]
-  0x080007E8:  3101         ADDS       R1, #1
-  0x080007EA:  6001         STR        R1, [R0]
-  0x080007EC:  4770         BX         LR
+
    SysTick_Handler:
+  0x08000B06:  F240 0024    MOVW       R0, #36                  ; 0x30000024 = uwTick
+  0x08000B0A:  F2C3 0000    MOVT       R0, #0x3000              ; 0x30000024 = uwTick
+  0x08000B0E:  6801         LDR        R1, [R0]
+  0x08000B10:  3101         ADDS       R1, #1
+  0x08000B12:  6001         STR        R1, [R0]
+  0x08000B14:  4770         BX         LR
 
    
 
    Section .text.HAL_InitTick from charger_lto.o, size=128, align=2
    
 
    -
    HAL_InitTick:
-  0x080007EE:  F240 0108    MOVW       R1, #8                   ; 0x30000008 = SystemCoreClock
-  0x080007F2:  F644 52D3    MOVW       R2, #0x4DD3
-  0x080007F6:  F2C3 0100    MOVT       R1, #0x3000              ; 0x30000008 = SystemCoreClock
-  0x080007FA:  F2C1 0262    MOVT       R2, #0x1062
-  0x080007FE:  6809         LDR        R1, [R1]
-  0x08000800:  FBA1 1202    UMULL      R1, R2, R1, R2
-  0x08000804:  F04F 31FF    MOV.W      R1, #0xFFFFFFFF
-  0x08000808:  EB01 1292    ADD.W      R2, R1, R2, LSR #6
-  0x0800080C:  0E11         LSRS       R1, R2, #24
-  0x0800080E:  D001         BEQ        .L1                      ; 0x08000814
-  0x08000810:  2001         MOVS       R0, #1
-  0x08000812:  4770         BX         LR
+
    HAL_InitTick:
+  0x08000B16:  F240 012C    MOVW       R1, #44                  ; 0x3000002C = SystemCoreClock
+  0x08000B1A:  F644 52D3    MOVW       R2, #0x4DD3
+  0x08000B1E:  F2C3 0100    MOVT       R1, #0x3000              ; 0x3000002C = SystemCoreClock
+  0x08000B22:  F2C1 0262    MOVT       R2, #0x1062
+  0x08000B26:  6809         LDR        R1, [R1]
+  0x08000B28:  FBA1 1202    UMULL      R1, R2, R1, R2
+  0x08000B2C:  F04F 31FF    MOV.W      R1, #0xFFFFFFFF
+  0x08000B30:  EB01 1292    ADD.W      R2, R1, R2, LSR #6
+  0x08000B34:  0E11         LSRS       R1, R2, #24
+  0x08000B36:  D001         BEQ        .L1                      ; 0x08000B3C
+  0x08000B38:  2001         MOVS       R0, #1
+  0x08000B3A:  4770         BX         LR
 
    .L1:
-  0x08000814:  F24E 0310    MOVW       R3, #0xE010
-  0x08000818:  280F         CMP        R0, #15
-  0x0800081A:  F2CE 0300    MOVT       R3, #0xE000
-  0x0800081E:  F04F 0001    MOV.W      R0, #1
-  0x08000822:  F603 4CFC    ADDW       R12, R3, #0x0CFC
-  0x08000826:  605A         STR        R2, [R3, #4]
-  0x08000828:  F04F 02F0    MOV.W      R2, #240
-  0x0800082C:  F88C 2017    STRB.W     R2, [R12, #23]
-  0x08000830:  F04F 0207    MOV.W      R2, #7
-  0x08000834:  6099         STR        R1, [R3, #8]
-  0x08000836:  601A         STR        R2, [R3]
-  0x08000838:  BF88         IT         HI
-  0x0800083A:  4770         BXHI       LR
-  0x0800083C:  F8DC 2000    LDR.W      R2, [R12]
-  0x08000840:  43C9         MVNS       R1, R1
-  0x08000842:  F3C2 2202    UBFX       R2, R2, #8, #3
-  0x08000846:  F082 0307    EOR        R3, R2, #7
-  0x0800084A:  2B04         CMP        R3, #4
-  0x0800084C:  BF28         IT         CS
-  0x0800084E:  2304         MOVCS      R3, #4
-  0x08000850:  4099         LSLS       R1, R3
-  0x08000852:  43C9         MVNS       R1, R1
-  0x08000854:  3A03         SUBS       R2, #3
-  0x08000856:  BF28         IT         CS
-  0x08000858:  4091         LSLCS      R1, R2
-  0x0800085A:  0109         LSLS       R1, R1, #4
-  0x0800085C:  F88C 1017    STRB.W     R1, [R12, #23]
-  0x08000860:  F240 0104    MOVW       R1, #4                   ; 0x30000004 = uwTickPrio
-  0x08000864:  F2C3 0100    MOVT       R1, #0x3000              ; 0x30000004 = uwTickPrio
-  0x08000868:  7008         STRB       R0, [R1]
-  0x0800086A:  2000         MOVS       R0, #0
-  0x0800086C:  4770         BX         LR
+  0x08000B3C:  F24E 0310    MOVW       R3, #0xE010
+  0x08000B40:  280F         CMP        R0, #15
+  0x08000B42:  F2CE 0300    MOVT       R3, #0xE000
+  0x08000B46:  F04F 0001    MOV.W      R0, #1
+  0x08000B4A:  F603 4CFC    ADDW       R12, R3, #0x0CFC
+  0x08000B4E:  605A         STR        R2, [R3, #4]
+  0x08000B50:  F04F 02F0    MOV.W      R2, #240
+  0x08000B54:  F88C 2017    STRB.W     R2, [R12, #23]
+  0x08000B58:  F04F 0207    MOV.W      R2, #7
+  0x08000B5C:  6099         STR        R1, [R3, #8]
+  0x08000B5E:  601A         STR        R2, [R3]
+  0x08000B60:  BF88         IT         HI
+  0x08000B62:  4770         BXHI       LR
+  0x08000B64:  F8DC 2000    LDR.W      R2, [R12]
+  0x08000B68:  43C9         MVNS       R1, R1
+  0x08000B6A:  F3C2 2202    UBFX       R2, R2, #8, #3
+  0x08000B6E:  F082 0307    EOR        R3, R2, #7
+  0x08000B72:  2B04         CMP        R3, #4
+  0x08000B74:  BF28         IT         CS
+  0x08000B76:  2304         MOVCS      R3, #4
+  0x08000B78:  4099         LSLS       R1, R3
+  0x08000B7A:  43C9         MVNS       R1, R1
+  0x08000B7C:  3A03         SUBS       R2, #3
+  0x08000B7E:  BF28         IT         CS
+  0x08000B80:  4091         LSLCS      R1, R2
+  0x08000B82:  0109         LSLS       R1, R1, #4
+  0x08000B84:  F88C 1017    STRB.W     R1, [R12, #23]
+  0x08000B88:  F240 0128    MOVW       R1, #40                  ; 0x30000028 = uwTickPrio
+  0x08000B8C:  F2C3 0100    MOVT       R1, #0x3000              ; 0x30000028 = uwTickPrio
+  0x08000B90:  7008         STRB       R0, [R1]
+  0x08000B92:  2000         MOVS       R0, #0
+  0x08000B94:  4770         BX         LR
 
    
 
    Section .init.Reset_Handler from Cortex_M_Startup.o, size=24, align=2
    
 
    -
    Reset_Handler:
-reset_handler:
-  0x0800086E:  F7FF FE3E    BL         SystemInit               ; 0x080004EE
-  0x08000872:  F64E 5088    MOVW       R0, #0xED88
-  0x08000876:  F2CE 0000    MOVT       R0, #0xE000
-  0x0800087A:  6801         LDR        R1, [R0]
-  0x0800087C:  F451 0170    ORRS       R1, R1, #0xF00000
-  0x08000880:  6001         STR        R1, [R0]
-  0x08000882:  F7FF FDA9    BL         _start                   ; 0x080003D8
+
    Reset_Handler:
+reset_handler:
+  0x08000B96:  F7FF FDB6    BL         SystemInit               ; 0x08000706
+  0x08000B9A:  F64E 5088    MOVW       R0, #0xED88
+  0x08000B9E:  F2CE 0000    MOVT       R0, #0xE000
+  0x08000BA2:  6801         LDR        R1, [R0]
+  0x08000BA4:  F451 0170    ORRS       R1, R1, #0xF00000
+  0x08000BA8:  6001         STR        R1, [R0]
+  0x08000BAA:  F7FF FC15    BL         _start                   ; 0x080003D8
 
    
 
    Section .rodata.D1CorePrescTable from charger_lto.o, size=16, align=1
    
 
    -
    D1CorePrescTable:
-  0x08000886:  00           DC.B       0x00                     ; '\0'
-  0x08000887:  00           DC.B       0x00                     ; '\0'
-  0x08000888:  00           DC.B       0x00                     ; '\0'
-  0x08000889:  00           DC.B       0x00                     ; '\0'
-  0x0800088A:  00           DC.B       0x00                     ; '\0'
-  0x0800088B:  00           DC.B       0x00                     ; '\0'
-  0x0800088C:  00           DC.B       0x00                     ; '\0'
-  0x0800088D:  00           DC.B       0x00                     ; '\0'
-  0x0800088E:  01           DC.B       0x01                     ; '\x01'
-  0x0800088F:  02           DC.B       0x02                     ; '\x02'
-  0x08000890:  03           DC.B       0x03                     ; '\x03'
-  0x08000891:  04           DC.B       0x04                     ; '\x04'
-  0x08000892:  06           DC.B       0x06                     ; '\x06'
-  0x08000893:  07           DC.B       0x07                     ; '\x07'
-  0x08000894:  08           DC.B       0x08                     ; '\b'
-  0x08000895:  09           DC.B       0x09                     ; '\t'
+
    D1CorePrescTable:
+  0x08000BAE:  00           DC.B       0x00                     ; '\0'
+  0x08000BAF:  00           DC.B       0x00                     ; '\0'
+  0x08000BB0:  00           DC.B       0x00                     ; '\0'
+  0x08000BB1:  00           DC.B       0x00                     ; '\0'
+  0x08000BB2:  00           DC.B       0x00                     ; '\0'
+  0x08000BB3:  00           DC.B       0x00                     ; '\0'
+  0x08000BB4:  00           DC.B       0x00                     ; '\0'
+  0x08000BB5:  00           DC.B       0x00                     ; '\0'
+  0x08000BB6:  01           DC.B       0x01                     ; '\x01'
+  0x08000BB7:  02           DC.B       0x02                     ; '\x02'
+  0x08000BB8:  03           DC.B       0x03                     ; '\x03'
+  0x08000BB9:  04           DC.B       0x04                     ; '\x04'
+  0x08000BBA:  06           DC.B       0x06                     ; '\x06'
+  0x08000BBB:  07           DC.B       0x07                     ; '\x07'
+  0x08000BBC:  08           DC.B       0x08                     ; '\b'
+  0x08000BBD:  09           DC.B       0x09                     ; '\t'
 
    
 
    Section .segger.init.table from [ Linker created ], size=32, align=4
    
 
    -  0x08000898:  080008BD     DC.W       __SEGGER_init_zero
-  0x0800089C:  00           DC.B       0x00                     ; '\0'
-  0x0800089D:  00           DC.B       0x00                     ; '\0'
-  0x0800089E:  00           DC.B       0x00                     ; '\0'
-  0x0800089F:  30           DC.B       0x30                     ; '0'
-  0x080008A0:  05           DC.B       0x05                     ; '\x05'
-  0x080008A1:  00           DC.B       0x00                     ; '\0'
-  0x080008A2:  00           DC.B       0x00                     ; '\0'
-  0x080008A3:  00           DC.B       0x00                     ; '\0'
-  0x080008A4:  080008CF     DC.W       __SEGGER_init_copy
-  0x080008A8:  08           DC.B       0x08                     ; '\b'
-  0x080008A9:  00           DC.B       0x00                     ; '\0'
-  0x080008AA:  00           DC.B       0x00                     ; '\0'
-  0x080008AB:  30           DC.B       0x30                     ; '0'
-  0x080008AC:  080008B8     DC.W       0x080008B8               ; R_ARM_ABS32
-  0x080008B0:  04           DC.B       0x04                     ; '\x04'
-  0x080008B1:  00           DC.B       0x00                     ; '\0'
-  0x080008B2:  00           DC.B       0x00                     ; '\0'
-  0x080008B3:  00           DC.B       0x00                     ; '\0'
-  0x080008B4:  080003E3     DC.W       __SEGGER_init_done
+  0x08000BC0:  08000BE5     DC.W       __SEGGER_init_zero
+  0x08000BC4:  00           DC.B       0x00                     ; '\0'
+  0x08000BC5:  00           DC.B       0x00                     ; '\0'
+  0x08000BC6:  00           DC.B       0x00                     ; '\0'
+  0x08000BC7:  30           DC.B       0x30                     ; '0'
+  0x08000BC8:  29           DC.B       0x29                     ; ')'
+  0x08000BC9:  00           DC.B       0x00                     ; '\0'
+  0x08000BCA:  00           DC.B       0x00                     ; '\0'
+  0x08000BCB:  00           DC.B       0x00                     ; '\0'
+  0x08000BCC:  08000BF7     DC.W       __SEGGER_init_copy
+  0x08000BD0:  2C           DC.B       0x2C                     ; ','
+  0x08000BD1:  00           DC.B       0x00                     ; '\0'
+  0x08000BD2:  00           DC.B       0x00                     ; '\0'
+  0x08000BD3:  30           DC.B       0x30                     ; '0'
+  0x08000BD4:  08000BE0     DC.W       0x08000BE0               ; R_ARM_ABS32
+  0x08000BD8:  04           DC.B       0x04                     ; '\x04'
+  0x08000BD9:  00           DC.B       0x00                     ; '\0'
+  0x08000BDA:  00           DC.B       0x00                     ; '\0'
+  0x08000BDB:  00           DC.B       0x00                     ; '\0'
+  0x08000BDC:  080003E3     DC.W       __SEGGER_init_done
 
    
 
    Section .segger.init.data from [ Linker created ], size=4, align=4
    
 
    -  0x080008B8:  00           DC.B       0x00                     ; '\0'
-  0x080008B9:  90           DC.B       0x90                     ; '\x90'
-  0x080008BA:  D0           DC.B       0xD0                     ; '\xD0'
-  0x080008BB:  03           DC.B       0x03                     ; '\x03'
+  0x08000BE0:  00           DC.B       0x00                     ; '\0'
+  0x08000BE1:  90           DC.B       0x90                     ; '\x90'
+  0x08000BE2:  D0           DC.B       0xD0                     ; '\xD0'
+  0x08000BE3:  03           DC.B       0x03                     ; '\x03'
 
    
 
    Section .segger.init.__SEGGER_init_zero from SEGGER_crtinit.o (SEGGER_crtinit_v7em_fpv5_d16_hard_t_le_eabi_balanced.a), size=18, align=2
    
 
    -
    __SEGGER_init_zero:
-  0x080008BC:  6820         LDR        R0, [R4]
-  0x080008BE:  6861         LDR        R1, [R4, #4]
-  0x080008C0:  3408         ADDS       R4, #8
-  0x080008C2:  2200         MOVS       R2, #0
-  0x080008C4:  E000         B          .L2                      ; 0x080008C8
+
    __SEGGER_init_zero:
+  0x08000BE4:  6820         LDR        R0, [R4]
+  0x08000BE6:  6861         LDR        R1, [R4, #4]
+  0x08000BE8:  3408         ADDS       R4, #8
+  0x08000BEA:  2200         MOVS       R2, #0
+  0x08000BEC:  E000         B          .L2                      ; 0x08000BF0
 
    .L1:
-  0x080008C6:  5442         STRB       R2, [R0, R1]
+  0x08000BEE:  5442         STRB       R2, [R0, R1]
 
    .L2:
-  0x080008C8:  3901         SUBS       R1, #1
-  0x080008CA:  D5FC         BPL        .L1                      ; 0x080008C6
-  0x080008CC:  4770         BX         LR
+  0x08000BF0:  3901         SUBS       R1, #1
+  0x08000BF2:  D5FC         BPL        .L1                      ; 0x08000BEE
+  0x08000BF4:  4770         BX         LR
 
    
 
    Section .segger.init.__SEGGER_init_copy from SEGGER_crtinit.o (SEGGER_crtinit_v7em_fpv5_d16_hard_t_le_eabi_balanced.a), size=20, align=2
    
 
    -
    __SEGGER_init_copy:
-  0x080008CE:  6820         LDR        R0, [R4]
-  0x080008D0:  6861         LDR        R1, [R4, #4]
-  0x080008D2:  68A2         LDR        R2, [R4, #8]
-  0x080008D4:  340C         ADDS       R4, #12
-  0x080008D6:  E001         B          .L2                      ; 0x080008DC
+
    __SEGGER_init_copy:
+  0x08000BF6:  6820         LDR        R0, [R4]
+  0x08000BF8:  6861         LDR        R1, [R4, #4]
+  0x08000BFA:  68A2         LDR        R2, [R4, #8]
+  0x08000BFC:  340C         ADDS       R4, #12
+  0x08000BFE:  E001         B          .L2                      ; 0x08000C04
 
    .L1:
-  0x080008D8:  5C8B         LDRB       R3, [R1, R2]
-  0x080008DA:  5483         STRB       R3, [R0, R2]
+  0x08000C00:  5C8B         LDRB       R3, [R1, R2]
+  0x08000C02:  5483         STRB       R3, [R0, R2]
 
    .L2:
-  0x080008DC:  3A01         SUBS       R2, #1
-  0x080008DE:  D5FB         BPL        .L1                      ; 0x080008D8
-  0x080008E0:  4770         BX         LR
+  0x08000C04:  3A01         SUBS       R2, #1
+  0x08000C06:  D5FB         BPL        .L1                      ; 0x08000C00
+  0x08000C08:  4770         BX         LR
+
    
+
    Section .bss.hrtc from charger_lto.o, size=36, align=4
    
+
    +
    hrtc:
+  0x30000000:  00           DC.B       0x00                     ; '\0'
+  0x30000001:  00           DC.B       0x00                     ; '\0'
+  0x30000002:  00           DC.B       0x00                     ; '\0'
+  0x30000003:  00           DC.B       0x00                     ; '\0'
+  0x30000004:  00           DC.B       0x00                     ; '\0'
+  0x30000005:  00           DC.B       0x00                     ; '\0'
+  0x30000006:  00           DC.B       0x00                     ; '\0'
+  0x30000007:  00           DC.B       0x00                     ; '\0'
+  0x30000008:  01           DC.B       0x01                     ; '\x01'
+  0x30000009:  02           DC.B       0x02                     ; '\x02'
+  0x3000000A:  03           DC.B       0x03                     ; '\x03'
+  0x3000000B:  04           DC.B       0x04                     ; '\x04'
+  0x3000000C:  06           DC.B       0x06                     ; '\x06'
+  0x3000000D:  07           DC.B       0x07                     ; '\x07'
+  0x3000000E:  08           DC.B       0x08                     ; '\b'
+  0x3000000F:  09           DC.B       0x09                     ; '\t'
+  0x30000010:  00           DC.B       0x00                     ; '\0'
+  0x30000011:  90           DC.B       0x90                     ; '\x90'
+  0x30000012:  D0           DC.B       0xD0                     ; '\xD0'
+  0x30000013:  03           DC.B       0x03                     ; '\x03'
+  0x30000014:  FF           DC.B       0xFF                     ; '\xFF'
+  0x30000015:  FF           DC.B       0xFF                     ; '\xFF'
+  0x30000016:  FF           DC.B       0xFF                     ; '\xFF'
+  0x30000017:  FF           DC.B       0xFF                     ; '\xFF'
+  0x30000018:  D6           DC.B       0xD6                     ; '\xD6'
+  0x30000019:  09           DC.B       0x09                     ; '\t'
+  0x3000001A:  00           DC.B       0x00                     ; '\0'
+  0x3000001B:  08           DC.B       0x08                     ; '\b'
+  0x3000001C:  0C           DC.B       0x0C                     ; '\x0C'
+  0x3000001D:  00           DC.B       0x00                     ; '\0'
+  0x3000001E:  00           DC.B       0x00                     ; '\0'
+  0x3000001F:  00           DC.B       0x00                     ; '\0'
+  0x30000020:  1A           DC.B       0x1A                     ; '\x1A'
+  0x30000021:  00           DC.B       0x00                     ; '\0'
+  0x30000022:  00           DC.B       0x00                     ; '\0'
+  0x30000023:  00           DC.B       0x00                     ; '\0'
 
    
 
    Section .bss.uwTick from charger_lto.o, size=4, align=4
    
 
    -
    uwTick:
-  0x30000000:  00           DC.B       0x00                     ; '\0'
-  0x30000001:  90           DC.B       0x90                     ; '\x90'
-  0x30000002:  D0           DC.B       0xD0                     ; '\xD0'
-  0x30000003:  03           DC.B       0x03                     ; '\x03'
+
    uwTick:
+  0x30000024:  00           DC.B       0x00                     ; '\0'
+  0x30000025:  00           DC.B       0x00                     ; '\0'
+  0x30000026:  00           DC.B       0x00                     ; '\0'
+  0x30000027:  00           DC.B       0x00                     ; '\0'
 
    
 
    Section .bss.uwTickPrio from charger_lto.o, size=1, align=4
    
 
    -
    uwTickPrio:
-  0x30000004:  00           DC.B       0x00                     ; '\0'
+
    uwTickPrio:
+  0x30000028:  00           DC.B       0x00                     ; '\0'
 
    
 
    Section .data.SystemCoreClock from charger_lto.o, size=4, align=4
    
 
    -
    SystemCoreClock:
-  0x30000008:  00           DC.B       0x00                     ; '\0'
-  0x30000009:  90           DC.B       0x90                     ; '\x90'
-  0x3000000A:  D0           DC.B       0xD0                     ; '\xD0'
-  0x3000000B:  03           DC.B       0x03                     ; '\x03'
+
    SystemCoreClock:
+  0x3000002C:  00           DC.B       0x00                     ; '\0'
+  0x3000002D:  90           DC.B       0x90                     ; '\x90'
+  0x3000002E:  D0           DC.B       0xD0                     ; '\xD0'
+  0x3000002F:  03           DC.B       0x03                     ; '\x03'
 
    
 
    Section .bss.block.stack from [ Linker created ], size=8192, align=8
    
@@ -8376,7 +9070,7 @@
 
    LINK SUMMARY
    
 
-  2 220 bytes read-only  code    + 
-     52 bytes read-only  data    =   2 272 bytes read-only (total)
-  8 201 bytes read-write data
+  3 028 bytes read-only  code    + 
+     52 bytes read-only  data    =   3 080 bytes read-only (total)
+  8 237 bytes read-write data
 
 
@@ -8393,6 +9087,6 @@
     
-    
-    
+    
+    
@@ -8401,6 +9095,6 @@
     
-    
-    
+    
+    
Index: /ctrl/firmware/Main/SES/charger.emProject
===================================================================
--- /ctrl/firmware/Main/SES/charger.emProject	(revision 43)
+++ /ctrl/firmware/Main/SES/charger.emProject	(revision 44)
@@ -105,4 +105,5 @@
           
           
+          
           
         

    08000000-0807ffff
     524 2882 272   0.43%522 016  99.57%3 080   0.59%521 208  99.41%
     0   0.00%
   
    30000000-30007fff
     32 7688 201  25.03%24 564  74.96%8 237  25.14%24 528  74.85%
     3   0.01%